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Chin %*A Decidable Fragment in Separation Logic with Inductive Predicates and Arithmetic %f/cav/gxdqzzmyjd3p2ulhtir6kof0emsqxhca.pdf %m68ec6ef354fd2d3c016a4c6fc740cdee %ccav %@Andrei Marian Dan,Manu Sridharan,Satish Chandra,Jean-Baptiste Jeannin,Martin Vechev %*Finding Fix Locations for CFL-Reachability Analyses via Minimum Cuts %f/cav/exsbmduz6v9jq3flwp4jfhisyqkina5t.pdf %maef459e2491c758a1de67c9622ea2f1e %ccav %@Ahmed Bouajjani,Michael Emmi,Constantin Enea,Suha Orhun Mutluergil %*Proving Linearizability Using Forward Simulations %f/cav/fp7w9brt1aylmg02go6lmwzj3znheosv.pdf %m210e47373d8151b8209f89936e094637 %ccav %@Bernd Finkbeiner,Christopher Hahn,Marvin Stenger %*EAHyper: Satisfiability, Implication, and Equivalence Checking of Hyperproperties %f/cav/ghkbq9ss7amwt1pnv0jyelp2t6r3zc4m.pdf %mff37ba82db8987961e41d698dead63bf %ccav %@Hiroshi Unno,Sho Torii,Hiroki Sakamoto %*Automating Induction for Solving Horn Clauses %f/cav/ujdxbwho4fgmui67nirfwz9qjpolqs51.pdf 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Ben-Amram,Samir Genaim %*On Multiphase-Linear Ranking Functions %f/cav/hnonf9img21ceszrrx30cglkutuylivj.pdf %mdb009df683131fc067acb5d1f727f22e %ccav %@Kyoko Makino,Martin Berz %*Verified Computations Using Taylor Models and Their Applications %f/cav/uhdtdyk1emaoeasmkvc5ipfsn8gwqry6.pdf %m1c319d6935cf6c849d5e8aed5906e59c %ccav %@Nathalie Revol %*Introduction to the IEEE 1788-2015 Standard for Interval Arithmetic %f/cav/yuk2gd7nixuzejip5q816kbrapr3svfb.pdf %m79cef46c4105c5ae8e81524c23efbd45 %ccav %@Arthur Blot,Jean-Michel Muller,Laurent Théry %*Formal Correctness of Comparison Algorithms Between Binary64 and Decimal64 Floating-Point Numbers %f/cav/xeav6qbysqwo7nuvz8xdcoligj34mhct.pdf %m4745c2c9e4af4081eb7782d2bf1e3550 %ccav %@Dario Cattaruzza,Alessandro Abate,Peter Schrammel,Daniel Kroening %*Sound Numerical Computations in Abstract Acceleration %f/cav/v6m3vt9isbea1hwl0yg2cikwxrdyfeoq.pdf %m69781561370b33d230b7202b2cb34576 %ccav %@François Févotte,Bruno Lathuilière %*Studying the Numerical Quality of an Industrial Computing Code: A Case Study on Code_aster %f/cav/fiywoo8qle4siu9dzaxvt6rehwpjgmbm.pdf %m1d10b207fe28a4bdfa198a66eb113fa9 %ccav %@Stanley Bak,Sergiy Bogomolov,Thomas A. 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Hu %*Fast, Flexible, and Minimal CTL Synthesis via SMT %f/cav/wxrzlyqdhvsutropl4c10akm7ufis3aq.pdf %m401bdd42a4ebbe03a72d160b0fb2dc66 %ccav %@Roderick Bloem,Nicolas Braud-Santoni,Swen Jacobs %*Synthesis of Self-Stabilising and Byzantine-Resilient Distributed Systems %f/cav/i03lfiuqwveygbmnjfozn8stvzap75qs.pdf %m77311c116580858f18d6557bd4ce7d30 %ccav %@Maximiliano Cristiá,Gianfranco Rossi %*A Decision Procedure for Sets, Binary Relations and Partial Functions %f/cav/mfrwh5noqnt6qs14gguo3vd78e2etyuz.pdf %mdd12636c07bcf0e43d9999ba6ead8068 %ccav %@Aina Niemetz,Mathias Preiner,Armin Biere %*Precise and Complete Propagation Based Local Search for Satisfiability Modulo Theories %f/cav/xogdbv2cflyt4arrb5snezgxd1ywquhp.pdf %m438ec7ec157e14adc9c8255c78d1f5e4 %ccav %@Minh-Thai Trinh,Duc-Hiep Chu,Joxan Jaffar %*Progressive Reasoning over Recursively-Defined Strings %f/cav/pwybwgqu53nbhxmivhyrk1cfq8ajdp69.pdf %m7b8d9852f2ef5de174aeca7a84d0357e %ccav %@Hung-En Wang,Tzung-Lin Tsai,Chun-Han Lin,Fang Yu,Jie-Hong R. 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Teitelbaum %*Model Checking x86 Executables with CodeSurfer/x86 and WPDS++ %f/cav/dhgbzte3yock8ch5i20enfpqdzakvflb.pdf %mbc98e3b32d90a6bf4083479882d691ec %ccav %@Sagar Chaki,James Ivers,Natasha Sharygina,Kurt Wallnau %*The ComFoRT Reasoning Framework %f/cav/uunij1qgq5mzcrypenk36szm4jvo9beh.pdf %m54e2fe30a8ad1f3f81e01849c9e4fde7 %ccav %@Roope Kaivola %*Formal Verification of Pentium ® 4 Components with Symbolic Simulation and Inductive Invariants %f/cav/qaq26meussvzklt7chogfu8dwzdvixh9.pdf %m150c7107260415d23e0cb13795bf6ca3 %ccav %@Tamarah Arons,Elad Elster,Limor Fix,Sela Mador-Haim,Michael Mishaeli,Jonathan Shalev,Eli Singerman,Andreas Tiemeyer,Moshe Y. Vardi,Lenore D. Zuck %*Formal Verification of Backward Compatibility of Microcode %f/cav/ebzdqowlmif7z9v81gsigyusylpr3awf.pdf %mcfb6b01f14e6edb0d2f70d03ea896078 %ccav %@David Monniaux %*Compositional Analysis of Floating-Point Linear Numerical Filters %f/cav/3jegzsuorti6smmkwiczol14wnqpdfbx.pdf %m86e59df64501360ffc42161662b2df11 %ccav %@Eric Vecchié,Robert de Simone %*Syntax-Driven Reachable State Space Construction of Synchronous Reactive Programs %f/cav/tdvlhkxekdm9jl3bpj1ymcfxi4gf7tcp.pdf %mc4b4e3b8799a669912f5400a7d73bec8 %ccav %@Barbara Jobstmann,Andreas Griesmayer,Roderick Bloem %*Program Repair as a Game %f/cav/vbk5itnxmr3pg7ufe0soqzavr4wyzsfl.pdf %m767b8e6af39b2c17d1e0a3d1c30e13ab %ccav %@Amitabha Roy,K. Gopinath %*Improved Probabilistic Models for 802.11 Protocol Verification %f/cav/gzjmwe3qd87qdvrylm20icekiu6rufna.pdf %mce09167f07e6a48c58af6c1be4610bae %ccav %@Håkan L. S. Younes %*Probabilistic Verification for “Black-Box” Systems %f/cav/ygdxzhek3adqiris9vcfu71ot2g8vrpk.pdf %m9e56d40e73a9db82f5d8fc22e8813a0f %ccav %@Koushik Sen,Mahesh Viswanathan,Gul Agha %*On Statistical Model Checking of Stochastic Systems %f/cav/foksl80ugd3in6vpqdg2kanmuvsjxhph.pdf %m148422789946c2cd60749d6663d637ee %ccav %@A. Armando,D. Basin,Y. Boichut,Y. Chevalier,L. Compagna,J. Cuellar,P. Hankes Drielsma,P. C. Heám,O. Kouchnarenko,J. Mantovani,S. Mödersheim,D. von Oheimb,M. Rusinowitch,J. Santiago,M. Turuani,L. Viganò,L. Vigneron %*The AVISPA Tool for the Automated Validation of Internet Security Protocols and Applications %f/cav/zmrrohqbdecyyon3lbwc94sfvdkw6xmu.pdf %m11ae9058afcc15afbad19c4b5fc27b66 %ccav %@Julien Olivain,Jean Goubault-Larrecq %*The Orchids Intrusion Detection Tool %f/cav/yqytuwimddookefjwjbba2vzi4vurklp.pdf %me90a35e79e40db6f83b66c20794d83a4 %ccav %@Clark Barrett,Yi Fang,Benjamin Goldberg,Ying Hu,Amir Pnueli,Lenore Zuck %*TVOC: A Translation Validator for Optimizing Compilers %f/cav/dkfjmj2ve8ecgysu37bnqhovwy956r1m.pdf %mf88d0e29189d865f5a506e9d8284a916 %ccav %@Byron Cook,Daniel Kroening,Natasha Sharygina %*Cogent: Accurate Theorem Proving for Program Verification %f/cav/sfivteqcvyxpgmrq1ui08clho9en5fb3.pdf %m09fd8ee502787e6ded7cccb221cea0c3 %ccav %@F. Ivančić,Z. Yang,M. K. Ganai,A. Gupta,I. Shlyakhter,P. Ashar %*F-Soft: Software Verification Platform %f/cav/vuds0tx9x1y8kw7ukcmfzq54il3see6d.pdf %m161a894e96fb7adacd94ed0b2190a1bf %ccav %@Orly Meir,Ofer Strichman %*Yet Another Decision Procedure for Equality Logic %f/cav/zjgqtb2wheknvv7rdhxpueiqxsklgjan.pdf %mdb85d45adb843ed6e12552192c9d36f3 %ccav %@Robert Nieuwenhuis,Albert Oliveras %*DPLL(T) with Exhaustive Theory Propagation and Its Application to Difference Logic %f/cav/rntm8lmbbzduhjhcq4zcktyosg1ikdvw.pdf %m1c3c3073f756f6286f260e29b7a628e6 %ccav %@Marco Bozzano,Roberto Bruttomesso,Alessandro Cimatti,Tommi Junttila,Silvio Ranise,Peter van Rossum,Roberto Sebastiani %*Efficient Satisfiability Modulo Theories via Delayed Theory Combination %f/cav/m5izrugzb0ffhmd9ekcsj348axvqylio.pdf %m1d70b231be39f6b8f19a7fa0bca9d0ce %ccav %@Roberto Sebastiani,Stefano Tonetta,Moshe Y. Vardi %*Symbolic Systems, Explicit Properties: On Hybrid Approaches for LTL Symbolic Model Checking %f/cav/7ntygfjmlscgvb589bt0oaihn3i6erq2.pdf %mda1d00aa2a650dbe08de2dd84b59554c %ccav %@Marcelo d’Amorim,Grigore Roşu %*Efficient Monitoring of ω-Languages %f/cav/7cdzlxcw82v9xmt1kmarsizepqo3hdl6.pdf %mb938ad3fd3b9588e6ce8ad9b64365b9c %ccav %@Michael Benedikt,Angela Bonifati,Sergio Flesca,Avinash Vyas %*Verification of Tree Updates for Optimization %f/cav/y2rwarjbxi8kmoszntqstpuibf6y0jhz.pdf %m65242e12cf0e9d8aa35a2452f324087c %ccav %@Gilles Geeraerts,Jean-François Raskin,Laurent Van Begin %*Expand, Enlarge and Check... Made Efficient %f/cav/oan29v8tlcnhf1jiexs6rubfygvek5k3.pdf %md7dab2c60de41087bb73f1038dd28ac3 %ccav %@Ittai Balaban,Yi Fang,Amir Pnueli,Lenore D. Zuck %*IIV: An Invisible Invariant Verifier %f/cav/yl8pai3mmtshfpr1necxsdbk7otgn6ul.pdf %m46cd9d59d68d9cdc234ddaa8865f4d3f %ccav %@Tuba Yavuz-Kahveci,Constantinos Bartzis,Tevfik Bultan %*Action Language Verifier, Extended %f/cav/jsfrumqgsaclkbq6lgxm7z0tkpdxd8wi.pdf %mdfbd4eb94c79728913975825fd369ede %ccav %@Guillaume Gardey,Didier Lime,Morgan Magnin,Olivier (H. ) Roux %*Romeo: A Tool for Analyzing Time Petri Nets %f/cav/ossjz8ahxbwvyk1erttk9jdwdq3ncvq5.pdf %m053f3cba21d0f58b2e905bdfd44a3859 %ccav %@Enric Pastor,Marco A. Peña,Marc Solé %*TRANSYT:A Tool for the Verification of Asynchronous Concurrent Systems %f/cav/5eurizvyszndw1u6qpg8fxgcc7vosoiq.pdf %m1f85c9a249dee213b58fb5bc0100b382 %ccav %@Håkan L. S. Younes %*Ymer: A Statistical Model Checker %f/cav/g5mwt0rlg2fex1nlhotrj3ovfqj8ai6y.pdf %mc4dba474fa86aa3271784d0809c27da5 %ccav %@Akash Lal,Thomas Reps,Gogul Balakrishnan %*Extended Weighted Pushdown Systems %f/cav/0asj6eazdvewxbx3hyipmdnq1pqrjwmy.pdf %m8af47b754ee0898cc1baf499316f241e %ccav %@Christopher L. Conway,Kedar S. Namjoshi,Dennis Dams,Stephen A. Edwards %*Incremental Algorithms for Inter-procedural Analysis of Safety Properties %f/cav/siq8j3omafdgevb2lld1rvxottygca0w.pdf %m91b081054412296707b8303d67319ba4 %ccav %@A. Costan,S. Gaubert,E. Goubault,M. Martel,S. Putot %*A Policy Iteration Algorithm for Computing Fixed Points in Static Analysis of Programs %f/cav/ean1nddfw74xbwcfkormyovxjlz3ps9b.pdf %m664694f1c6e86f376e58c8a13435f570 %ccav %@Scott McPeak,George C. Necula %*Data Structure Specifications via Local Equality Axioms %f/cav/f30oszclkx1zna9v4colaiedfywhmpki.pdf %m9adddd69026cd8e147a1b5095f29b4c4 %ccav %@Aaron R. Bradley,Zohar Manna,Henny B. Sipma %*Linear Ranking with Reachability %f/cav/uopzs92ggccfupketafjlnq1atdo5hsj.pdf %mce716c89a81a5133c45bf5a32e5c1787 %ccav %@Vineet Kahlon,Franjo Ivančić,Aarti Gupta %*Reasoning About Threads Communicating via Locks %f/cav/zfnvxbhnwice3uyqyjoravgdetrpjka9.pdf %m944c238dc152e592c6633eddf520753c %ccav %@Alexey Loginov,Thomas Reps,Mooly Sagiv %*Abstraction Refinement via Inductive Learning %f/cav/1fwmbtxw3kygphfbaquzpvyan6lq024h.pdf %m8aef869034ab88d5b485ca31686dfb24 %ccav %@Sagar Chaki,Edmund Clarke,Nishant Sinha,Prasanna Thati %*Automated Assume-Guarantee Reasoning for Simulation Conformance %f/cav/na5glq1ezhvophwyp6fimeyxiccbdkx4.pdf %mdab72738ed99bba818b6464dc552f3d9 %ccav %@Rajeev Alur,P. Madhusudan,Wonhong Nam %*Symbolic Compositional Verification by Learning Assumptions %f/cav/y2ji4smsbmglc3qqbrphkvvoraf09pxi.pdf %m48779bd204235339124d75e65ebffca0 %ccav %@Bernard Boigelot,Patrice Godefroid %*Symbolic verification of communication protocols with infinite state spaces using QDDs %f/cav/tpc9xsbfwo7k8nyl6wnqvmghh5gzp1m0.pdf %m8342532147b9c26b20e90ba212bd04d0 %ccav %@George S. Avrunin %*Symbolic model checking using algebraic geometry %f/cav/k96gayiz3ompqlekbpgclqybdoxaj1c5.pdf %m49d1308d40c0d51153b2e9de13affe12 %ccav %@Marco Pistore,Davide Sangiorgi %*A partition refinement algorithm for the π-calculus %f/cav/ae65uiiqsnkts3ryvepc7wfnjalhb0w4.pdf %mbd5455e43cbf38bb4b8a118b11601b64 %ccav %@Christel Baier %*Polynomial time algorithms for testing probabilistic bisimulation and simulation %f/cav/ilzjkyhwqzs3ujx97qikofuvba245arb.pdf %mf7fd6cbe6d9da47cfe7e35a9d45a64ff %ccav %@Igor Walukiewicz %*Pushdown processes: Games and model checking %f/cav/o7elna9h4grk8ynisb5xgttfwrzz1dv2.pdf %md6e16a96d52bc675f606c88551436438 %ccav %@Orna Kupferman,Moshe Y. Vardi %*Module checking %f/cav/5tby9hkpwdjfxogtju8girqoanexss3c.pdf %m29ed9958243e8cb9273041e79efb73a8 %ccav %@E. Allen Emerson,Kedar S. Namjoshi %*Automatic verification of parameterized synchronous systems %f/cav/adfbzhxwoijv2btwoje1hsrg4cr7ynlk.pdf %m7f8db23eb05c7a657130fcdc0bcdd929 %ccav %@Sandeep K. Shukla,Harry B. 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Dill %*Verifying systems with replicated components in murϕ %f/cav/d8ienlh5epmcmbgw4iqfaoyuka2cbjzs.pdf %m48646f7874581de29db78b905b549582 %ccav %@Masahiro Fujita %*Verification of arithmetic circuits by comparing two similar circuits %f/cav/fiavrhrp9q8fdc0pjtbemjnbsmzowqit.pdf %mdf3660d8fbd6ab1b587adef9ece8a2dd %ccav %@John Rushby %*Automated deduction and formal methods %f/cav/4q6vrs7lgn2pw1ubrdziusecl0akotwh.pdf %mb459aa092d698faf6d4910732424ed14 %ccav %@Amir Pnueli,Elad Shahar %*A platform for combining deductive with algorithmic verification %f/cav/9nkevzuxenfs1qamii5bp0bpur6dw2lj.pdf %m01f89a3ca70d89387008574cb6c317e3 %ccav %@Susanne Graf,Hassen Saïdi %*Verifying invariants using theorem proving %f/cav/nbcqh7iryud0263tsjix5qztuenskb1f.pdf %m344b19eba42a9f574aa1404e46343a86 %ccav %@Henny B. Sipma,Tomás E. Uribe,Zohar Manna %*Deductive model checking %f/cav/sxzqal9stwzuo4e02l8byv1r6qheckig.pdf %m984cf27883d9974bf1982b52b48fde7f %ccav %@Narjes Berregeb,Adel Bouhoula,Michaël Rusinowitch %*Automated verification by induction with associative-commutative operators %f/cav/k5xymmharvsixv7o2r6znwuewsd14bjc.pdf %mcd323f3ea9e32cf0cd836967422892c3 %ccav %@S. Tripakis,S. Yovine %*Analysis of timed systems based on time-abstracting bisimulations %f/cav/dfa5wl9rb4zgymkfwvoqrd8aitgu7qxp.pdf %md4b53c8fec25f6fc47132b55f63c462b %ccav %@Johan Bengtsson,W. O. David Griffioen,Kåre J. Kristoffersen,Kim G. Larsen,Fredrik Larsson,Paul Pettersson,Wang Yi %*Verification of an Audio Protocol with bus collision using Uppaal %f/cav/egpowoikzyqtmxb3hsau2zciwr0jlrhp.pdf %m2c59c553a8c38dc463b2e5da98a6ac5c %ccav %@Sérgio Campos,Orna Grumberg %*Selective quantitative analysis and interval model checking: Verifying different facets of a system %f/cav/kw4zlqu2mv8lzgyahnextfceoix3nrhi.pdf %mb153848b34aa71c2f8d76ee462c88c3c %ccav %@Adnan Aziz,Kumud Sanwal,Vigyan Singhal,Robert Brayton %*Verifying continuous time Markov chains %f/cav/ftyikarub4xunlqvd10we327rpdzcgjb.pdf %mb01acc30044af93615eb9bd611a7b224 %ccav %@Mark R. Greenstreet %*Verifying safety properties of differential equations %f/cav/8ntzmlk4nozpygruqb75aw6her91ce3x.pdf %m78e912d03edbe35e724259f4465bbb86 %ccav %@Luca de Alfaro,Zohar Manna %*Temporal verification by diagram transformations %f/cav/6vfwyibpqlg23ayghri1unu89x5ofpjz.pdf %m0b724c2949c64cb964803d64ba6d96a3 %ccav %@Seungjoon Park,David L. Dill %*Protocol verification by aggregation of distributed transactions %f/cav/o28mdfwzbe4obs3ht70uql1tvpw5j9zq.pdf %m1f42276980a225a6acc6e650f57b0d3a %ccav %@E. Pascal Gribomont %*Atomicity refinement and trace reduction theorems %f/cav/orfmsiaga2kozcw4ebjk8rbcupydvhpi.pdf %mc2f71bca48e299d30c521158488b0e2b %ccav %@Saddek Bensalem,Yassine Lakhnech,Hassen Saidi %*Powerful techniques for the automatic generation of invariants %f/cav/fekr1xmaopz7r5ylisiqvwnahpj4gh2t.pdf %mfb065a7615f52e99ba386f9a130de493 %ccav %@Hillel Miller,Shmuel Katz %*Saving space by fully exploiting invisible transitions %f/cav/zny7a21qtdfstegxvw6vafuwkkm5304i.pdf %me0f8b107665ea2c56c3074a0caa18266 %ccav %@Jean -Claude Fernandez,Claude Jard,Thierry Jéron,César Viho %*Using on-the-fly verification techniques for the generation of test suites %f/cav/eliyaytz0rowhkpwj7obq3p9rctcixnq.pdf %mb7117fd6afe43c8370a417d88097e9be %ccav %@Rani Nelken,Nissim Francez %*Automatic translation of natural language system specifications into temporal logic %f/cav/8dsoeb3taxotyrxur567azciwvhz4hje.pdf %m7a40aec9ea2ab6ca3f1c04079c7332a6 %ccav %@Orna Kupferman,Moshe Y. Vardi %*Verification of fair transition systems %f/cav/j8reroftgdfu9u7z5ktpzsbbswjaaiix.pdf %m32e9a303881d5dbea78dba273be0e25b %ccav %@Gerard J. Holzmann,Doron Peled %*The state of Spin %f/cav/schkpzdmv6due0i19xws73tlq2orhwqt.pdf %ma25ed6af067cb2e2e114aff65bc0bad5 %ccav %@David L. Dill %*The Mur ϕ verification system %f/cav/4bygz3j7qsg5nulapn8lhd0kmwhe9wy1.pdf %ma397c87d5e98e37e1f12d5c2724a15ce %ccav %@Rance Cleaveland,Steve Sims %*The NCSU Concurrency Workbench %f/cav/miktkfsmvy3wlcjxf0cnz57quo4pnr92.pdf %mb87577d768c9baa760de5f134a63b8ec %ccav %@Rance Cleaveland,Philip M. Lewis,Scott A. Smolka,Oleg Sokolsky %*The Concurrency Factory: A development environment for concurrent systems %f/cav/aod927gt4kruljxvwsjqebizb6ppdev8.pdf %me929f15674bccd9543584116dc84e5c6 %ccav %@Duncan Clarke,Hanêne Ben-Abdallah,Insup Lee,Hong -Liang Xie,Oleg Sokolsky %*XVERSA: An integrated graphical and textual toolset for the specification and analysis of resource-bound real-time systems %f/cav/rjudkb6nb9pskevgpmnjtdwcxyx4a8ya.pdf %m2aeef7643b204bf3b5c25a018cf2fadb %ccav %@P. Merino,J. M. Troya %*EVP: Integration of FDTs for the analysis and verification of communication protocols %f/cav/zzsy1u74rjtxubgog2ncw9efhakmwjvn.pdf %m6b93ff8a98351448088bd63bb9ec02e3 %ccav %@S. Owre,S. Rajan,J. M. Rushby,N. Shankar,M. Srivas %*PVS: Combining specification, proof checking, and model checking %f/cav/bvphoarv4mzw6iwdgnq8tp5qae3xuleh.pdf %m5034bc19d03ce94922486f7b569d1d80 %ccav %@Nikolaj Bjørner,Anca Browne,Eddie Chang,Michael Colón,Arjun Kapur,Zohar Manna,Henny B. Sipma,Tomás E. Uribe %*STeP: Deductive-algorithmic verification of reactive and real-time systems %f/cav/bz6dnkxf34hacm1mkwditzljugwa0uqv.pdf %maea9ac6bb4a4271c10b64ddb0bb2d96e %ccav %@E. Clarke,K. McMillan,S. Campos,V. Hartonas-Garmhausen %*Symbolic model checking %f/cav/2a0pk1cptuqzqgjbxms9hlw4chgoausl.pdf %m9936034e4ce92d90f8c80c7bea4093fe %ccav %@Robert K. Brayton,Gary D. Hachtel,Alberto Sangiovanni-Vincentelli,Fabio Somenzi,Adnan Aziz,Szu -Tsung Cheng,Stephen Edwards,Sunil Khatri,Yuji Kukimoto,Abelardo Pardo,Shaz Qadeer,Rajeev K. Ranjan,Shaker Sarwary,Thomas R. Staple,Gitanjali Swamy,Tiziano Villa %*VIS: A system for verification and synthesis %f/cav/cahgjd8fekkaqiwcot3smxywqlzm10vr.pdf %m1d88a6a9671ba4992e7d316a9f9d4f90 %ccav %@K. D. Anon,N. Boulerice,E. Cerny,F. Corella,M. Langevin,X. Song,S. Tahar,Y. Xu,Z. Zhou %*MDG tools for the verification of RTL designs %f/cav/p0lamxfycdisfoueps8rqekqw3bdxz5g.pdf %mc9c5664fb87fe111dfe6f9135507e8e8 %ccav %@Jean -Claude Fernandez,Hubert Garavel,Alain Kerbrat,Laurent Mounier,Radu Mateescu,Mihaela Sighireanu %*CADP a protocol validation and verification toolbox %f/cav/c3onlr2d17mgchozbz8la6vvkw5pgsay.pdf %me92b5e9a175b0af0e18b3ffd77701485 %ccav %@Amar Bouali,Annie Ressouche,Valérie Roy,Robert de Simone %*The FC2TOOLS set %f/cav/vbwgi4unfs9oqdctzh5ml1p0zc2afyxx.pdf %m2a9b08291b17a3b844d1ac979d6878ab %ccav %@L. E. Moser,P. M. Melliar-Smith,Y. S. Ramakrishna,G. Kutty,L. K. Dillon %*The Real-Time Graphical Interval Logic toolset %f/cav/uf6uyxtm7wgjipw02ksqieyolezc9xm3.pdf %m555264acc261a38c4c58c5feaa8ab30b %ccav %@Bernhard Steffen,Tiziana Margaria,Andreas Claßen,Volker Braun %*The METAFrame'95 environment %f/cav/9topsjcbmdxaykdo4c5imuxelrlgbhei.pdf %m62cf79a3b58a9b7c68c02da680d9f8be %ccav %@Frank Koob,Markus Ullmann,Stefan Wittmann %*Verification Support Environment %f/cav/fbxfpoy86spvci0seqa5cxkgw7wuakhy.pdf %m1b3b4ca1b0620d1895908fa7a7b54c01 %ccav %@Dominique Ambroise,Brigitte Rozoy %*Marrella: A tool for simulation and verification %f/cav/g2ot7cmygxs4duko98kczfn6tlvalihw.pdf %m39e71f9f3275af8f3d2970d21fd0e77d %ccav %@Georges Gonthier %*Verifying the safety of a practical concurrent garbage collector %f/cav/mvvdnbwec28gzxhkuohrf1pldgyuyfir.pdf %m2059aeb226b28c5ab62efc6793c17450 %ccav %@Carla Capellmann,Ralph Demant,Farhad Fatahi-Vanani,Rafael Galvez-Estrada,Ulrich Nitsche,Peter Ochsenschläger %*Verification by behaviour abstraction %f/cav/ythrufanvueawlyiow04gk3jvsmdbxt2.pdf %m15934d9592715611ecfd2aef6d46af8e %ccav %@Randal E. Bryant %*Multipliers and dividers: Insights on arithmetic circuit verification (extended abstract) %f/cav/o5le8zdqybtshmvfjmrcpxajptiz6gf4.pdf %m5dafe09c4594bd9522402500e8eba5cd %ccav %@Jochen Bern,Christoph Meinel,Anna Slobodová %*Global rebuilding of OBDDs avoiding memory requirement maxima %f/cav/yzytiaw6jgsondlmnru2pl1rtmc8bhdb.pdf %m0da9f01ddaba959f71a1c93d50241ca2 %ccav %@Ashvin Dsouza,Bard Bloom %*Generating BDD models for process algebra terms %f/cav/in9gjqzfqoafrstchjvyg6dw4ku3upbc.pdf %m0d3d0bee6e48f3b2a1229899b7d72324 %ccav %@David A. Basin,Nils Klarlund %*Hardware verification using monadic second-order logic %f/cav/teqqmh0n6tdbclg4robwyxz9sjniufzu.pdf %m46de08af72a1a9e94686794e40ef0fda %ccav %@Bengt Jonsson,Lars Kempe %*Verifying safety properties of a class of infinite-state distributed algorithms %f/cav/6cornfq0wueikmahuw1bxh7sqp543ft2.pdf %mf22309d2ef1de3b642dcf08882dfd681 %ccav %@Jürgen Dingel,Thomas Filkorn %*Model checking for infinite state systems using data abstraction, assumption-commitment style reasoning and theorem proving %f/cav/9lwuxyvqetnxycm85i3v41hsf6bnohgp.pdf %m912023ce0e37555832248905b3dc517e %ccav %@E. Pascal Gribomont,Didier Rossetto %*CAVEAT: technique and tool for computer aided verification and transformation %f/cav/w8sfabcgmhs40912dl3ytz7zvihvxflu.pdf %md8933b21d6badbce0171b0f4633ab9a7 %ccav %@S. Rajan,N. Shankar,M. K. Srivas %*An integration of model checking with automated proof checking %f/cav/xnofvcby2hbqpmku0rw1hlssgrvjj7cu.pdf %ma6b021c1a0a68008778479bb664ddeb6 %ccav %@Ramin Hojati,Robert K. Brayton %*Automatic datapath abstraction in hardware systems %f/cav/lhv0qm8le2ujpg3zowzdkwxieqnp96k7.pdf %m58e31acc2018bb2acecf4453b331a4b5 %ccav %@Antoine Rauzy %*Toupie=μ-calculus+constraints %f/cav/fwxog7uuehvmjy92iwi5aqbcnlc6ap8q.pdf %ma857dd97010991992ff84d2fdacb7932 %ccav %@Lalita Jategaonkar Jagadeesan,Carlos Puchol,James E. Von Olnhausen %*Safety property verification of Esterel programs and applications to telecommunications software %f/cav/jcpvu6fdbk5qln2mehwr3al9roebyn8s.pdf %mc424c30483f50836fdd9588d64626250 %ccav %@E. A. Emerson %*Methods for Mu-calculus model checking: A tutorial %f/cav/fwkpudbrcikveiljz1lsjsh5tf74pbvr.pdf %m8c261edc70e3ef344080bbe88de150fe %ccav %@Henrik Reif Andersen,Bart Vergauwen %*Efficient checking of behavioural relations and modal assertions using fixed-point inversion %f/cav/d4khvmrym0aasdcbptoyce6qjwlbjilf.pdf %m6722db1269b2c4e1bb00c01fd8ce4bc4 %ccav %@Adnan Aziz,Vigyan Singhal,Felice Balarin,Robert K. Brayton,Alberto L. Sangiovanni-Vincentelli %*It usually works: The temporal logic of stochastic systems %f/cav/5eytz6qqjkv4lyurdzpgcc0bloa19kmw.pdf %m177fccca562a3b52685f606da358d218 %ccav %@Rajeev Alur,Thomas A. Henzinger %*Local liveness for compositional modeling of fair reactive systems %f/cav/pwhubstliypmetvx0nkwj8rvj3z9qukr.pdf %mc60b9e8bd8ffe5db569ba8cb878372e4 %ccav %@K. L. McMillan %*Trace theoretic verification of asynchronous circuits using unfoldings %f/cav/tc6xypdkbjv9vpa2rtuubewhn5ie4fqx.pdf %m94a57635c50a0a17758bae4f1a5615fe %ccav %@Ahmed Bouajjani,Yassine Lakhnech,Riadh Robbana %*From duration calculus to linear hybrid automata %f/cav/mjgcorwy18m6deas0bh7bfog5elpj3ci.pdf %m5a55cc7d3bd20654932745977621806d %ccav %@Oleg V. Sokolsky,Scott A. Smolka %*Local model checking for real-time systems %f/cav/xwijn29stkkuoqgpylogclytwqnafmb6.pdf %mc0c85d61b5c5518921927e1d45d1008c %ccav %@Thomas A. Henzinger,Pei -Hsin Ho %*Algorithmic analysis of nonlinear hybrid systems %f/cav/itmwfbymb8xl2iu3axraueznfvcjwr47.pdf %m8f843f35615d72fc414179131c0e51cb %ccav %@Helmut Lescow %*On polynomial-size programs winning finite-state games %f/cav/3b8frfdsw4zgo6mcneykt9xhs2mbicwz.pdf %m0fc09ac1e0eb8e39dc18e1c1f33affba %ccav %@Sriram C. Krishnan,Anuj Puri,Robert. K. Brayton,Pravin P. Varaiya %*The rabin index and chain automata, with applications to automata and games %f/cav/nhp4ycgbfqno3ytf50eabj2rvdmkqpsl.pdf %mc0ba183756a556c90a995ffa0a634bb9 %ccav %@Moshe Y. Vardi %*An automata-theoretic approach to fair realizability and synthesis %f/cav/bdbmgqv7txsom4qo5piwrcz9ep2u3fkw.pdf %m0c4ad92e663b94c8664f7bb0196af8ae %ccav %@A. Aziz,F. Balarin,R. K. Brayton,M. D. DiBenedetto,A. Saldanha,A. L. Sangiovanni-Vincentelli %*Supervisory control of finite state machines %f/cav/efntibvny7ckdschiom2opzwdutkzgge.pdf %m56430d771e0cbd36d158ea28f65f6cbb %ccav %@Patrick Cousot,Radhia Cousot %*Compositional and inductive semantic definitions in fixpoint, equational, constraint, closure-condition, rule-based and game-theoretic form %f/cav/rxva3agpqlzbypzcrd9o5qvjom60yhi4.pdf %m3e322e21fbaae3c76f5cfed1c9917bbb %ccav %@E. A. Emerson,A. P. Sistla %*Utilizing symmetry when model checking under fairness assumptions: An automata-theoretic approach %f/cav/ek4v56yqsn231bfoblhgeigrcwwp7z8o.pdf %m12338e0770921efba45865f0af9fa55a %ccav %@Orna Kupferman (Bernholtz) %*Augmenting branching temporal logics with existential quantification over atomic propositions %f/cav/ylwcf7yru6fje8hcownvtg1j4kpvss5n.pdf %m603c690f45a1350c7732c625ee5142f6 %ccav %@R. P. Kurshan,M. Merritt,A. Orda,S. R. Sachs %*Modelling asynchrony with a synchronous model %f/cav/1v0boxqf4pccum7t3kynjmt9rlihejiy.pdf %m9c72df4b9ee890e80e35173f649156d3 %ccav %@Javier Esparza,Astrid Kiehn %*On the model checking problem for branching time logics and basic parallel processes %f/cav/zya3lftvj70ikb2prnc49milwthcgafx.pdf %mc5d847a32e20aef6e336d7fdd8b7ea40 %ccav %@Ásgeir Th. Eiríksson,Ken L. McMillan %*Using formal verification/analysis methods on the critical path in system design: A case study %f/cav/dzrn5kb96zsfub3vanpgioytoc1fyhel.pdf %mb08cb4f2e22fe9d7440a4cf0b29b4aee %ccav %@Pei -Hsin Ho,Howard Wong-Toi %*Automated analysis of an audio control protocol %f/cav/fbwfylqzgwa9u8lqecmv2ktsmdv1ixrh.pdf %m92add2b9ef37622c33edba0b2a1ca1c2 %ccav %@Colin Fidge,Peter Kearney,Mark Utting %*Interactively verifying a simple real-time scheduler %f/cav/sj6lbf2vv0eyp1wumozczoputgks4nyi.pdf %m251a77b898c7981b26c70476476311b8 %ccav %@David L. Dill,Howard Wong-Toi %*Verification of real-time systems by successive over and under approximation %f/cav/51o69ahpozpwmijwqx7hal8mscjsndbf.pdf %m621910d42a472b1547423acbb6359346 %ccav %@Henrik Hulgaard,Steven M. Burns %*Efficient timing analysis of a class of Petri nets %f/cav/wlc2qtxgv8awciazgufn6prisqjkd59m.pdf %m9441c242eff2cac9f6d42f4a8b4653ee %ccav %@Ahmed Bouajjani,Riadh Robbana %*Verifying ω-regular properties for a subclass of linear hybrid systems %f/cav/ra062k7ufuyjaspsdznhqor8ie34xbwo.pdf %mfa4b00f45941d9cf056a6bad574df8a0 %ccav %@Rajeev Alur,Limor Fix,Thomas A. Henzinger %*A determinizable class of timed automata %f/cav/eshtxkjqurgekop5axjvltdfnfgd1b6i.pdf %ma44e9aedbd1b2ab0ef974c93ef1ddea4 %ccav %@Roberto Gorrieri,Glauco Siliprandi %*Real-time system verification using P/T nets %f/cav/qsvgmx87i31jcbhcpnrxzvtp4hgkdqwu.pdf %m69a55c24f1f5601d4e19e615f323ed81 %ccav %@William K. C. Lam,Robert K. Brayton %*Criteria for the simple path property in timed automata %f/cav/plzfqtqwjbfzhypooubyv7msg1mjcra3.pdf %m8b3be65b567040b7e751bdff9a322e1f %ccav %@K. L. McMillan %*Hierarchical representations of discrete functions, with application to model checking %f/cav/hkiru5jj6941oga0yrl3vavptxbp8nwe.pdf %m686c783d5ed4c1b48c1a23d0417194da %ccav %@Bernard Boigelot,Pierre Wolper %*Symbolic verification with periodic sets %f/cav/xprnfp7bsgclhyig3u5q2kxtn1wz0mqm.pdf %m6d4c6c0916ae64a3d422464f245a2883 %ccav %@Jerry R. Burch,David L. Dill %*Automatic verification of pipelined microprocessor control %f/cav/d7psmvo9w6scw3euam2czhk5ttl1uqff.pdf %m20b6a688719923253ec786c69a33afe1 %ccav %@A. Olivero,J. Sifakis,S. Yovine %*Using abstractions for the verification of linear hybrid systems %f/cav/lbesz0aylb1jimzddiw76kugfoy2fmph.pdf %m62b425b1bf13faaa9c4f2443ad5b152b %ccav %@Anuj Puri,Pravin Varaiya %*Decidability of hybrid systems with rectangular differential inclusions %f/cav/db2fogls3l0auqfknjw6h5npvugsmxee.pdf %mc3e12ef5143541cfce56ffefa3dfdd93 %ccav %@Jennifer McManis,Pravin Varaiya %*Suspension automata: A decidable class of hybrid automata %f/cav/mjnkvsacrkbljuto1dwewy9iqucrtpqh.pdf %m276a19a1dd318f31bf15572bfef461ae %ccav %@Ahmed Bouajjani,Rachid Echahed,Riadh Robbana %*Verification of context-free timed systems using linear hybrid observers %f/cav/5cbo30dnlfzgd29lrvt6xjimpm1qazf4.pdf %m2bc6a67e65650d1e696c8105b79a2417 %ccav %@Milena Mihail,Christos H. Papadimitriou %*On the random walk method for protocol testing %f/cav/dnokhw4yetix1fcqxnlmgmw9g6ds3jr2.pdf %m4cf3ebe10c22661a37b27e16497914db %ccav %@Orna Bernholtz,Moshe Y. Vardi,Pierre Wolper %*An automata-theoretic approach to branching-time model checking (Extended abstract) %f/cav/mnqoesjgwra64jctdpnb5bmzkgeuxyvh.pdf %m7d33e5d4e76ee0969dd8580bfce11676 %ccav %@Anuchit Anuchitanukul,Zohar Manna %*Realizability and synthesis of reactive modules %f/cav/tg0i4hccgv6mirzkvx3o9awjym5lnbaj.pdf %mb1a142c5f916c44eafc0230919d6fa02 %ccav %@Hardi Hungar %*Model checking of macro processes %f/cav/vzj7tsx9i4q2cdxmsilwbh8breovzduo.pdf %m70f2535fe8ce55354fb7d24e819bf9e1 %ccav %@Ilan Beer,Shoham Ben-David,Daniel Geist,Raanan Gewirtzman,Michael Yoeli %*Methodology and system for practical formal verification of reactive hardware %f/cav/rfr6kahvjcmsykbiugnyduefiqmvpebl.pdf %m3c1e5171b75d4f84bdd6fdbc96db55d8 %ccav %@Vivek G. Naik,A. P. Sistla %*Modeling and verification of a real life protocol using symbolic model checking %f/cav/moalhjv7k95u4jwhyncprc63qgydxssx.pdf %mf4906826411d6c5a400093153599d908 %ccav %@Susanne Graf %*Verification of a distributed cache memory by using abstractions %f/cav/no7ht4xozesr9wkwbaeiy5zv1dfa6vqf.pdf %mdca263b003e0d4dc2288b3c06b96f9b7 %ccav %@Zohar Manna %*Beyond model checking %f/cav/qi8l6ugvmdt1sbmfrcqzcwe4f90pgrba.pdf %m1093b1670b5cb183ee4f01825131c3bf %ccav %@R. P. Kurshan %*Models whose checks don't explode %f/cav/6fklea0qnbdj8ihhvrczcgiurawos5tm.pdf %m70575a0d1b066f2cb7f89039c6e5b38b %ccav %@Felice Balarin,Alberto L. Sangiovanni-Vincentelli %*On the automatic computation of network invariants %f/cav/m2k4utynegkwmalrozhvi9siyh8qwva5.pdf %mc32961dd979a7b68c7cbf0b4757aeca0 %ccav %@David Cyrluk,Paliath Narendran %*Ground temporal logic: A logic for hardware verification %f/cav/zcf6iloaxjlprjobvgkpq35ekchdryxb.pdf %m1680b4753c6abbe454c5f321cc98127c %ccav %@E. Thomas Schubert %*A hybrid model for reasoning about composed hardware systems %f/cav/4z07fncngyuv8kzr6qfc5rj1uapomoms.pdf %m7af1c03bac045c67bd1053c5568c94f0 %ccav %@Scott Hazelhurst,Carl-Johan H. Seger %*Composing symbolic trajectory evaluation results %f/cav/hvqbrizgl1ork0fhnotuj4zwyda5yx26.pdf %m794c30f30123fd2d6226c5eb3380e3ac %ccav %@Zheng Zhu,C-J Seger %*The completeness of a hardware inference system %f/cav/1qipzbsvcrya32yad4hsmxnfhidg0jt5.pdf %m39b52ac920c5df180fba14a8d80cc975 %ccav %@Daniel Geist,Ilan Beer %*Efficient model checking by automated ordering of transition relation partitions %f/cav/rzymtckon2c09jeluqguvbaydlmnwf4x.pdf %mcbb6543ac85b50015774b2992e88a1f1 %ccav %@Vigyan Singhal,Carl Pixley %*The verification problem for safe replaceability %f/cav/fv7vcy8jqryahuse1czmsp5bm40nlprt.pdf %m16fca2434461d0e1cfb070a0281329a6 %ccav %@Adnan Aziz,Thomas R. Shiple,Vigyan Singhal,Alberto L. Sangiovanni-Vincentelli %*Formula-dependent equivalence for compositional CTL model checking %f/cav/48elsiunmizxmc59nbkp0ar2ov1crqjw.pdf %mb4317b9b6b1c121fe50bff922d210c6f %ccav %@David E. Long,Anca Browne,Edmund M. Clarke,Somesh Jha,Wilfredo R. Marrero %*An improved algorithm for the evaluation of fixpoint expressions %f/cav/wfmg3s2yubepkdhvq09lew4ca7yno8pr.pdf %m4c7963aec4fa752b0c3850e1057a1f4e %ccav %@Oleg V. Sokolsky,Scott A. Smolka %*Incremental model checking in the modal mu-calculus %f/cav/1fn5gmnajcz6dtdeyqufvlwrkwxh3j49.pdf %m0f8d60bef49b3c3326c2a8233b10c453 %ccav %@Bernard Cousin,Jean-michel Hélary %*Performance improvement of state space exploration by regular & differential hashing functions %f/cav/pc9yheiyuafnhqlrjr4ns6zdfslpdmxx.pdf %maaeaedf76333efeb3d7af79acbd02539 %ccav %@Doron Peled %*Combining partial order reductions with on-the-fly model-checking %f/cav/lu6qftkj9wiblzxqknef1vovg0ganxiz.pdf %mc0de31cf860b034ceae8225d8a6ebfb8 %ccav %@Ramin Hojati,Robert Mueller-Thuns,Robert K. Brayton %*Improving language containment using fairness graphs %f/cav/1mbvjzg0hxyedmulbsuhf5pjrcv8iled.pdf %m2a89e49db6ed1afd74209e493aeb3c69 %ccav %@Insup Lee,S. Rajasekaran %*A parallel algorithm for relational coarsest partition problems and its implementation %f/cav/r9boa35t8nh4losufkqaudvylxtwkfbm.pdf %m5b424d20165c9a6ef226166f975d69c2 %ccav %@E. Clarke,O. Grumberg,K. Hamaguchi %*Another look at LTL model checking %f/cav/fkv4pdbrqicmplnb9j0gua16smd7otxy.pdf %m5b48c3e63925969d14f1c6ae184cc8b7 %ccav %@Björn Victor,Faron Moller %*The mobility workbench — A tool for the π-Calculus %f/cav/2rmslblvertixehwdcf6qgxyuj7acw9z.pdf %mf48edd9abb4a3825352768dae8069ad3 %ccav %@R. de Simone,A. Ressouche %*Compositional semantics of Esterel and verification by compositional reductions %f/cav/ywclubvwlhzakmdstemrozh4p5jfsq8c.pdf %mbc2bcab0d825df3f70d1063f89b856dc %ccav %@Dennis Dams,Rob Gerth,Gert Döhmen,Ronald Herrmann,Peter Kelb,Hergen Pargmann %*Model checking using adaptive state and data abstraction %f/cav/enwdyrtxb0pca6zjlz5li72kfdgyktse.pdf %m942b5582e630d30683d88207d329eb97 %ccav %@Tomas G. Rokicki,Chris J. Myers %*Automatic verification of timed circuits %f/cav/j1suqwtfkfalv9u4xiznb07lgvw28eqg.pdf %m66c2da3216da795681ca889e4d54adcb %ccav %@Robert K. Brayton %*Logic synthesis and design verification %f/cav/vhfhpaa0rt8qq6bfizxd54oxtw2njgc3.pdf %mec2123a1dcf5dd35eb87511869671a31 %ccav %@Alan J. Hu,David L. Dill %*Efficient verification with BDDs using implicitly conjoined invariants %f/cav/cw0enabryojhbyvj1z36qskpnmlquacw.pdf %md0927fbf76d4217a2d07b1050420c001 %ccav %@Aarti Gupta,Allan L. Fisher %*Parametric circuit representation using inductive Boolean functions %f/cav/tfwqf7hzg6scp3qvtus1pimnzka9c2ye.pdf %mc41eabb99d6c18a4df7947f18378345c %ccav %@Felice Balarin,Alberto L. Sangiovanni-Vincentelli %*An iterative approach to language containment %f/cav/rsqzpl0naekitnsbye9vm5waotulx81j.pdf %m019d9792b67f67a9605c9f6563b2e891 %ccav %@Ramin Hojati,Robert K. Brayton,Robert P. Kurshan %*BDD-Based debugging of designs using language containment and fair CTL %f/cav/yl9gfxur4pphqonka702stdbvwelyefz.pdf %mff57dd2270bdd5df371716f33a89219f %ccav %@Pierre Wolper,Denis Leroy %*Reliable hashing without collision detection %f/cav/jmevki4gzfl86uqyoxvmpsaicp3rty9k.pdf %mfd3ee7bb8bd786325fb49d344db89675 %ccav %@Susanne Graf,Claire Loiseaux %*A tool for symbolic program verification and abstraction %f/cav/p7iapiv2l8j4n3xyajbhzhrduuqegkdc.pdf %m26e987d0680d32116d61cec60258211c %ccav %@J. C. Fernandez,A. Kerbrat,L. Mounier %*Symbolic equivalence checking %f/cav/p8yxki1hudjmlkbtiyz4t3neuapqed0x.pdf %mf8d57a2a13679d4eb3e94896571d02b9 %ccav %@Y. Kesten,Z. Manna,H. McGuire,A. Pnueli %*A decision algorithm for full propositional temporal logic %f/cav/tl1ngovojdquq4a2zw7hef8rcxh0cldb.pdf %m53fbf956d4131fd06c5507c9b69fdd25 %ccav %@A. S. Krishnakumar %*Reachability and recurrence in Extended Finite State Machines: Modular Vector Addition Systems %f/cav/g1sci2tpkiw5kzjmw0eqfyduquxrthrg.pdf %mb9aadd9b6178d57b456dfa64e52db307 %ccav %@June-Kyung Rho,Fabio Somenzi %*Automatic generation of network invariants for the verification of iterative sequential systems %f/cav/dkamxlyuxwkseajvudlgbhyqiz4ncvnf.pdf %m417e72d458b795cb2a2c12027d172ecf %ccav %@G. Kutty,Y. S. Ramakrishna,L. E. Moser,L. K. Dillon,P. M. Melliar-Smith %*A Graphical Interval Logic toolset for verifying concurrent systems %f/cav/gyvidesrc9o6tzjl2taskpqhofiju04p.pdf %m12f953483a282fc45e9498f81f54c091 %ccav %@Hardi Hungar %*Combining model checking and theorem proving to verify parallel processes %f/cav/khhgtolqjrtnams45xjfu9g3ycrizfxe.pdf %m88dc7367a7d8f8797445bbb571e19dbd %ccav %@R. P. Kurshan,Leslie Lamport %*Verification of a multiplier: 64 bits and beyond %f/cav/upwhjgiekx3pflmzolvvqt2nu6hcqsyi.pdf %mfda035261265ee89d80c14da2395879c %ccav %@Pravin Varaiya %*Protocol design for an automated highway system %f/cav/ifvn4b9smxdaglz7tgoxnij5uqfsapyk.pdf %mf127e103be77d61319904a0379f288bb %ccav %@Rajeev Alur,Costas Courcoubetis,Thomas A. Henzinger %*Computing accumulated delays in real-time systems %f/cav/nhbmaso3jpnvkp5z1aitjweuwer8fz9g.pdf %mc832f3d072691f3130864ecc65caf3f3 %ccav %@Oded Maler,Amir Pnueli %*Reachability analysis of planar multi-linear systems %f/cav/nfvkvato6himreylqclpdpgtfnbrbchu.pdf %mb0e20f71531db79e25224a602f79e9af %ccav %@Mihalis Yannakakis,David Lee %*An efficient algorithm for minimizing real-time transition systems %f/cav/xfhrizqq54falwwri76gdbc12hpubmet.pdf %m8c0fa65370283a5c618be0f10bea3fea %ccav %@Costas Courcoubetis,Werner Damm,Bernhard Josko %*Verification of timing properties of VHDL %f/cav/6z4c9rzkeqtprj5audplsthnqhynbsmw.pdf %mea6e0fecf62de6cc280a2c8c863b9a37 %ccav %@William K. C. Lam,Robert K. Brayton %*Alternating RQ timed automata %f/cav/o4nawx8wgpj3u5ykpdvytqmrjflhide9.pdf %m9ed46baa8945bba1310ea7a3a13427b3 %ccav %@Kārlis Čerāns,Jens Chr. Godskesen,Kim G. Larsen %*Timed modal specification — Theory and tools %f/cav/8itygp9gvuqcyk5jadobnonvrzmjtsk1.pdf %mc4f980e6b9ad442d178934093fe9776f %ccav %@Matthew Wilding %*A mechanically verified application for a mechanically verified environment %f/cav/i5uldntzafhzmrpw68xdqxbmgbygqklo.pdf %mf5d1eac789d0f61f3d1f41ed918e851f %ccav %@N. Shankar %*Verification of real-time systems using PVS %f/cav/pqwrkb8azh4xlq716xwyd2mns3ggecsf.pdf %m8a4f9ee3859ff0d7da62959412715314 %ccav %@Patrick Lincoln,John Rushby %*The formal verification of an algorithm for interactive consistency under a hybrid fault model %f/cav/zngd7v80imk6asxpzqsyfvclyhok2uwh.pdf %mb831a27ce4dfb03bdb1b130515bd7f1b %ccav %@Jørgen F. Søgaard-Andersen,Stephen J. Garland,John V. Guttag,Nancy A. Lynch,Anna Pogosyants %*Computer-assisted simulation proofs %f/cav/mfvqhdlxta86a1owjtukgr2pczmixg7h.pdf %m0e8dd316bea964d9648a122cf6c833c1 %ccav %@M. J. C. Gordon %*A verifier and timing analyser for simple imperative programs %f/cav/fi2tmqwngs1okbmhwsroh7vzcdvgy3jz.pdf %meb19d2124be1f3b94de83355403c50f8 %ccav %@Tomohiro Yoneda,Atsufumi Shibayama,Bernd-Holger Schlingloff,Edmund M. Clarke %*Efficient verification of parallel real-time systems %f/cav/hafuzyg0pwl26jiv4txhmyvbue9dkgxc.pdf %m665b0bd81b4b8ba2edbe4595879103ce %ccav %@Nicolas Halbwachs %*Delay analysis in synchronous programs %f/cav/gd8ftkoslwrhziisqe90nzql4jmyovvr.pdf %mc43d7cb21c9aacf494cfaff66026bf57 %ccav %@M. Jourdan,F. Maraninchi,A. Olivero %*Verifying quantitative real-time properties of synchronous programs %f/cav/mxvjtzle1gagxduhtk03bfibqo9wes87.pdf %mec0f115daa8ce0b3dfa21ed6576fe517 %ccav %@M. Hennessy,X. Liu %*A modal logic for message passing processes %f/cav/oifqu3myslgt5jiajfu8mnb0hc7sz6dn.pdf %m96966c2012cf6669e72c31841a6147f3 %ccav %@Ed Brinksma,Rom Langerak,Peter Broekroelofs %*Functionality decomposition by compositional correctness preserving transformation %f/cav/94m0tjsjwzdorgfcxiophulfiw83qzur.pdf %mf32964370e23744dfba320e82981fd17 %ccav %@E. A. Emerson,C. S. Jutla,A. P. Sistla %*On model-checking for fragments of μ-calculus %f/cav/uamn2xrcqfxs8bhrdcovju4yik0ilgbo.pdf %med1929408357400b05d0909d41110b47 %ccav %@Antti Valmari %*On-the-fly verification with stubborn sets %f/cav/ibn7pbu6euvegyrjm5vddi4fflhwoo1c.pdf %m8f0cb8f4a260b166779bdb9186e2316d %ccav %@Doron Peled %*All from one, one for all: on model checking using representatives %f/cav/sagfhdhopuozc43fsux8xlpw19ndwckr.pdf %m74657db12001aa19efef4737997ed7d3 %ccav %@David K. Probst,Hon F. Li %*Verifying timed behavior automata with input/output critical races %f/cav/y5yebuizdpczfmgx0j6pgjchkndqonut.pdf %md7c190adcf9bf2a64c2de9105bf5ceb1 %ccav %@Patrice Godefroid,Didier Pirottin %*Refining dependencies improves partial-order verification methods (extended abstract) %f/cav/edhwtvoqv41smw5aiqx0rbo6xgg379yy.pdf %m53631ca1cd911f5d9b2e7151cf9179ca %ccav %@E. M. Clarke,T. Filkorn,S. Jha %*Exploiting symmetry in temporal logic model checking %f/cav/q3klpgxixfeao9ejgnpyctz1c4b8av25.pdf %m922ff871b8e64d40321ade9bf2063370 %ccav %@E. Allen Emerson,A. Prasad Sistla %*Symmetry and model checking %f/cav/rcyljonqp1za0szid4b3chugbmxqhdwp.pdf %me5e234be138a48d991fa79fb967e83e2 %ccav %@Dennis Dams,Orna Grumberg,Rob Gerth %*Generation of reduced models for checking fragments of CTL %f/cav/tldtlsgfy0zmre93uaaqf1kizdksrjwq.pdf %m0164ed13c6f2b8b638a059de35252191 %ccav %@R. P. Kurshan,M. Merritt,A. Orda,S. R. Sachs %*A Structural linearization principle for processes %f/cav/gr7a3ygi502jqfnyefxujvdrvbtop1lc.pdf %m7a8eee424d4774e09a264d449248c37c %ccav %@Leslie Lamport %*Computer-hindered verification (humans can do it too) %f/cav/j5tmywsaza76kxv0fh9ldk8ofcplered.pdf %mb59078cbcc0919bca86e30a8beb4331c %ccav %@Hana De-Leon,Orna Grumberg %*Modular abstractions for verifying real-time distributed systems %f/cav/a2dxveywrjbmh35zzt4b90fcntkd7yss.pdf %m81e5a5caace63f19508727e8c809fd2e %ccav %@Mannes Poel,Job Zwiers %*Layering techniques for development of parallel systems %f/cav/27zkex0iscrfbpjdgatymgl9v1aswkuq.pdf %m6b02e34890c5ae1a38fcc7c42af10f2c %ccav %@Kim Guldstrand Larsen %*Efficient local correctness checking %f/cav/wsuhzjcsxq7rpnkywedl38fa1n2ozqyj.pdf %m69367447dc4ba199745dbbea47f016f3 %ccav %@Urban Engberg,Peter Grønning,Leslie Lamport %*Mechanical verification of concurrent systems with TLA %f/cav/qxw3icl57cpgmj4bzuals2o0teaybv6y.pdf %m15794d7a5ae5ec8d7f75a5ffdbee2171 %ccav %@Joakim von Wright,Thomas Långbacka %*Using a theorem prover for reasoning about concurrent algorithms %f/cav/zo5dkvwlgq0vpbxx1wrusknyad9azhjq.pdf %mba39930ba7536642af1f29e7132856b1 %ccav %@Mark Aagaard,Miriam Leeser %*Verifying a logic synthesis tool in Nuprl: A case study in software verification %f/cav/dwjezjdguz7mc5n4cepor9qxkhfiiakw.pdf %mc0ee967b0aafaf189b546204d6128764 %ccav %@Alan J. Hu,David L. Dill,Andreas J. Drexler,C. Han Yang %*Higher-level specification and verification with BDDs %f/cav/8zmvprzg02sbeaa5jmiw4iuqn3lfdkog.pdf %ma9a28aebf4233d7809b0b29cb81a2166 %ccav %@Amar Bouali,Robert de Simone %*Symbolic bisimulation minimisation %f/cav/wtuxkzegrlunc5n9gdkih4mara1qvyiy.pdf %m2e93f0cedb123cf84ef4bc5ea663abf0 %ccav %@Prabhat Jain,Prabhakar Kudva,Ganesh Gopalakrishnan %*Towards a verification technique for large synchronous circuits %f/cav/ukts2eqh9rxzicjlrvcv8gjofn5xko31.pdf %mf39f5e5953671e877f6036dea2ccded3 %ccav %@David K. Probst,Hon F. Li %*Verifying timed behavior automata with nonbinary delay constraints %f/cav/7jslugctz9vbgr4j6ep5qofandtrmln1.pdf %mfc6edf0f26847571ac35c095908032ce %ccav %@R. Alur,A. Itai,R. Kurshan,M. Yannakakis %*Timing verification by successive approximation %f/cav/jz3tora0hoeaivcbdy4sh75ptkqgwupu.pdf %maf2da8ad158c5d55408fc221f1ed09ab %ccav %@Felice Balarin,Alberto L. Sangiovanni-Vincentelli %*A verification strategy for timing constrained systems %f/cav/podqmcark9shywxg0d5qthogeulcjiwn.pdf %m58fbc4f3b65d52bfecc94ab2ba3bf66b %ccav %@K. L. McMillan %*Using unfoldings to avoid the state explosion problem in the verification of asynchronous circuits %f/cav/zcq2eizo3od5lpdjek6vivu7x9s4xwly.pdf %m3f11e5dd87f0bf33dbf37039157949f0 %ccav %@Patrice Godefroid,Gerard J. Holzmann,Didier Pirottin %*State space caching revisited %f/cav/uytmwszq4ipdlxvrktb9ekgnoc0c2hig.pdf %m91817335df675a63850d8dc9bea91fa1 %ccav %@Siegfried Fischer,Andreas Scholz,Dirk Taubner %*Verification in process algebra of the distributed control of track vehicles—A case study %f/cav/jqvoy1cbger9dhsm6ud5maktv7wn8qfw.pdf %mb37b6ec47e943f77c046f660cb977a6b %ccav %@Kiyoharu Hamaguchi,Hiromi Hiraishi,Shuzo Yajima %*Design verification of a microprocessor using branching time regular temporal logic %f/cav/ya3l45ybouz0tcq6dggxecswv1kfmerf.pdf %m5e3795c547c2f36bb73280c3590b5f0a %ccav %@Glenn Bruns %*A case study in safety-critical design %f/cav/v9dw6hxf32bzuaqzqklmr0nkvxjat1s8.pdf %m5cfc03d634a3f8108df413f7ac6408c4 %ccav %@Thomas R. Shiple,Massimiliano Chiodo,Alberto L. Sangiovanni-Vincentelli,Robert K. Brayton %*Automatic reduction in CTL compositional model checking %f/cav/4tdfmnygiwqpv8xz5gpbu71k3efurkhc.pdf %m66a7266d9769fe9eb178a2ab94aeecb4 %ccav %@Roope Kaivola %*Compositional model checking for linear-time temporal logic %f/cav/s1tdwfpty3q7bhslveu8agzxorq9iwng.pdf %m014a5433235263938a70f6cf756c2b77 %ccav %@S. Bensalem,A. Bouajjani,C. Loiseaux,J. Sifakis %*Property preserving simulations %f/cav/ykobxcmaltpgfjljp4kzz6eo10dyxu2i.pdf %me54203ab76b4c5ec597bfa4ff2743c31 %ccav %@C. Courcoubetis,D. Dill,M. Chatzaki,P. Tzounakis %*Verification with real-time COSPAN %f/cav/50pgjwz3fcpqkq1nscdyihmvofltkb2i.pdf %mb977d6687f1adeb18c5f7af857b45445 %ccav %@N. Rico,G. v. Bochmann,O. Cherkaoui %*Model-checking for real-time systems specified in Lotos %f/cav/m1tsapq5alk7wvzxcr8nhokzrcl2ybgy.pdf %m521e34f291260bf43f4081deb7ffefbe %ccav %@Kārlis Čerāns %*Decidability of bisimulation equivalences for parallel timer processes %f/cav/znej9fv8xxlyh0wsd7wlokt4jqeifv36.pdf %m17fe6a397aeb1a09204e1352fd7496c6 %ccav %@J. C. Bradfield %*A proof assistant for symbolic model-checking %f/cav/ua6q2dcrcypvishlsoezzmh7tmrufiyo.pdf %m7e798cf0d5a391816ceef3519c2f6773 %ccav %@Angelika Mader %*Tableau recycling %f/cav/edfk25plc8nsm6wxhd1iyvcqnahbxuob.pdf %m070373f93086896439a20301bf24bd6a %ccav %@Dominique Méry,Abdelillah Mokkedem %*Crocos: An integrated environment for interactive verification of SDL specifications %f/cav/86binz4tccl0bijmszsdf5qqoh73k1fm.pdf %m41c498425418567d9e359fc443b36025 %ccav %@James C. Corbett %*Verifying general safety and liveness properties with integer programming %f/cav/anihblgcj0p6dzzvxmu5eoxnqwo4yukh.pdf %m7958c22883f77373ab81ace6a3931e9c %ccav %@Ufuk Celikkan,Ranee Cleaveland %*Generating diagnostic information for behavioral preorders %f/cav/wwoj6iu24da9ynhdxfgvumc0rkzsltgl.pdf %mbf72f9b1121023cc3b804976a72524ee %ccav %@Masahiro Higuchi,Osamu Shirakawa,Hiroyuki Seki,Mamoru Fujii,Tadao Kasami %*A verification procedure via invariant for extended communicating finite-state machines %f/cav/jav1nrpc8uz0iqxsrtycqfglvydefoo9.pdf %m5dea879b47ada3bb8294b76f19a14627 %ccav %@Ramin Hojati,Herve Touati,Robert P. Kurshan,Robert K. Brayton %*Efficient ω-regular language containment %f/cav/kpa1qtwym29zopn4bke3srjxil6mbhgx.pdf %mdae18ca8cfd95b462393d9544e46d2d9 %ccav %@Ranee Cleaveland,Marion Klein,Bernhard Steffen %*Faster model checking for the modal Mu-Calculus %f/cav/nkoirinmkxbajgcx91jheowswdcz7qys.pdf %m6c8f3d8f8eee9f56ebbaae938fa558b4 %ccav %@Colin Sterling %*Taming infinite state spaces %f/cav/ucqpnxvdjwomatfie4cbu61qmzzkyyrh.pdf %md3168ad46c0a5bdac1dcd8f88fc1ce87 %ccav %@Hans Hüttel %*Silence is golden: Branching bisimilarity is decidable for context-free processes %f/cav/tpfdpweunav4qiilolhykck7g9ofzmyj.pdf %mdf08dc192d3644adcf1edbc2165e362b %ccav %@Henri Korver %*Computing distinguishing formulas for branching bisimulation %f/cav/wka6iqic3tugm4fdpms815vkz9fyhjpz.pdf %ma39b75373255a26e0e4b9611559822f7 %ccav %@Henrik Reif Andersen,Glynn Winskel %*Compositional checking of satisfaction %f/cav/dvyx6mq2zhxuhriiqovwtks8sflbdjcy.pdf %m2050beb0d97aad8bab3bdff0fb9f8d19 %ccav %@R. De Nicola,A. Fantechi,S. Gnesi,G. Ristori %*An action based framework for verifying logical and behavioural properties of concurrent systems %f/cav/bgcwk6pmevgsiuohvxfqa8ymjpten5wc.pdf %m0b6991be4f75034b8c01a56f58b42805 %ccav %@Ranee Cleaveland,Bernhard Steffen %*A linear-time model-checking algorithm for the alternation-free modal mu-calculus %f/cav/3gj7dno4x1zwa5boglxp0mmebrj2qkh8.pdf %mbf384a0e7acc53659b99e73149773d60 %ccav %@A. Prasad Sistla,Lenore D. Zuck %*Automatic temporal verification of buffer systems %f/cav/nqekwj70vcse81lvmphdpbirugut2lky.pdf %m7e59993c3c3aaa38cac5b53e3bae3d5a %ccav %@William R. Bevier,JØrgen F. SØgaard-Andersen %*Mechanically checked proofs of kernel specifications %f/cav/g3hx92yblya6zoqdeutmkb7vtzspj8dj.pdf %me646aa68f09842ae89261762b82b05d6 %ccav %@Stein Gjessing,Stein Krogdahl,Ellen Munthe-Kaas %*A top down approach to the formal specification of SCI cache coherence %f/cav/1tbjkrhlcu0v7xel9zrm256agnxtoihf.pdf %mdee80711074729bb33fdd46baf6cf98e %ccav %@George S. Avrunin,Ugo A. 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%uhttp://dl.acm.org/ft_gateway.cfm?id=2516652&type=pdf %f/ccs/nx6wch0t1j5rlvj3utb2yovpzansxwlp.pdf %m455f10be78c890b7b4e27d57699c6d93 %cccs %@Bana, Gergei, Hasebe, Koji, Okada, Mitsuhir %*Computationally complete symbolic attacker and key exchange %uhttp://dl.acm.org/ft_gateway.cfm?id=2516710&type=pdf %f/ccs/vu8zes1wwkjrzq6f0oibgdr79apmftdy.pdf %m79c302b9a822bd653942eeca3ed0dc11 %cccs %@Barthe, Gilles, Crespo, Juan Manuel, Grégoire, Benjamin, Kunz, César, Lakhnech, Yassine, Schmidt, Benedikt, Zanella-Béguelin, Santiag %*Fully automated analysis of padding-based encryption in the computational model %uhttp://dl.acm.org/ft_gateway.cfm?id=2516663&type=pdf %f/ccs/n4szkru8lgczbw5piauhfhoxtpjidyql.pdf %ma3b0b6814ebe4f57c50476a96673eb04 %cccs %@Böhl, Florian, Cortier, Véronique, Warinschi, Bogda %*Deduction soundness: prove one, get five for free %uhttp://dl.acm.org/ft_gateway.cfm?id=2516711&type=pdf %f/ccs/oyaimyuab6fdkdupwzqeizw03xls2vph.pdf %mf609bb17a703c9aee90810ff0919c5c2 %cccs %@Cairns, Kelsey, Gamage, Thoshitha, Hauser, Car %*Efficient targeted key subset retrieval in fractal hash sequences %uhttp://dl.acm.org/ft_gateway.cfm?id=2516739&type=pdf %f/ccs/rslz6ovprdnimtz9kwvhse8i24x1yfkb.pdf %mc7e332969923c3cdc75d4845ee26ec16 %cccs %@Bajaj, Sumeet, Sion, Rad %*HIFS: history independence for file systems %uhttp://dl.acm.org/ft_gateway.cfm?id=2516724&type=pdf %f/ccs/4l6kzzu9wnbtcpmnxo8j3wuhoesdabgj.pdf %mc5b9064aa2422113ca2124297a11203c %cccs %@Tople, Shruti, Shinde, Shweta, Chen, Zhaofeng, Saxena, Pratee %*AUTOCRYPT: enabling homomorphic computation on servers to protect sensitive web content %uhttp://dl.acm.org/ft_gateway.cfm?id=2516666&type=pdf %f/ccs/2fzkgy5jm6jyukplrhvxxwvafsut41s3.pdf %m5802aadfaa2b3905ed2fb42b028c3add %cccs %@Dong, Xinshu, Chen, Zhaofeng, Siadati, Hossein, Tople, Shruti, Saxena, Prateek, Liang, Zhenka %*Protecting sensitive web content from client-side vulnerabilities with CRYPTONS %uhttp://dl.acm.org/ft_gateway.cfm?id=2516743&type=pdf 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verification systems based on handwritten signature %uhttp://dl.acm.org/ft_gateway.cfm?id=2512497&type=pdf %f/ccs/p4nl0qthaxsq9bv8rzufclg2yvzk6oku.pdf %m69b3b0a70719a161c54d279b1ec2d347 %cccs %@Shukla, Manish, Radadia, Purushotam, Karande, Shirish Subhash, Lodha, Sachi %*DEMO: On the real-time masking of the sound of credit cards using hot patching %uhttp://dl.acm.org/ft_gateway.cfm?id=2512498&type=pdf %f/ccs/ch5ep6wnhtkpnstsciqezym8vf7j3b4a.pdf %m4a04cb30aa7b1124ef1114f3ec58dfc5 %cccs %@Neuhaus, Stephan, Gheorghe, Gabriel %*POSTER: Critique of the CISSP common body of knowledge of cryptography %uhttp://dl.acm.org/ft_gateway.cfm?id=2512499&type=pdf %f/ccs/d4m6jiyzntc7x13akforfwn9hygeztkv.pdf %mcd32a2c27b559a452b0df0cca905c5ed %cccs %@Gheorghe, Gabriela, Neuhaus, Stepha %*POSTER: Preserving privacy and accountability for personal devices %uhttp://dl.acm.org/ft_gateway.cfm?id=2512500&type=pdf %f/ccs/odxsaklwpg1vt64dzyxwezbvmhc9fkqj.pdf %mc0fb9eb4b554234cfc70d35cc05d6912 %cccs %@Brenner, Michael, Smith, Matthe %*POSTER: Caching oblivious memory access: an extension to the HCRYPT virtual machine %uhttp://dl.acm.org/ft_gateway.cfm?id=2512501&type=pdf %f/ccs/waj8o4xolwezgnb63fdyk0qcm5hvtxld.pdf %m50dc0cb593babe28f8ce83dc83294a6f %cccs %@Reznik, Leon, Bertino, Elis %*POSTER: Data quality evaluation: integrating security and accuracy %uhttp://dl.acm.org/ft_gateway.cfm?id=2512502&type=pdf %f/ccs/3mk0fih9cjpekhtuvcbqdyfayuzj4o1l.pdf %mb1de13928f2c42c03366104b0c8ad49f %cccs %@Nguyen, Cuong Xuan, Huang, Hung-Hsuan, Kawagoe, Kyoj %*POSTER: Graphical password using object-based image ranking %uhttp://dl.acm.org/ft_gateway.cfm?id=2512503&type=pdf %f/ccs/mxaydq1fvkpzrsob47ngnuh3ephmwdix.pdf %m30e2036890b0176969a251f8fa7cfae8 %cccs %@Zhang, Hao, Yao, Danfeng Daphne, Ramakrishnan, Nare %*POSTER: A semantic-aware approach to reasoning about network traffic relations %uhttp://dl.acm.org/ft_gateway.cfm?id=2512504&type=pdf %f/ccs/rdx98lpqlatweg6jei5nhazxiympodov.pdf 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%f/ccs/okse0lxx79bjfi3alyvvp1wm2yquhedf.pdf %mf0682971cc5af69500c7595d5409f154 %cccs %@Li, Dan, Liu, Chaoge, Cui, Xu, Cui, Xian %*POSTER: Sniffing and propagating malwares through WPAD deception in LANs %uhttp://dl.acm.org/ft_gateway.cfm?id=2512520&type=pdf %f/ccs/toeq0kid9ws6ylj4mvg8ecg1acpsrnaj.pdf %m2b41f1ee0b700cddd2d14c6482d89dff %cccs %@Javed, Asha %*POSTER: A footprint of third-party tracking on mobile web %uhttp://dl.acm.org/ft_gateway.cfm?id=2512521&type=pdf %f/ccs/sciz64kpl1i3otmaycbzxgohkvsww0gm.pdf %m6b8d3b80d1600a595d1ca8bacfcbabf4 %cccs %@Bhat, Wasim Ahmad, Quadri, S.M.K %*POSTER: Dr. Watson provides data for post-breach analysis %uhttp://dl.acm.org/ft_gateway.cfm?id=2512522&type=pdf %f/ccs/w2hoq50koraievtdu8gtxfrn41ywvbas.pdf %mbe39cc432b5cf95220a513bd3df37a83 %cccs %@Husák, Martin, Vizváry, Marti %*POSTER: Reflected attacks abusing honeypots %uhttp://dl.acm.org/ft_gateway.cfm?id=2512523&type=pdf %f/ccs/d7yqlesgzjryowmacehqvd8kitgxpz0k.pdf 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%f/ccs/iww0x7xg6ihltbvea8ctvmscyb45no3z.pdf %m4272b2e5e777daa55c8bd4f0ddc6983e %cccs %@Maqsood, Sana, Chiasson, Sonia, Girouard, Audre %*POSTER: Passwords on flexible display devices %uhttp://dl.acm.org/ft_gateway.cfm?id=2512528&type=pdf %f/ccs/8svmpz1tirokmqhbboyw0unhf9lea4tj.pdf %m0400971ba9e456081c3e9a7ba48cd9b5 %cccs %@Ashfaq, Ayesha Binte, Ali, Muhammad Qasim, Al-Shaer, Ehab, Khayam, Syed Al %*POSTER: Revisiting anomaly detection system design philosophy %uhttp://dl.acm.org/ft_gateway.cfm?id=2512529&type=pdf %f/ccs/nx8qiowjvfjv2ytrm7dzykcf6okpz9hq.pdf %m84897e52eeb5f2d41cda7bc547d355d9 %cccs %@Foresti, Sar %*12th workshop on privacy in the electronic society (WPES 2013) %uhttp://dl.acm.org/ft_gateway.cfm?id=2509028&type=pdf %f/ccs/hurmz07fld5jehig4riq6exkystwnusd.pdf %m4fa8b3d72b8ff8f4020f3b012f539555 %cccs %@Armknecht, Frederik, Seifert, Jean-Pierr %*Third international workshop on trustworthy embedded devices (TrustED 2013) %uhttp://dl.acm.org/ft_gateway.cfm?id=2509029&type=pdf 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Morle %*SocialWatch: detection of online service abuse via large-scale social graphs %uhttp://dl.acm.org/ft_gateway.cfm?id=2484330&type=pdf %f/ccs/spmduf0h3rxvnokfgqvi8alw65tybxhd.pdf %m20f2e7048b7e1ecf18a1bd4c258c8f99 %cccs %@Masoumzadeh, Amirreza, Joshi, Jame %*Privacy settings in social networking systems: what you cannot control %uhttp://dl.acm.org/ft_gateway.cfm?id=2484331&type=pdf %f/ccs/alxywc6jbyra2fvzkmhqvpob0ul9mjog.pdf %m0525a2b31cd7686501bc4fc707159779 %cccs %@Mohaisen, Abedelaziz, Tran, Huy, Chandra, Abhishek, Kim, Yongda %*Trustworthy distributed computing on social networks %uhttp://dl.acm.org/ft_gateway.cfm?id=2484332&type=pdf %f/ccs/toq8urwaisnk06fd2hnqu9awbygzjfje.pdf %m7714bc9fa1c8c63f8d7d7a60c11652db %cccs %@Ahmadinejad, Seyed Hossein, Fong, Philip W.L %*On the feasibility of inference attacks by third-party extensions to social network systems %uhttp://dl.acm.org/ft_gateway.cfm?id=2484333&type=pdf %f/ccs/syqevq2nb856ctvzfpntx1a04cfgsbh3.pdf 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Jean-Yve %*Aligot: cryptographic function identification in obfuscated binary programs %uhttp://dl.acm.org/ft_gateway.cfm?id=2382217&type=pdf %f/ccs/ehzejkxn4htrq27n5v13wpikc9ywarcz.pdf %m190ff73d70ecbeb1f0285c8aad87326b %cccs %@Edwards, Nigel, Chen, Liqu %*An historical examination of open source releases and their vulnerabilities %uhttp://dl.acm.org/ft_gateway.cfm?id=2382218&type=pdf %f/ccs/cfzegyxfv9q3t6csmpnjxvwpbgnbsk8e.pdf %m7c6d62bea46b4cc1fb6e781208eecdae %cccs %@Peng, Chunyi, Li, Chi-yu, Tu, Guan-Hua, Lu, Songwu, Zhang, Lixi %*Mobile data charging: new attacks and countermeasures %uhttp://dl.acm.org/ft_gateway.cfm?id=2382220&type=pdf %f/ccs/cma3wgznirvondrbt1vchbymqfqkuw9x.pdf %m57f87be58e8ce87a748ab45feef744a0 %cccs %@Arapinis, Myrto, Mancini, Loretta, Ritter, Eike, Ryan, Mark, Golde, Nico, Redon, Kevin, Borgaonkar, Ravishanka %*New privacy issues in mobile telephony: fix and verification %uhttp://dl.acm.org/ft_gateway.cfm?id=2382221&type=pdf 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%uhttp://dl.acm.org/ft_gateway.cfm?id=2046742&type=pdf %f/ccs/qsp8jmaqlfvyg6itxsl4h3ykknwx7rou.pdf %mf397373f27348a3080df9b1451bb1795 %cccs %@Cheval, Vincent, Comon-Lundh, Hubert, Delaune, Stéphani %*Trace equivalence decision: negative tests and non-determinism %uhttp://dl.acm.org/ft_gateway.cfm?id=2046744&type=pdf %f/ccs/tgad5l0iurrhbjmydzxq6kwukv3s4ozx.pdf %m5b3dbcc44950d8b93445a13273564846 %cccs %@Aizatulin, Mihhail, Gordon, Andrew D., Jürjens, Ja %*Extracting and verifying cryptographic models from C protocol code by symbolic execution %uhttp://dl.acm.org/ft_gateway.cfm?id=2046745&type=pdf %f/ccs/lppnk5ruzznmhdy0bjvgiqfsey8kg27c.pdf %ma15b3f0b8f257c3628a50eac05925884 %cccs %@Fournet, Cédric, Kohlweiss, Markulf, Strub, Pierre-Yve %*Modular code-based cryptographic verification %uhttp://dl.acm.org/ft_gateway.cfm?id=2046746&type=pdf %f/ccs/xuk2eqw8oldketnp6v5g0iym9jvl1zhu.pdf %m3f9fd614ecd7f23069c6c4fb22ac3470 %cccs %@Fournet, Cédric, Planul, Jérémy, Rezk, Tamar %*Information-flow types for homomorphic encryptions %uhttp://dl.acm.org/ft_gateway.cfm?id=2046747&type=pdf %f/ccs/qmzmhpiriktwxncofjjg2ls1elvb0xkq.pdf %m2727ac583f2620fbc016513cad8d0295 %cccs %@Camenisch, Ja %*Cryptographic primitives for building secure and privacy respecting protocols %uhttp://dl.acm.org/ft_gateway.cfm?id=2046749&type=pdf %f/ccs/q1nwqckyij0tfrozdcvo3jlg2bp86mhk.pdf %m5400dec53769076fb247b2242dd5a84e %cccs %@Srinivasan, Deepa, Wang, Zhi, Jiang, Xuxian, Xu, Dongya %*Process out-grafting: an efficient out-of-VM approach for fine-grained process execution monitoring %uhttp://dl.acm.org/ft_gateway.cfm?id=2046751&type=pdf %f/ccs/ztrhvltmemqjpqhycnygz4apfulkedvr.pdf %mb0ddc5ad3e2be0dfa41fbf862c643bc2 %cccs %@Azab, Ahmed M., Ning, Peng, Zhang, Xiaola %*SICE: a hardware-level strongly isolated computing environment for x86 multi-core platforms %uhttp://dl.acm.org/ft_gateway.cfm?id=2046752&type=pdf %f/ccs/vysnbuf9rtk5qx2lj3awownesdmvh7e6.pdf %m1f5a303f877eb19ab121a33b338929d1 %cccs %@Bugiel, Sven, Nürnberger, Stefan, Pöppelmann, Thomas, Sadeghi, Ahmad-Reza, Schneider, Thoma %*AmazonIA: when elasticity snaps back %uhttp://dl.acm.org/ft_gateway.cfm?id=2046753&type=pdf %f/ccs/me5twu7gnfqhwxsorsmnkxpcj42i8hld.pdf %mf7e460d7fae94b877009383e2a86a425 %cccs %@Szefer, Jakub, Keller, Eric, Lee, Ruby B., Rexford, Jennife %*Eliminating the hypervisor attack surface for a more secure cloud %uhttp://dl.acm.org/ft_gateway.cfm?id=2046754&type=pdf %f/ccs/yecgtqnq3x8i7zdlwk0tsn4moudy5pvr.pdf %m0ba6a8bc0831dd6964eadd75e66be1f1 %cccs %@Jager, Tibor, Somorovsky, Jura %*How to break XML encryption %uhttp://dl.acm.org/ft_gateway.cfm?id=2046756&type=pdf %f/ccs/tkzs9ecx4d1biuahx6fgi3rjgoq8pkfv.pdf %mc8d71aa35324ec521a99268d4597f7da %cccs %@Bellare, Mihir, Cash, David, Keelveedhi, Srira %*Ciphers that securely encipher their own keys %uhttp://dl.acm.org/ft_gateway.cfm?id=2046757&type=pdf %f/ccs/2qys1wdxugpkvotjqczl06t3wrjrxgiz.pdf %me946100ef60facc54e2c64e8dcbfdeec %cccs %@Bagherzandi, Ali, Jarecki, Stanislaw, Saxena, Nitesh, Lu, Yanbi %*Password-protected secret sharing %uhttp://dl.acm.org/ft_gateway.cfm?id=2046758&type=pdf %f/ccs/fxdspfcylukzcxmnh8vrgebongzi4q5w.pdf %m954c008abd216681b5012eb760e2fed4 %cccs %@Canetti, Ran, Riva, Ben, Rothblum, Guy N %*Practical delegation of computation using multiple servers %uhttp://dl.acm.org/ft_gateway.cfm?id=2046759&type=pdf %f/ccs/ctz4ftakwi0jsnr8zhbxmdiw9mrx7uqv.pdf %m9b79d6a9ff7ab39037c341ef48ea2a19 %cccs %@Moore, Tyler, Leontiadis, Nektarios, Christin, Nicola %*Fashion crimes: trending-term exploitation on the web %uhttp://dl.acm.org/ft_gateway.cfm?id=2046761&type=pdf %f/ccs/fdxjfa7q8wwro26pylbghglvmzroeiqp.pdf %m8cad35102d142ee34797b850adccea77 %cccs %@Lu, Long, Perdisci, Roberto, Lee, Wenk %*SURF: detecting and measuring search poisoning %uhttp://dl.acm.org/ft_gateway.cfm?id=2046762&type=pdf %f/ccs/kxw15jpsaqtgexccrsvugohltdfdk3b6.pdf %m605beb056b976c8a2a6d4b6a63d79a88 %cccs %@Wang, David Y., Savage, Stefan, Voelker, Geoffrey M %*Cloak and dagger: dynamics of web search cloaking %uhttp://dl.acm.org/ft_gateway.cfm?id=2046763&type=pdf %f/ccs/je51yamrttvmkrsvhiynfn2gbjdc79uc.pdf %m9bf074038abdc2956dbd4d918eaa728d %cccs %@Halevi, Shai, Harnik, Danny, Pinkas, Benny, Shulman-Peleg, Alexandr %*Proofs of ownership in remote storage systems %uhttp://dl.acm.org/ft_gateway.cfm?id=2046765&type=pdf %f/ccs/vemv5efixgwmd8j2ro4irxb9qhakpnt0.pdf %mc04a1e99568534cc463489321ecef4d3 %cccs %@Bowers, Kevin D., van Dijk, Marten, Juels, Ari, Oprea, Alina, Rivest, Ronald L %*How to tell if your cloud files are vulnerable to drive crashes %uhttp://dl.acm.org/ft_gateway.cfm?id=2046766&type=pdf %f/ccs/k8jm5fmo3uanrxwvisqylnet0ayhdlgp.pdf %m7108a6448468d953cf4853c789283af0 %cccs %@Zhang, Kehuan, Zhou, Xiaoyong, Chen, Yangyi, Wang, XiaoFeng, Ruan, Yaopin %*Sedic: privacy-aware data intensive computing on hybrid clouds %uhttp://dl.acm.org/ft_gateway.cfm?id=2046767&type=pdf %f/ccs/onu3okq6jjpvch7getm4zaaxx5ndlzmr.pdf %mdb630fb59dafa2bf0b28c11f9b7d957c %cccs %@Raguram, Rahul, White, Andrew M., Goswami, Dibyendusekhar, Monrose, Fabian, Frahm, Jan-Michae %*iSpy: automatic reconstruction of typed input from compromising reflections %uhttp://dl.acm.org/ft_gateway.cfm?id=2046769&type=pdf %f/ccs/xzqtnnfsjrjopglbdvscmhal35befmhg.pdf %m684e58c425ec838b8edf410d5578dc51 %cccs %@Enev, Miro, Gupta, Sidhant, Kohno, Tadayoshi, Patel, Shwetak N %*Televisions, video privacy, and powerline electromagnetic interference %uhttp://dl.acm.org/ft_gateway.cfm?id=2046770&type=pdf %f/ccs/p8m2sd0va9unw1iliph7usgaegzqcxyy.pdf %m9beef4e112aab3c8cb3bb52f5c8358cf %cccs %@Marquardt, Philip, Verma, Arunabh, Carter, Henry, Traynor, Patric %*(sp)iPhone: decoding vibrations from nearby keyboards using mobile phone accelerometers %uhttp://dl.acm.org/ft_gateway.cfm?id=2046771&type=pdf %f/ccs/aepihmhcbovsq0lde7p9g2v6f8zdxwsc.pdf %m98c0b16c5f769c0f7521c3326c2c0e05 %cccs %@Zhang, Danfeng, Askarov, Aslan, Myers, Andrew C %*Predictive mitigation of timing channels in interactive systems %uhttp://dl.acm.org/ft_gateway.cfm?id=2046772&type=pdf %f/ccs/0ejodl3thiic8myxthbn9bawrwzyqzx1.pdf %m009e1bf98a2d12cb18e6aa1a2aae3916 %cccs %@Bisht, Prithvi, Hinrichs, Timothy, Skrupsky, Nazari, Venkatakrishnan, V. N %*WAPTEC: whitebox analysis of web applications for parameter tampering exploit construction %uhttp://dl.acm.org/ft_gateway.cfm?id=2046774&type=pdf %f/ccs/z7kxhyswqt8xrvnfoh5g40b2vpjbdny1.pdf %m836203fd20100099233ddcc5addf4e4d %cccs %@Samuel, Mike, Saxena, Prateek, Song, Daw %*Context-sensitive auto-sanitization in web templating languages using type qualifiers %uhttp://dl.acm.org/ft_gateway.cfm?id=2046775&type=pdf %f/ccs/q8tdxlijkesaup21p4zmor7r9fj5wmyg.pdf %mca69fb5bd568d4bfbe5ef6d08fbf3e85 %cccs %@Saxena, Prateek, Molnar, David, Livshits, Benjami %*SCRIPTGARD: automatic context-sensitive sanitization for large-scale legacy web applications %uhttp://dl.acm.org/ft_gateway.cfm?id=2046776&type=pdf %f/ccs/lyhais5gm1cnoxflpi73rawwjsx8tqvm.pdf %mc97ae4e0e41915b3c219a071f5958b00 %cccs %@Tang, Shuo, Dautenhahn, Nathan, King, Samuel T %*Fortifying web-based applications automatically %uhttp://dl.acm.org/ft_gateway.cfm?id=2046777&type=pdf %f/ccs/0wrodfuiw2jkgnacpiqo9bzy1sex5tzp.pdf %ma0f09ae2af5162f6d2c32b7c16edba43 %cccs %@Felt, Adrienne Porter, Chin, Erika, Hanna, Steve, Song, Dawn, Wagner, Davi %*Android permissions demystified %uhttp://dl.acm.org/ft_gateway.cfm?id=2046779&type=pdf %f/ccs/ggvrn6c7mhxdhsibzj5sy2x84yjdenuf.pdf %mfea7db7693f00d6e59044f391ed30603 %cccs %@Hornyack, Peter, Han, Seungyeop, Jung, Jaeyeon, Schechter, Stuart, Wetherall, Davi %*These aren't the droids you're looking for: retrofitting android to protect data from imperious applications %uhttp://dl.acm.org/ft_gateway.cfm?id=2046780&type=pdf %f/ccs/wnbyowksmyhlu3vrxuafdi6o1tnc59kz.pdf %ma952d02f5cb39bd4d311acb917643702 %cccs %@Popa, Raluca Ada, Blumberg, Andrew J., Balakrishnan, Hari, Li, Frank H %*Privacy and accountability for location-based aggregate statistics %uhttp://dl.acm.org/ft_gateway.cfm?id=2046781&type=pdf %f/ccs/yn58qhkjz7iexk4fge9clohmrgpabwfs.pdf %m6382a8622784170b10772d595ebfdefb %cccs %@Reznichenko, Alexey, Guha, Saikat, Francis, Pau %*Auctions in do-not-track compliant internet advertising %uhttp://dl.acm.org/ft_gateway.cfm?id=2046782&type=pdf %f/ccs/tyuwozt52zyrbsjkgsdfbi41vwhmo8ir.pdf %m42abc2e5478790c894aa0d0a34e96652 %cccs %@Henry, Ryan, Olumofin, Femi, Goldberg, Ia %*Practical PIR for electronic commerce %uhttp://dl.acm.org/ft_gateway.cfm?id=2046784&type=pdf %f/ccs/ni9dl6qrbyrd4z1esmc8x0quxhtfgya2.pdf %mffdebfca0b0871110cdac64bda9b8939 %cccs %@Baldi, Pierre, Baronio, Roberta, De Cristofaro, Emiliano, Gasti, Paolo, Tsudik, Gen %*Countering GATTACA: efficient and secure testing of fully-sequenced human genomes %uhttp://dl.acm.org/ft_gateway.cfm?id=2046785&type=pdf %f/ccs/npn6gezkyko8jt9xw3sdezjfwvqtu0dm.pdf %m7b69345c0d01d5f79683796f5f5a74eb %cccs %@Kerschbaum, Floria %*Automatically optimizing secure computation %uhttp://dl.acm.org/ft_gateway.cfm?id=2046786&type=pdf %f/ccs/lyiazr4tkuvdof7nwhc1ujs0krpz92qv.pdf %me5965cbee55142d96f19c713475f7303 %cccs %@Malka, Lio %*VMCrypt: modular software architecture for scalable secure computation %uhttp://dl.acm.org/ft_gateway.cfm?id=2046787&type=pdf %f/ccs/bvr5c8imfh4msuxefkv1xk2qlrhuztjz.pdf %mf809efed1cd4a4e95ec327fd65c85e67 %cccs %@Adamsky, Florian, Khan, Hassan, Rajarajan, Muttukrishnan, Khayam, Syed Ali, Jäger, Rudol %*Poster: Destabilizing BitTorrent's clusters to attack high bandwidth leechers %uhttp://dl.acm.org/ft_gateway.cfm?id=2093478&type=pdf %f/ccs/flcdnwrb0zhjrgscxtqv8o5lj7pnuyay.pdf %m8d5bbbcba73fc32c543a8579a51fc845 %cccs %@Ahmadzadeh, Seyed Ali, Agnew, Gordon B %*Poster: a geometric approach for multicast authentication in adversarial channels %uhttp://dl.acm.org/ft_gateway.cfm?id=2093479&type=pdf %f/ccs/1zynomtk2wgcu4gnzt0svqweljd36lhe.pdf %m43c2b1e5178a3ac665856e2069aaa827 %cccs %@Bichsel, Patrik, Preiss, Franz-Stefa %*Demo: a comprehensive framework enabling data-minimizing authentication %uhttp://dl.acm.org/ft_gateway.cfm?id=2093480&type=pdf %f/ccs/dintfcbgvuhmg0emvq3kelnwsjp1bk7l.pdf %m32c9606f8e9e7e05033bee235aa111a3 %cccs %@Blass, Erik-Oliver, Elkhiyaoui, Kaoutar, Molva, Refik, Savry, Olivier, Vérhilac, Cédri %*Demo: the f f hardware prototype for privacy-preserving RFID authentication %uhttp://dl.acm.org/ft_gateway.cfm?id=2093481&type=pdf %f/ccs/txagm9e02scjydnfyb8wtlhrzki45lr1.pdf %m545eaad307ee14af45730c94b35facfb %cccs %@Bugiel, Sven, Davi, Lucas, Dmitrienko, Alexandra, Fischer, Thomas, Sadeghi, Ahmad-Reza, Shastry, Bhargav %*Poster: the quest for security against privilege escalation attacks on android %uhttp://dl.acm.org/ft_gateway.cfm?id=2093482&type=pdf %f/ccs/pyk8zeo01cvywn3xigxldtsjj7mn2btq.pdf %m09ef21ec656de9c8134c406493b02081 %cccs %@Cao, Yinzhi, Yegneswaran, Vinod, Porras, Phillip, Chen, Ya %*Poster: a path-cutting approach to blocking XSS worms in social web networks %uhttp://dl.acm.org/ft_gateway.cfm?id=2093483&type=pdf %f/ccs/2dp4algcn6v0xubi8qfjm9btrshnomgz.pdf %mef2bf142c9c5e1bbf65f3b8601272226 %cccs %@Davi, Lucas, Dmitrienko, Alexandra, Egele, Manuel, Fischer, Thomas, Holz, Thorsten, Hund, Ralf, Nürnberger, Stefan, Sadeghi, Ahmad-Rez %*Poster: control-flow integrity for smartphones %uhttp://dl.acm.org/ft_gateway.cfm?id=2093484&type=pdf %f/ccs/yx2gzceouks7favnmq1btlwrxds0depj.pdf %md75c3f2773832b36af455f9750600eaa %cccs %@Dolev, Shlomi, Gilboa, Niv, Hermoni, Ofe %*Poster: arbitrators in the security infrastructure, supporting positive anonymity %uhttp://dl.acm.org/ft_gateway.cfm?id=2093485&type=pdf %f/ccs/bv6noq15scuvyhj89gdmmaetszhek3fc.pdf %m3a6f032e7a2dbf3ac7e0bb4d14e907c9 %cccs %@Dolev, Shlomi, Gilboa, Niv, Kopeetsky, Marin %*Poster: attribute based broadcast encryption with permanent revocation %uhttp://dl.acm.org/ft_gateway.cfm?id=2093486&type=pdf %f/ccs/nmighpdbwat0clxez2oqrictykqgxsez.pdf %mded54bb395d6aaa58e8798d2f64b71a2 %cccs %@Fung, Carol, Zhu, Quanyan, Boutaba, Raouf, Basar, Tame %*Poster: SMURFEN: a rule sharing collaborative intrusion detection network %uhttp://dl.acm.org/ft_gateway.cfm?id=2093487&type=pdf %f/ccs/8emgvsadqkbhjhf3nd0petjtipxcqf2i.pdf %m4cfe65a2b025def3e37e6d6946987593 %cccs %@Gafny, Ma'ayan, Shabtai, Asaf, Rokach, Lior, Elovici, Yuva %*Poster: applying unsupervised context-based analysis for detecting unauthorized data disclosure %uhttp://dl.acm.org/ft_gateway.cfm?id=2093488&type=pdf %f/ccs/ikqblmpzn8juj7pdv0fvoaatzwsdkgem.pdf %m0fd99c630a5d5c57c964d227bceaf77e %cccs %@Gao, Hongyu, Chen, Yan, Lee, Kathy, Palsetia, Diana, Choudhary, Alo %*Poster: online spam filtering in social networks %uhttp://dl.acm.org/ft_gateway.cfm?id=2093489&type=pdf %f/ccs/razmxwqe2f3uv1eiqvxyalshl9sd7nym.pdf %m2b26e57c1abe96a0ce338275c6c75cd2 %cccs %@Gong, Xi, Yu, Ting, Lee, Ada %*Poster: on trust evaluation with missing information in reputation systems %uhttp://dl.acm.org/ft_gateway.cfm?id=2093490&type=pdf %f/ccs/ovdztamkepr0hg1cj3qnplr9tflyisd2.pdf %m2a71cb72cfb660e3c9cf9bf938067481 %cccs %@Han, Weili, Fang, Zheran, Chen, Weifeng, Xu, Wenyuan, Lei, Chan %*Poster: collaborative policy administration %uhttp://dl.acm.org/ft_gateway.cfm?id=2093491&type=pdf %f/ccs/nsib6bakz3npg9jpacwetumqqy17ztvr.pdf %m3eba4c62e18b397c78d7a21ca9256cc8 %cccs %@Han, Weili, Shen, Chenguang, Yin, Yuliang, Gu, Yun, Chen, Che %*Poster: using quantified risk and benefit to strengthen the security of information sharing %uhttp://dl.acm.org/ft_gateway.cfm?id=2093492&type=pdf %f/ccs/ekh1zkn3mrbxyycaw5f6tewozjs9ulsb.pdf %m77c9e3931adaa4e7c2c01d5cceee985c %cccs %@Hu, Jun, Gao, Hongyu, Li, Zhichun, Chen, Ya %*Poster: CUD: crowdsourcing for URL spam detection %uhttp://dl.acm.org/ft_gateway.cfm?id=2093493&type=pdf %f/ccs/7rif0zociblghvane31lxtafk86xusmr.pdf %m08534be364baf20ab6aef5103910dd23 %cccs %@Javed, Asha %*Poster: DIEGO: a fine-grained access control for web browsers %uhttp://dl.acm.org/ft_gateway.cfm?id=2093494&type=pdf %f/ccs/tiulwf32nscdlo8voxrjkk5s4ezp0p6j.pdf %m54132a651de5979b712bcd93f2ebf6f8 %cccs %@Jeckmans, Arjan, Tang, Qiang, Hartel, Piete %*Poster: privacy-preserving profile similarity computation in online social networks %uhttp://dl.acm.org/ft_gateway.cfm?id=2093495&type=pdf %f/ccs/dkutmuvb2ng3ajmsqzpxrawo9ekwobig.pdf %mcc9e63b40dd4684970b784cdde4eebed %cccs %@Kocabas, Ünal, Sadeghi, Ahmad Reza, Wachsmann, Christian, Schulz, Steffe %*Poster: practical embedded remote attestation using physically unclonable functions %uhttp://dl.acm.org/ft_gateway.cfm?id=2093496&type=pdf %f/ccs/dlp6m30garc9ou2amjykfpnizwjer4ws.pdf %m2e2a9d8b19a87791fbfae4ffdae5c5f0 %cccs %@Liu, Yao, Ning, Pen %*Poster: mimicry attacks against wireless link signature %uhttp://dl.acm.org/ft_gateway.cfm?id=2093497&type=pdf %f/ccs/el0wmywalr1haxknpusdrcovtc7s9i4b.pdf %ma69c6fea00979983996b7e6edec9b115 %cccs %@Maggi, Federico, Volpatto, Alberto, Gasparini, Simone, Boracchi, Giacomo, Zanero, Stefan %*Poster: fast, automatic iPhone shoulder surfing %uhttp://dl.acm.org/ft_gateway.cfm?id=2093498&type=pdf %f/ccs/qncueyt8tbfqgclvpahsksko5mpy37vh.pdf %mb39d242fbf53b2b1dc5dc764361f0fe2 %cccs %@Mahmood, Shah, Desmedt, Yv %*Poster: preliminary analysis of Google+'s privacy %uhttp://dl.acm.org/ft_gateway.cfm?id=2093499&type=pdf %f/ccs/ptabokee4yaqsvbgoflnshcdp8uuyfg9.pdf %m48f02cdc79175bb1ee91e9a6fe009909 %cccs %@Mallesh, Nayantara, Wright, Matthe %*Poster: shaping network topology for privacy and performance %uhttp://dl.acm.org/ft_gateway.cfm?id=2093500&type=pdf %f/ccs/nanbowkpojtxyl3wpx2zmqsk5lscva7e.pdf %m6e48bb15621c6d72b2765af19a6890af %cccs %@Mejia, Ramon Francisco Pacquiao, Kaji, Yuichi, Seki, Hiroyuk %*Poster: trans-organizational role-based access control %uhttp://dl.acm.org/ft_gateway.cfm?id=2093501&type=pdf %f/ccs/ybdren4fvhttia1c6xhxqiwapu07om5w.pdf %m183f38542a50b71c3c3b808e3e0e9f25 %cccs %@Nabeel, Mohamed, Bertino, Elis %*Poster: towards attribute based group key management %uhttp://dl.acm.org/ft_gateway.cfm?id=2093502&type=pdf %f/ccs/urrtiv4pdswcnaxqasoe72cmgxiwvyn0.pdf %ma0a79c04a897dc675b0cf28cb1af06d9 %cccs %@Nithyanand, Rishab, Sion, Radu, Solis, Joh %*Poster: making the case for intrinsic personal physical unclonable functions (IP-PUFs) %uhttp://dl.acm.org/ft_gateway.cfm?id=2093503&type=pdf %f/ccs/ymikjvc7xwh1f4kteqfwlaznuuo0rblg.pdf %m187ebf26e3155723b0182fa331fe5982 %cccs %@Niu, Ben, Tan, Gan %*Poster: uPro: a compartmentalization tool supporting fine-grained and flexible security configuration %uhttp://dl.acm.org/ft_gateway.cfm?id=2093504&type=pdf %f/ccs/biu2tmz4qxdx8ln9lejrwhmeoujyz6o1.pdf %mc7d4320b994155a4ed5d912c467d0993 %cccs %@Peng, Liao, Xiang, Cui, Shuhao, Li, Chaoge, Li %*Poster: recoverable botnets: a hybrid C&C approach %uhttp://dl.acm.org/ft_gateway.cfm?id=2093505&type=pdf %f/ccs/hzofzcrm3thaedxb5upg8nl0jabsx6km.pdf %m259680e1e155a4cdb7334fc4712e5f00 %cccs %@Perl, Henning, Brenner, Michael, Smith, Matthe %*Poster: an implementation of the fully homomorphic smart-vercauteren crypto-system %uhttp://dl.acm.org/ft_gateway.cfm?id=2093506&type=pdf %f/ccs/hfhpult0ig3go4pe8jldw7ftcxdxwcku.pdf %m525234bb39a35c6a59ec6b93d6d03580 %cccs %@Asghar, Muhammad Rizwan, Russello, Giovanni, Crispo, Brun %*Poster: ESPOON ERBAC : enforcing security policies in outsourced environments with encrypted RBAC %uhttp://dl.acm.org/ft_gateway.cfm?id=2093507&type=pdf %f/ccs/dcfkgxv1dm4vgtzftp9keemnx57n6bhq.pdf %m8c1397750d8106cf3f9288b4a51f118d %cccs %@Islam, Mohammad Saiful, Kuzu, Mehmet, Kantarcioglu, Mura %*Poster: inference attacks against searchable encryption protocols %uhttp://dl.acm.org/ft_gateway.cfm?id=2093508&type=pdf %f/ccs/lpkdo0fyizlk1t2sba76drrjjhxenpwq.pdf %mc50ba4fd8ce3d9a527ca57a8cb3b088b %cccs %@Schroepfer, Axel, Kerschbaum, Floria %*Demo: secure computation in JavaScript %uhttp://dl.acm.org/ft_gateway.cfm?id=2093509&type=pdf %f/ccs/74ycmd9pivbwe0sl5s38freikanzunug.pdf %m08ade8cf494764e918359a08f58e34b7 %cccs %@Shen, Chao, Cai, Zhongmin, Guan, Xiaohon %*Poster: can it be more practical?: improving mouse dynamics biometric performance %uhttp://dl.acm.org/ft_gateway.cfm?id=2093510&type=pdf %f/ccs/nszchkmeo7rt5jakpxw21cvdhiqfydie.pdf %m2a1c86e3573e973eb46c871d7894d704 %cccs %@Stewin, Patrick, Seifert, Jean-Pierre, Mulliner, Colli %*Poster: Towards detecting DMA malware %uhttp://dl.acm.org/ft_gateway.cfm?id=2093511&type=pdf %f/ccs/qrwpavcbhkuetxt9zym7hxgg8um5ldks.pdf %mf131ef59daa9890c563551c68a71ad22 %cccs %@Sun, Pengfei, Shen, Qingni, Chen, Ying, Wu, Zhonghai, Zhang, Cong, Ruan, Anbang, Gu, Lian %*Poster: LBMS: load balancing based on multilateral security in cloud %uhttp://dl.acm.org/ft_gateway.cfm?id=2093512&type=pdf %f/ccs/u5yfd0zwpdrcewebqpvybum1qz6ms9ot.pdf %m67ed764a5c60b9423ecc31573d31e2e5 %cccs %@Trivellato, Daniel, Zannone, Nicola, Etalle, Sandr %*Poster: protecting information in systems of systems %uhttp://dl.acm.org/ft_gateway.cfm?id=2093513&type=pdf %f/ccs/k5af37c6miqp91edwczhp0wjosxylhns.pdf %m93f242efe7c2979d9fa07a04225a4f18 %cccs %@Wu, Xiaoxin, Xu, Lei, Zhang, Xinwe %*Poster: a certificateless proxy re-encryption scheme for cloud-based data sharing %uhttp://dl.acm.org/ft_gateway.cfm?id=2093514&type=pdf %f/ccs/e1unc4joyhwgnzkay9qp5tblwxsmc2di.pdf %m89e4dfc4f98718823515b4c9f9612528 %cccs %@Yang, Zhi, Yin, Lihua, Duan, Miyi, Jin, Shuyua %*Poster: towards formal verification of DIFC policies %uhttp://dl.acm.org/ft_gateway.cfm?id=2093515&type=pdf %f/ccs/awl5jimg1rf63lkkxgbud8nihnaxojpo.pdf %me07be1b6b4e74b346105d3173b47fbf4 %cccs %@Zhu, Ji, Srivatsa, Mudhaka %*Poster: on quantitative information flow metrics %uhttp://dl.acm.org/ft_gateway.cfm?id=2093516&type=pdf %f/ccs/1iqkl5nb7khtsijtsdgzcpxa34aomhvf.pdf %mf560ba79c78c1b4a2002e3252a68ed09 %cccs %@Zhu, Yan, Hu, Hongxin, Ahn, Gail-Joon, Gong, Xiaorui, Chen, Shimi %*Poster: temporal attribute-based encryption in clouds %uhttp://dl.acm.org/ft_gateway.cfm?id=2093517&type=pdf %f/ccs/m51hcqwcuxi24y0tglqotjfrfinoseuw.pdf %med13680ea97f719b872fdb15a714f95a %cccs %@Wang, Xiaoyun, Liu, Mingjie, Tian, Chengliang, Bi, Jinggu %*Improved Nguyen-Vidick heuristic sieve algorithm for shortest vector problem %uhttp://dl.acm.org/ft_gateway.cfm?id=1966915&type=pdf %f/ccs/h06d1fv5ygu3gmobro2cdschzvu8xxmi.pdf %m4f6ce807c94469eaa9ab1aa5a72fb353 %cccs %@Bertino, Elisa, Ghinita, Gabrie %*Towards mechanisms for detection and prevention of data exfiltration by insiders: keynote talk paper %uhttp://dl.acm.org/ft_gateway.cfm?id=1966916&type=pdf %f/ccs/ebqaytzrbxtioy3inp5d1jlmf9rkhe2s.pdf %mf2022aced6039c1abfe145315535f633 %cccs %@Chen, Ping, Xing, Xiao, Mao, Bing, Xie, Li, Shen, Xiaobin, Yin, Xinchu %*Automatic construction of jump-oriented programming shellcode (on the x86) %uhttp://dl.acm.org/ft_gateway.cfm?id=1966918&type=pdf %f/ccs/b7muk48jqk1pe2xinqglaxvzjhzbcuoa.pdf %m24fb0d110b00d9596db243f4b657a530 %cccs %@Bletsch, Tyler, Jiang, Xuxian, Freeh, Vince W., Liang, Zhenka %*Jump-oriented programming: a new class of code-reuse attack %uhttp://dl.acm.org/ft_gateway.cfm?id=1966919&type=pdf %f/ccs/mpczy5a0kjsg3qnlfmhy7nbuwiztfogp.pdf %mbcc3b8b233559b64996e9e096c6afa9e %cccs %@Davi, Lucas, Sadeghi, Ahmad-Reza, Winandy, Marce %*ROPdefender: a detection tool to defend against return-oriented programming attacks %uhttp://dl.acm.org/ft_gateway.cfm?id=1966920&type=pdf %f/ccs/36tbogmrxea0fp8hiqz2jeaskkmwphct.pdf %mb0480d143cb55d5128de8326d6ee51a3 %cccs %@Chow, Sherman S. M., Liu, Joseph K., Zhou, Jianyin %*Identity-based online/offline key encapsulation and encryption %uhttp://dl.acm.org/ft_gateway.cfm?id=1966922&type=pdf %f/ccs/gowuhxea2g1chxfpbqrcojvysd4tmk97.pdf %m0b2527f432d46a75b0370d484c016f96 %cccs %@Baek, Joonsang, Zhou, Jianyin %*Compact identity-based encryption without strong symmetric cipher %uhttp://dl.acm.org/ft_gateway.cfm?id=1966923&type=pdf %f/ccs/un851jy3xpltnmm2atzp7xioa9fhrolc.pdf %me7433356ad5ee823297e8ef798a54ab4 %cccs %@Yang, Guomin, Tan, Chik-Ho %*Strongly secure certificateless key exchange without pairing %uhttp://dl.acm.org/ft_gateway.cfm?id=1966924&type=pdf %f/ccs/y9hqaulozx2bd8rptaecnpkvngsiy57g.pdf %md195eb2c681255be5c191ddab6a16081 %cccs %@Cremers, Ca %*Examining indistinguishability-based security models for key exchange protocols: the case of CK, CK-HMQV, and eCK %uhttp://dl.acm.org/ft_gateway.cfm?id=1966925&type=pdf %f/ccs/tqf2dr7li3koaiapjvjhesxyubed6nm1.pdf %m34da4728dcfecca61493ea608e216649 %cccs %@Li, Qi, Xu, Mingwei, Wu, Jianping, Zhang, Xinwen, Lee, Patrick P. C., Xu, K %*Enhancing the trust of internet routing with lightweight route attestation %uhttp://dl.acm.org/ft_gateway.cfm?id=1966927&type=pdf %f/ccs/kehxbasb9mgauetkgnfqwhcyp123o7vq.pdf %ma11b385ded5567a304d30efa8f7cfde2 %cccs %@Alsaleh, Mansour, van Oorschot, P. C %*Network scan detection with LQS: a lightweight, quick and stateful algorithm %uhttp://dl.acm.org/ft_gateway.cfm?id=1966928&type=pdf %f/ccs/dyoyjxgsk3er0f4alpnbkm8vn27uhw1m.pdf %m79ad4ea053ec5e10951a21dfd707f473 %cccs %@Rangasamy, Jothi, Stebila, Douglas, Boyd, Colin, Nieto, Juan Gonzále %*An integrated approach to cryptographic mitigation of denial-of-service attacks %uhttp://dl.acm.org/ft_gateway.cfm?id=1966929&type=pdf %f/ccs/odqonjsm1eq802jzr76trixxt3vhfhgk.pdf %m7421e50112f7133820342434f9488056 %cccs %@Zhang, Junjie, Luo, Xiapu, Perdisci, Roberto, Gu, Guofei, Lee, Wenke, Feamster, Nic %*Boosting the scalability of botnet detection using adaptive traffic sampling %uhttp://dl.acm.org/ft_gateway.cfm?id=1966930&type=pdf %f/ccs/ovkfp9iq0wugsnatue3db1djyxch574t.pdf %mf712b7e078a751c2b9ec2e13bedc8ea1 %cccs %@Shan, Zhiyong, Wang, Xin, Chiueh, Tzi-cke %*Tracer: enforcing mandatory access control in commodity OS with the support of light-weight intrusion detection and tracing %uhttp://dl.acm.org/ft_gateway.cfm?id=1966932&type=pdf %f/ccs/gr61vnwq9ezxp2bloaost5sjjtirkvxz.pdf %m4702f8ab8aad86b85b04c4128eee8cf3 %cccs %@Minami, Kazuhiro, Borisov, Nikita, Winslett, Marianne, Lee, Adam J %*Confidentiality-preserving proof theories for distributed proof systems %uhttp://dl.acm.org/ft_gateway.cfm?id=1966933&type=pdf %f/ccs/ric4egk8fztrucqhb1wxs5lbjl7xuq0d.pdf %m0173c3613810585ff159c3541842c84e %cccs %@Kirkpatrick, Michael S., Kerr, Sam, Bertino, Elis %*PUF ROKs: a hardware approach to read-once keys %uhttp://dl.acm.org/ft_gateway.cfm?id=1966934&type=pdf %f/ccs/ytkjcvgboaen0wlfen6qxlzsu3uodrv4.pdf %m7839ab8eb830d531a60bea3882b9c59f %cccs %@Alberti, Francesco, Armando, Alessandro, Ranise, Silvi %*Efficient symbolic automated analysis of administrative attribute-based RBAC-policies %uhttp://dl.acm.org/ft_gateway.cfm?id=1966935&type=pdf %f/ccs/in35ktd8vdtl9zwoehpbnm42uha1sxjy.pdf %m98e2b8e0b57b7990e185a73affc9d47a %cccs %@Wiesmaier, Alex, Horsch, Moritz, Braun, Johannes, Kiefer, Franziskus, Hhnlein, Detlef, Strenzke, Falko, Buchmann, Johanne %*An efficient mobile PACE implementation %uhttp://dl.acm.org/ft_gateway.cfm?id=1966936&type=pdf %f/ccs/zva8o7qbh6rp0fm9scupsdhwib3wq2ua.pdf %m237ad0f25357e9c6a86cc05c088a77f5 %cccs %@Chen, Kevin Zhijie, Gu, Guofei, Zhuge, Jianwei, Nazario, Jose, Han, Xinhu %*WebPatrol: automated collection and replay of web-based malware scenarios %uhttp://dl.acm.org/ft_gateway.cfm?id=1966938&type=pdf %f/ccs/u0kupxt62yjwr8li3zfql5jx4nbgmfwm.pdf %mfe835dfa2e0610e8dc8b76bd1901bd22 %cccs %@Yan, Guanhua, Chen, Guanling, Eidenbenz, Stephan, Li, Na %*Malware propagation in online social networks: nature, dynamics, and defense implications %uhttp://dl.acm.org/ft_gateway.cfm?id=1966939&type=pdf %f/ccs/tpsslooyfzmrzf13lry29juemg8e7hgv.pdf %md126ce59403daff646d8c7e82ceab245 %cccs %@Rhee, Junghwan, Lin, Zhiqiang, Xu, Dongya %*Characterizing kernel malware behavior with kernel data access patterns %uhttp://dl.acm.org/ft_gateway.cfm?id=1966940&type=pdf %f/ccs/ntyijnawmqf3zz05p9cbwlat4ijoeqeh.pdf %m8cf4a7632203269b10a8c18d9e0bdef4 %cccs %@Liang, Bin, You, Wei, Shi, Wenchang, Liang, Zhaohu %*Detecting stealthy malware with inter-structure and imported signatures %uhttp://dl.acm.org/ft_gateway.cfm?id=1966941&type=pdf %f/ccs/7ujbdqwai34mz5lvyteyhlz9fwmrhcqp.pdf %m836c34aa43851dc71df5930791038421 %cccs %@Chu, Cheng-Kang, Zhu, Wen Tao, Chow, Sherman S. M., Zhou, Jianying, Deng, Robert H %*Secure mobile subscription of sensor-encrypted data %uhttp://dl.acm.org/ft_gateway.cfm?id=1966943&type=pdf %f/ccs/oqluvjtnasihluwb9iymwjqm20yzhra5.pdf %m465feac3a97330cc24b7ed6b594501c2 %cccs %@Hasan, Ragib, Winslett, Mariann %*Efficient audit-based compliance for relational data retention %uhttp://dl.acm.org/ft_gateway.cfm?id=1966944&type=pdf %f/ccs/dqdlspqp3wahhg7emnfwkif0zge5ytra.pdf %m08408ae0fd9cb7a6e4bddf51d0da54b0 %cccs %@Conti, Mauro, Zachia-Zlatea, Irina, Crispo, Brun %*Mind how you answer me!: transparently authenticating the user of a smartphone when answering or placing a call %uhttp://dl.acm.org/ft_gateway.cfm?id=1966945&type=pdf %f/ccs/xdnuc3al4wgxoj6hm0r2nt9adhbwqoz1.pdf %mc30f9c2bfab8e5a6b79863896e982d3d %cccs %@Yuen, Tsz Hon, Liu, Joseph K., Au, Man Ho, Susilo, Willy, Zhou, Jianyin %*Threshold ring signature without random oracles %uhttp://dl.acm.org/ft_gateway.cfm?id=1966947&type=pdf %f/ccs/qdz4u19bvyeiznknaxticem367sv2aum.pdf %mf1b492192094b68118daefaaba9b11ae %cccs %@Xia, Fubiao, Wang, Guilin, Xue, Ru %*On the invisibility of designated confirmer signatures %uhttp://dl.acm.org/ft_gateway.cfm?id=1966948&type=pdf %f/ccs/tenvl6gjpiybhmeon745yartud0dxcs9.pdf %mbfd42c4e36d5e78be5028ac2e7c26d07 %cccs %@Wei, Lei, Coull, Scott E., Reiter, Michael K %*Bounded vector signatures and their applications %uhttp://dl.acm.org/ft_gateway.cfm?id=1966949&type=pdf %f/ccs/jo9nixuxrg3bsqydnfw1hp0rzetgmmsu.pdf %m86593013cccc3557bdac5c291f6b1bbf %cccs %@Manulis, Mark, Poettering, Bertra %*Practical affiliation-hiding authentication from improved polynomial interpolation %uhttp://dl.acm.org/ft_gateway.cfm?id=1966950&type=pdf %f/ccs/ip0m6a1bvhekhtyulnfgso75leqcgzja.pdf %m4d31b2e267e56ee752f03fc27de6a0bd %cccs %@Abdul-Latip, Shekh Faisal, Reyhanitabar, Mohammad Reza, Susilo, Willy, Seberry, Jennife %*Extended cubes: enhancing the cube attack by extracting low-degree non-linear equations %uhttp://dl.acm.org/ft_gateway.cfm?id=1966952&type=pdf %f/ccs/now2b4sh7kwqszztyemlv0r6hqnbytaj.pdf %m1c4475d2e60abd84514d7e35a6752d0d %cccs %@Molloy, Ian, Li, Ninghu %*Attack on the GridCode one-time password %uhttp://dl.acm.org/ft_gateway.cfm?id=1966953&type=pdf %f/ccs/uyyrg45sgvkkjwmlc91ahahzjqsobtnu.pdf %m4e175a4567f7224d42be50a337d14d94 %cccs %@Li, Zhiwei, Wang, Weicha %*Rethinking about guessing attacks %uhttp://dl.acm.org/ft_gateway.cfm?id=1966954&type=pdf %f/ccs/lhfe6ypxn0acgbplt87iqzfoma24tkwk.pdf %m9bef132242074f7142b202a730ad1a86 %cccs %@Groza, Bogdan, Minea, Mariu %*Formal modelling and automatic detection of resource exhaustion attacks %uhttp://dl.acm.org/ft_gateway.cfm?id=1966955&type=pdf %f/ccs/4temlksqxyjnfph39hrvzu62sqgwwdfo.pdf %mc99ac85393d9c229df3f1b053c83b338 %cccs %@Yan, Qiang, Han, Jin, Li, Yingjiu, Deng, Robert H., Li, Tieya %*A software-based root-of-trust primitive on multicore platforms %uhttp://dl.acm.org/ft_gateway.cfm?id=1966957&type=pdf %f/ccs/7khrmak48is2ng15cxg0pzyfipzc9ve3.pdf %mf68ebdb46b4458fc670bea7adb3b5468 %cccs %@Fenz, Stefa %*An ontology- and Bayesian-based approach for determining threat probabilities %uhttp://dl.acm.org/ft_gateway.cfm?id=1966958&type=pdf %f/ccs/gnfvh6gorqlesdi4v7wnhjekmtytzosp.pdf %med541a07c51047bb133e9387477f7436 %cccs %@Cárdenas, Alvaro A., Amin, Saurabh, Lin, Zong-Syun, Huang, Yu-Lun, Huang, Chi-Yen, Sastry, Shanka %*Attacks against process control systems: risk assessment, detection, and response %uhttp://dl.acm.org/ft_gateway.cfm?id=1966959&type=pdf %f/ccs/icqgekvbcfgqaxrthfp24xedklm3ap71.pdf %mdc294c560a220fa260b7d5b368551707 %cccs %@Backes, Michael, Berg, Matthias, Köpf, Bori %*Non-uniform distributions in quantitative information-flow %uhttp://dl.acm.org/ft_gateway.cfm?id=1966960&type=pdf %f/ccs/zvbuyhfrxikgu5jf2ylhieoscparp38w.pdf %m3114025ed09f2373aaf6ba3313082f4a %cccs %@Susilo, Willy, Baek, Joonsan %*On the security of the identity-based encryption based on DHIES from ASIACCS 2010 %uhttp://dl.acm.org/ft_gateway.cfm?id=1966962&type=pdf %f/ccs/fknlb2zpwggjrh6hidmslxrqz4uaavb8.pdf %m05f0e68292e43a0f0aae5f3bff375944 %cccs %@Lin, Huang, Cao, Zhenfu, Fang, Yuguang, Zhou, Muxin, Zhu, Haoji %*How to design space efficient revocable IBE from non-monotonic ABE %uhttp://dl.acm.org/ft_gateway.cfm?id=1966963&type=pdf %f/ccs/8gon1mszsrb6rxkjcvoqtjzcbdawgfeu.pdf %mcb90bda5868541cd39b2c576ee4684bc %cccs %@Li, Jin, Huang, Qiong, Chen, Xiaofeng, Chow, Sherman S. M., Wong, Duncan S., Xie, Dongqin %*Multi-authority ciphertext-policy attribute-based encryption with accountability %uhttp://dl.acm.org/ft_gateway.cfm?id=1966964&type=pdf %f/ccs/wjs235cwpker6velnmxig1s7tm0oqdxi.pdf %mcf05087be96c0aefcecb0ae65b563f88 %cccs %@Kutyłowski, Mirosław, Shao, Ju %*1-out-of-2 signature %uhttp://dl.acm.org/ft_gateway.cfm?id=1966965&type=pdf %f/ccs/xbraa5hivdstcnm7owtlgnv4f0wg9jxy.pdf %m701a98bb254c3d2a05d06a07351cdc90 %cccs %@Li, Nan, Mu, Yi, Susilo, Willy, Guo, Fuchu %*Self-certified ring signatures %uhttp://dl.acm.org/ft_gateway.cfm?id=1966966&type=pdf %f/ccs/yf7msvio4lchcronft3uh9pkdtqyjwsv.pdf %m213825e4b4a3cb8f80c1b9652a4ea47f %cccs %@Chow, Sherman S. M., Au, Man Ho, Susilo, Will %*Server-aided signatures verification secure against collusion attack %uhttp://dl.acm.org/ft_gateway.cfm?id=1966967&type=pdf %f/ccs/tknediv8lqpm9yjykxmr0bs1jgwuoop4.pdf %m90aef37acc910f15cd14d6a6679f7d12 %cccs %@Wang, Qihua, Jin, Hongxi %*Quantified risk-adaptive access control for patient privacy protection in health information systems %uhttp://dl.acm.org/ft_gateway.cfm?id=1966969&type=pdf %f/ccs/jzbf4ahthoqzkgju59p3x1lcoxsmaglr.pdf %mde97b753c7085e4a7e282ccd75e4a1c3 %cccs %@Jahid, Sonia, Mittal, Prateek, Borisov, Nikit %*EASiER: encryption-based access control in social networks with efficient revocation %uhttp://dl.acm.org/ft_gateway.cfm?id=1966970&type=pdf %f/ccs/65e78sladtf0u2cdkivy4tayzq9eopuc.pdf %mb21398d5ea8e30d04a7c7cfb28a768a7 %cccs %@Felt, Adrienne Porter, Finifter, Matthew, Weinberger, Joel, Wagner, Davi %*Diesel: applying privilege separation to database access %uhttp://dl.acm.org/ft_gateway.cfm?id=1966971&type=pdf %f/ccs/bkjivstqdbsf2rcd5na3plqtgy0rxwxn.pdf %ma593decf4fe92b8e7e2a9a3e0f1d0758 %cccs %@Basin, David, Burri, Samuel J., Karjoth, Günte %*Separation of duties as a service %uhttp://dl.acm.org/ft_gateway.cfm?id=1966972&type=pdf %f/ccs/eiyt0y9gpkmczv3bkjgucm2nobqffth8.pdf %m4b00fea37fdc0d02d42d6c8373cfa5d7 %cccs %@Adams, Andrew K., Lee, Adam J., Mossé, Danie %*Receipt-mode trust negotiation: efficient authorization through outsourced interactions %uhttp://dl.acm.org/ft_gateway.cfm?id=1966973&type=pdf %f/ccs/jgnrznsbkp9ml7oflda0ywzewc15vkqc.pdf %mbb9f37adfca054addabb7273220aca6c %cccs %@Zhao, Jianjie, Gu, Dawu, Gorantla, M. Choudar %*Stronger security model of group key agreement %uhttp://dl.acm.org/ft_gateway.cfm?id=1966975&type=pdf %f/ccs/pmag8wp5mifhi96nekcxe2brbc7duy3g.pdf %m39e021f25b59927c71944f75a8970522 %cccs %@Moriyama, Daisuke, Okamoto, Tatsuak %*Leakage resilient eCK-secure key exchange protocol without random oracles %uhttp://dl.acm.org/ft_gateway.cfm?id=1966976&type=pdf %f/ccs/sk61kfb4gqhb2szea59uwpapqcrjmthj.pdf %m18ab33d2ac82704990a534b699c79cee %cccs %@Morozov, Kirill, Savvides, Georg %*Efficient computational oblivious transfer using interactive hashing %uhttp://dl.acm.org/ft_gateway.cfm?id=1966977&type=pdf %f/ccs/58sl6w31brmo9nkthdqyaekpgc2sa0pc.pdf %md97671b82456e2643ec04bb439f45b08 %cccs %@Safavi-Naini, Reihaneh, Tuhin, Mohammed Ashraful Alam, Shi, Hongson %*Optimal message transmission protocols with flexible parameters %uhttp://dl.acm.org/ft_gateway.cfm?id=1966978&type=pdf %f/ccs/aytb9kc0yakuvwmigh6jpsq21gtxcsof.pdf %m54ac667411cf417592dc1a1425d46857 %cccs %@Sun, Yue, Wang, Meiqin, Sun, Qiume %*How to search linear approximation for large non-surjective S-box %uhttp://dl.acm.org/ft_gateway.cfm?id=1966979&type=pdf %f/ccs/5gj4vmyr27xgbyolzdwjpqskihcwvfnu.pdf %mcfa139af10f7166b434f5a56f010b63a %cccs %@Chen, Caisen, Wang, Ta %*A new and extended fault analysis on RSA %uhttp://dl.acm.org/ft_gateway.cfm?id=1966980&type=pdf %f/ccs/nyc2nhsevftquaazm1lxo5rwjgm9phli.pdf %m3694434c48a4bb0fac5d43a953857f6e %cccs %@Chim, T. W., Hui, Lucas C. K., Yiu, S. M., Li, Victor O. K %* MLAS : multiple level authentication scheme for VANETs %uhttp://dl.acm.org/ft_gateway.cfm?id=1966982&type=pdf %f/ccs/fqz3x8epimydiwatu0sn2klnpvhzoery.pdf %m84438a250642db81fccbbadd98945ca9 %cccs %@Jorgensen, Zach, Yu, Tin %*On mouse dynamics as a behavioral biometric for authentication %uhttp://dl.acm.org/ft_gateway.cfm?id=1966983&type=pdf %f/ccs/gh6vkasbojljg3qzcobyzeiuedmfwium.pdf %mad99e108a79b8f0147c42a992146b7aa %cccs %@Peddinti, Sai Teja, Saxena, Nites %*On the effectiveness of anonymizing networks for web search privacy %uhttp://dl.acm.org/ft_gateway.cfm?id=1966984&type=pdf %f/ccs/mdta8py5fkvc2vpurfs34zwx6sneomji.pdf %mef9ab88e05ca9295279d78f413039504 %cccs %@Oishi, Kazuomi, Matsumoto, Tsutom %*Self destructive tamper response for software protection %uhttp://dl.acm.org/ft_gateway.cfm?id=1966985&type=pdf %f/ccs/hgwlb5ejf1y4j7kyrms6xinlae8w3utp.pdf %mb302f5415e53bfaded9dbc6b96962c3d %cccs %@Park, Younghee, Reeves, Dougla %*Deriving common malware behavior through graph clustering %uhttp://dl.acm.org/ft_gateway.cfm?id=1966986&type=pdf %f/ccs/oqxynlgzwd0c4uz6hripgvaanm2tlwxd.pdf %mb324e7d762da1087b48b793a4272ed9b %cccs %@Wu, Yongzheng, Yap, Roland H. C %*Towards a binary integrity system for windows %uhttp://dl.acm.org/ft_gateway.cfm?id=1966987&type=pdf %f/ccs/oibus3evc0int7qjbydenf1ayarzvxpl.pdf %m172cf102708de34c6d7ceaf8f3fe3eab %cccs %@Rrushi, Julian, Mokhtari, Ehsan, Ghorbani, Ali A %*A statistical approach to botnet virulence estimation %uhttp://dl.acm.org/ft_gateway.cfm?id=1966988&type=pdf %f/ccs/egrmq7xtifgkwehf6ysbjpncvjqubhk1.pdf %m2f09b0999b3dfb69a4ee4c607ed116e4 %cccs %@Wolchok, Scott, Wustrow, Eric, Halderman, J. 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Wu %*Watermarking Cryptographic Functionalities from Standard Lattice Assumptions %f/crypto/nxbr5nzfiuaeebwav3yj6k9qdko2msz0.pdf %m382a9f97e70ed475160cf034fb2d60d9 %ccrypto %@Nico Döttling,Sanjam Garg %*Identity-Based Encryption from the Diffie-Hellman Assumption %f/crypto/otnhwqjygcv31yq6mdflu9woebx2xmck.pdf %m3fc43d72e699b1985c53455980539555 %ccrypto %@Marc Stevens,Elie Bursztein,Pierre Karpman,Ange Albertini,Yarik Markov %*The First Collision for Full SHA-1 %f/crypto/mxox65la9zfkbsskg7c4riuveghtrazy.pdf %m8eb72252ccbcc656a2bfbb515ff680a6 %ccrypto %@Huijia Lin %*Indistinguishability Obfuscation from SXDH on 5-Linear Maps and Locality-5 PRGs %f/crypto/ugk6yrj3pen2iztjyp05wvhcm4xzu9fk.pdf %m92bfd099bb4759512175f3b2ad38a0a9 %ccrypto %@Huijia Lin,Stefano Tessaro %*Indistinguishability Obfuscation from Trilinear Maps and Block-Wise Local PRGs %f/crypto/s4jp56tn2gfhcyc7bavslqkwq3rteivj.pdf %m385f552d895b39a5de58feace5fa725d %ccrypto %@Sanjam Garg,Mohammad Mahmoody,Ameer Mohammed %*Lower Bounds on Obfuscation from All-or-Nothing Encryption Primitives %f/crypto/eh03rijqun5pkbyv1rimktfhdd2vegat.pdf %m3d5b97f9ad9454bebdc840d773a3d26a %ccrypto %@Nir Bitansky,Akshay Degwekar,Vinod Vaikuntanathan %*Structure vs. Hardness Through the Obfuscation Lens %f/crypto/unphf0xey7bxtrc9elzpisrz2a8qyj4b.pdf %maf0612eb5880284d50369ad445937d11 %ccrypto %@Benny Applebaum,Barak Arkis,Pavel Raykov,Prashant Nalini Vasudevan %*Conditional Disclosure of Secrets: Amplification, Closure, Amortization, Lower-Bounds, and Separations %f/crypto/9sp8aqqndb4j16ugouxkjfelk5t7yhzw.pdf %m520c1271ef2985c7be0d5d864f84689b %ccrypto %@Tianren Liu,Vinod Vaikuntanathan,Hoeteck Wee %*Conditional Disclosure of Secrets via Non-linear Reconstruction %f/crypto/ay52zjcnhtxhbmu7fkrxkg3ygorlvnli.pdf %mffca2982b27252a67e0a1fddb1535011 %ccrypto %@Alexander R. Block,Hemanta K. Maji,Hai H. Nguyen %*Secure Computation Based on Leaky Correlations: High Resilience Setting %f/crypto/3tgmz9l75jodo8gsdxnwaecsvqlqiuxe.pdf %m9773aa3bbb909bff6311c08beb81ac13 %ccrypto %@Chongwon Cho,Nico Döttling,Sanjam Garg,Divya Gupta,Peihan Miao,Antigoni Polychroniadou %*Laconic Oblivious Transfer and Its Applications %f/crypto/tqtwjzfakvyndbd7c2ej1woscmnxeirb.pdf %m8f8247c94bbd6a0c48c90e3266cab941 %ccrypto %@Steve Lu,Rafail Ostrovsky %*Black-Box Parallel Garbled RAM %f/crypto/lz0hbgd4jfyol5x9mmvqbcrpe61kdw3z.pdf %m2607e50291c9bdc2ad5c7e63f7f06417 %ccrypto %@Sebastian Faust,Kristina Hostáková,Pratyay Mukherjee,Daniele Venturi %*Non-Malleable Codes for Space-Bounded Tampering %f/crypto/mph86gkzdfmawyzrsbcjpit94uhdba1i.pdf %m4ade3a9bf82a3ab2abb059bffa61dc3b %ccrypto %@Michele Ciampi,Rafail Ostrovsky,Luisa Siniscalchi,Ivan Visconti %*Four-Round Concurrent Non-Malleable Commitments from One-Way Functions %f/crypto/vjo3vmsoewuchzar6ydfijytlqgxm5gk.pdf %m8a98efacf917e404694413c0b4d4bac4 %ccrypto %@Abhishek Jain,Yael Tauman Kalai,Dakshita Khurana,Ron Rothblum %*Distinguisher-Dependent Simulation in Two Rounds and its Applications %f/crypto/rkib3fahpqusv2p8nloc1wgc5ldexmt4.pdf %md1c485b9f3d670e3f96efdabbabefd90 %ccrypto %@Sanjam Garg,Omkant Pandey %*Incremental Program Obfuscation %f/crypto/ylxqeibjfagucwdunn8bahmzocv5g1dz.pdf %m4dae2db7b82fff7a1ad9e1b18614c415 %ccrypto %@Yael Tauman Kalai,Guy N. Rothblum,Ron D. Rothblum %*From Obfuscation to the Security of Fiat-Shamir for Proofs %f/crypto/wxc3jnnbldoj0k2sfreyahi8zc51ubq9.pdf %m4dffe452b9f31b202eceaec87b785584 %ccrypto %@Prabhanjan Ananth,Abhishek Jain,Amit Sahai %*Indistinguishability Obfuscation for Turing Machines: Constant Overhead and Amortization %f/crypto/bkn2ubymupvqtj4srrpdx10dcnzq6ea9.pdf %mdeedb50166dfced547afa388a553502e %ccrypto %@Fang Song,Aaram Yun %*Quantum Security of NMAC and Related Constructions %f/crypto/68ldhwksi45bwnnfluecdipytsac2vga.pdf %m5e8afcc5f3c157f17ab976d799d938b0 %ccrypto %@Gorjan Alagic,Christian Majenz %*Quantum Non-malleability and Authentication %f/crypto/0rm5nutoay1qjshyv9bcgdpezlizb8ax.pdf %ma5e53f482296f2b438e542138d2b4e0d %ccrypto %@Sumegha Garg,Henry Yuen,Mark Zhandry %*New Security Notions and Feasibility Results for Authentication of Quantum Data %f/crypto/tcpgvmputhmbrohz8rssz390y4lcifoa.pdf %m4f6ca5f4724252412ed804f8cd942788 %ccrypto %@Zhenzhen Bao,Lei Wang,Jian Guo,Dawu Gu %*Functional Graph Revisited: Updates on (Second) Preimage Attacks on Hash Combiners %f/crypto/qvuwclr6cmzxgdi57ssa4oqj8fz3nbrh.pdf %md56b43f1a33bed131588afd740815a01 %ccrypto %@Ling Song,Guohong Liao,Jian Guo %*Non-full Sbox Linearization: Applications to Collision Attacks on Round-Reduced Keccak %f/crypto/lwzivnyh3whrpyx9j6caqaxmpbti2b0c.pdf %m099baf65896c2279f028b82d875c8564 %ccrypto %@Daniele Micciancio,Michael Walter %*Gaussian Sampling over the Integers: Efficient, Generic, Constant-Time %f/crypto/vpydzzb45maggheq1tirot79ynqlwesk.pdf %md6b28783e775cd35a8275e7db1b95fd7 %ccrypto %@Andre Esser,Robert Kübler,Alexander May %*LPN Decoded %f/crypto/aslah9ottcekk30g7nwx4jvbrq2smf15.pdf %mb9643ce413b13104e75ba41766dc303b %ccrypto %@Fuchun Guo,Rongmao Chen,Willy Susilo,Jianchang Lai,Guomin Yang,Yi Mu %*Optimal Security Reductions for Unique Signatures: Bypassing Impossibilities with a Counterexample %f/crypto/qjmyb1h7bpfn4ktlcrree65hpdwuougm.pdf %m254149c1853d91b3807a12619829b0cb %ccrypto %@Masayuki Abe,Dennis Hofheinz,Ryo Nishimaki,Miyako Ohkubo,Jiaxin Pan %*Compact Structure-Preserving Signatures with Almost Tight Security %f/crypto/9gxc485bdknprfmz10zbj6aqtosnuqyl.pdf %m4192b7d4d9d50e919523755ac47698f2 %ccrypto %@Jens Groth,Mary Maller %*Snarky Signatures: Minimal Signatures of Knowledge from Simulation-Extractable SNARKs %f/crypto/hwhvrywn46zl5qjomj7q1s8lrkaa0kfn.pdf %m6b61b3da3ebf06195911a89e05b9f574 %ccrypto %@Yehuda Lindell %*Fast Secure Two-Party ECDSA Signing %f/crypto/0h6w7ahjc1gy2c3dbqxanwqk4uomeemt.pdf %m479729bbe137f7b6353f4ec3a0467ebf %ccrypto %@Christof Beierle,Anne Canteaut,Gregor Leander,Yann Rotella %*Proving Resistance Against Invariant Attacks: How to Choose the Round Constants %f/crypto/j8oc1hxauqetinkyrd97dyjnba4ulkpq.pdf %m00834e0b9461291d81fc92fd87f4fd2c %ccrypto %@F. Betül Durak,Serge Vaudenay %*Breaking the FF3 Format-Preserving Encryption Standard over Small Domains %f/crypto/ccdkf6q50falzh3d1qtkiu7wwevaxxro.pdf %m894604cbbbe3e85478b9d08615092239 %ccrypto %@Bart Mennink %*Insuperability of the Standard Versus Ideal Model Gap for Tweakable Blockcipher Security %f/crypto/r5z27cfswvdkma0nj9mxq8eyqusiuogv.pdf %me9b2ac86f98237172f9190d49dd71e18 %ccrypto %@Tomer Ashur,Orr Dunkelman,Atul Luykx %*Boosting Authenticated Encryption Robustness with Minimal Modifications %f/crypto/cadfmi1mpgl5ikwectdsfs29j3tqlzug.pdf %m35d1b245645fd098442e50c902e5dc22 %ccrypto %@Tetsu Iwata,Kazuhiko Minematsu,Thomas Peyrin,Yannick Seurin %*ZMAC: A Fast Tweakable Block Cipher Mode for Highly Secure Message Authentication %f/crypto/uza6krs7ugr1pctvdlft5aplix2ew4kj.pdf %me5335b101389de03a0cec6d94a52e345 %ccrypto %@Paul Grubbs,Jiahui Lu,Thomas Ristenpart %*Message Franking via Committing Authenticated Encryption %f/crypto/rsxopvfiyyiaef6xatnzm7pgcn4rj8wq.pdf %m877b4e5aedbf06481d5e6e0df7193b87 %ccrypto %@Adam Everspaugh,Kenneth Paterson,Thomas Ristenpart,Sam Scott %*Key Rotation for Authenticated Encryption %f/crypto/rvet8wi3uxm4omi1gvbsnsltjr2af5ko.pdf %me355771fc52512c63699797bf49e69bb %ccrypto %@Romain Gay,Dennis Hofheinz,Lisa Kohl %*Kurosawa-Desmedt Meets Tight Security %f/crypto/xlgxsiceit97jamwebro5ucbrldkd4n1.pdf %me1a57c1a0d56ab706a664d637836d878 %ccrypto %@Shota Yamada %*Asymptotically Compact Adaptively Secure Lattice IBEs and Verifiable Random Functions via Generalized Partitioning Techniques %f/crypto/76h3sxngt4ahw2jcfleobm15r0ylicre.pdf %m90705ab7e9fe3695b68398d5f25e0674 %ccrypto %@Philippe Gaborit,Adrien Hauteville,Duong Hieu Phan,Jean-Pierre Tillich %*Identity-Based Encryption from Codes with Rank Metric %f/crypto/9xiswomgolzyhcz04ujd7ybrk26rqnws.pdf %mb8eea5bf0a03e070061894365c076632 %ccrypto %@Meicheng Liu %*Degree Evaluation of NFSR-Based Cryptosystems %f/crypto/o1ytguynwvvksc4hcmq5lpxziz6sdjb9.pdf %md13ac94a3a4945f4283ddc5db7741bb7 %ccrypto %@Yosuke Todo,Takanori Isobe,Yonglin Hao,Willi Meier %*Cube Attacks on Non-Blackbox Polynomials Based on Division Property %f/crypto/cl45xfgnax9bhaoj21fmczrebddkq0sy.pdf %mea39d0e0789bf96b10aa8412176f71eb %ccrypto %@Miruna Roşca,Amin Sakzad,Damien Stehlé,Ron Steinfeld %*Middle-Product Learning with Errors %f/crypto/0qkidi3faull8rtkco7afdh1jmvm9szy.pdf %m2cf1103a602a97e73bf91e6800a8d687 %ccrypto %@Xavier Boyen,Qinyi Li %*All-But-Many Lossy Trapdoor Functions from Lattices and Applications %f/crypto/rwnbpieoe0j7gcim8xt5sfhvl4uoqny3.pdf %m048ae668b98205915bbe8449cb277f77 %ccrypto %@Benoît Libert,Amin Sakzad,Damien Stehlé,Ron Steinfeld %*All-But-Many Lossy Trapdoor Functions and Selective Opening Chosen-Ciphertext Security from LWE %f/crypto/mqhps1kpdqwoauabkf5rwj093ngemxj2.pdf %m21204177cf83c7b9e0bd0e18669fd2e7 %ccrypto %@Rafael del Pino,Vadim Lyubashevsky %*Amortization with Fewer Equations for Proving Knowledge of Small Secrets %f/crypto/aqpcn6emkddbzlgttvfsxirwbosq9vu4.pdf %m195ca74c3e9b555e218cc1db23d874bf %ccrypto %@Sonia Belaïd,Fabrice Benhamouda,Alain Passelègue,Emmanuel Prouff,Adrian Thillard,Damien Vergnaud %*Private Multiplication over Finite Fields %f/crypto/drfeiwumblxmnjtz1la6pnotwqhj5yab.pdf %mf4297a319c5820b495c7fed3b85e6024 %ccrypto %@Jan Camenisch,Manu Drijvers,Anja Lehmann %*Anonymous Attestation with Subverted TPMs %f/crypto/wmd6a5xusbao9uycmc1ys32hp7ejxrkg.pdf %ma34e43e1cbec6ef2e2e3c4c70c90f400 %ccrypto %@Alexandra Boldyreva,Christopher Patton,Thomas Shrimpton %*Hedging Public-Key Encryption in the Real World %f/crypto/6nr2y7ctemlzbmifz5nbfhjhpx4gyuqw.pdf %m6f5cdcfd8e89a041e2c92aea166622ec %ccrypto %@Wei Dai,Viet Tung Hoang,Stefano Tessaro %*Information-Theoretic Indistinguishability via the Chi-Squared Method %f/crypto/jrcf08xbdu9352dyostrhqc4s1kzmpez.pdf %m7fbf2148749d718f4f5b23284beaf57f %ccrypto %@Yuanxi Dai,Yannick Seurin,John Steinberger,Aishwarya Thiruvengadam %*Indifferentiability of Iterated Even-Mansour Ciphers with Non-idealized Key-Schedules: Five Rounds Are Necessary and Sufficient %f/crypto/vuicx390aodfmzzrybntl6niwqgtdhsy.pdf %m10388c92ceedb0422725672faee7e7f2 %ccrypto %@Bart Mennink,Samuel Neves %*Encrypted Davies-Meyer and Its Dual: Towards Optimal Security Using Mirror Theory %f/crypto/h6irtpd0o1esq2utxkl3ynji5qdznaox.pdf %mabfa206f6b8d1c157bcd372314e07f95 %ccrypto %@Felix Günther,Sogol Mazaheri %*A Formal Treatment of Multi-key Channels %f/crypto/k2ysr4ae5b86qjmktxfblyo10evccmha.pdf %m5e5255544970224fcb21e42c6b12b04a %ccrypto %@Mihir Bellare,Asha Camper Singh,Joseph Jaeger,Maya Nyayapati,Igors Stepanovs %*Ratcheted Encryption and Key Exchange: The Security of Messaging %f/crypto/evfhxar1mlrscq0bmngozu34o79jpkny.pdf %m2ad7a24dd5c87643a5b63c549ee48655 %ccrypto %@Jacqueline Brendel,Marc Fischlin,Felix Günther,Christian Janson %*PRF-ODH: Relations, Instantiations, and Impossibility Results %f/crypto/i0jnzlfaymgorkxohaqusm6c2ybelbg8.pdf %mdc93213540e46505f3bcff415a40f18e %ccrypto %@Joanne Woodage,Rahul Chatterjee,Yevgeniy Dodis,Ari Juels,Thomas Ristenpart %*A New Distribution-Sensitive Secure Sketch and Popularity-Proportional Hashing %f/crypto/mpqp39vkh06soi2jgi8nducjayytt51a.pdf %m42b1c5005cadbf4a7188267772894f46 %ccrypto %@Viet Tung Hoang,Stefano Tessaro %*Key-Alternating Ciphers and Key-Length Extension: Exact Bounds and Multi-user Security %f/crypto/dganti93rpa2xcelr0ydumjnzqc5fibt.pdf %m0de30febb44e480694444772bb9c15a9 %ccrypto %@Thomas Peyrin,Yannick Seurin %*Counter-in-Tweak: Authenticated Encryption Modes for Tweakable Block Ciphers %f/crypto/nvfkldecxzhpyot9qyvbw5ob2zrgciid.pdf %ma49d2f1b81c0977fcb592adc57402cff %ccrypto %@Bart Mennink %*XPX: Generalized Tweakable Even-Mansour with Improved Security Guarantees %f/crypto/vywtteokj3iuiczgd2zc9rbr4xeuhwm8.pdf %m7635e7f0b5df84794da41bf1f134569c %ccrypto %@Yuanxi Dai,John Steinberger %*Indifferentiability of 8-Round Feistel Networks %f/crypto/vddcqmoqtaebzrpufsglx82thwv1ogaj.pdf %m0d6aa8a4a133298e431493ed8ed939f1 %ccrypto %@Benoît Cogliati,Yannick Seurin %*EWCDM: An Efficient, Beyond-Birthday Secure, Nonce-Misuse Resistant MAC %f/crypto/fa0vzswhc1eoje2yrg9wkxzdtiubdqy7.pdf %ma68ad48bfef434c2940612362499e613 %ccrypto %@Martin Albrecht,Shi Bai,Léo Ducas %*A Subfield Lattice Attack on Overstretched NTRU Assumptions %f/crypto/b85hvp69fkjqlfyygrwtdzq37ubapdkc.pdf %m5b553a4099bfd5e5ab5b2dd0c319f746 %ccrypto %@Adi Ben-Zvi,Simon R. Blackburn,Boaz Tsaban %*A Practical Cryptanalysis of the Algebraic Eraser %f/crypto/fmalrlpx8ejbywotzbf0pirw4msxd6nv.pdf %m14ba6f3fdae939c5befb315c2d542e09 %ccrypto %@Zvika Brakerski,Renen Perlman %*Lattice-Based Fully Dynamic Multi-key FHE with Short Ciphertexts %f/crypto/i7evszmjr2ozyudkbkxtlmd89ab4ipfn.pdf %mb42fb807d64cc5c73bc0c173dd2ee3fc %ccrypto %@Yu Yu,Jiang Zhang %*Cryptography with Auxiliary Input and Trapdoor from Constant-Noise LPN %f/crypto/caiogamqonlujtpvq2fhxwmb5gde1u43.pdf %m94ae49435e093ca9ead0a28f1b6a8ae9 %ccrypto %@Mihir Bellare,Björn Tackmann %*The Multi-user Security of Authenticated Encryption: AES-GCM in TLS 1.3 %f/crypto/ruww6ktal0bzce7qdgzik94mfbn2syoi.pdf %ma3942a0811d27242dfcaf522ca690c8b %ccrypto %@Thomas Shrimpton,Martijn Stam,Bogdan Warinschi %*A Modular Treatment of Cryptographic APIs: The Symmetric-Key Case %f/crypto/svczd3y9yhefilr51pqcgnmxmklw6vob.pdf %m5b779beaf178bc8aecf499cc2ca38fdd %ccrypto %@Geoffroy Couteau,Thomas Peters,David Pointcheval %*Encryption Switching Protocols %f/crypto/tqrj9el5owb72frxih6vogz0xnbtfia3.pdf %m830c14955c06ed5cd6075b57bdcd1f6c %ccrypto %@Yevgeniy Dodis,Ilya Mironov,Noah Stephens-Davidowitz %*Message Transmission with Reverse Firewalls—Secure Communication on Corrupted Machines %f/crypto/y72ohe3ska4jptcj56dytnalnqvbbug1.pdf %m834abeeb64f4c895972675bff1a5a5ac %ccrypto %@Mihir Bellare,Daniel Kane,Phillip Rogaway %*Big-Key Symmetric Encryption: Resisting Key Exfiltration %f/crypto/lalsxz6o3cpgqidmb9iv5jkewf1pdmca.pdf %mf391ecce37a55ebeb38d8c0675343871 %ccrypto %@Jean Paul Degabriele,Kenneth G. Paterson,Jacob C. N. Schuldt,Joanne Woodage %*Backdoors in Pseudorandom Number Generators: Possibility and Impossibility Results %f/crypto/kavbckm3ysje2yl8w64nbquardfx9qvp.pdf %mf982084af88777f0290bbd114f6c4919 %ccrypto %@Achiya Bar-On,Nathan Keller %*A 2^{70} Attack on the Full MISTY1 %f/crypto/llpaskvdhwgovzitseenazx2mtx3jjyq.pdf %m023404c83fd67c932df65d6669169f05 %ccrypto %@Sébastien Duval,Virginie Lallemand,Yann Rotella %*Cryptanalysis of the FLIP Family of Stream Ciphers %f/crypto/akdmduivays6i0ptctvxrge4n5wcwjoz.pdf %ma50004fcf8bef709227d40f091d1b41b %ccrypto %@Mark Zhandry %*The Magic of ELFs %f/crypto/5iqdn4tg1xuswk3fozdqfmlcpynu7hxj.pdf %m5bdb768f1a2c776870f7a0ab029a6282 %ccrypto %@Elette Boyle,Niv Gilboa,Yuval Ishai %*Breaking the Circuit Size Barrier for Secure Computation Under DDH %f/crypto/dpgzxrn7onsyeqlw18z3jgrmyxoqbm2h.pdf %mdac95927d8651afbea4624136f7fb44b %ccrypto %@Taechan Kim,Razvan Barbulescu %*Extended Tower Number Field Sieve: A New Complexity for the Medium Prime Case %f/crypto/t4ounfxkbs03c2pmubfijcrnzqwgshzt.pdf %ma8ca4445587afa26280b992175924004 %ccrypto %@Craig Costello,Patrick Longa,Michael Naehrig %*Efficient Algorithms for Supersingular Isogeny Diffie-Hellman %f/crypto/lg7juqbuneh41mfqsorsvr9epyiiv6bc.pdf %mbd2db36dc305464bc6a667be4feab0d2 %ccrypto %@Bing Sun,Meicheng Liu,Jian Guo,Longjiang Qu,Vincent Rijmen %*New Insights on AES-Like SPN Ciphers %f/crypto/v5ew6funngtasrqxmv0hbkd1c7lz4m9w.pdf %m0382f3ca6c2c762c50bc77ce8974747e %ccrypto %@Christof Beierle,Thorsten Kranz,Gregor Leander %*Lightweight Multiplication in GF(2^n) with Applications to MDS Matrices %f/crypto/8rsdtky2edvyq37nhcgcekamx5qb0owm.pdf %mb88c2d99c83b3cfdcbaadc582d1ae12f %ccrypto %@Christina Boura,Anne Canteaut %*Another View of the Division Property %f/crypto/ujia4hcfvtzk6sgqrdb873rnjp5omtnq.pdf %m313b7954b422cbe198509d15be7a71f5 %ccrypto %@Takashi Yamakawa,Shota Yamada,Goichiro Hanaoka,Noboru Kunihiro %*Adversary-Dependent Lossy Trapdoor Function from Hardness of Factoring Semi-smooth RSA Subgroup Moduli %f/crypto/nff79t2kcjuwydagodamz1vpyq6jtrl8.pdf %m49b631011f7866e5e69deb5e75b91903 %ccrypto %@Eike Kiltz,Daniel Masny,Jiaxin Pan %*Optimal Security Proofs for Signatures from Identification Schemes %f/crypto/pgx4d1fohvye3tlznmqtv6lwyc5a089b.pdf %maa4bb7584e6591deb339c696dd3888ea %ccrypto %@Florian Bourse,Rafaël Del Pino,Michele Minelli,Hoeteck Wee %*FHE Circuit Privacy Almost for Free %f/crypto/hvgqeulkoi61akyxgp4lqdc95z7ctoj8.pdf %m3eee28b5ce42b80fb850dbbd05f9bcd3 %ccrypto %@Léo Perrin,Aleksei Udovenko,Alex Biryukov %*Cryptanalysis of a Theorem: Decomposing the Only Known Solution to the Big APN Problem %f/crypto/mgbxgxzljwy1nui47aracnuwsftre3ym.pdf %m92715faa8b6fbb31f012261bf39e8c69 %ccrypto %@Christof Beierle,Jérémy Jean,Stefan Kölbl,Gregor Leander,Amir Moradi,Thomas Peyrin,Yu Sasaki,Pascal Sasdrich,Siang Meng Sim %*The SKINNY Family of Block Ciphers and Its Low-Latency Variant MANTIS %f/crypto/65vrti1jxnlzutjoo3c0alqecgvwmx9n.pdf %m65563cd3a33debec02c2c6b1ec98dcef %ccrypto %@Patrick Derbez,Pierre-Alain Fouque %*Automatic Search of Meet-in-the-Middle and Impossible Differential Attacks %f/crypto/f3czi6qi5ezuods4ghmj897tlywrrbdk.pdf %m46c8609b04b3c7b282ef6900bbb97152 %ccrypto %@Itai Dinur,Orr Dunkelman,Nathan Keller,Adi Shamir %*Memory-Efficient Algorithms for Finding Needles in Haystacks %f/crypto/k2r8np5f0xh9ta1bcrnlkzjqvuesgqvs.pdf %m75a9e984d84fbcdfec328f557629ed30 %ccrypto %@Marc Kaplan,Gaëtan Leurent,Anthony Leverrier,María Naya-Plasencia %*Breaking Symmetric Cryptosystems Using Quantum Period Finding %f/crypto/01n6uv5goauoxzmvcwydffyqhgibjk3m.pdf %m9414c9c598f0c41806387f9b7fb25015 %ccrypto %@Joël Alwen,Jeremiah Blocki %*Efficiently Computing Data-Independent Memory-Hard Functions %f/crypto/7d9kjasxjhtouw4f2sneb5ezprlz8x6q.pdf %mccf8f6220649a6ed9f3e59d300c996d4 %ccrypto %@Stefan Dziembowski,Sebastian Faust,Gottfried Herold,Anthony Journault,Daniel Masny,François-Xavier Standaert %*Towards Sound Fresh Re-keying with Hard (Physical) Learning Problems %f/crypto/jawgnsrl0copn1xiefjut5vhwz8qkoyb.pdf %mc1a2cfe1a0c61beec064661d0fb9da05 %ccrypto %@Tobias Schneider,Amir Moradi,Tim Güneysu %*ParTI – Towards Combined Hardware Countermeasures Against Side-Channel and Fault-Injection Attacks %f/crypto/dawmrki1vkocgj56pul0njigvpbztxud.pdf %m97d6902770ce0562104df514b551e063 %ccrypto %@Martin Hirt,Ueli Maurer,Daniel Tschudi,Vassilis Zikas %*Network-Hiding Communication and Applications to Multi-party Protocols %f/crypto/tsmcmxkqzkoqw7ugjfyil9blit1sge2w.pdf %md94309723bf345278984f2d9be3a6365 %ccrypto %@Ranjit Kumaresan,Srinivasan Raghuraman,Adam Sealfon %*Network Oblivious Transfer %f/crypto/wdhvlvtwmxc0euepzj76bsarfiridglk.pdf %m6c398d183eb7ea1751b8e327f0852fa6 %ccrypto %@Carmit Hazay,Muthuramakrishnan Venkitasubramaniam %*On the Power of Secure Two-Party Computation %f/crypto/hjyiqbavlzrct934fnso8kf0uit5edrw.pdf %med560bd15f63279f901d64f0cfd90b1b %ccrypto %@Yuval Ishai,Eyal Kushilevitz,Manoj Prabhakaran,Amit Sahai,Ching-Hua Yu %*Secure Protocol Transformations %f/crypto/oqm3fwbl4ptf1nvsorvisrj72nmbtzua.pdf %m8683fc4871fde512571f824e540f25c1 %ccrypto %@Ivan Damgård,Jesper Buus Nielsen,Antigoni Polychroniadou,Michael Raskin %*On the Communication Required for Unconditionally Secure Multiplication %f/crypto/oircdgfybypjvn8cuwazejvzq2u5egid.pdf %m39f9abeb6b736a210626b30e960e831a %ccrypto %@Prabhanjan Ananth,Aayush Jain,Moni Naor,Amit Sahai,Eylon Yogev %*Universal Constructions and Robust Combiners for Indistinguishability Obfuscation and Witness Encryption %f/crypto/olnj3rygzpcbwv4qpwftlaxskehithmv.pdf %m2b1cff720a40ec2fb2cbe76ec0adfb62 %ccrypto %@Marc Fischlin,Amir Herzberg,Hod Bin-Noon,Haya Shulman %*Obfuscation Combiners %f/crypto/qe8kgimyu51xaagblphwvrxlzfedojdc.pdf %m1d287071c341e922b50d2cddf84ecdb7 %ccrypto %@Zvika Brakerski,Christina Brzuska,Nils Fleischhacker %*On Statistically Secure Obfuscation with Approximate Correctness %f/crypto/5qmd8eq69wfslkrkmgyx1zofteg2a7nw.pdf %m9705dc0602f341a65f74bc027f6c79ca %ccrypto %@Sanjam Garg,Omkant Pandey,Akshayaram Srinivasan %*Revisiting the Cryptographic Hardness of Finding a Nash Equilibrium %f/crypto/suoq3wxcg0fadlpqyv4fstkw2b8xe7k6.pdf %m51df5cd51082baaacf66664d0c49402e %ccrypto %@Jean-Sébastien Coron,Moon Sung Lee,Tancrède Lepoint,Mehdi Tibouchi %*Cryptanalysis of GGH15 Multilinear Maps %f/crypto/guqik4rymfnrba13ejhwso6voy08fcdc.pdf %m3fe958b7d85982cc93ef76d1c8bb97d4 %ccrypto %@Eric Miles,Amit Sahai,Mark Zhandry %*Annihilation Attacks for Multilinear Maps: Cryptanalysis of Indistinguishability Obfuscation over GGH13 %f/crypto/mqcyz56os3annpyt4gsxt8iweq2pfjix.pdf %m8335b0a999f58286723f832e1a9c2e16 %ccrypto %@Navid Alamati,Chris Peikert %*Three’s Compromised Too: Circular Insecurity for Any Cycle Length from (Ring-)LWE %f/crypto/1wcnagyv0sst4fp6dyuq7cagjzq8ermh.pdf %mdf838554bfd8843f690117fc723099df %ccrypto %@Venkata Koppula,Brent Waters %*Circular Security Separations for Arbitrary Length Cycles from LWE %f/crypto/tdmnxlzkm4koab7ceaogiss2zhw3n06x.pdf %m4ed5a3d58e0fa5e28715b66f2a385924 %ccrypto %@Yfke Dulek,Christian Schaffner,Florian Speelman %*Quantum Homomorphic Encryption for Polynomial-Sized Circuits %f/crypto/7xtzpsrrtmx1yilmhlpvuo6kajs8wcny.pdf %ma93f05a48c264f2c095a15a25d30f40e %ccrypto %@Frédéric Dupuis,Serge Fehr,Philippe Lamontagne,Louis Salvail %*Adaptive Versus Non-Adaptive Strategies in the Quantum Setting with Applications %f/crypto/yofjhpcrtoianup0i39cquabkw6l4hde.pdf %m9484489b8c0efb5e35348126a033ae23 %ccrypto %@Tommaso Gagliardoni,Andreas Hülsing,Christian Schaffner %*Semantic Security and Indistinguishability in the Quantum World %f/crypto/m7shxb98jfmkievhpraswuyol1rlkzuj.pdf %mec835bb84ce451e633bcb6a48afe2fe6 %ccrypto %@Yevgeniy Dodis,Shai Halevi,Ron D. Rothblum,Daniel Wichs %*Spooky Encryption and Its Applications %f/crypto/hpff6tjcwm9dho8dlub3ejmi2nbkkr0v.pdf %m306acfd93ed2dcdbf035dbc3231c9b37 %ccrypto %@Cynthia Dwork,Moni Naor,Guy N. Rothblum %*Spooky Interaction and Its Discontents: Compilers for Succinct Two-Message Argument Systems %f/crypto/0ybgrqphlccvjnnd2b5gdfmwmaejyafk.pdf %mbd80f0a07ce38d483e34bc1ff8457406 %ccrypto %@Brett Hemenway,Zahra Jafargholi,Rafail Ostrovsky,Alessandra Scafuro,Daniel Wichs %*Adaptively Secure Garbled Circuits from One-Way Functions %f/crypto/j1pdm8w6kxinngcfryjrqu0ua9g4oi2m.pdf %md9bde381b7042a8eb4f2a4089f7779e2 %ccrypto %@Ignacio Cascudo,Ivan Damgård,Bernardo David,Nico Döttling,Jesper Buus Nielsen %*Rate-1, Linear Time and Additively Homomorphic UC Commitments %f/crypto/zq7ol62jcm3kkiwjupub08taysdetnxr.pdf %m11862e1e20a044cc5b6ad94f409c7326 %ccrypto %@Jan Camenisch,Maria Dubovitskaya,Alfredo Rial %*UC Commitments for Modular Protocol Design and Applications to Revocation and Attribute Tokens %f/crypto/vdoytbel05sp94bqkc78rznuhaupwxrs.pdf %md99bdf0249059de179481fd6ed47366a %ccrypto %@Ran Cohen,Sandro Coretti,Juan Garay,Vassilis Zikas %*Probabilistic Termination and Composability of Cryptographic Protocols %f/crypto/9cfepjyd4slxfxeuicsmwhulo3hptqam.pdf %m2e9ccf1a2279b0dcd0b532a5bad4b0af %ccrypto %@Michele Ciampi,Rafail Ostrovsky,Luisa Siniscalchi,Ivan Visconti %*Concurrent Non-Malleable Commitments (and More) in 3 Rounds %f/crypto/om5tbv8icdh9ks3moed6pekawj04liu2.pdf %m6a18642c06ff79acb1ce68872bf568c8 %ccrypto %@Jiang Zhang,Yu Chen,Zhenfeng Zhang %*Programmable Hash Functions from Lattices: Short Signatures and IBEs with Small Key Sizes %f/crypto/x82r4atuwpe5djqci0smekaymt3rgfnn.pdf %m9613c9f9523884396bdd35245a3c81a4 %ccrypto %@Shweta Agrawal,Benoît Libert,Damien Stehlé %*Fully Secure Functional Encryption for Inner Products, from Standard Assumptions %f/crypto/cu8xncpqrvtos0eeqt1wf3fiyibgrakd.pdf %m9b71bc2dd878e856e51c5a067cea4107 %ccrypto %@Zvika Brakerski,Vinod Vaikuntanathan %*Circuit-ABE from LWE: Unbounded Attributes and Semi-adaptive Security %f/crypto/vfmwzloelecsahsxzvr5p0gnpcayb9i4.pdf %m94da60213d47f35f47ddbfb2ef5f624b %ccrypto %@Masayuki Abe,Fumitaka Hoshino,Miyako Ohkubo %*Design in Type-I, Run in Type-III: Fast and Scalable Bilinear-Type Conversion Using Integer Programming %f/crypto/3cracoefddt5phwako6tsxlwsm2n1hur.pdf %m26197dcefda6ac611ae712d87c660788 %ccrypto %@Brent Carmer,Mike Rosulek %*Linicrypt: A Model for Practical Cryptography %f/crypto/unypkecsig6yavjxo3lqmqogkewn9hf5.pdf %me2a02e28be252a9684424f7270e2f6a8 %ccrypto %@Benny Applebaum,Pavel Raykov %*On the Relationship Between Statistical Zero-Knowledge and Statistical Randomized Encodings %f/crypto/rsjwnk75abuxt0rq2wynkucf1i8zgpgl.pdf %mf85c5aa37772a0e6ad2093ad517b2095 %ccrypto %@Carsten Baum,Ivan Damgård,Kasper Green Larsen,Michael Nielsen %*How to Prove Knowledge of Small Secrets %f/crypto/rpjfbljhaiozoptx7utdu4iyfeak2rwh.pdf %ma5e7b4caac4d4867f439e38f70281227 %ccrypto %@Melissa Chase,Chaya Ganesh,Payman Mohassel %*Efficient Zero-Knowledge Proof of Algebraic and Non-Algebraic Statements with Applications to Privacy Preserving Credentials %f/crypto/uvj82mnrko9gbfzpkap6f7etwhbisnlw.pdf %mf3bfa15ba0f260c6362182e013c4de3c %ccrypto %@Akshay Degwekar,Vinod Vaikuntanathan,Prashant Nalini Vasudevan %*Fine-Grained Cryptography %f/crypto/kcoqtusfrhm316yvkxfit20oprymz5jn.pdf %m43b8cf009900928b7e3fd1127953a3d8 %ccrypto %@Sanjam Garg,Payman Mohassel,Charalampos Papamanthou %*TWORAM: Efficient Oblivious RAM in Two Rounds with Applications to Searchable Encryption %f/crypto/fofbqa6eansrpxvwpogt7kdgiqz2cslu.pdf %m3782adea026da4ef62bcc582158f2c37 %ccrypto %@Andrej Bogdanov,Yuval Ishai,Emanuele Viola,Christopher Williamson %*Bounded Indistinguishability and the Complexity of Recovering Secrets %f/crypto/end2ijdx5qzzypnogpqwvuwl3kbxfhsc.pdf %m76816fcdf0bd57f7f954616991e96129 %ccrypto %@Nico Döttling,Nils Fleischhacker,Johannes Krupp,Dominique Schröder %*Two-Message, Oblivious Evaluation of Cryptographic Functionalities %f/crypto/gyn5mz8rq9bhjc4ouhtekwuxsomvq7py.pdf %m4c33a2a6dc6505f4800bf5f1302b1197 %ccrypto %@Thijs Laarhoven %*Sieving for Shortest Vectors in Lattices Using Angular Locality-Sensitive Hashing %f/crypto/itbfvvedza1iln7xpwccsmkojtlnursq.pdf %m0d81dccbdc7f0b7a8b4e1a85c982c359 %ccrypto %@Qian Guo,Thomas Johansson,Paul Stankovski %*Coded-BKW: Solving LWE Using Lattice Codes %f/crypto/vfmgyxpmt06iraezwtz94wusav5h7q2k.pdf %m757ed8e0bdba32b1cf72ad45af530328 %ccrypto %@Paul Kirchner,Pierre-Alain Fouque %*An Improved BKW Algorithm for LWE with Applications to Cryptography and Lattices %f/crypto/k4sp6taxvihjfeo2uqrgbd1a3tljrysn.pdf %m5b926c97052707ad8be6d9637e40fcb7 %ccrypto %@Yara Elias,Kristin E. Lauter,Ekin Ozman,Katherine E. Stange %*Provably Weak Instances of Ring-LWE %f/crypto/70n5kjjqpyecs3vruul2wdzftr6thywg.pdf %m409742d7d69076d3c382d29915732dc1 %ccrypto %@Bing Sun,Zhiqiang Liu,Vincent Rijmen,Ruilin Li,Lei Cheng,Qingju Wang,Hoda Alkhzaimi,Chao Li %*Links Among Impossible Differential, Integral and Zero Correlation Linear Cryptanalysis %f/crypto/wgi4kejmhnhz3biujqkteynp7rmcvsug.pdf %mb61275b06f593aa92506566ea81eb94d %ccrypto %@Alex Biryukov,Léo Perrin %*On Reverse-Engineering S-Boxes with Hidden Design Criteria or Structure %f/crypto/n9fw8og4fuqjxcrvhbdztspw3x1zle7a.pdf %m771368db208968c25f741373500cf921 %ccrypto %@Jialin Huang,Serge Vaudenay,Xuejia Lai,Kaisa Nyberg %*Capacity and Data Complexity in Multidimensional Linear Attack %f/crypto/jxpfkyfi506cbmreoas4ctbwtjp7gunh.pdf %m7ccfd964ecdfba26be19ad0b49779fdb %ccrypto %@Stefan Kölbl,Gregor Leander,Tyge Tiessen %*Observations on the SIMON Block Cipher Family %f/crypto/z26arrujyva8b1xbnuchgelpifdtd79k.pdf %m57abce6350dc7d22979e99b045ecf412 %ccrypto %@Benoît Cogliati,Rodolphe Lampe,Yannick Seurin %*Tweaking Even-Mansour Ciphers %f/crypto/suvqga5tyhrjmfn1zpibxcres23pix6m.pdf %m28c2d44405f855cad9fa4d68b103a822 %ccrypto %@Nicky Mouha,Atul Luykx %*Multi-key Security: The Even-Mansour Construction Revisited %f/crypto/qspycxmrhefzfqdhpy4dnmgjg3vboib5.pdf %m33faf51e5d73e7d3c2706c335369e543 %ccrypto %@Mohammad Hajiabadi,Bruce M. Kapron %*Reproducible Circularly-Secure Bit Encryption: Applications and Realizations %f/crypto/vwz49jr5vhnaidrt03bmuybhipkxfjtx.pdf %mef23f3e6051c0eea9d95f82e43cbcf17 %ccrypto %@Jean-Sébastien Coron,Craig Gentry,Shai Halevi,Tancrède Lepoint,Hemanta K. Maji,Eric Miles,Mariana Raykova,Amit Sahai,Mehdi Tibouchi %*Zeroizing Without Low-Level Zeroes: New MMAP Attacks and their Limitations %f/crypto/jl8es9yhcsfzgakmeqoplfrmb1wdovnp.pdf %me214ba87e10a2b882ebaa92ae8ea6eff %ccrypto %@Jean-Sébastien Coron,Tancrède Lepoint,Mehdi Tibouchi %*New Multilinear Maps Over the Integers %f/crypto/yutxiri6qbznv37whfpcyac8dnbjv0uh.pdf %m3b9fc55f83be03c36a8bd267d67a9a06 %ccrypto %@Kai-Min Chung,Huijia Lin,Rafael Pass %*Constant-Round Concurrent Zero-Knowledge from Indistinguishability Obfuscation %f/crypto/zbciuxjvydalgnqmej5ahkrtfhn4li6o.pdf %m67f3910e25a8cbd836f49b07cb3cd5e2 %ccrypto %@Prabhanjan Ananth,Abhishek Jain %*Indistinguishability Obfuscation from Compact Functional Encryption %f/crypto/xn1glzuceq2fi4bmsqdwoyaiyaskprkc.pdf %m3478099fb536813c26959f120037f2f5 %ccrypto %@Nico Döttling,Dominique Schröder %*Efficient Pseudorandom Functions via On-the-Fly Adaptation %f/crypto/2su1xtkd3cq9bczkffpg7ozjljrmyet4.pdf %md8920c2d886a2c6d43a4b0da625e5b71 %ccrypto %@Brice Minaud,Yannick Seurin %*The Iterated Random Permutation Problem with Applications to Cascade Encryption %f/crypto/softqwdnlvdkc0zaus7r3jfpyhiiqvmz.pdf %m9b6610df4c001369dc4a4f20fc2c791d %ccrypto %@Peter Gaži,Krzysztof Pietrzak,Stefano Tessaro %*The Exact PRF Security of Truncation: Tight Bounds for Keyed Sponges and Truncated CBC %f/crypto/0bxj63ynzvwwh4dmtnebizr1ptdvsqqj.pdf %mac0cbedd0ab6c86ea68167cbf8c61bfc %ccrypto %@Michel Abdalla,Fabrice Benhamouda,Alain Passelègue %*An Algebraic Framework for Pseudorandom Functions and Applications to Related-Key Security %f/crypto/u3aeemgcvjzbxl0hprzsrgjwfqtifuk6.pdf %md10cdfed0bd9f8e94d3baf2e1efb3f8c %ccrypto %@Yosuke Todo %*Integral Cryptanalysis on Full MISTY1 %f/crypto/gpdv89m6tvqi5pyxb0bc1uhelysukn4j.pdf %ma3095151d292d31fd7f071b886ac3393 %ccrypto %@Itai Dinur,Orr Dunkelman,Nathan Keller,Adi Shamir %*New Attacks on Feistel Structures with Improved Memory Complexities %f/crypto/a6czkcu70i4yivfdzpn8gtb32qedf5xr.pdf %m1fbbe47f988ff665fc6a51a24b4cd5de %ccrypto %@Céline Blondeau,Thomas Peyrin,Lei Wang %*Known-Key Distinguisher on Full PRESENT %f/crypto/zpq57b1hadewc3p9lnmd8yybz4tsi6vj.pdf %m9d6f510b3a1a117d8dd6d79c8d2d0158 %ccrypto %@Henri Gilbert,Jérôme Plût,Joana Treger %*Key-Recovery Attack on the ASASA Cryptosystem with Expanding S-Boxes %f/crypto/rxosdfz7dwsla9uhiirytgbvnokanf5p.pdf %m997d7f8bbea46630fa4f8804ee33e610 %ccrypto %@Viet Tung Hoang,Reza Reyhanitabar,Phillip Rogaway,Damian Vizár %*Online Authenticated-Encryption and its Nonce-Reuse Misuse-Resistance %f/crypto/un6bvh1shzwz8lkpndcf35xocmdygjia.pdf %mf811cde707264beb3fb176b30e056e5c %ccrypto %@Avradip Mandal,Arnab Roy %*Relational Hash: Probabilistic Hash for Verifying Relations, Secure Against Forgery and More %f/crypto/8f5jsgf4ziwt3iewqxl0xkooykd1mgu7.pdf %me578696ba916d91249a0e042d0f81b37 %ccrypto %@Shashank Agrawal,Divya Gupta,Hemanta K. Maji,Omkant Pandey,Manoj Prabhakaran %*Explicit Non-malleable Codes Against Bit-Wise Tampering and Permutations %f/crypto/d84rfvfvhmngsuju5qokcpshaznxw1q7.pdf %m1bcbb956000e3b53a6b93203b88aa51a %ccrypto %@Pierre-Alain Fouque,Moon Sung Lee,Tancrède Lepoint,Mehdi Tibouchi %*Cryptanalysis of the Co-ACD Assumption %f/crypto/ywfqt9uoik2gtswsrf8znjbzy64oprlb.pdf %m7c54507252200680636fd3c4a0912529 %ccrypto %@Ming-Deh A. Huang,Michiel Kosters,Sze Ling Yeo %*Last Fall Degree, HFE, and Weil Descent Attacks on ECDLP %f/crypto/2k6ughladp0qjauefdew8zybvnq9lkry.pdf %m2b39a01a1eeee8a06a8d32a286f4236c %ccrypto %@Georg Fuchsbauer,Zahra Jafargholi,Krzysztof Pietrzak %*A Quasipolynomial Reduction for Generalized Selective Decryption on Trees %f/crypto/tnebxfj6szc0hb3dz9glixn2vpcwvujr.pdf %m2569bc7d5596b79655ccd5cb7012ad1e %ccrypto %@Pierre Karpman,Thomas Peyrin,Marc Stevens %*Practical Free-Start Collision Attacks on 76-step SHA-1 %f/crypto/cs7di1khmyoqfjgqpb4jmyuazutlnafc.pdf %m1d2dcb80ec65232de7071e6c66c863f1 %ccrypto %@Bin Zhang,Chao Xu,Willi Meier %*Fast Correlation Attacks over Extension Fields, Large-Unit Linear Approximation and Cryptanalysis of SNOW 2.0 %f/crypto/zuhur3vh9kom5t1oqxz4jbs2nasaiw8l.pdf %m5c729a09a0af9bcbec874b0eff80d00f %ccrypto %@Virginie Lallemand,María Naya-Plasencia %*Cryptanalysis of Full Sprout %f/crypto/nlxsxlwejd1hgmuanrfhsbypzucgmqiy.pdf %m29f4e7c3e3d96c71c66d7b80290be1cc %ccrypto %@Thomas Espitau,Pierre-Alain Fouque,Pierre Karpman %*Higher-Order Differential Meet-in-the-middle Preimage Attacks on SHA-1 and BLAKE %f/crypto/lezobs6ixqdahtdvi10knwujxpjyfomt.pdf %m0a3c54de231df3dd96669fb1b9127e83 %ccrypto %@Mike Hamburg %*Decaf: Eliminating Cofactors Through Point Compression %f/crypto/d71s3kohuzxiohvrq8ap0f9vtsnfygpk.pdf %mf986724d13476f2978a2112d933bd45f %ccrypto %@Marcel Keller,Emmanuela Orsini,Peter Scholl %*Actively Secure OT Extension with Optimal Overhead %f/crypto/u9xtwvngmfp376tjcbsa2c45bpdrmvdq.pdf %m1a0f92597eb5f9f9979ad8728bcd4380 %ccrypto %@Claude Carlet,Emmanuel Prouff,Matthieu Rivain,Thomas Roche %*Algebraic Decomposition for Probing Security %f/crypto/vb3y61oltz4xmp07wnd8rduevrfscgkm.pdf %me1ca0947bf60048bf2001b3ea48e9c6d %ccrypto %@Oscar Reparaz,Begül Bilgin,Svetla Nikova,Benedikt Gierlichs,Ingrid Verbauwhede %*Consolidating Masking Schemes %f/crypto/b4gmjyv7pktof2lhfiaxsrlqut5p10on.pdf %mec051afe9539798898467d00d25d1e34 %ccrypto %@Ran Canetti,Asaf Cohen,Yehuda Lindell %*A Simpler Variant of Universally Composable Security for Standard Multiparty Computation %f/crypto/sm924tvqjwfjm0ildonzintxug5r1r6z.pdf %m38f32279cc1a41c71bf4fc2c17eb4c5b %ccrypto %@Vipul Goyal,Divya Gupta,Amit Sahai %*Concurrent Secure Computation via Non-Black Box Simulation %f/crypto/jmqmcytwvngbgohixevl7par3d5l409k.pdf %ma4a5ffbf048fa6a2331fa0ad86d02e22 %ccrypto %@Ran Canetti,Vipul Goyal,Abhishek Jain %*Concurrent Secure Computation with Optimal Query Complexity %f/crypto/wrdbe8m2f1ua3j6t4avzsv0qgjrhfueb.pdf %m2671eecf73506f6bfa5043f9203f9c35 %ccrypto %@S. Dov Gordon,Feng-Hao Liu,Elaine Shi %*Constant-Round MPC with Fairness and Guarantee of Output Delivery %f/crypto/5d6yso3xx7n8pfsga1lupvt2bbriajqz.pdf %mee7a50ed8f51cd9037166444a2e5989f %ccrypto %@Susumu Kiyoshima %*Statistical Concurrent Non-malleable Zero-Knowledge from One-Way Functions %f/crypto/3wymzbfpsait12uwxmodigdvonslkjrp.pdf %mf860a63168ca0d7bc5edab2c8d20700e %ccrypto %@Fabrice Benhamouda,Geoffroy Couteau,David Pointcheval,Hoeteck Wee %*Implicit Zero-Knowledge Arguments and Applications to the Malicious Setting %f/crypto/mzcqg8o1fwlurtjqzhesyjnmdoe7g2w0.pdf %m7093d8f0bd05c51936c553c33a858738 %ccrypto %@Rafail Ostrovsky,Giuseppe Persiano,Ivan Visconti %*Impossibility of Black-Box Simulation Against Leakage Attacks %f/crypto/ujexivdowc5u9qlfblvskkgzd6oeg2n4.pdf %m5ebd79a2e259fb9b5d16e038c9ce71db %ccrypto %@Zhangxiang Hu,Payman Mohassel,Mike Rosulek %*Efficient Zero-Knowledge Proofs of Non-algebraic Statements with Sublinear Amortized Cost %f/crypto/1zqgk4tioxy8c2hdi7ynlkqewhpb5uof.pdf %m679c739cd9bba196ccd15a19ca1434ea %ccrypto %@Iftach Haitner,Yuval Ishai,Eran Omri,Ronen Shaltiel %*Parallel Hashing via List Recoverability %f/crypto/9ocqtjlvehobnndwmruqhsw4gbcxpx62.pdf %m4ca76340565fef8615613afa72aefa5d %ccrypto %@Sanjam Garg,Yuval Ishai,Eyal Kushilevitz,Rafail Ostrovsky,Amit Sahai %*Cryptography with One-Way Communication %f/crypto/709nmybcsdtabt3xwzeigoh4zivlhemp.pdf %m25a5d4294472d94028a4442c588363e8 %ccrypto %@Yu Yu,Dawu Gu,Xiangxue Li,Jian Weng %*(Almost) Optimal Constructions of UOWHFs from 1-to-1, Regular One-Way Functions and Beyond %f/crypto/mruedvqs2i18wqhsdpv6ktag9gfz5lnk.pdf %m19ae8d899ec44de266c32bba42e31326 %ccrypto %@Georg Fuchsbauer,Christian Hanser,Daniel Slamanig %*Practical Round-Optimal Blind Signatures in the Standard Model %f/crypto/i51ggzmvqbrudfjhq8iwske9czxbvk46.pdf %meb916f4fdd8bdb9ca89894758629bd8f %ccrypto %@Dario Catalano,Dario Fiore,Luca Nizzardo %*Programmable Hash Functions Go Private: Constructions and Applications to (Homomorphic) Signatures with Shorter Public Keys %f/crypto/9v2ywubgrhftmlpfnzqmx6nkgysdes07.pdf %mc858cca476cb0988d23864d71e50b0d4 %ccrypto %@Eike Kiltz,Jiaxin Pan,Hoeteck Wee %*Structure-Preserving Signatures from Standard Assumptions, Revisited %f/crypto/rukrgauwfqv1s8ehkbi3ptwmftbyil0x.pdf %m65b61f1d2e56307cb9496be2fc3be4ba %ccrypto %@Benoît Libert,Thomas Peters,Moti Yung %*Short Group Signatures via Structure-Preserving Signatures: Standard Model Security from Simple Assumptions %f/crypto/wpqehrzpqs9v5w42ogjbdxd8tftabs6c.pdf %m8f4e89830323e7b0b5062a1dc8e9603d %ccrypto %@Yehuda Lindell,Benny Pinkas,Nigel P. Smart,Avishay Yanai %*Efficient Constant Round Multi-party Computation Combining BMR and SPDZ %f/crypto/gavylwe5nue6xkox4d80hf3hif27prba.pdf %m37492455995adc5d138581068e12c03a %ccrypto %@Rafail Ostrovsky,Silas Richelson,Alessandra Scafuro %*Round-Optimal Black-Box Two-Party Computation %f/crypto/fmr9cmzxekoadbekchjtqp0qyuvunnds.pdf %mb2c7569f95b24d774d95a974d2ffe77d %ccrypto %@Yuval Ishai,Ranjit Kumaresan,Eyal Kushilevitz,Anat Paskin-Cherniavsky %*Secure Computation with Minimal Interaction, Revisited %f/crypto/p9nsbvs7mtyvzfekcrgjbghxp5icm6u2.pdf %m022c37b9775649f695267510f900e4aa %ccrypto %@Marcin Andrychowicz,Stefan Dziembowski %*PoW-Based Distributed Cryptography with No Trusted Setup %f/crypto/i0sb7nknajx5h4ruyczwdf38gg6rba1l.pdf %m952b0826f3346eb8e9af19687d6f4bf2 %ccrypto %@Serge Fehr,Max Fillinger %*Multi-prover Commitments Against Non-signaling Attacks %f/crypto/wqbcdsaue7kfftjm3oxyrktz28jrn1cl.pdf %m1fa09c9924cd2e7e1193a79bd4c090ef %ccrypto %@Yael Tauman Kalai,Ron D. Rothblum %*Arguments of Proximity %f/crypto/xmmcraxsaqqugw0felkvb5e8opvjh6nt.pdf %m4df9450fa1773059ffed37ab1c87bd45 %ccrypto %@Eric Chitambar,Benjamin Fortescue,Min-Hsiu Hsieh %*Distributions Attaining Secret Key at a Rate of the Conditional Mutual Information %f/crypto/g8ytpgjaqe7czmxzofdid9w6npjnc04b.pdf %m906915285ec15b049b3351208f1f2edf %ccrypto %@Yevgeniy Dodis,Yanqing Yao %*Privacy with Imperfect Randomness %f/crypto/a7pdnf5gxrjri8qnujbcvtall9k3dv0f.pdf %m4041148f8e6ebede2e1d823d31929af2 %ccrypto %@Romain Gay,Iordanis Kerenidis,Hoeteck Wee %*Communication Complexity of Conditional Disclosure of Secrets and Attribute-Based Encryption %f/crypto/gdyzouayxs0zi2vo71epbfmml4w38ctw.pdf %md2a27055ef0549381ecde98d05df12d4 %ccrypto %@Sergey Gorbunov,Vinod Vaikuntanathan,Hoeteck Wee %*Predicate Encryption for Circuits from LWE %f/crypto/f0icgjygi98ep7td4xtdabehnqy1ljs6.pdf %m955b92d85b9cdecdcc8539b017794f22 %ccrypto %@Lucas Kowalczyk,Allison Bishop Lewko %*Bilinear Entropy Expansion from the Decisional Linear Assumption %f/crypto/sos7tycqbanrhi056koavvzqf8gutujz.pdf %med158161b7337c235c545327f792310b %ccrypto %@Marc Fischlin,Felix Günther,Giorgia Azzurra Marson,Kenneth G. Paterson %*Data Is a Stream: Security of Stream-Based Channels %f/crypto/34fi2clckmwrznx6jnrgtaitfe1oqwxb.pdf %m1c031bb1fc87092017e7dad82c58b0d9 %ccrypto %@Moni Naor,Eylon Yogev %*Bloom Filters in Adversarial Environments %f/crypto/ovuktmzwxaiuqjob0hca6sxflkv32wmy.pdf %m75885fb025c73478d9839fd082d49b5b %ccrypto %@Stefan Dziembowski,Sebastian Faust,Vladimir Kolmogorov,Krzysztof Pietrzak %*Proofs of Space %f/crypto/cd8nmmaw6snlpkuzf50byoosrghi1rcz.pdf %md55f0fe912d25250c83e9b16002d4c09 %ccrypto %@Anne Broadbent,Stacey Jeffery %*Quantum Homomorphic Encryption for Circuits of Low T-gate Complexity %f/crypto/lkskz3bnucwr49j7hfanerxipqgwtom0.pdf %mb5b222d156117f24200d8ff5f360df76 %ccrypto %@Michael Clear,Ciarán McGoldrick %*Multi-identity and Multi-key Leveled FHE from Learning with Errors %f/crypto/ddzmagub8pjqumylf4jrxlvq2onychte.pdf %m12b85ea31368b3d6f32600d42ef22cd5 %ccrypto %@Prabhanjan Ananth,Zvika Brakerski,Gil Segev,Vinod Vaikuntanathan %*From Selective to Adaptive Security in Functional Encryption %f/crypto/9zdd6fozl4usgrncwpskkhv2jewujt5y.pdf %m6ea3b50d7d777c1c0c0cfe770132b5ca %ccrypto %@Brent Waters %*A Punctured Programming Approach to Adaptively Secure Functional Encryption %f/crypto/bo0dlneazavsnqk2hj7fscult5oriupy.pdf %m0dfe4ac215820a2b19b19bb1e42100f2 %ccrypto %@Divya Gupta,Yuval Ishai,Hemanta K. Maji,Amit Sahai %*Secure Computation from Leaky Correlated Randomness %f/crypto/r3etx95sz8pcijhano0vvkdb2imwtf6h.pdf %me402f7b43a2f603432b8bb80131e5017 %ccrypto %@Daniel Genkin,Yuval Ishai,Antigoni Polychroniadou %*Efficient Multi-party Computation: From Passive to Active Security via Secure SIMD Circuits %f/crypto/zaplmwuxv4fj9ckfgtczeajesdi6ikrn.pdf %m9e256edf01a595fa7f3480157d24f4b9 %ccrypto %@Elette Boyle,Kai-Min Chung,Rafael Pass %*Large-Scale Secure Computation: Multi-party Computation for (Parallel) RAM Programs %f/crypto/oj80bhtaxofblu7sxnggz2tpnv9lwf4u.pdf %mae7f6664b0f91384ee2d2f482a99e3f3 %ccrypto %@Joël Alwen,Rafail Ostrovsky,Hong-Sheng Zhou,Vassilis Zikas %*Incoercible Multi-party Computation and Universally Composable Receipt-Free Voting %f/crypto/gtwzamlmqjeqyfol6vzkkyjp7iewr5cc.pdf %m3003d92ac67b8d970b5c9db921001ee9 %ccrypto %@Mihir Bellare,Kenneth G. Paterson,Phillip Rogaway %*Security of Symmetric Encryption against Mass Surveillance %f/crypto/2dqysixccffzwvnbeprugzh84gdqi6py.pdf %m82398e6ad2bbd27b4685aa11a2cb0a67 %ccrypto %@Yuanxi Dai,Jooyoung Lee,Bart Mennink,John Steinberger %*The Security of Multiple Encryption in the Ideal Cipher Model %f/crypto/7ngcro4zmbdsspn1vmiypaxg6f3yqdrx.pdf %m70e207ffff81f304ff84c01ec64725d5 %ccrypto %@Shan Chen,Rodolphe Lampe,Jooyoung Lee,Yannick Seurin,John Steinberger %*Minimizing the Two-Round Even-Mansour Cipher %f/crypto/ytjxzpwcf2g3dnsonz97xlusuibaervk.pdf %mfbe01b10b48a07aace6f83f659b571a0 %ccrypto %@Martin R. Albrecht,Benedikt Driessen,Elif Bilge Kavun,Gregor Leander,Christof Paar,Tolga Yalçın %*Block Ciphers – Focus on the Linear Layer (feat. PRIDE) %f/crypto/mvqlzdbqcntchvrkgaf9yjztuikahw01.pdf %md326114c434076ff8dc703127f0ff386 %ccrypto %@Michel Abdalla,Fabrice Benhamouda,Alain Passelègue,Kenneth G. Paterson %*Related-Key Security for Pseudorandom Functions Beyond the Linear Barrier %f/crypto/ybxmidxebuotkk8pzwnricj6vhhvd57r.pdf %meb5fd2eab5075ec8855caf76ba6e155c %ccrypto %@Gilles Barthe,Edvard Fagerholm,Dario Fiore,John Mitchell,Andre Scedrov,Benedikt Schmidt %*Automated Analysis of Cryptographic Assumptions in Generic Group Models %f/crypto/eflvrqnr8vnbgwkc4h5gjiai2x716teh.pdf %m82b54271734403c4e683fb81c75f006f %ccrypto %@Peter Gaži,Krzysztof Pietrzak,Michal Rybár %*The Exact PRF-Security of NMAC and HMAC %f/crypto/1x6axsqpvf0zpd7vlucobc9sbiaftktw.pdf %m064c0eda5d7fb048dd944bf30d1dd7f7 %ccrypto %@Jian Guo,Thomas Peyrin,Yu Sasaki,Lei Wang %*Updates on Generic Attacks against HMAC and NMAC %f/crypto/eujxofjdvzplucvrtoyab9gz04aqksmq.pdf %m0e886b17abd1bb4af6b24c03f69e3de7 %ccrypto %@Itai Dinur,Gaëtan Leurent %*Improved Generic Attacks against Hash-Based MACs and HAIFA %f/crypto/vkjpb3bsts0yfcm4c1e7phjayhuvfuek.pdf %m1f10983d710d4bf2346cf36efa5dc472 %ccrypto %@Mihir Bellare,Viet Tung Hoang,Sriram Keelveedhi %*Cryptography from Compression Functions: The UCE Bridge to the ROM %f/crypto/fl1hipgx4j3rwz9kj60oqsgzf7kn5y8q.pdf %m6690d3da2e6e829ae70b7aa3699df2e7 %ccrypto %@Christina Brzuska,Pooya Farshim,Arno Mittelbach %*Indistinguishability Obfuscation and UCEs: The Case of Computationally Unpredictable Sources %f/crypto/vsgf9qov8wzjw7ckblu2igdsna6p1tch.pdf %m4058d14f8a00be5acabd46efe5fbc71b %ccrypto %@Dan Boneh,Brent Waters,Mark Zhandry %*Low Overhead Broadcast Encryption from Multilinear Maps %f/crypto/g6nbe0opcv5kafemu2nwqhlmditj4xi1.pdf %m1a1b9ce4b54bd76ed0ae023037291c7d %ccrypto %@Hyung Tae Lee,Jae Hong Seo %*Security Analysis of Multilinear Maps over the Integers %f/crypto/soaxoqea5clzg2r0ixtbf3svhblym1yk.pdf %m43ac7dac99709b7b2ca3d3532ecc7fcf %ccrypto %@Masayuki Abe,Jens Groth,Miyako Ohkubo,Takeya Tango %*Converting Cryptographic Schemes from Symmetric to Asymmetric Bilinear Groups %f/crypto/0ilzkhu3r6t4xqftbrpddasyeoxsjo5g.pdf %mab33e9ecc655795f6498f5e172c92d82 %ccrypto %@Gottfried Herold,Julia Hesse,Dennis Hofheinz,Carla Ràfols,Andy Rupp %*Polynomial Spaces: A New Framework for Composite-to-Prime-Order Transformations %f/crypto/pqkm9n41t5puhuesw2tfb3nmolfjwirv.pdf %meebc99eee96a50536b671c06aa9f1e45 %ccrypto %@H. W. Lenstra,A. Silverberg %*Revisiting the Gentry-Szydlo Algorithm %f/crypto/yxe5vqfb8xugjp7muaneztl2nwirdzq4.pdf %m7f432fc0fed97a62cceabb70fff863b9 %ccrypto %@Jacob Alperin-Sheriff,Chris Peikert %*Faster Bootstrapping with Polynomial Error %f/crypto/dlkuwvmzjmiybsuf7c46vgqo3925szg1.pdf %ma2b53561336e6d4164230bb4d8ea2551 %ccrypto %@San Ling,Duong Hieu Phan,Damien Stehlé,Ron Steinfeld %*Hardness of k-LWE and Applications in Traitor Tracing %f/crypto/pl9vb4lrnqbsptzywgjom8whfk2qnkhe.pdf %m3790f3765e4e94cc1cae76f3f5cf4759 %ccrypto %@Léo Ducas,Daniele Micciancio %*Improved Short Lattice Signatures in the Standard Model %f/crypto/0iyeqqlsp8r3rn7dofwgtpnzojgfku59.pdf %m04786e4c4d085e51e284a9e20fc46b36 %ccrypto %@Abhishek Banerjee,Chris Peikert %*New and Improved Key-Homomorphic Pseudorandom Functions %f/crypto/3thv2w9gfrl7nzmv4ty1genxs5o0xwup.pdf %m61a11326a4d85eb19d08a0efb601e7f0 %ccrypto %@Dario Catalano,Dario Fiore,Bogdan Warinschi %*Homomorphic Signatures with Efficient Verification for Polynomial Functions %f/crypto/gathvmq9b6xrozyndz580ykki4ohbplt.pdf %m73c8f1ec439c071370423b8207f04ed7 %ccrypto %@Masayuki Abe,Jens Groth,Miyako Ohkubo,Mehdi Tibouchi %*Structure-Preserving Signatures from Type II Pairings %f/crypto/7abtgkahpe50eylhs1rvn2fj8w9cdogu.pdf %mf7cae9b1c6649e901f794b234acb0a73 %ccrypto %@Olivier Blazy,Eike Kiltz,Jiaxin Pan %*(Hierarchical) Identity-Based Encryption from Affine Message Authentication %f/crypto/wvcpf6mqjasov7rclid3bidgx5fnxeth.pdf %me0c4a79719887b9b1fa84513d19bdbf9 %ccrypto %@Craig Gentry,Allison Lewko,Brent Waters %*Witness Encryption from Instance Independent Assumptions %f/crypto/xeciqztnw0zukx8ctwaharhybgd7lnlf.pdf %ma0934f21266b341b5d1d71f500d2029d %ccrypto %@Daniel Genkin,Adi Shamir,Eran Tromer %*RSA Key Extraction via Low-Bandwidth Acoustic Cryptanalysis %f/crypto/tsi3p0gen5quwcwbg8tohkclf1veuaab.pdf %ma6966e4bdcc3a32ae6b112c35bb66f81 %ccrypto %@Per Austrin,Kai-Min Chung,Mohammad Mahmoody,Rafael Pass,Karn Seth %*On the Impossibility of Cryptography with Tamperable Randomness %f/crypto/od0vmsgquhjjeig9akvwo1kwt3ybrzep.pdf %md59af85807503094196a0993d55d0399 %ccrypto %@Dan Boneh,Mark Zhandry %*Multiparty Key Exchange, Efficient Traitor Tracing, and More from Indistinguishability Obfuscation %f/crypto/r6ep3utclekiryg54ht1xifujp0wqxgh.pdf %m4f91839baecb0fc122f3b2285f29674a %ccrypto %@Rafael Pass,Karn Seth,Sidharth Telang %*Indistinguishability Obfuscation from Semantically-Secure Multilinear Encodings %f/crypto/ajq7dxvcvslgejzht5sbpyumlor8c3bt.pdf %m69691027b70a71a95c91c804c152e83b %ccrypto %@Sanjam Garg,Craig Gentry,Shai Halevi,Daniel Wichs %*On the Implausibility of Differing-Inputs Obfuscation and Extractable Witness Encryption with Auxiliary Input %f/crypto/ilpcytoydo6nvbnhduaf31xg8puxaw7i.pdf %m2a76cf2e44178d6c5a49ec77bc5c97ee %ccrypto %@Rafail Ostrovsky,Anat Paskin-Cherniavsky,Beni Paskin-Cherniavsky %*Maliciously Circuit-Private FHE %f/crypto/h95jezwqplvavrnges06mg2cfhy3byia.pdf %mc6c1132841060f18dc6d2eb736790b4a %ccrypto %@Shai Halevi,Victor Shoup %*Algorithms in HElib %f/crypto/kvomglwqzt6obuc0pypjcxuz3aiwng74.pdf %mb4ac1c616a015ad55f4b97f4cd573c87 %ccrypto %@Dominique Unruh %*Quantum Position Verification in the Random Oracle Model %f/crypto/vyn52zl81qpjkxdiubs6aoatuernqm73.pdf %mc528cd704cffda21e9cc0daef4886ba5 %ccrypto %@Yi-Kai Liu %*Single-Shot Security for One-Time Memories in the Isolated Qubits Model %f/crypto/ythvg3na4u6syljqrtde0r7xapwef1om.pdf %m924574ce3f5f86d2345a88188f2581a4 %ccrypto %@Yevgeniy Dodis,Adi Shamir,Noah Stephens-Davidowitz,Daniel Wichs %*How to Eat Your Entropy and Have It Too – Optimal Recovery Strategies for Compromised RNGs %f/crypto/e14tc0ghmfaddcizshstwkbygfwupvab.pdf %m316f0813f80b81c5dab7ab630b9ef421 %ccrypto %@Periklis A. Papakonstantinou,Guang Yang %*Cryptography with Streaming Algorithms %f/crypto/f6epxqh4wokg5ufcnxsyviu3bim2kzev.pdf %mc296a4fe6183957d528ffa40c4e29086 %ccrypto %@Nir Bitansky,Ran Canetti,Henry Cohn,Shafi Goldwasser,Yael Tauman Kalai,Omer Paneth,Alon Rosen %*The Impossibility of Obfuscation with Auxiliary Input or a Universal Simulator %f/crypto/ror1eiaqnyslv0jkfest9gnau6kxltpy.pdf %m34b4a7601663e7c7c4aae291b8602477 %ccrypto %@Takashi Yamakawa,Shota Yamada,Goichiro Hanaoka,Noboru Kunihiro %*Self-bilinear Map on Unknown Order Groups from Indistinguishability Obfuscation and Its Applications %f/crypto/worp29degbsgwqymlt5cje6xaovmihpf.pdf %m5e84398fe2cef113cd0e2eb692648e21 %ccrypto %@Nir Bitansky,Ran Canetti,Yael Tauman Kalai,Omer Paneth %*On Virtual Grey Box Obfuscation for General Circuits %f/crypto/zo4bfi6ytnywrfexumxq57dgighrzjev.pdf %m11480b6bd1fbfdf12b82b869570341a8 %ccrypto %@Robert Granger,Thorsten Kleinjung,Jens Zumbrägel %*Breaking ‘128-bit Secure’ Supersingular Binary Curves %f/crypto/wo7dcwailgcqbp3qtr0uie5z24jnbzue.pdf %m6dbe4207a18a1592ace40b0aa8dd9b55 %ccrypto %@Nir Bitansky,Dana Dachman-Soled,Huijia Lin %*Leakage-Tolerant Computation with Input-Independent Preprocessing %f/crypto/n6e1lz4akgvxbomunbi9yrffgaqdwkz8.pdf %m3bcb359bdf31a53b94002a00de6a73e6 %ccrypto %@Prabhanjan Ananth,Vipul Goyal,Omkant Pandey %*Interactive Proofs under Continual Memory Leakage %f/crypto/umr0cqxjlf6fnuhvxkqaglm3tb1c29b5.pdf %m8ea40eac29c9cb7e44158a46126d791b %ccrypto %@Divesh Aggarwal,Yevgeniy Dodis,Zahra Jafargholi,Eric Miles,Leonid Reyzin %*Amplifying Privacy in Privacy Amplification %f/crypto/eh05lswtwxjazjfs32i1pp6un8l9tood.pdf %mfccbff6ece30b21a4f257edfa1beea92 %ccrypto %@Deepesh Data,Manoj M. Prabhakaran,Vinod M. Prabhakaran %*On the Communication Complexity of Secure Computation %f/crypto/jbxi3iyxoujf9bspedmsdc7enqt5ha0c.pdf %m4afa20f458db16bc21f19bb0cdd53aa6 %ccrypto %@Oriol Farràs,Torben Hansen,Tarik Kaced,Carles Padró %*Optimal Non-perfect Uniform Secret Sharing Schemes %f/crypto/jtq0bzwc1w9u7oirjetl65gnmibyrnx4.pdf %m459a9ee873c36154b5a6d11be657a6e0 %ccrypto %@Karthikeyan Bhargavan,Cédric Fournet,Markulf Kohlweiss,Alfredo Pironti,Pierre-Yves Strub,Santiago Zanella-Béguelin %*Proving the TLS Handshake Secure (As It Is) %f/crypto/2igqgavsr38j1xnmbrpxwfdtilh7t5eh.pdf %m5e992e705b8d38cd767503a900b2efbc %ccrypto %@Jan Camenisch,Anja Lehmann,Anna Lysyanskaya,Gregory Neven %*Memento: How to Reconstruct Your Secrets from a Single Password in a Hostile Environment %f/crypto/by2kv94hjgrmiqtyfbflsseeu0xp1n8u.pdf %m57189739da9ac94ebd70f6591c034faf %ccrypto %@Eli Ben-Sasson,Alessandro Chiesa,Eran Tromer,Madars Virza %*Scalable Zero Knowledge via Cycles of Elliptic Curves %f/crypto/v4g0ysoidtjhle5l9ycwqmhprdna2zia.pdf %m628dfd64457f8dd653f450a38e702f2d %ccrypto %@Charanjit S. Jutla,Arnab Roy %*Switching Lemma for Bilinear Tests and Constant-Size NIZK Proofs for Linear Subspaces %f/crypto/fskhjnpukajgsqvcrreod8u6qz4d3wvt.pdf %mf847bb512403583d05c8519290156679 %ccrypto %@Ben Fisch,Daniel Freund,Moni Naor %*Physical Zero-Knowledge Proofs of Physical Properties %f/crypto/gsxzju5wy6hprl84afcfq9xtid21vmos.pdf %m3312fb5576494a76955d391db9a698d1 %ccrypto %@Ran Canetti,Abhishek Jain,Omer Paneth %*Client-Server Concurrent Zero Knowledge with Constant Rounds and Guaranteed Complexity %f/crypto/9rzdfc5nl2miwmrk4au0v6hxezjtbwpi.pdf %m66a829c82a2d1d372c2d4ea7efded44f %ccrypto %@Susumu Kiyoshima %*Round-Efficient Black-Box Construction of Composable Multi-Party Computation %f/crypto/vpcruq7s0l1afgzkw39mmhx4tbxlzugk.pdf %m2eea79437eae80ce4a49d93e84791d0c %ccrypto %@Yuval Ishai,Rafail Ostrovsky,Vassilis Zikas %*Secure Multi-Party Computation with Identifiable Abort %f/crypto/rdkbxiq286ahlczrmfaycw0uinjosoxm.pdf %m544e9fe4ef3e60d13521aaa6b98287bb %ccrypto %@Amos Beimel,Ariel Gabizon,Yuval Ishai,Eyal Kushilevitz,Sigurd Meldgaard,Anat Paskin-Cherniavsky %*Non-Interactive Secure Multiparty Computation %f/crypto/vsd6w48wcrjuq1ozokby03enegzcvuqj.pdf %m23ec7a055342eb1430c503365a4430ce %ccrypto %@Dana Dachman-Soled,Nils Fleischhacker,Jonathan Katz,Anna Lysyanskaya,Dominique Schröder %*Feasibility and Infeasibility of Secure Computation with Malicious PUFs %f/crypto/yn9woc572hblpfgvunckzqydl3pgkti8.pdf %m05dd173fe68fca4f3c16dfbe5c0973a2 %ccrypto %@Iddo Bentov,Ranjit Kumaresan %*How to Use Bitcoin to Design Fair Protocols %f/crypto/sdw9w0znr2exbqgcvvli4ckztladyygn.pdf %me85d149873a2a897ede45b231ef88ff1 %ccrypto %@Vladimir Kolesnikov,Payman Mohassel,Mike Rosulek %*FleXOR: Flexible Garbling for XOR Gates That Beats Free-XOR %f/crypto/oqjbvua9cghqbizns1yam0e3grmz8ehw.pdf %m92118c0124e7228e6eee7c16897dcd8d %ccrypto %@Yan Huang,Jonathan Katz,Vladimir Kolesnikov,Ranjit Kumaresan,Alex J. Malozemoff %*Amortizing Garbled Circuits %f/crypto/osi9drzlkh5gjbmvaoyz7plfcpewu3t8.pdf %m83080b9a225431dc632d2c545824c456 %ccrypto %@Yehuda Lindell,Ben Riva %*Cut-and-Choose Yao-Based Secure Computation in the Online/Offline and Batch Settings %f/crypto/lz9mkhbx6tzwbns2icaywxgsnorq0jct.pdf %m584482a0f88d78b7c2eded3e0abcabef %ccrypto %@Enrique Larraia,Emmanuela Orsini,Nigel P. Smart %*Dishonest Majority Multi-Party Computation for Binary Circuits %f/crypto/bmrb7g39epuxlcwtindguzlewzroqv10.pdf %meef5f93add6c247c9d18198c6afd3aff %ccrypto %@Seung Geol Choi,Jonathan Katz,Alex J. Malozemoff,Vassilis Zikas %*Efficient Three-Party Computation from Cut-and-Choose %f/crypto/wye07ijfmrolibh4sf3e9lvkuxtd2zqw.pdf %m1b6ec165eb704824900cf12be1423540 %ccrypto %@Jacob Alperin-Sheriff,Chris Peikert %*Practical Bootstrapping in Quasilinear Time %f/crypto/r9vk5g72phakzn1qogp3hc4liqdlxur6.pdf %md496643dd29e4df4cd3de8579ae9c02f %ccrypto %@Daniele Micciancio,Chris Peikert %*Hardness of SIS and LWE with Small Parameters %f/crypto/zd9rqaxpj83enkfbrlobtscagi4hefm7.pdf %m61937b6db20f6f076f6d608cf41f1b52 %ccrypto %@Léo Ducas,Alain Durmus,Tancrède Lepoint,Vadim Lyubashevsky %*Lattice Signatures and Bimodal Gaussians %f/crypto/cgk7sfic4ut3nyz1n8s6edmibumw0hx2.pdf %mae5de41f3470a0cd81362df93665965e %ccrypto %@Joël Alwen,Stephan Krenn,Krzysztof Pietrzak,Daniel Wichs %*Learning with Rounding, Revisited %f/crypto/8w07rlphjmcnvf3z9rtmewba6yxgk51s.pdf %me3bd8a8b3f8817a17f3ef8d05debab31 %ccrypto %@Craig Gentry,Amit Sahai,Brent Waters %*Homomorphic Encryption from Learning with Errors: Conceptually-Simpler, Asymptotically-Faster, Attribute-Based %f/crypto/hotncgewpxwcbm7nujk0zvs2alkrhqm1.pdf %mc7a842ee0318902f347a946379d4a15b %ccrypto %@Salil Vadhan,Colin Jia Zheng %*A Uniform Min-Max Theorem with Applications in Cryptography %f/crypto/lshcf23fleid0pynghxgzp8m6ojrdzr4.pdf %m60f2777ace3143e03d73e3d9062ab8ef %ccrypto %@Andrej Bogdanov,Chin Ho Lee %*Limits of Provable Security for Homomorphic Encryption %f/crypto/ofbs8ynco2qtfun5vagewgzkcwpri1ly.pdf %m9c08e8ba3a8528cc2fd162f6bbd94138 %ccrypto %@Marc Stevens %*Counter-Cryptanalysis %f/crypto/axddb0nlrhbxegp6ymjvzo84kszy5n1u.pdf %mcecc453c3551ce0765e56a561e79559e %ccrypto %@Daehyun Strobel,Benedikt Driessen,Timo Kasper,Gregor Leander,David Oswald,Falk Schellenberg,Christof Paar %*Fuming Acid and Cryptanalysis: Handy Tools for Overcoming a Digital Locking and Access Control System %f/crypto/mxzd4otqgfxannvrmeu19cbuy0bpkjhc.pdf %m1b12a08a0f5cdaf647a5f431d05d3c98 %ccrypto %@Bin Zhang,Chao Xu,Dengguo Feng %*Real Time Cryptanalysis of Bluetooth Encryption with Condition Masking %f/crypto/txqcr6eoizjy9lersf4q8fd0h5uyvzbp.pdf %m7afeb91f2edf0414a30d941a98efe9a0 %ccrypto %@Pierre-Alain Fouque,Jérémy Jean,Thomas Peyrin %*Structural Evaluation of AES and Chosen-Key Distinguisher of 9-Round AES-128 %f/crypto/nzi87qg5bhtcyplcmsw62eauydbjxgv4.pdf %mf9da409eccd517cddd8ed496f88d0eab %ccrypto %@Céline Blondeau,Andrey Bogdanov,Gregor Leander %*Bounds in Shallows and in Miseries %f/crypto/gdqvkeuedjpohwmcrsa5iyszzp3mbwl6.pdf %m9990baaaf47248ddf06d848bf5bd5285 %ccrypto %@Anne Canteaut,María Naya-Plasencia,Bastien Vayssière %*Sieve-in-the-Middle: Improved MITM Attacks %f/crypto/tm4pgorhmzziyf9uxewjjcu76ikepnon.pdf %m2af159d276736bd6c9f78b96715e6493 %ccrypto %@Gaëtan Leurent %*Construction of Differential Characteristics in ARX Designs Application to Skein %f/crypto/sdxu1mfgr8thi4pwlgwcvl6eyrn3uf5k.pdf %m31c2b094f3cf613977ec928423bb8289 %ccrypto %@Shashank Agrawal,Manoj Prabhakaran %*On Fair Exchange, Fair Coins and Fair Sampling %f/crypto/tvrhbpa7fsufd5yqklvoc8mxitedwjy2.pdf %md8efcd4c0c187812e592f98baddc50bd %ccrypto %@Pavel Hubáček,Jesper Buus Nielsen,Alon Rosen %*Limits on the Power of Cryptographic Cheap Talk %f/crypto/tyxgq82dwetvwyolpbiiknenu9h06xv7.pdf %ma9d2f516ecae896a4b3c4d1b1ab71be5 %ccrypto %@Vipul Goyal,Ilya Mironov,Omkant Pandey,Amit Sahai %*Accuracy-Privacy Tradeoffs for Two-Party Differentially Private Protocols %f/crypto/cov9naktlqqgphirx7f5js4m2y3ncf0b.pdf %m16d98c0714e9cee3a971f7da51583d61 %ccrypto %@Elette Boyle,Sanjam Garg,Abhishek Jain,Yael Tauman Kalai,Amit Sahai %*Secure Computation against Adaptive Auxiliary Information %f/crypto/dp9h8lyekiukx0t3mgtq4cxfoecsr6vj.pdf %m7c758db928372884a681e0f5f0dc57bb %ccrypto %@François-Xavier Standaert,Olivier Pereira,Yu Yu %*Leakage-Resilient Symmetric Cryptography under Empirically Verifiable Assumptions %f/crypto/mb6uh83epx1lqinmazriwh4sozcj5ctn.pdf %m43f3ac2512e5c8106108399592b7d541 %ccrypto %@David Cash,Stanislaw Jarecki,Charanjit Jutla,Hugo Krawczyk,Marcel-Cătălin Roşu,Michael Steiner %*Highly-Scalable Searchable Symmetric Encryption with Support for Boolean Queries %f/crypto/illt4pegsfmikqjgmarrkhzbwscno2b0.pdf %ma24a0ff96ad6aea7c464bb445f25bf3c %ccrypto %@Martín Abadi,Dan Boneh,Ilya Mironov,Ananth Raghunathan,Gil Segev %*Message-Locked Encryption for Lock-Dependent Messages %f/crypto/nfr5vjx39ndlatrskcqg4wuzdbuvezki.pdf %mdf9935bf621aa237d7a4f6236839594b %ccrypto %@Thomas Ristenpart,Scott Yilek %*The Mix-and-Cut Shuffle: Small-Domain Encryption Secure against N Queries %f/crypto/tdoja4bkzwnjgudefzhhqpcsy3fimx81.pdf %md4c5d01e1cea6e8e934fc0641332deff %ccrypto %@Dan Boneh,Kevin Lewi,Hart Montgomery,Ananth Raghunathan %*Key Homomorphic PRFs and Their Applications %f/crypto/gb5qjtihi8rz6cg3auvozapxy42twhnk.pdf %me30ba6c4b619c1d3c4668731c1665efb %ccrypto %@Hugo Krawczyk,Kenneth G. Paterson,Hoeteck Wee %*On the Security of the TLS Protocol: A Systematic Analysis %f/crypto/tud7hwsfv1whut9q8r3c60ojilpyrfon.pdf %mbbeb404d0e3548d0a248428b81158b7e %ccrypto %@Fabrice Benhamouda,Olivier Blazy,Céline Chevalier,David Pointcheval,Damien Vergnaud %*New Techniques for SPHFs and Efficient One-Round PAKE Protocols %f/crypto/v9l5u0jekolcms4hygbasf6ranhod7qr.pdf %m711e413865633147b14626383902221c %ccrypto %@Jean-Sébastien Coron,Tancrède Lepoint,Mehdi Tibouchi %*Practical Multilinear Maps over the Integers %f/crypto/9z1qfb2r7a4m8oxsdwji0xvvnyuiqwbh.pdf %mb2926570f3bd507be2b896ee529e7ed2 %ccrypto %@Susan Hohenberger,Amit Sahai,Brent Waters %*Full Domain Hash from (Leveled) Multilinear Maps and Identity-Based Aggregate Signatures %f/crypto/az75f01hisulnuvz6tckn3wwveymoicp.pdf %m6414cff7266c086fec8e72b9fa648723 %ccrypto %@Eduarda S. V. Freire,Dennis Hofheinz,Kenneth G. Paterson,Christoph Striecks %*Programmable Hash Functions in the Multilinear Setting %f/crypto/zy8ioqgbacpuiewv40hp32orsfxv5wkz.pdf %m206c723850a5f79d6c820c01795ded84 %ccrypto %@Elena Andreeva,Andrey Bogdanov,Yevgeniy Dodis,Bart Mennink,John P. Steinberger %*On the Indifferentiability of Key-Alternating Ciphers %f/crypto/v6rncy8zz1ugepslm05mpofiyjb9bogv.pdf %maf6786794dc00f8434b90f641ec52938 %ccrypto %@Peter Gaži %*Plain versus Randomized Cascading-Based Key-Length Extension for Block Ciphers %f/crypto/oxhlidvbyvn7c8j5x1spto6qlekz9gdz.pdf %m75f349d4688fb8b1c7756a1b1382662a %ccrypto %@Eike Kiltz,Krzysztof Pietrzak,Mario Szegedy %*Digital Signatures with Minimal Overhead from Indifferentiable Random Invertible Functions %f/crypto/gkynimd7l3qjjz9uhasi8k4cznx5ysgf.pdf %m3ccc5f63137348b317264f4102e52afc %ccrypto %@Yehuda Lindell %*Fast Cut-and-Choose Based Protocols for Malicious and Covert Adversaries %f/crypto/uzbnawokpfrxlgyss6meheypl1uz2inq.pdf %m5a7d9421da16a459ab4ae69a0e9a83d5 %ccrypto %@Yan Huang,Jonathan Katz,David Evans %*Efficient Secure Two-Party Computation Using Symmetric Cut-and-Choose %f/crypto/wduptaqr0zpzqlgj6kscxvkewmoyimlj.pdf %m0ae76aa693d4097e7e91849c19861be1 %ccrypto %@Payman Mohassel,Ben Riva %*Garbled Circuits Checking Garbled Circuits: More Efficient and Secure Two-Party Computation %f/crypto/e6ge9qksd1um04hmlpbwknigojrliv78.pdf %m989ed991bfd95ae61086af6af630c770 %ccrypto %@Vladimir Kolesnikov,Ranjit Kumaresan %*Improved OT Extension for Transferring Short Secrets %f/crypto/rzvamodsib57sfww8dknyhnx0kxtp3fa.pdf %m7b78de185cad3793fb3cf21308a830a3 %ccrypto %@Justin Thaler %*Time-Optimal Interactive Proofs for Circuit Evaluation %f/crypto/fvnbzxuxh089rcgyowr3qelmtam4zdsk.pdf %me6d5a906d0c0a9fc8f800d954afd3be2 %ccrypto %@Eli Ben-Sasson,Alessandro Chiesa,Daniel Genkin,Eran Tromer,Madars Virza %*SNARKs for C: Verifying Program Executions Succinctly and in Zero Knowledge %f/crypto/q0baurh3gbqpdtfreiloewpdcvuzmsnl.pdf %m0e97dbf7b8b7fbbcd01f6a8b9ba52b67 %ccrypto %@Faruk Göloğlu,Robert Granger,Gary McGuire,Jens Zumbrägel %*On the Function Field Sieve and the Impact of Higher Splitting Probabilities %f/crypto/4qkcz378irascwmk6mgvvoxdutlneapb.pdf %m13b1328b16270bb34ad7aa5076df7802 %ccrypto %@Alex Escala,Gottfried Herold,Eike Kiltz,Carla Ràfols,Jorge Villar %*An Algebraic Framework for Diffie-Hellman Assumptions %f/crypto/e9pvc8yqulwriv7reqfhzmd4skk0np3w.pdf %m731f98d9691aa1acb3155d303d673527 %ccrypto %@Nelly Fazio,Rosario Gennaro,Irippuge Milinda Perera,William E. Skeith %*Hard-Core Predicates for a Diffie-Hellman Problem over Finite Fields %f/crypto/0e4n5bujcoxyorihuq9fsqmit3gpechz.pdf %m0c5f4c23f783f00cc054118747168a60 %ccrypto %@Benny Applebaum,Yuval Ishai,Eyal Kushilevitz,Brent Waters %*Encoding Functions with Constant Online Rate or How to Compress Garbled Circuits Keys %f/crypto/7tocc5bm9pu1ddihyzxlsax0je3wygfz.pdf %m44b229b6b70b7173bc90bcc80f4a38a8 %ccrypto %@Gil Cohen,Ivan Bjerre Damgård,Yuval Ishai,Jonas Kölker,Peter Bro Miltersen,Ran Raz,Ron D. Rothblum %*Efficient Multiparty Protocols via Log-Depth Threshold Formulae %f/crypto/ysa80kqv63zlnnfcijacfslugbmtheow.pdf %m072dc818d48ed8491fd4d6bad9af8eaf %ccrypto %@Martin Hirt,Ueli Maurer,Christoph Lucas %*A Dynamic Tradeoff between Active and Passive Corruptions in Secure Multi-Party Computation %f/crypto/c3vbiodvjseruc60trwqgbyzihmktwn4.pdf %m6556798f2bbb369f38d77d1ff43ac2b0 %ccrypto %@Martin Hirt,Christoph Lucas,Ueli Maurer %*Erratum: A Dynamic Tradeoff between Active and Passive Corruptions in Secure Multi-Party Computation %f/crypto/qrqt4sxoudkwjz7pbafcplfokyb6nvgj.pdf %m15d80ec6a59653bf5d1396134a47b722 %ccrypto %@Vipul Goyal,Divya Gupta,Abhishek Jain %*What Information Is Leaked under Concurrent Composition? %f/crypto/2diuemr1vszttwpc3bfhlbolnkjsrype.pdf %m7dae0d28d243293d7ea6653e83c80578 %ccrypto %@Stefan Dziembowski,Tomasz Kazana,Maciej Obremski %*Non-malleable Codes from Two-Source Extractors %f/crypto/rqyauz0plmrpsxi3jsdkco2j1qwggx57.pdf %me8c62ba1591f71f1554fbe78ac79cd78 %ccrypto %@Matthew Franklin,Ran Gelles,Rafail Ostrovsky,Leonard J. Schulman %*Optimal Coding for Streaming Authentication and Interactive Communication %f/crypto/xxzwpandobmc70vlvs5q9frpuo1ksnt8.pdf %m4ff2b63f388988b112b537d427a3ad3b %ccrypto %@Sebastià Martín,Carles Padró,An Yang %*Secret Sharing, Rank Inequalities and Information Inequalities %f/crypto/foctbvixg2ylk3uaep1d9cawrbojftr8.pdf %md296f97dd99d2194216da144dfe67823 %ccrypto %@Benoît Libert,Thomas Peters,Marc Joye,Moti Yung %*Linearly Homomorphic Structure-Preserving Signatures and Their Applications %f/crypto/8zojbd4s9gvfja0iqohcp6n1wkkxxln5.pdf %m71521ecf9c29c70d8800a3489823eeaf %ccrypto %@Vadim Lyubashevsky,Daniel Masny %*Man-in-the-Middle Secure Authentication Schemes from LPN and Weak PRFs %f/crypto/gnj6livmot2rx518lbcheakpg7rju0bw.pdf %mea2ff45fb99213ea1ba8f42043587288 %ccrypto %@Frédéric Dupuis,Omar Fawzi,Stephanie Wehner %*Achieving the Limits of the Noisy-Storage Model Using Entanglement Sampling %f/crypto/rw6i4jqvcbr8lpo5s07oxy2lu3zwehav.pdf %m405cd6a41cb1b35426482aed7dd151d8 %ccrypto %@Anne Broadbent,Gus Gutoski,Douglas Stebila %*Quantum One-Time Programs %f/crypto/d75qnvgkwxtfrmqacpoz8jp3169jreuu.pdf %mdf2ef5df2d44a98b539bfb1de989e2b9 %ccrypto %@Dan Boneh,Mark Zhandry %*Secure Signatures and Chosen Ciphertext Security in a Quantum Computing World %f/crypto/nb0tr4mzrbvuyofn5ldw6eiyoxvzdgj8.pdf %md862e48eda9d6e768a4d94bc6e318032 %ccrypto %@Dominique Unruh %*Everlasting Multi-party Computation %f/crypto/4pzeqkm6ctbwxfh1nwyjscvnqgo5muof.pdf %m10101a5ddbeee13684524726d9994ec8 %ccrypto %@Mihir Bellare,Viet Tung Hoang,Sriram Keelveedhi %*Instantiating Random Oracles via UCEs %f/crypto/t4kyr2rdc8ibpuvnxdupsqawbm3ghxgh.pdf %mdb4afca84638e6ff1f53249af636a08f %ccrypto %@Zvika Brakerski,Guy N. Rothblum %*Obfuscating Conjunctions %f/crypto/gnkuywzi4cdsmwb9r3hppereuvjba5j8.pdf %m6faf8208ac08c27b8c7b9f20e3e7cf40 %ccrypto %@Jie Chen,Hoeteck Wee %*Fully, (Almost) Tightly Secure IBE and Dual System Groups %f/crypto/otqjcfkuup5ner071diphbcnlqh63jiz.pdf %m0dec747baca300d5961064af5e85f512 %ccrypto %@Dan Boneh,Ananth Raghunathan,Gil Segev %*Function-Private Identity-Based Encryption: Hiding the Function in Functional Encryption %f/crypto/gfaqk7dxw1yjqazuhectnsbkdom5voi0.pdf %mb52ffbf0108220f26ba04fd967035ee2 %ccrypto %@Sanjam Garg,Craig Gentry,Shai Halevi,Amit Sahai,Brent Waters %*Attribute-Based Encryption for Circuits from Multilinear Maps %f/crypto/swduxhie6btyfmarozpuhjtni9ko5vvb.pdf %mf18fcedd2fe9e4c8bbfb3c5465086130 %ccrypto %@Shweta Agrawal,Sergey Gorbunov,Vinod Vaikuntanathan,Hoeteck Wee %*Functional Encryption: New Perspectives and Lower Bounds %f/crypto/fvxb7gyjbkx9gkqiwyznn4ttmzcrsjpe.pdf %m523d89433d7017b4c289613e6e91d5b2 %ccrypto %@Angelo De Caro,Vincenzo Iovino,Abhishek Jain,Adam O’Neill,Omer Paneth,Giuseppe Persiano %*On the Achievability of Simulation-Based Security for Functional Encryption %f/crypto/lfuekckg4hjio7j8fw3xsxorvsrbm1ly.pdf %m46bce3540fa49ffd6e1c81e7c2a6912d %ccrypto %@Shafi Goldwasser,Yael Tauman Kalai,Raluca Ada Popa,Vinod Vaikuntanathan,Nickolai Zeldovich %*How to Run Turing Machines on Encrypted Data %f/crypto/c2dut41bfqzxijor9ovegmwylaixke6n.pdf %mce83007b3a7ed5280260553e6191b83a %ccrypto %@Viet Tung Hoang,Ben Morris,Phillip Rogaway %*An Enciphering Scheme Based on a Card Shuffle %f/crypto/tmdcqns8rp04pknbyymwsjflgaib3cwe.pdf %m052788550b413d2106ad0e5ba57e6435 %ccrypto %@Will Landecker,Thomas Shrimpton,R. Seth Terashima %*Tweakable Blockciphers with Beyond Birthday-Bound Security %f/crypto/hgmotpnw2uy5xemkthzg4jfrs0d9ilx6.pdf %mf754ea9edbb1a382fd39b39084f4ff28 %ccrypto %@Tetsu Iwata,Keisuke Ohashi,Kazuhiko Minematsu %*Breaking and Repairing GCM Security Proofs %f/crypto/ykeu4fyjqvp95iozln6rjismvqdar38g.pdf %md7eb625900fcc30b9f9cceb3eea24b18 %ccrypto %@Mohamed Ahmed Abdelraheem,Martin Ågren,Peter Beelen,Gregor Leander %*On the Distribution of Linear Biases: Three Instructive Examples %f/crypto/jb8cqlmh6torkngt3fuv5y49mupedfko.pdf %mf07e2b933d96b22ecab50446de8c90d5 %ccrypto %@Eric Miles,Emanuele Viola %*Substitution-Permutation Networks, Pseudorandom Functions, and Natural Proofs %f/crypto/jw0i9dw3tchkaazruitpn6oexs4gf1gk.pdf %m39be2dde542098ec5a8de703f1bbfffe %ccrypto %@Jonathan Zittrain %*The End of Crypto %f/crypto/b1f8k9guwtrm7uqafsznorn4qthjey6g.pdf %m83acd1ea10ab596c1179ca6049f1bf18 %ccrypto %@Mike Rosulek %*Must You Know the Code of f to Securely Compute f? %f/crypto/3xkoyr9lgj6baqfhvbqucmeefvlpmnrt.pdf %mf039a53443a474c2e8baa8fc94a167bb %ccrypto %@Sanjam Garg,Amit Sahai %*Adaptively Secure Multi-Party Computation with Dishonest Majority %f/crypto/j6klxvi4k7cvunztozmxtyshsfi38cdf.pdf %m85cc0f2937a013a7ba61ab3fcf9da173 %ccrypto %@Joël Alwen,Jonathan Katz,Ueli Maurer,Vassilis Zikas %*Collusion-Preserving Computation %f/crypto/uadkbteiybo3nsdrqcx8lheumvqim6ct.pdf %m55deea6cdcba9173d720107ee180cb3b %ccrypto %@Amos Beimel,Oriol Farràs,Yuval Mintz %*Secret Sharing Schemes for Very Dense Graphs %f/crypto/5oosxnipbpg1x8hdbrelajm37gycneiv.pdf %m57a6a035afc789161561f45c5c697440 %ccrypto %@Sergey Gorbunov,Vinod Vaikuntanathan,Hoeteck Wee %*Functional Encryption with Bounded Collusions via Multi-party Computation %f/crypto/rewm7blbgrp9uywy6sd1f43okafzdocg.pdf %mfc73eee437cf0fd7a027c9d62d1ea31c %ccrypto %@Allison Lewko,Brent Waters %*New Proof Methods for Attribute-Based Encryption: Achieving Full Security through Selective Techniques %f/crypto/5i4gus2ecevprp7lid31tgjncqmos0yy.pdf %m21aedd287d5b1ac651c842075034e0d2 %ccrypto %@Amit Sahai,Hakan Seyalioglu,Brent Waters %*Dynamic Credentials and Ciphertext Delegation for Attribute-Based Encryption %f/crypto/studqbfmuitzpvoe8h24qarw5xr6vzjf.pdf %m8dd669c859e52ce4697c37f0b96f1699 %ccrypto %@Brent Waters %*Functional Encryption for Regular Languages %f/crypto/dbyxe5azuxmedvjvi1iwmbfhk6zrqnsq.pdf %m8279e35e73ace3a693329e85cff46800 %ccrypto %@Melissa Chase,Ivan Visconti %*Secure Database Commitments and Universal Arguments of Quasi Knowledge %f/crypto/o0lxgvuqqmygncivycjj9as3wrzltfek.pdf %m95fe3040c095fbd7969a8c64d8934e74 %ccrypto %@Nir Bitansky,Alessandro Chiesa %*Succinct Arguments from Multi-prover Interactive Proofs and Their Efficiency Benefits %f/crypto/e3cajvkmzxmgchxvdqlb0dtkfah5p6wy.pdf %m1fbc8fd256a4a05dd8d77cdce8ab73ee %ccrypto %@Tibor Jager,Florian Kohlar,Sven Schäge,Jörg Schwenk %*On the Security of TLS-DHE in the Standard Model %f/crypto/zalt5awhemfnjdgefqbnymoi97wdk2p4.pdf %mcf8ba0940673f7dee875899247d06b37 %ccrypto %@Mihir Bellare,Stefano Tessaro,Alexander Vardy %*Semantic Security for the Wiretap Channel %f/crypto/f47tzkbnekai1lgjfo6sr0bwphwjpah9.pdf %m27d2aca8663dd9133b0df8d0a37e08ef %ccrypto %@Mihir Bellare,Thomas Ristenpart,Stefano Tessaro %*Multi-instance Security and Its Application to Password-Based Cryptography %f/crypto/kv5e0ndsgv4mdnqrmxy8t3pf6bcwtjjr.pdf %m72de80977e629b19899f6f87a5e9f6b0 %ccrypto %@Bart Mennink,Bart Preneel %*Hash Functions Based on Three Permutations: A Generic Security Analysis %f/crypto/wwxpzzm3407jlcgmcsokvfbvsbyepueh.pdf %m021c534618b2fe77cf564e1bca15df7c %ccrypto %@Yevgeniy Dodis,Thomas Ristenpart,John Steinberger,Stefano Tessaro %*To Hash or Not to Hash Again? (In)Differentiability Results for H^2 and HMAC %f/crypto/vptdnm4blq7aoyqe1csbmkudt3ogwzrf.pdf %m9c80e286f72a97e8aadb9b4e536890ed %ccrypto %@Simon Knellwolf,Dmitry Khovratovich %*New Preimage Attacks against Reduced SHA-1 %f/crypto/qntsdqzvt80r3liyjxzrmnogew4of6pj.pdf %mfcc189a9253defcb7fc8cd2f34527147 %ccrypto %@John Steinberger,Xiaoming Sun,Zhe Yang %*Stam’s Conjecture and Threshold Phenomena in Collision Resistance %f/crypto/gzydq0af9itpu1tc64sxpfhiqwwoeynv.pdf %m44b58cbfacab1d75c043ee0873f19a7a %ccrypto %@Mike Rosulek %*Universal Composability from Essentially Any Trusted Setup %f/crypto/u8aqba6lym7gppv4sw9rq3kdezjhbnul.pdf %mec5aa9abd786daaac3d8e1136255c54c %ccrypto %@Sanjam Garg,Abishek Kumarasubramanian,Rafail Ostrovsky,Ivan Visconti %*Impossibility Results for Static Input Secure Computation %f/crypto/eiu1kanjreg2nmj8x09dvxp6uqthfobb.pdf %m26a63ac34a9ad9c7353d75e7cb362498 %ccrypto %@Shweta Agrawal,Vipul Goyal,Abhishek Jain,Manoj Prabhakaran,Amit Sahai %*New Impossibility Results for Concurrent Composition and a Non-interactive Completeness Theorem for Secure Computation %f/crypto/63foq4pfoy0hv78njhra9ykg1gibqxdu.pdf %m84461ef9fd7fe9053b5937f200b7303a %ccrypto %@Huijia Lin,Rafael Pass %*Black-Box Constructions of Composable Protocols without Set-Up %f/crypto/byl0azkgum2vrnf3l6c8p5vcbxqwtizw.pdf %m9bac1e01937907b8721ddc3217496e04 %ccrypto %@Johannes Gehrke,Michael Hay,Edward Lui,Rafael Pass %*Crowd-Blending Privacy %f/crypto/vfbphjf5gnewz2bomylxh4q1sark93yi.pdf %ma1398f023a4a504a8a6aba3d47ade380 %ccrypto %@Yevgeniy Dodis,Adriana López-Alt,Ilya Mironov,Salil Vadhan %*Differential Privacy with Imperfect Randomness %f/crypto/qaubgxlrc9ezty8tn27foil5ijhogfdn.pdf %mce57c3759112ebbef1d555ff5f79dcd0 %ccrypto %@Feng-Hao Liu,Anna Lysyanskaya %*Tamper and Leakage Resilience in the Split-State Model %f/crypto/x4zb0g8icjdt76yswcgfsjrfma2hbe1u.pdf %mae9eb15e9f993c5b989fcb795ea97135 %ccrypto %@Dana Dachman-Soled,Yael Tauman Kalai %*Securing Circuits against Constant-Rate Tampering %f/crypto/3b7hfwmuvkew6ztq9lirdgey0kn4sliq.pdf %m3a28d861c1411815e2ce9d5d50c76f49 %ccrypto %@Guy N. Rothblum %*How to Compute under {\mathcal {\varvec{AC}}}^\mathbf{0} Leakage without Secure Hardware %f/crypto/sziv7kwp0oh1e2mqaolrergqgytunlmf.pdf %mf9e765985e1621641ea7556f286aaf74 %ccrypto %@Ernie Brickell %*Recent Advances and Existing Research Questions in Platform Security %f/crypto/iaw9rbtkfkdt2uqip4xgpryye6jvgdjz.pdf %mf82e58d26d6ab5fd140fbd6e15d8c448 %ccrypto %@Benoît Libert,Thomas Peters,Moti Yung %*Group Signatures with Almost-for-Free Revocation %f/crypto/zilfdvgslnpeq9j7krqid5yykun1wegj.pdf %md1905e2aa87c555db6fa6577473783df %ccrypto %@Dennis Hofheinz,Tibor Jager %*Tightly Secure Signatures and Public-Key Encryption %f/crypto/8ucjv2vbnwtgk6z0euqj3s9fwpf7pxtd.pdf %mcb0650913c21a01c50d2b334da00b30d %ccrypto %@Romain Bardou,Riccardo Focardi,Yusuke Kawamoto,Lorenzo Simionato,Graham Steel,Joe-Kai Tsay %*Efficient Padding Oracle Attacks on Cryptographic Hardware %f/crypto/imjzrcokudqglhiptvpwba5b8v72aefx.pdf %m4d6f4db14c2c965af713121998d51fd5 %ccrypto %@Arjen K. Lenstra,James P. Hughes,Maxime Augier,Joppe W. Bos,Thorsten Kleinjung,Christophe Wachter %*Public Keys %f/crypto/1r0vnufsrzqfihvowmsj9etdkjl7id5l.pdf %mf773c32409bc623d21a92a19a3b2610a %ccrypto %@Ivan Damgård,Valerio Pastro,Nigel Smart,Sarah Zakarias %*Multiparty Computation from Somewhat Homomorphic Encryption %f/crypto/zark6cvdghtksib0ojigw2axfqqepb7e.pdf %m60287215df146da3722a1468e1252e82 %ccrypto %@Eli Ben-Sasson,Serge Fehr,Rafail Ostrovsky %*Near-Linear Unconditionally-Secure Multiparty Computation with a Dishonest Minority %f/crypto/75inkfm4p8mcrsgaehoza0ekwqtbsjjb.pdf %m5ec98118991710222a2b8d93d451a36f %ccrypto %@Jesper Buus Nielsen,Peter Sebastian Nordholt,Claudio Orlandi,Sai Sheshank Burra %*A New Approach to Practical Active-Secure Two-Party Computation %f/crypto/rxdl128ynk0iv7lostxuc65bzjfpwaek.pdf %m5b4afb03cb6ce9ff8b230c2bbbaca8db %ccrypto %@Mohammad Mahmoody,Rafael Pass %*The Curious Case of Non-Interactive Commitments – On the Power of Black-Box vs. Non-Black-Box Use of Primitives %f/crypto/6ll1fetvtqckzqodwbfmciy5uvzpjagg.pdf %m960cbbd0e493ad5860db22a6ad14fea5 %ccrypto %@Itai Dinur,Orr Dunkelman,Nathan Keller,Adi Shamir %*Efficient Dissection of Composite Problems, with Applications to Cryptanalysis, Knapsacks, and Combinatorial Search Problems %f/crypto/y2bzs3h1lrul5syekd09t4owpjx6qaqd.pdf %mde34d0f5ae6b48869f4c6634a4e9cef6 %ccrypto %@Aslı Bay,Atefeh Mashatan,Serge Vaudenay %*Resistance against Iterated Attacks by Decorrelation Revisited %f/crypto/fnnsgqcy5wgh81zxm7tisevd6x9qjhpm.pdf %mb36d4adefb3b3088aee8f9b737afe3b6 %ccrypto %@Mark Zhandry %*Secure Identity-Based Encryption in the Quantum Random Oracle Model %f/crypto/1eoew9xkvtzv0msbduo5jczqdf84ukyc.pdf %m2e3c095d3fc74d9271bcbe8457314bda %ccrypto %@Mario Berta,Omar Fawzi,Stephanie Wehner %*Quantum to Classical Randomness Extractors %f/crypto/se7hmri5g4mvx8intdytvxbbzcwusu0f.pdf %m562a6e1c98c16c80314c86379f13f7fa %ccrypto %@Frédéric Dupuis,Jesper Buus Nielsen,Louis Salvail %*Actively Secure Two-Party Evaluation of Any Quantum Operation %f/crypto/3s6odeca429yinqspuzfgpwrizvxve8t.pdf %m4b9d5374ffad111ed1af9260aa1c7627 %ccrypto %@Goichiro Hanaoka,Takahiro Matsuda,Jacob C. N. Schuldt %*On the Impossibility of Constructing Efficient Key Encapsulation and Programmable Hash Functions in Prime Order Groups %f/crypto/uovcdjwjqbblsxe2pqyzamv4akkefpmt.pdf %m706394db7f5271f29bb38a2e2c465b0a %ccrypto %@Alexandre Duc,Dimitar Jetchev %*Hardness of Computing Individual Bits for One-Way Functions on Elliptic Curves %f/crypto/8xe4wtdl0gv7ifkn6qsejafmhxcr2awi.pdf %mb5637a5a3ee2e5deba9c6ce9c7716bdf %ccrypto %@Craig Gentry,Shai Halevi,Nigel P. Smart %*Homomorphic Evaluation of the AES Circuit %f/crypto/pxehpgfzrkusd9kin2mtnzbecqj67hdm.pdf %m0d9e2b9784d47d36bd8041941676860d %ccrypto %@Zvika Brakerski %*Fully Homomorphic Encryption without Modulus Switching from Classical GapSVP %f/crypto/zeylrblcxjdpwnr1gmktiouki6nzd9xg.pdf %m7066909f69543a730ce94122616b54e6 %ccrypto %@Boaz Barak,Yevgeniy Dodis,Hugo Krawczyk,Olivier Pereira,Krzysztof Pietrzak,François-Xavier Standaert,Yu Yu %*Leftover Hash Lemma, Revisited %f/crypto/0o26v7wjzhov3tjihbrwqrmucsdgzyix.pdf %m3910b6d945f0cfdb4848a2649729059f %ccrypto %@Paul Baecher,Marc Fischlin %*Random Oracle Reducibility %f/crypto/avuqcvj9ejg2nxwmybm8sqfidtexr3g4.pdf %m8c89091db24b868cddd284d9a4d37c9d %ccrypto %@Mohammad Mahmoody,Tal Moran,Salil Vadhan %*Time-Lock Puzzles in the Random Oracle Model %f/crypto/bnnqvmc1aqkepad930ip2rlz4o5w8te7.pdf %m55e0a8dbe86119de98d11b0cd003219e %ccrypto %@Christina Brzuska,Marc Fischlin,Heike Schröder,Stefan Katzenbeisser %*Physically Uncloneable Functions in the Universal Composition Framework %f/crypto/honv7xgj8pjq4m3pztw1fss9ihxlkey6.pdf %mf5eb0c049971ce5f933ab829a2d4c4f0 %ccrypto %@Gilles Barthe,Benjamin Grégoire,Sylvain Heraud,Santiago Zanella Béguelin %*Computer-Aided Security Proofs for the Working Cryptographer %f/crypto/a5omtvdzuwo7glnmxc4wv9jkbyg3b12z.pdf %m4e290ef173452a6cadfa7b0dd5f819b1 %ccrypto %@Charalampos Papamanthou,Roberto Tamassia,Nikos Triandopoulos %*Optimal Verification of Operations on Dynamic Sets %f/crypto/cek53gv7ntcmtyxwfbu0qgnoreprhasl.pdf %mcee7e8feb9e45becf65363aaa5ca3a8a %ccrypto %@Siavosh Benabbas,Rosario Gennaro,Yevgeniy Vahlis %*Verifiable Delegation of Computation over Large Datasets %f/crypto/g6bf9nlnoduxlg5u84irhqfpej3aq71t.pdf %m3debbdfaf3ab74432521ea7e545463a2 %ccrypto %@Shai Halevi,Yehuda Lindell,Benny Pinkas %*Secure Computation on the Web: Computing without Simultaneous Interaction %f/crypto/k6s09amm2hcwdvekxotafq7y4hjer8n5.pdf %m37a971c62a5fe204847fd641261e264a %ccrypto %@Kai-Min Chung,Yael Tauman Kalai,Feng-Hao Liu,Ran Raz %*Memory Delegation %f/crypto/c4droqkh3g7jutu2by5lzlwvocfs8wz0.pdf %m8a6f8fd60a9da8a1b2b25cba52c02949 %ccrypto %@Charles Bouillaguet,Patrick Derbez,Pierre-Alain Fouque %*Automatic Search of Attacks on Round-Reduced AES and Applications %f/crypto/kaypcmuwexxdl1ga5vfnqob8rf9siuqs.pdf %md0e5e2895f8006955c3131d821634c43 %ccrypto %@María Naya-Plasencia %*How to Improve Rebound Attacks %f/crypto/rc1zaj0ayghmnxsivkr65fyeqfbgo9id.pdf %m4b460637db7248b751fcfa1b16de8209 %ccrypto %@Gregor Leander,Mohamed Ahmed Abdelraheem,Hoda AlKhzaimi,Erik Zenner %*A Cryptanalysis of PRINTcipher: The Invariant Subspace Attack %f/crypto/oxrt4rklfqws65ivbqzb8hayfu3thnmx.pdf %m0dd70c28c6eb705b27ea660f06234cb0 %ccrypto %@Jian Guo,Thomas Peyrin,Axel Poschmann %*The PHOTON Family of Lightweight Hash Functions %f/crypto/8szqbpvhg3ydfidgrnhl2jma49n56pvj.pdf %m4d51a213651d8cb37c75310f7dedd939 %ccrypto %@Gilad Asharov,Yehuda Lindell,Tal Rabin %*Perfectly-Secure Multiplication for Any t < n/3 %f/crypto/tucdbonqpszh6jbrj5umayhxqvl7nd1i.pdf %m8d4d636d8f72e5d6da1d4ae4c7dd0aa8 %ccrypto %@Yehuda Lindell,Eli Oxman,Benny Pinkas %*The IPS Compiler: Optimizations, Variants and Concrete Efficiency %f/crypto/ls8e2mo7xghvzbzamjusnuviecn6yp1r.pdf %m2f7deff1fec091ad7eb8753254fab3a4 %ccrypto %@Amos Beimel,Yehuda Lindell,Eran Omri,Ilan Orlov %*1/p-Secure Multiparty Computation without Honest Majority and the Best of Both Worlds %f/crypto/uqdnscwek9mfv25etnrp7mh3bip4zgxz.pdf %mfe681ad8ae72f9a5c0c363e561c506d8 %ccrypto %@Sanjam Garg,Abhishek Jain,Amit Sahai %*Leakage-Resilient Zero Knowledge %f/crypto/uz50bsoj41nuvtxgk7rtmbywce2wr98f.pdf %m0748d78175b12b6ceb44d5c2a08cd9d3 %ccrypto %@Carolyn Whitnall,Elisabeth Oswald %*A Comprehensive Evaluation of Mutual Information Analysis Using a Fair Evaluation Framework %f/crypto/n8ewiozgjmxfvsanbragclld75hpmvyk.pdf %m22b4977f92208960796a8a3fac399169 %ccrypto %@Stefan Dziembowski,Tomasz Kazana,Daniel Wichs %*Key-Evolution Schemes Resilient to Space-Bounded Leakage %f/crypto/gfrkcxj9vgtnemo1im6lckvaf3uzwbs7.pdf %mf4eea1b6a2bb438ead2fb21940dafbd2 %ccrypto %@Nicolas Veyrat-Charvillon,François-Xavier Standaert %*Generic Side-Channel Distinguishers: Improvements and Limitations %f/crypto/s0uxk2pnhyr6kaw7ngrezzvgmta8cjyc.pdf %mfcc6c3f2d25b4588af2e0fe6852c997b %ccrypto %@Yael Tauman Kalai,Bhavana Kanukurthi,Amit Sahai %*Cryptography with Tamperable and Leaky Memory %f/crypto/a7djfkbwkzu3irnhtrsexbzn4sp1eooy.pdf %m2e5dbde1327cbbb4b3232fe6366cf90d %ccrypto %@Gilles Brassard,Peter Høyer,Kassem Kalach,Marc Kaplan,Sophie Laplante,Louis Salvail %*Merkle Puzzles in a Quantum World %f/crypto/quxruow1yb6vwhgez79kmhnc3sxicyas.pdf %m3ea5d4919afef28404cba0bfca18a3c8 %ccrypto %@Sean Hallgren,Adam Smith,Fang Song %*Classical Cryptographic Protocols in a Quantum World %f/crypto/q7xtrp8euimhv1nmygwn9w5dgsskv6x0.pdf %m25cb608724c7694b59ab2cba57e244f8 %ccrypto %@Harry Buhrman,Nishanth Chandran,Serge Fehr,Ran Gelles,Vipul Goyal,Rafail Ostrovsky,Christian Schaffner %*Position-Based Quantum Cryptography: Impossibility and Constructions %f/crypto/tznv9yqezvfhbla2c3ijfxuqexndmpoc.pdf %m593e51d478f3ddce184a0ceb25fde957 %ccrypto %@Guillaume Hanrot,Xavier Pujol,Damien Stehlé %*Analyzing Blockwise Lattice Algorithms Using Dynamical Systems %f/crypto/ykouzrts5jomlvxlvk9bwbuifnhc3sd0.pdf %mf0ac0edc3ac144ad42b313353f46fd24 %ccrypto %@Daniele Micciancio,Petros Mol %*Pseudorandom Knapsacks and the Sample Complexity of LWE Search-to-Decision Reductions %f/crypto/rl1gt9de4jvcqx3cooqrti0wmxzuas27.pdf %ma91764bfe3911214e2ea8b59eda2f12b %ccrypto %@Roger Dingledine %*Tor and Circumvention: Lessons Learned %f/crypto/qygagzfbtafbmcij40znvcrsd8hq7tvd.pdf %m5e9a89ee6c67b328e56c8dd099ae8021 %ccrypto %@Jean-Sébastien Coron,Avradip Mandal,David Naccache,Mehdi Tibouchi %*Fully Homomorphic Encryption over the Integers with Shorter Public Keys %f/crypto/c0ximobmo4l92pyuanjdvqfu15p8ejnq.pdf %m31de8e7be8e0112fbc3caae5b554215b %ccrypto %@Zvika Brakerski,Vinod Vaikuntanathan %*Fully Homomorphic Encryption from Ring-LWE and Security for Key Dependent Messages %f/crypto/mhv0ki5yeouosltxgdx3ba91rizr6gf2.pdf %mc9936acb46e52b6ff207529dc3d6b70a %ccrypto %@Adam O’Neill,Chris Peikert,Brent Waters %*Bi-Deniable Public-Key Encryption %f/crypto/mrzhvndd64g7n0ezyxav2ckwia89epr1.pdf %ma353f9627b9c8b9993048c65fd36b41e %ccrypto %@Zvika Brakerski,Gil Segev %*Better Security for Deterministic Public-Key Encryption: The Auxiliary-Input Setting %f/crypto/m8sgtdgrha5c3ilq4jcbwoe9piualth6.pdf %ma5f2bee2bab30fde2b36833825ea1444 %ccrypto %@Jooyoung Lee,Martijn Stam,John Steinberger %*The Collision Security of Tandem-DM in the Ideal Cipher Model %f/crypto/ehfmqbcurhv3mwipqa2g7etl1uzykn86.pdf %m13bd3a78bfa3521d07d715a4da954950 %ccrypto %@Alexandra Boldyreva,Nathan Chenette,Adam O’Neill %*Order-Preserving Encryption Revisited: Improved Security Analysis and Alternative Solutions %f/crypto/u5rlvdsonyt7b4pq208cpgftyogwhe6l.pdf %m1c541882c615563209404cb208f76f03 %ccrypto %@Kan Yasuda %*A New Variant of PMAC: Beyond the Birthday Bound %f/crypto/fdxepdssm4hcuucta6xo5bqbyr07w2hy.pdf %mf7bc792da7756262407af7cf25db9157 %ccrypto %@Mihir Bellare,Sriram Keelveedhi %*Authenticated and Misuse-Resistant Encryption of Key-Dependent Data %f/crypto/unatcg1veuaix7lqwhyzsxbr8lootik2.pdf %m078e7aa3db857817be42dd8be249a1da %ccrypto %@Sanjam Garg,Vanishree Rao,Amit Sahai,Dominique Schröder,Dominique Unruh %*Round Optimal Blind Signatures %f/crypto/y8s0vpqaqm1ziugjcp5vtthke6zdw2mh.pdf %mbc5af003d8b6cad670f7b7b3a9c837a3 %ccrypto %@Masayuki Abe,Jens Groth,Kristiyan Haralambiev,Miyako Ohkubo %*Optimal Structure-Preserving Signatures in Asymmetric Bilinear Groups %f/crypto/koahnegzsbis6tm7yt3zvj2rfqbnfq4o.pdf %mb4c1bf8b1948088445501dd6227bcb59 %ccrypto %@Yuval Ishai,Eyal Kushilevitz,Rafail Ostrovsky,Manoj Prabhakaran,Amit Sahai,Jürg Wullschleger %*Constant-Rate Oblivious Transfer from Noisy Channels %f/crypto/cwdf4ysltkmaruv57tal1jidyfpe2xzq.pdf %m553d3384433c433cee22f39d23cb9538 %ccrypto %@Ignacio Cascudo,Ronald Cramer,Chaoping Xing %*The Torsion-Limit for Algebraic Function Fields and Its Application to Arithmetic Secret Sharing %f/crypto/a1bgrwwzjo4jeqa2pft8elhuyurfkxk3.pdf %m832aeafc88e30846cf96bfa59064a73c %ccrypto %@Koichi Sakumoto,Taizo Shirai,Harunaga Hiwatari %*Public-Key Identification Schemes Based on Multivariate Quadratic Polynomials %f/crypto/phdolbzk8evtcysvp4wbs3inl5gzmnrh.pdf %m863c518ae31be2954f25f5defc3c97d0 %ccrypto %@Jintai Ding,Timothy J. Hodges %*Inverting HFE Systems Is Quasi-Polynomial for All Fields %f/crypto/dkvc3sxe5grxiugllhc1yeqop7motr2b.pdf %m09a69d30ea7ee1f83ca3f8fafeafa31d %ccrypto %@Daniel J. Bernstein,Tanja Lange,Christiane Peters %*Smaller Decoding Exponents: Ball-Collision Decoding %f/crypto/qfjbo4ign35nh7yx8fmtkbrslevquu6t.pdf %mfb4904a3aa4a000cacc2f4020df32cf7 %ccrypto %@Hang Dinh,Cristopher Moore,Alexander Russell %*McEliece and Niederreiter Cryptosystems That Resist Quantum Fourier Sampling Attacks %f/crypto/uswo4hhgvdfmwlb6qnprx8akp13yc0eg.pdf %m8daba0cdfb92dcc168a9cd83f6c42de9 %ccrypto %@Zvika Brakerski,Shafi Goldwasser %*Circular and Leakage Resilient Public-Key Encryption under Subgroup Indistinguishability %f/crypto/p3gnwrb6q9ezqc0lpyio2jjltsvmnzhu.pdf %m5e23b998a33f090c10976eef94d51665 %ccrypto %@Yevgeniy Dodis,Krzysztof Pietrzak %*Leakage-Resilient Pseudorandom Functions and Side-Channel Attacks on Feistel Networks %f/crypto/8gfpwaowuszni0y1lxykdot5qhnm7ztu.pdf %m6021d0996abd7517549a83491f6b61d0 %ccrypto %@Ali Juma,Yevgeniy Vahlis %*Protecting Cryptographic Keys against Continual Leakage %f/crypto/2suooa5simmchg0x37fvrw1trb69zxq8.pdf %m631bb99b825f3340c627799174c20a38 %ccrypto %@Shafi Goldwasser,Guy N. Rothblum %*Securing Computation against Continuous Leakage %f/crypto/nqoyfsh1wdcjlex4a7gq9nmtmir8ifws.pdf %m07297a83f211334ffd795bcd21cb777d %ccrypto %@Chris Peikert %*An Efficient and Parallel Gaussian Sampler for Lattices %f/crypto/hu1jx97kmsycxdg3wnegryu0piv5cia6.pdf %m128dc691c9c98d2eef1050f0df75509f %ccrypto %@Shweta Agrawal,Dan Boneh,Xavier Boyen %*Lattice Basis Delegation in Fixed Dimension and Shorter-Ciphertext Hierarchical IBE %f/crypto/cz6triy5obc9pyrwafpgjd8lh3moqmvk.pdf %mc5b9f21984d7653ea2b7f7156574dd20 %ccrypto %@Craig Gentry %*Toward Basing Fully Homomorphic Encryption on Worst-Case Hardness %f/crypto/0d5vqzw9j3iklbxxe1sy8vdomfh7wsci.pdf %m4d5f38c7b4f3291e7d94949c9148058c %ccrypto %@Carlos Aguilar Melchor,Philippe Gaborit,Javier Herranz %*Additively Homomorphic Encryption with d-Operand Multiplications %f/crypto/uvsjuizacosmfr4d0qtp8oxfe2p6zbwh.pdf %m1635660e9bcdfd845e9376c21653d30e %ccrypto %@Craig Gentry,Shai Halevi,Vinod Vaikuntanathan %*i-Hop Homomorphic Encryption and Rerandomizable Yao Circuits %f/crypto/cqm6fjabe4hwv2ixyv0wtn5bxl7udg1a.pdf %mbdaa5ecc0e0dc05abb18492680c30699 %ccrypto %@Vipul Goyal,Yuval Ishai,Mohammad Mahmoody,Amit Sahai %*Interactive Locking, Zero-Knowledge PCPs, and Unconditional Cryptography %f/crypto/vz28dfehpoth3qw5yuwinoidrc1spamy.pdf %m3a743f69dcc3259f50bdbacd7004acf6 %ccrypto %@Tatsuaki Okamoto,Katsuyuki Takashima %*Fully Secure Functional Encryption with General Relations from the Decisional Linear Assumption %f/crypto/5lfjyfv1dvh9sbpybxzceqha23tirm0l.pdf %m2ab418402d1832776253c2187f22b451 %ccrypto %@Masayuki Abe,Georg Fuchsbauer,Jens Groth,Kristiyan Haralambiev,Miyako Ohkubo %*Structure-Preserving Signatures and Commitments to Group Elements %f/crypto/ctmkbrno6q9kd2lgjospy1eiphhf3xuy.pdf %m7925044920654cd3a16410f0a9219802 %ccrypto %@Eric Brier,Jean-Sébastien Coron,Thomas Icart,David Madore,Hugues Randriam,Mehdi Tibouchi %*Efficient Indifferentiable Hashing into Ordinary Elliptic Curves %f/crypto/bzgkwdyouu2mq0vl6e8rjfj7dnt5sqb4.pdf %md2d122226dd42929080df920b52ba273 %ccrypto %@Jan Camenisch,Nathalie Casati,Thomas Gross,Victor Shoup %*Credential Authenticated Identification and Key Exchange %f/crypto/xoj731xl8m9trkflcycijbed5qawtgr4.pdf %m5ca59b037c0ec6ff447ee3919081de39 %ccrypto %@Vipul Goyal,Abhishek Jain,Rafail Ostrovsky %*Password-Authenticated Session-Key Generation on the Internet in the Plain Model %f/crypto/05ifmr42gzyt1p8vwkl7dbdtcyguxhlp.pdf %m215ec08069cc49ff8297e17c5c4310d0 %ccrypto %@Eike Kiltz,Adam O’Neill,Adam Smith %*Instantiability of RSA-OAEP under Chosen-Plaintext Attack %f/crypto/y5kugiczbwd71lq2mxpzurtemvhdg4f6.pdf %m9e39373bf2172eb73208558d2d472953 %ccrypto %@Hoeteck Wee %*Efficient Chosen-Ciphertext Security via Extractable Hash Proofs %f/crypto/mvr52efqxy0aomtdbhujid1pk6wo9x3y.pdf %mfbfb2feb18ff112f61b6c4c6edd3822f %ccrypto %@Thorsten Kleinjung,Kazumaro Aoki,Jens Franke,Arjen K. Lenstra,Emmanuel Thomé,Joppe W. Bos,Pierrick Gaudry,Alexander Kruppa,Peter L. Montgomery,Dag Arne Osvik,Herman te Riele,Andrey Timofeev,Paul Zimmermann %*Factorization of a 768-Bit RSA Modulus %f/crypto/zq6atpuuskaypi3wy0zcjvhqhgm1nx8b.pdf %m458366dea67948d1070de569621a7a34 %ccrypto %@Wilko Henecka,Alexander May,Alexander Meurer %*Correcting Errors in RSA Private Keys %f/crypto/2ksrq0cco8dz6vnre1yohh5wafnmstpu.pdf %m83456d3e29acbd501ed4443676850094 %ccrypto %@Thomas Peyrin %*Improved Differential Attacks for ECHO and Grøstl %f/crypto/8ocy1nyqgbhxgdzckf5pd0rikufaew34.pdf %mb342d8b2ebc7d297001b00f9d96b6b0f %ccrypto %@Orr Dunkelman,Nathan Keller,Adi Shamir %*A Practical-Time Related-Key Attack on the KASUMI Cryptosystem Used in GSM and 3G Telephony %f/crypto/bxocsijzx840jcmlsphuzhgf3eydd5wt.pdf %ma4c7e0ea9e178ad09e5b674a68c21edb %ccrypto %@Dominique Unruh,Jörn Müller-Quade %*Universally Composable Incoercibility %f/crypto/jm7k5nlghtjms6dw1d4vbepazfh9iaoe.pdf %mbc734260c176bf6efd857dde9b3c599b %ccrypto %@Huijia Lin,Rafael Pass,Wei-Lung Dustin Tseng,Muthuramakrishnan Venkitasubramaniam %*Concurrent Non-Malleable Zero Knowledge Proofs %f/crypto/cbkytm4giqgwzht0hr9je1rvfasxqe3z.pdf %m461f978d36f147900afea585145916a5 %ccrypto %@Chongwon Cho,Chen-Kuei Lee,Rafail Ostrovsky %*Equivalence of Uniform Key Agreement and Composition Insecurity %f/crypto/ixggk8ezthbvdo0qa45anb97uc1qfhyv.pdf %maa5f99912809d0684bdc3ae45e64f2bf %ccrypto %@Rosario Gennaro,Craig Gentry,Bryan Parno %*Non-interactive Verifiable Computing: Outsourcing Computation to Untrusted Workers %f/crypto/fkvxgtcira8jon9k7fbscxqt4wes6pg1.pdf %ma747e3336acdee254c8a6ca2b58260da %ccrypto %@Kai-Min Chung,Yael Kalai,Salil Vadhan %*Improved Delegation of Computation Using Fully Homomorphic Encryption %f/crypto/giprdlxmnbutqeokxgh6tzld54rfoyw8.pdf %m536877f2964d886dbb21b487675a59cf %ccrypto %@Benny Pinkas,Tzachy Reinman %*Oblivious RAM Revisited %f/crypto/7c84dxabyzi2thjgrr5sfojv3ihungku.pdf %m4b388e551f06891e8164c0e55e183e88 %ccrypto %@Nir Bitansky,Ran Canetti %*On Strong Simulation and Composable Point Obfuscation %f/crypto/8dj1pydua02yqw4fgi6hqvbgevxrnmms.pdf %m21aa38954cc11df9cb1777e62931aba3 %ccrypto %@Amos Beimel,Eran Omri,Ilan Orlov %*Protocols for Multiparty Coin Toss with Dishonest Majority %f/crypto/ptu45pahluy6rqc3ec9gonwmyd7fd8ro.pdf %m2997fb8acc153074c67ef590b2a3bac0 %ccrypto %@Ivan Damgård,Claudio Orlandi %*Multiparty Computation for Dishonest Majority: From Passive to Active Security at Low Cost %f/crypto/vchq1wctfkeim6mdoohlpgjqzdxtxvzp.pdf %mfdc12aef4f1f16b030c798544e5951e7 %ccrypto %@Yuval Ishai,Eyal Kushilevitz,Anat Paskin %*Secure Multiparty Computation with Minimal Interaction %f/crypto/yq23m7rifho4ayazcjdkll6wzbfvngtg.pdf %m895f23e5b89d88cb2ed6cc33c4efc5b5 %ccrypto %@Hemanta K. Maji,Manoj Prabhakaran,Mike Rosulek %*A Zero-One Law for Cryptographic Complexity with Respect to Computational UC Security %f/crypto/oyyhirjblenklp41axpc7gvewncioh5z.pdf %m7b67a83d8994475a7010cb379419734a %ccrypto %@Viet Tung Hoang,Phillip Rogaway %*On Generalized Feistel Networks %f/crypto/6ek4cwygeiscohlfvwdj78ntnu1frpr0.pdf %mbf14db714d4b18085f7788a86a2380c3 %ccrypto %@Hugo Krawczyk %*Cryptographic Extraction and Key Derivation: The HKDF Scheme %f/crypto/gyupdniae02jirtaqevhlwdw43nckqv8.pdf %m7a6b6f1520505f43930eaba4120dc90f %ccrypto %@Anindya De,Luca Trevisan,Madhur Tulsiani %*Time Space Tradeoffs for Attacks against One-Way Functions and PRGs %f/crypto/vcej6ywalekossd58zftcgbnjxk32liu.pdf %m3183bc50777caa90240b4789bb512299 %ccrypto %@Mihir Bellare,David Cash %*Pseudorandom Functions and Permutations Provably Secure against Related-Key Attacks %f/crypto/qvdrvnayrsx85paozd2tomqiepf7bxuy.pdf %m04b3b392ca67b436b4adf8b694b55ca2 %ccrypto %@Frédéric Dupuis,Jesper Buus Nielsen,Louis Salvail %*Secure Two-Party Quantum Evaluation of Unitaries against Specious Adversaries %f/crypto/xmaoyuwgt8ahlhibzrxqdr6vzvqsst0p.pdf %md0671a92473a9bfd325c9212bbe51364 %ccrypto %@Severin Winkler,Jürg Wullschleger %*On the Efficiency of Classical and Quantum Oblivious Transfer Reductions %f/crypto/7ca0azekjkyviqfudzmtvfbpow92ql53.pdf %m26f1e5a413c9bd2f3dea1eddbdb54ec7 %ccrypto %@Niek J. Bouman,Serge Fehr %*Sampling in a Quantum Population, and Applications %f/crypto/wr3ifjbt0epyvz7nlwshhx21praddktq.pdf %m09e57f382d7595823944d7705c9fa087 %ccrypto %@Nadia Heninger,Hovav Shacham %*Reconstructing RSA Private Keys from Random Key Bits %f/crypto/1aoxvgsgijzztq0wihpec67nr35qyr9a.pdf %m8799b9d839b16d9b7dd2131d52248c4e %ccrypto %@Moni Naor,Gil Segev %*Public-Key Cryptosystems Resilient to Key Leakage %f/crypto/ywpsg2ogauynebf7rjmvaneql3h8wotx.pdf %mdbca0adc9af8b6c1d78a3d64bbb591f9 %ccrypto %@Joël Alwen,Yevgeniy Dodis,Daniel Wichs %*Leakage-Resilient Public-Key Cryptography in the Bounded-Retrieval Model %f/crypto/5spsbk8ihay41gxunonpgvrlh6fi7jer.pdf %m2b2a503e6ac83688ed376b2c0e396dff %ccrypto %@Marc Stevens,Alexander Sotirov,Jacob Appelbaum,Arjen Lenstra,David Molnar,Dag Arne Osvik,Benne de Weger %*Short Chosen-Prefix Collisions for MD5 and the Creation of a Rogue CA Certificate %f/crypto/eqallfiy5t4oykvowfprh0e8u3gzxg9n.pdf %m11943866982c18ee2c877e3a5df6fbf9 %ccrypto %@Kazumaro Aoki,Yu Sasaki %*Meet-in-the-Middle Preimage Attacks Against Reduced SHA-0 and SHA-1 %f/crypto/tetfxissig7gba6uekuyrvjqzvf5kp39.pdf %m55c25e9251384cc6d9717d6a8e03d4db %ccrypto %@Stanisław Jarecki,Xiaomin Liu %*Private Mutual Authentication and Conditional Oblivious Transfer %f/crypto/0uhgiceyodrqibyf5t1wp4ckv2vm6sfl.pdf %ma4f4075bb22888c0c8e322678ff27d05 %ccrypto %@Mira Belenkiy,Jan Camenisch,Melissa Chase,Markulf Kohlweiss,Anna Lysyanskaya,Hovav Shacham %*Randomizable Proofs and Delegatable Anonymous Credentials %f/crypto/i3yvr7mzplvhnmbcofwxg0e5pl9iba2g.pdf %me117823602dc16104d63c73c485297b9 %ccrypto %@Ilya Mironov,Omkant Pandey,Omer Reingold,Salil Vadhan %*Computational Differential Privacy %f/crypto/t6o0ozul3fsvirvy1eqaqdw8fetml2i5.pdf %mb6ba7a7ee99fe0b8bc27c6b3ea4040f0 %ccrypto %@Yael Tauman Kalai,Ran Raz %*Probabilistically Checkable Arguments %f/crypto/hikwl0qbvyko8s5x4xa9bzftqjicgng1.pdf %ma2b9b548eae517ff139d642037197833 %ccrypto %@Rafael Pass,Wei-Lung Dustin Tseng,Douglas Wikström %*On the Composition of Public-Coin Zero-Knowledge Protocols %f/crypto/bpuicptaeqzt6gfx0v2k5srowab7frcn.pdf %m78186a9b439cb7bc250cb67498597a39 %ccrypto %@Ronald Cramer,Ivan Damgård %*On the Amortized Complexity of Zero-Knowledge Protocols %f/crypto/4obwy5q7p2mru8i3k1tbzxdlv9ueepns.pdf %mab2d6f75f0f23e20edad9631d14ba618 %ccrypto %@Jens Groth %*Linear Algebra with Sub-linear Zero-Knowledge Arguments %f/crypto/5gtxvvr6la8d24sxuofpiopjlamugeqe.pdf %mc8776ec2712d7624031caa939ce4c909 %ccrypto %@Zheng Yuan,Wei Wang,Keting Jia,Guangwu Xu,Xiaoyun Wang %*New Birthday Attacks on Some MACs Based on Block Ciphers %f/crypto/prioqdbvdtevzwfcufmhmza25er6xkt1.pdf %m817b5f068bb2c7b0cf791a19982ffb8c %ccrypto %@Alex Biryukov,Dmitry Khovratovich,Ivica Nikolić %*Distinguisher and Related-Key Attack on the Full AES-256 %f/crypto/5tlphsefdyqwxqbg4g6ocz931okctrin.pdf %mfdc4b6ce72140cade9b93ea2c71a760e %ccrypto %@Julia Borghoff,Lars R. Knudsen,Gregor Leander,Krystian Matusiewicz %*Cryptanalysis of C2 %f/crypto/e6tp1gpfxquulv2n8ctbiiy9oayjsddk.pdf %m5da12c4fc536c8fa6abd11805a659a5b %ccrypto %@Yevgeniy Dodis,John Steinberger %*Message Authentication Codes from Unpredictable Block Ciphers %f/crypto/uwpfb7ehcdkhedgxnz4vzl6rst9nqvwy.pdf %m0a26d267f6630b9ed32c6920de2fe38f %ccrypto %@Ben Morris,Phillip Rogaway,Till Stegers %*How to Encipher Messages on a Small Domain %f/crypto/2zo7jibg8eyyubltq61m3sewh5sndkng.pdf %m16395d42be58aa215f2dbac35b82b3c3 %ccrypto %@Thomas Icart %*How to Hash into Elliptic Curves %f/crypto/4qmc78fwp6liaqywrlbbm0ngczdxi3ef.pdf %me169d2631bd62e09f5a223fd68954b2d %ccrypto %@Daniel J. Bernstein %*Batch Binary Edwards %f/crypto/lzmmb9ky4qril3ozrb0pwscdjpv6uhh1.pdf %m996195035291464b37b01a5e631fa1a7 %ccrypto %@Adi Akavia %*Solving Hidden Number Problem with One Bit Oracle and Advice %f/crypto/ndrgihqw7gs5cbn6djfyk3y92caukmou.pdf %m1465572f0a91bbfde6f2132abbe56204 %ccrypto %@Ueli Maurer,Stefano Tessaro %*Computational Indistinguishability Amplification: Tight Product Theorems for System Composition %f/crypto/8b3vnyrpgcerzty9e0ldmwdnzuqipa5g.pdf %m0efb286bf74da813f83d028c36742dcc %ccrypto %@Boaz Barak,Mohammad Mahmoody-Ghidary %*Merkle Puzzles Are Optimal — An O(n2)-Query Attack on Any Key Exchange from a Random Oracle %f/crypto/hs8tpwdpv0ouc7nvbkmraeyxrzmsigt4.pdf %mfc903f49c3ec3b91a10043b44181ca17 %ccrypto %@Nishanth Chandran,Vipul Goyal,Ryan Moriarty,Rafail Ostrovsky %*Position Based Cryptography %f/crypto/6qxezitf0otoa4g1b8bmkzspdrwpkmj2.pdf %m481449e4f9fb22efae545717ed01de25 %ccrypto %@Ivan Damgård,Serge Fehr,Carolin Lunemann,Louis Salvail,Christian Schaffner %*Improving the Security of Quantum Protocols via Commit-and-Open %f/crypto/bs5whcgnk1cptdxasreloe7j0oxrztg3.pdf %m62370c5975fb7d30717d29c88b680f17 %ccrypto %@Jean-Sébastien Coron,David Naccache,Mehdi Tibouchi,Ralf-Philipp Weinmann %*Practical Cryptanalysis of iso/iec 9796-2 and emv Signatures %f/crypto/nlzvbknu9rfqcoqsb5mg6ppguf38zdsj.pdf %m5e98adce3631e69b12396ba7c59d2a6f %ccrypto %@Gaëtan Leurent,Phong Q. Nguyen %*How Risky Is the Random-Oracle Model? %f/crypto/tkyj1ynnegtbwgx3hfiwozpd7lvamszp.pdf %m7428b8828f2c03c99014f31a404a78ea %ccrypto %@Ueli Maurer %*Abstraction in Cryptography %f/crypto/ix9rm5napzgbe61ocfv3hje7bigmwu2h.pdf %md84ad5f21e2cf9d456abdbec505c749c %ccrypto %@Ignacio Cascudo,Hao Chen,Ronald Cramer,Chaoping Xing %*Asymptotically Good Ideal Linear Secret Sharing with Strong Multiplication over Any Fixed Finite Field %f/crypto/mmgbip75uxxg2fsldirohnzcyoqk4wnt.pdf %m4b86918267b6fb5d305fc5cf98cd64ec %ccrypto %@Arpita Patra,Ashish Choudhary,Tal Rabin,C. Pandu Rangan %*The Round Complexity of Verifiable Secret Sharing Revisited %f/crypto/qfx2nd78b4vjxirnujhwypgkadqobcag.pdf %mf8bae284f7eee6be0ecd77d4763f65bc %ccrypto %@Juan A. Garay,Daniel Wichs,Hong-Sheng Zhou %*Somewhat Non-committing Encryption and Efficient Adaptively Secure Oblivious Transfer %f/crypto/bday47ri9jbgiqh1zmexpmflaxyuk3qt.pdf %m3244498158aafe234ed158afdea7f1ed %ccrypto %@Joël Alwen,Jonathan Katz,Yehuda Lindell,Giuseppe Persiano,abhi shelat,Ivan Visconti %*Collusion-Free Multiparty Computation in the Mediated Model %f/crypto/od3wsg7ax68ytzzj9v5ghff12cxjqwkn.pdf %m5d830ec5eaaf61f7635bb12b8a94b4c6 %ccrypto %@Peter Bro Miltersen,Jesper Buus Nielsen,Nikos Triandopoulos %*Privacy-Enhancing Auctions Using Rational Cryptography %f/crypto/jjvrziv9elngytdoslgemh5wnrcf7fso.pdf %m4c0b6d098a23a6633af2edec51e1af78 %ccrypto %@Gilad Asharov,Yehuda Lindell %*Utility Dependence in Correct and Fair Rational Secret Sharing %f/crypto/qhoaauqit71mekxgyfz0smp4xjdsv9n8.pdf %me7aae6cb4333f1fd54cb3e7f0c267437 %ccrypto %@Vadim Lyubashevsky,Daniele Micciancio %*On Bounded Distance Decoding, Unique Shortest Vectors, and the Minimum Distance Problem %f/crypto/ygwvtlhiebikyjmxhsmqd6u7rgwcaplk.pdf %m221e57d685525b25b03a533be804fe53 %ccrypto %@Benny Applebaum,David Cash,Chris Peikert,Amit Sahai %*Fast Cryptographic Primitives and Circular-Secure Encryption Based on Hard Learning Problems %f/crypto/eyhjz25o4gotnydsxccu9ivwdwbbfa0m.pdf %m47f6dec3a0762ff531fb0474013ab3bb %ccrypto %@Brent Waters %*Dual System Encryption: Realizing Fully Secure IBE and HIBE under Simple Assumptions %f/crypto/t1vyv6qdrzicotiakxbwfuzuh4els5hy.pdf %m9c291a305662f4f5d8a8647e166e6a7e %ccrypto %@Dennis Hofheinz,Eike Kiltz %*The Group of Signed Quadratic Residues and Applications %f/crypto/of9yqdiakswhrvisve6lxpnefxl7w0ku.pdf %m4acd67ad6c6998c4f20d6c457d830200 %ccrypto %@Susan Hohenberger,Brent Waters %*Short and Stateless Signatures from the RSA Assumption %f/crypto/gm1vdf9erk8uzdnmu456jns7if0tyo2c.pdf %m6887aafa465b6dc84016c6ca4da7a91b %ccrypto %@Michel Abdalla,Céline Chevalier,David Pointcheval %*Smooth Projective Hashing for Conditionally Extractable Commitments %f/crypto/y0qcoqn9khbril2fp8rgcjewm7vwkjdz.pdf %m4a2657861feee643801633a16dbde6f9 %ccrypto %@Jean-Sébastien Coron,Jacques Patarin,Yannick Seurin %*The Random Oracle Model and the Ideal Cipher Model Are Equivalent %f/crypto/vxore6u7glwotdflhakzwj1vk4t8byqj.pdf %m389d010b7588ce75833ade4ceb74d17d %ccrypto %@Dennis Hofheinz,Eike Kiltz %*Programmable Hash Functions and Their Applications %f/crypto/saxijghwit4umph2yq1c5g6nnkz0uter.pdf %m398bbbeb9c2755b0d79d35092dd85c4a %ccrypto %@Shafi Goldwasser,Yael Tauman Kalai,Guy N. Rothblum %*One-Time Programs %f/crypto/urhxpjcajrdh7kzsb6xvqwo5yti3n9q8.pdf %mcf0a8bc4f3ce26995df14fbdd4071ab4 %ccrypto %@Omkant Pandey,Rafael Pass,Vinod Vaikuntanathan %*Adaptive One-Way Functions and Applications %f/crypto/hfudyb45zzq8klacjphukq9itetgr1rm.pdf %md11206c9df5494164a492fea9944a1b4 %ccrypto %@Dimitar Jetchev,Ramarathnam Venkatesan %*Bits Security of the Elliptic Curve Diffie–Hellman Secret Keys %f/crypto/givxtyrn6o4c1ghzslipht5y7akfwmax.pdf %mf47b2d74526de2a0f422ee0037d70b7f %ccrypto %@Sanjam Garg,Raghav Bhaskar,Satyanarayana V. Lokam %*Improved Bounds on Security Reductions for Discrete Log Based Signatures %f/crypto/a7aqrjeukdlkx0vo6bm8yiqhs1mxe3vw.pdf %m3a3187c19328b44ec94127907beaf66d %ccrypto %@Dan Boneh,Shai Halevi,Mike Hamburg,Rafail Ostrovsky %*Circular-Secure Encryption from Decision Diffie-Hellman %f/crypto/cmax3emghot4pkoucib195ndbqrtln0w.pdf %m508d424c34c19c91e55b2616fc54aac4 %ccrypto %@Brett Hemenway,Rafail Ostrovsky %*Public-Key Locally-Decodable Codes %f/crypto/wtrbeqyvrz36pd5g4vnc1na7x9kkiopf.pdf %maddfadf50b4a0050d338833c8a9f63d4 %ccrypto %@Helena Handschuh,Bart Preneel %*Key-Recovery Attacks on Universal Hash Function Based MAC Algorithms %f/crypto/3zdrvwwauogym6ra4qdbcgx1x9z75k8j.pdf %m0564e5c94d1a8af0fd972d3cfdf6084c %ccrypto %@Florian Mendel,Norbert Pramstaller,Christian Rechberger,Marcin Kontak,Janusz Szmidt %*Cryptanalysis of the GOST Hash Function %f/crypto/4tbhvfcx9zaedd1g8p3klrrliocseut0.pdf %m5d7d0130ca5e57274735d4429e58b8bd %ccrypto %@Christophe De Cannière,Christian Rechberger %*Preimages for Reduced SHA-0 and SHA-1 %f/crypto/ayd8uhdc0ltwjx9akoelfu47cqsxp5is.pdf %mf2e6682be5492dbdc983bd8b3962ea0c %ccrypto %@Thomas Eisenbarth,Timo Kasper,Amir Moradi,Christof Paar,Mahmoud Salmasizadeh,Mohammad T. Manzuri Shalmani %*On the Power of Power Analysis in the Real World: A Complete Break of the KeeLoq Code Hopping Scheme %f/crypto/vsfdpts7b21q6a5rqpykujrgw8nxx4fh.pdf %m63d8cf1ef918c36c26e554382a2c856f %ccrypto %@Eli Biham,Yaniv Carmeli,Adi Shamir %*Bug Attacks %f/crypto/iibtse2kwmu0cyazokpdnlgthqobvsry.pdf %ma0ab1ddf7cec1e032125a48ddbd7a556 %ccrypto %@Ivan Damgård,Yuval Ishai,Mikkel Krøigaard,Jesper Buus Nielsen,Adam Smith %*Scalable Multiparty Computation with Nearly Optimal Work and Resilience %f/crypto/zcr7xtahgoq1b5vs8vjgdne3dpylfix0.pdf %m64beac38ddbb7cbb061e0655145734a8 %ccrypto %@Manoj Prabhakaran,Mike Rosulek %*Cryptographic Complexity of Multi-Party Computation Problems: Classifications and Separations %f/crypto/dyn0qk7tbw5vwoyjvsmrtluezkx9jghl.pdf %m8852dfc7d0cfd205de2c2b631198d0d9 %ccrypto %@Jean-Charles Faugère,Françoise Levy-dit-Vehel,Ludovic Perret %*Cryptanalysis of MinRank %f/crypto/nvs2tw1xeval4fhplre6ub7cc3zujqnk.pdf %m6267428de17d10115511f603c5f6b0a9 %ccrypto %@Alexander Maximov,Dmitry Khovratovich %*New State Recovery Attack on RC4 %f/crypto/7p4orqjulmpkvhxle85g0sb1hz6ra3wc.pdf %m73f610165186fe86beab252d2dc02d01 %ccrypto %@Cécile Delerablée,David Pointcheval %*Dynamic Threshold Public-Key Encryption %f/crypto/wlogtenpba6umka8slmry0izxqr9bofc.pdf %m84adfa7ad73adbad2d4e0f4c3b9120e4 %ccrypto %@Alexandra Boldyreva,Serge Fehr,Adam O’Neill %*On Notions of Security for Deterministic Encryption, and Efficient Constructions without Random Oracles %f/crypto/ce5jskz70byhipbi91oygo2lnqwhuw8a.pdf %mac6434fb25970a0a7cbd6c0707c6fd40 %ccrypto %@Mihir Bellare,Marc Fischlin,Adam O’Neill,Thomas Ristenpart %*Deterministic Encryption: Definitional Equivalences and Constructions without Random Oracles %f/crypto/dza5f6wg4ycclrqhupxodqbu7xm2snrt.pdf %m7bcd6c40ef3c5cef482fb84b36dc8da2 %ccrypto %@Rafail Ostrovsky,William E. Skeith %*Communication Complexity in Algebraic Two-Party Protocols %f/crypto/agxrqw95mte7ua3t1exh6sbzoov8qylb.pdf %m61d2ec216af6ffb96db5c243dc80240e %ccrypto %@Martijn Stam %*Beyond Uniformity: Better Security/Efficiency Tradeoffs for Compression Functions %f/crypto/lkf2e5wrwqkmu4jtlyu9iosyqvzon8td.pdf %mace4f9b853648964313509e0023ed922 %ccrypto %@Krzysztof Pietrzak %*Compression from Collisions, or Why CRHF Combiners Have a Long Output %f/crypto/ojze29wfuhkzyimosbuvyrn0m4tvnw7x.pdf %m24fe5a8524b2e486c1c365419bfa35dc %ccrypto %@Phillip Rogaway,John Steinberger %*Constructing Cryptographic Hash Functions from Fixed-Key Blockciphers %f/crypto/sz4c6fwxltu8jpl7uqkyhbgcs0fo5a3h.pdf %meff50137f45bc7170d289479bc02e309 %ccrypto %@Amos Beimel,Kobbi Nissim,Eran Omri %*Distributed Private Data Analysis: Simultaneously Solving How and What %f/crypto/zljug3consfkj4adimcyhwhrpo2qtb0a.pdf %m90ae760c2771c03a26ea2d99c1883c1a %ccrypto %@Cynthia Dwork,Sergey Yekhanin %*New Efficient Attacks on Statistical Disclosure Control Mechanisms %f/crypto/dbqmangtxnzvqswho0h62wjtxz5m839u.pdf %m8a3d823d1185d67c3e629b96ae66f269 %ccrypto %@Payman Mohassel,Enav Weinreb %*Efficient Secure Linear Algebra in the Presence of Covert or Computationally Unbounded Adversaries %f/crypto/uzvdr4fpkalcvgl28c5swh7m9qxitgyo.pdf %m6702e2a8dc5d924b500693666eb1401b %ccrypto %@Joël Alwen,Abhi Shelat,Ivan Visconti %*Collusion-Free Protocols in the Mediated Model %f/crypto/x2sduce4gfye6y1vbsjicvqndjokikzq.pdf %m006b495582d89b44018106f9b73e01a7 %ccrypto %@Yevgeniy Dodis,Victor Shoup,Shabsi Walfish %*Efficient Constructions of Composable Commitments and Zero-Knowledge Proofs %f/crypto/r1jlxdswejy7z5d9waaetpkcifry6mhn.pdf %mb60d53c2da6c72ed213b90b21944804e %ccrypto %@Chris Peikert,Vinod Vaikuntanathan %*Noninteractive Statistical Zero-Knowledge Proofs for Lattice Problems %f/crypto/kman495qsnlwv70itujrsgzlp8irdqow.pdf %m62c5409bfbfb0ea118fc5e9246749192 %ccrypto %@Chris Peikert,Vinod Vaikuntanathan,Brent Waters %*A Framework for Efficient and Composable Oblivious Transfer %f/crypto/j30glefa4rsvjzc8kqz7oxx5wm2knmid.pdf %m81c8c5a732d93394b600d1c80df7febb %ccrypto %@Yuval Ishai,Manoj Prabhakaran,Amit Sahai %*Founding Cryptography on Oblivious Transfer – Efficiently %f/crypto/mnbmzr7ugndkpgw9o8vfqrslswhe1c4i.pdf %m7df25eb5b212ccd91f8df8849c610cda %ccrypto %@Vivien Dubois,Pierre-Alain Fouque,Adi Shamir,Jacques Stern %*Practical Cryptanalysis of SFLASH %f/crypto/zofmgvhtwyudexj4cfimkxsw1uda2srq.pdf %m0156cf196551d38ed2a33eb9e3201777 %ccrypto %@Pierre-Alain Fouque,Gaëtan Leurent,Phong Q. Nguyen %*Full Key-Recovery Attacks on HMAC/NMAC-MD4 and NMAC-MD5 %f/crypto/hr8dskzfkwepqrtaw5icg4jnue2sudtm.pdf %md3aefef2c9754a43d530b8becb8c15ec %ccrypto %@Amos Beimel,Tal Malkin,Kobbi Nissim,Enav Weinreb %*How Should We Solve Search Problems Privately? %f/crypto/jfqovkkfaesxhubzlwi3d5ho9cq1yz0y.pdf %md32370d3b6c498cc6a4e0b214a4eb0bf %ccrypto %@Dan Boneh,Eyal Kushilevitz,Rafail Ostrovsky,William E. Skeith %*Public Key Encryption That Allows PIR Queries %f/crypto/gb5wdlmkj3hbuh0soapqndcavr4fczsi.pdf %me586af413c6d705b7ed374f9df36595b %ccrypto %@Ross Anderson,Tyler Moore %*Information Security Economics – and Beyond %f/crypto/aiqgu1uj489zcwbniroohekvplrpgce3.pdf %m7514229531c3bfcc613a213e19eac29a %ccrypto %@Benny Applebaum,Yuval Ishai,Eyal Kushilevitz %*Cryptography with Constant Input Locality %f/crypto/doolkzxs27neitir8fmsqhjemclv3ztg.pdf %m985e60ae551077a301189e09b6ffd100 %ccrypto %@Omer Horvitz,Jonathan Katz %*Universally-Composable Two-Party Computation in Two Rounds %f/crypto/s9rupqujh1niv5fxc8l0yezfbmyqddts.pdf %m3d2d3ece7b610e9562b12e19e99fae2b %ccrypto %@Ueli Maurer,Krzysztof Pietrzak,Renato Renner %*Indistinguishability Amplification %f/crypto/quyfdtf62nlmvhyok1uszmri5x9rv48w.pdf %mcfca7349e827c8e0c34534d5c0dd72d0 %ccrypto %@Nick Howgrave-Graham %*A Hybrid Lattice-Reduction and Meet-in-the-Middle Attack Against NTRU %f/crypto/idf2k7ypxmwzdoslunqsam4bg6qnf09g.pdf %mf9ce594a1f3447686c2fbd1799772cb3 %ccrypto %@Guillaume Hanrot,Damien Stehlé %*Improved Analysis of Kannan’s Shortest Lattice Vector Algorithm %f/crypto/2fdxbiaz5ue7f86i01lhthwevxqkl9ut.pdf %m579f7f325c10a40a2c528b047adf1790 %ccrypto %@Ueli Maurer,Stefano Tessaro %*Domain Extension of Public Random Functions: Beyond the Birthday Barrier %f/crypto/vxbcfe6tzewg1k7s58hlg4yndzpsoawi.pdf %m4ee0b80f627f55c6313e69adcc03f76a %ccrypto %@Dominique Unruh %*Random Oracles and Auxiliary Input %f/crypto/qmh0khlq9zrmrpdsccft7ypwebinxo8t.pdf %m5f71263d20208ce3fc32890573127f97 %ccrypto %@Marc Fischlin,Anja Lehmann %*Security-Amplifying Combiners for Collision-Resistant Hash Functions %f/crypto/porfexavttuc9p6yydkclmufwbaqr8i1.pdf %m6f20fbf7c2f678c0dfc568b2911069ce %ccrypto %@Antoine Joux,Thomas Peyrin %*Hash Functions and the (Amplified) Boomerang Attack %f/crypto/b19seehc8lhmtpdnxwsmnqkyyco3zgga.pdf %ma6c7f5797e0904088d1f0e5a5000d8f4 %ccrypto %@Ran Canetti,Ron Rivest,Madhu Sudan,Luca Trevisan,Salil Vadhan,Hoeteck Wee %*Amplifying Collision Resistance: A Complexity-Theoretic Treatment %f/crypto/paxok9br8w3sfg1eztqq0n2bduyaidci.pdf %m10c0225948d6d4038918749d4cfff1ca %ccrypto %@Danny Harnik,Yuval Ishai,Eyal Kushilevitz %*How Many Oblivious Transfers Are Needed for Secure Multiparty Computation? %f/crypto/dboallayjwg0vtproqckke7fxmiieuhs.pdf %m9a1298760bc3e06a1fc923c90b8fe797 %ccrypto %@Melissa Chase,Anna Lysyanskaya %*Simulatable VRFs with Applications to Multi-theorem NIZK %f/crypto/y7bdogpewdrlbmz6k5re0wvzkahlc2jh.pdf %mc5ed95577a137fd2cda0808eba543417 %ccrypto %@Jens Groth,Rafail Ostrovsky %*Cryptography in the Multi-string Model %f/crypto/vpkqeswdrzbx9rfhu1vwacdiam6lhibs.pdf %mb044b291335d9e53f7aa2e676db344c3 %ccrypto %@Ivan B. Damgård,Serge Fehr,Louis Salvail,Christian Schaffner %*Secure Identification and QKD in the Bounded-Quantum-Storage Model %f/crypto/8bixrpsm6oz1jzeyf5kyhd4rcwnejhls.pdf %mb1b69dda97f2af7b53318c1b1fabd3df %ccrypto %@Ivan B. Damgård,Serge Fehr,Renato Renner,Louis Salvail,Christian Schaffner %*A Tight High-Order Entropic Quantum Uncertainty Relation with Applications %f/crypto/fvigehavodigmoyt8fqa1r2h4upqzbml.pdf %m7bcdeb3610af06e391d8953b82c18557 %ccrypto %@Jean-Sébastien Coron %*Finding Small Roots of Bivariate Integer Polynomial Equations: A Direct Approach %f/crypto/vnzu2tnewhpcsjr0k9b16pq8idgd3b4a.pdf %ma909625c080ff9cdbdad938c7898910c %ccrypto %@Ellen Jochemsz,Alexander May %*A Polynomial Time Attack on RSA with Private CRT-Exponents Smaller Than N0.073 %f/crypto/jmlu7d4wrhstg3wvotaqxinz0cfgx9hs.pdf %mf3f582ac4411d838c9f3486c3741f06f %ccrypto %@Shai Halevi %*Invertible Universal Hashing and the TET Encryption Mode %f/crypto/et6owblvujobpfjgdi8hvqe7dz4ra1xk.pdf %m90fc792c5ab53815dc3af2f025798f54 %ccrypto %@Vipul Goyal %*Reducing Trust in the PKG in Identity Based Cryptosystems %f/crypto/fhybuade80lr31svesirzcx9opq5dgnt.pdf %m156256b4f209ead5b3b2ebb14cacbd8e %ccrypto %@Aggelos Kiayias,Serdar Pehlivanoglu %*Pirate Evolution: How to Make the Most of Your Traitor Keys %f/crypto/b1zscxiutfrn4qxg96dlfakpkciqo5jw.pdf %mc067565ffe42a43f20b48cae51d9e3ad %ccrypto %@Daniel R. L. Brown,Kristian Gjøsteen %*A Security Analysis of the NIST SP 800-90 Elliptic Curve Random Number Generator %f/crypto/rgzshjnnhqak1sipclkjfwubq6xm54gt.pdf %m701e656ea34ce24035acbb35c8cf4e22 %ccrypto %@Emmanuel Bresson,Yassine Lakhnech,Laurent Mazaré,Bogdan Warinschi %*A Generalization of DDH with Applications to Protocol Analysis and Computational Soundness %f/crypto/vayg5jmifs7cb9xrqa4lhnew6dsbroxu.pdf %m9d338ab9a2162084dbd93fa7ede1236e %ccrypto %@Russell Impagliazzo,Ragesh Jaiswal,Valentine Kabanets %*Chernoff-Type Direct Product Theorems %f/crypto/bpzeokj4z7ijt0qbaho2g6qrx9efaddl.pdf %md6d76b6564b8feb33a10bd7a83f2a390 %ccrypto %@Manoj Prabhakaran,Mike Rosulek %*Rerandomizable RCCA Encryption %f/crypto/9xyhojikacpxuvipm2n6ebnfgvs5mzlb.pdf %mece80fd22fa6d18f1f082113dd1c6603 %ccrypto %@Mihir Bellare,Alexandra Boldyreva,Adam O’Neill %*Deterministic and Efficiently Searchable Encryption %f/crypto/3vfurldwcwi2iagz8eukonz6fky4vnq7.pdf %m34c4d34589725027d8e9ba1ba3b0a3cb %ccrypto %@Dennis Hofheinz,Eike Kiltz %*Secure Hybrid Encryption from Weakened Key Encapsulation %f/crypto/fjq2zagslb79nthrbwfvzgs6uxewpj1k.pdf %mde779b2aa5f3860e992204f1d222bc7a %ccrypto %@Ivan Damgård,Jesper Buus Nielsen %*Scalable and Unconditionally Secure Multiparty Computation %f/crypto/t3ovljegtivfw8dm2w7z9yxrnu0sedmo.pdf %m0d6b1495c830747e0d362e0267c48b89 %ccrypto %@Yvo Desmedt,Josef Pieprzyk,Ron Steinfeld,Huaxiong Wang %*On Secure Multi-party Computation in Black-Box Groups %f/crypto/6svm83exqeliuqogptzwkhcnyhbjyb9r.pdf %mff07ed216b3bfaab7f7e811713b742cf %ccrypto %@Ronald Cramer,Eike Kiltz,Carles Padró %*A Note on Secure Computation of the Moore-Penrose Pseudoinverse and Its Application to Secure Linear Algebra %f/crypto/uswwntpzejb7l8x30ljvumfcg54hoya1.pdf %m0ef6aaf2aec273ca89a615becda5e772 %ccrypto %@Elad Barkan,Eli Biham,Adi Shamir %*Rigorous Bounds on Cryptanalytic Time/Memory Tradeoffs %f/crypto/mie06k8qeucy1r74sxinjogb9a2nka3v.pdf %mbfae80cea8bd714480ddae281bb826e9 %ccrypto %@Iftach Haitner,Danny Harnik,Omer Reingold %*On the Power of the Randomized Iterate %f/crypto/5tqkpbugzc8zxrl3ijahlxk271mn9sbf.pdf %mdfe3168c0367cda8c671473dc4362eab %ccrypto %@Shai Halevi,Hugo Krawczyk %*Strengthening Digital Signatures Via Randomized Hashing %f/crypto/f4sniklpu0nxmohwera96jvcqx5c3try.pdf %m1250498813df633281a34a687da5a6fb %ccrypto %@Marc Fischlin %*Round-Optimal Composable Blind Signatures in the Common Reference String Model %f/crypto/815wjv6sjfvnpxqpozymrmichzygtkdn.pdf %m9a15b4c61a698eb808db2d2cee1eeed1 %ccrypto %@Melissa Chase,Anna Lysyanskaya %*On Signatures of Knowledge %f/crypto/iuv032qlc7nfehdsabwbect8zd9sorgv.pdf %mae855bd425af5385b31ae2405bedae9a %ccrypto %@Jens Groth,Rafail Ostrovsky,Amit Sahai %*Non-interactive Zaps and New Techniques for NIZK %f/crypto/h1xl5fcj6syoedg0oe2rszbgmlx3hivk.pdf %mbe6a0f6712da1e6158d18f71d5d58272 %ccrypto %@Nicolas Gama,Nick Howgrave-Graham,Henrik Koy,Phong Q. Nguyen %*Rankin’s Constant and Blockwise Lattice Reduction %f/crypto/fyqx7i0dnco4sattegkqxejcwkvnufbi.pdf %m7718ee7499faba90d4525ac3f7ad34b4 %ccrypto %@Oded Regev %*Lattice-Based Cryptography %f/crypto/ah4ouioagfve90cq3p1nugnw8sypddj2.pdf %m781e0063f4fe029a217c0713959ff59c %ccrypto %@Craig Gentry,Philip MacKenzie,Zulfikar Ramzan %*A Method for Making Password-Based Key Exchange Resilient to Server Compromise %f/crypto/dcnvaj3x4g8aowrly9prkwuvxojh2zqs.pdf %me1ed6c37b8d1994fce20582dc54b8c98 %ccrypto %@Ran Canetti,Shai Halevi,Michael Steiner %*Mitigating Dictionary Attacks on Password-Protected Local Storage %f/crypto/g0ov7rjbhwkzehdu2fnpnxscq16zygj9.pdf %m34bf0d2448e268113bbc08d26e3f4894 %ccrypto %@Anna Lysyanskaya,Nikos Triandopoulos %*Rationality and Adversarial Behavior in Multi-party Computation %f/crypto/ujwxvtfp76y9xaojemc2gmgl51nbkzos.pdf %m469f4c43031eb9bfef13a555f99a21ef %ccrypto %@Kamalika Chaudhuri,Nina Mishra %*When Random Sampling Preserves Privacy %f/crypto/ktb437szspjr8mpb0exx2otridg1do5w.pdf %m87addf5acf5c4bcd4fea31dcf702e984 %ccrypto %@Moni Naor,Gil Segev,Adam Smith %*Tight Bounds for Unconditional Authentication Protocols in the Manual Channel and Shared Key Models %f/crypto/dptmgzriy82l4ayzdlqvtoejx1kj6ihw.pdf %m7088a2c00e03b9032c2f378a03f5d008 %ccrypto %@Yevgeniy Dodis,Jonathan Katz,Leonid Reyzin,Adam Smith %*Robust Fuzzy Extractors and Authenticated Key Agreement from Close Secrets %f/crypto/3fxabc4z0qtwjsjig8cro7he9aoyxe1s.pdf %m78d9378bffee994cad6d4a0d2d8deab8 %ccrypto %@Stefan Dziembowski %*On Forward-Secure Storage %f/crypto/1euczjnvpqga69yaowkthr8bmlt5imcf.pdf %mfbbd929f5cf2399db2c4369c9e5473bd %ccrypto %@Rafael Pass,abhi shelat,Vinod Vaikuntanathan %*Construction of a Non-malleable Encryption Scheme from Any Semantically Secure One %f/crypto/xuqlazbodvsw9mlwj0yqrzyidvpipc7o.pdf %m035525e9af0d7499e702969bfb9c79c0 %ccrypto %@Xavier Boyen,Brent Waters %*Anonymous Hierarchical Identity-Based Encryption (Without Random Oracles) %f/crypto/gm9riy34cea1j0lrjnez2cwq78odilqp.pdf %m0298819ef0a926a6281d5f41b64cef03 %ccrypto %@Zulfikar Ramzan,David P. Woodruff %*Fast Algorithms for the Free Riders Problem in Broadcast Encryption %f/crypto/usafnge9mxt8psnm3hkxgyey5ruhzf2w.pdf %m8c398e60f6f0e62e854997853fe33c43 %ccrypto %@Antoine Joux,Reynald Lercier,Nigel Smart,Frederik Vercauteren %*The Number Field Sieve in the Medium Prime Case %f/crypto/harm3qmknzblnxu9c4u8sttwebjfxsy2.pdf %mcf852abff44578e933bcf39cc102c71e %ccrypto %@Louis Granboulan,Antoine Joux,Jacques Stern %*Inverting HFE Is Quasipolynomial %f/crypto/mhywcahqkv2tzbgwmjli67qxfcibr1pe.pdf %m29a658320a316ef70387c694a7a9eb2e %ccrypto %@Jean-Charles Faugère,Ludovic Perret %*Cryptanalysis of 2R− Schemes %f/crypto/ze8j0k6wsqutgbmpitayvufsidxncnyr.pdf %mb78883f095486ba5302bd326787b36c7 %ccrypto %@Tal Moran,Moni Naor %*Receipt-Free Universally-Verifiable Voting with Everlasting Privacy %f/crypto/lpevz3nmwtzet5xq0w1cihigkmsafkax.pdf %mcce7def058027c3b0b12211793b636fc %ccrypto %@David Wagner %*Cryptographic Protocols for Electronic Voting %f/crypto/m1rzeel0kx2cfgh7towanjin3opmcqv8.pdf %m7150a44c924e07a84df93001c3a98386 %ccrypto %@Saurabh Agarwal,Ronald Cramer,Robbert de Haan %*Asymptotically Optimal Two-Round Perfectly Secure Message Transmission %f/crypto/pcsflmfz60ocywdr4tgtu5xplsa9nzby.pdf %m4983bc92ad1770e37f3d5d7dd220aa09 %ccrypto %@Ronen Gradwohl,Salil Vadhan,David Zuckerman %*Random Selection with an Adversarial Majority %f/crypto/tqlzcgj8xhcfvjvnh35ixferz0i2mou7.pdf %m424df7cb93762e155582aa68279a194f %ccrypto %@Ivan B. Damgård,Serge Fehr,Louis Salvail,Christian Schaffner %*Oblivious Transfer and Linear Functions %f/crypto/0g6cpdjkztsd8b2pluh3tysnwyfqagmm.pdf %mc5f4f5e97ec55da5d01d53d1dd17f80f %ccrypto %@Jonathan Katz,Chiu-Yuen Koo %*On Expected Constant-Round Protocols for Byzantine Agreement %f/crypto/d93hhucnymkqs2eabirl5pxontuviqd8.pdf %m04d83deeff189ff281c5cea5a369794b %ccrypto %@Martin Hirt,Jesper Buus Nielsen %*Robust Multiparty Computation with Linear Communication Complexity %f/crypto/i6xfokrgzw7cdhpux19sqtcfmba3wuys.pdf %mf2875edcb386def58d0583cafc386b8b %ccrypto %@Yuval Ishai,Eyal Kushilevitz,Yehuda Lindell,Erez Petrank %*On Combining Privacy with Guaranteed Output Delivery in Secure Multiparty Computation %f/crypto/woiwldem2yltv7qdtosvg3xnkfcb4r8u.pdf %m43f3825a70edf500246a86bf3b1a2e7e %ccrypto %@Ivan Damgård,Yuval Ishai %*Scalable Secure Multiparty Computation %f/crypto/7rloihcqckpdbjz9wgjugb1s5inf0ma4.pdf %m53189975488c58a05c6a86392fce4e8d %ccrypto %@Hao Chen,Ronald Cramer %*Algebraic Geometric Secret Sharing Schemes and Secure Multi-Party Computations over Small Fields %f/crypto/pbjclte1lqchwsyx38a5k4uiz2zwnxfv.pdf %m0e99f998ddb1c7050068aebbe5184d68 %ccrypto %@Bruno Blanchet,David Pointcheval %*Automated Security Proofs with Sequences of Games %f/crypto/dkwxcyehbybiosqntk6zsj89xmrdwr2c.pdf %m776dc462d291ceff863035d335c708d3 %ccrypto %@Remo Meier,Bartosz Przydatek %*On Robust Combiners for Private Information Retrieval and Other Primitives %f/crypto/hz2y5iisxez4kobrf36q9fqdt7nl8voj.pdf %mec1f7dd3d8566626434686df947254f1 %ccrypto %@Dan Boneh,Xavier Boyen %*On the Impossibility of Efficiently Combining Collision Resistant Hash Functions %f/crypto/f1s84vpobmud0mqcvhszlgebpdwtyqnj.pdf %m209eb1e0f4b2263e4f8594f92b08b1ff %ccrypto %@Mihir Bellare %*New Proofs for NMAC and HMAC: Security Without Collision-Resistance %f/crypto/uv2u7enoyntgfl9iwk8jafsmd1pzrc5t.pdf %m6a2b79db5434d8175884351d5f322911 %ccrypto %@Xiaoyun Wang,Hongbo Yu,Yiqun Lisa Yin %*Efficient Collision Search Attacks on SHA-0 %f/crypto/xvbxesqiirdngwrda30w2copz4ejhams.pdf %m01d1b1352db43a3e72ffeb4e0eaddcd1 %ccrypto %@Xiaoyun Wang,Yiqun Lisa Yin,Hongbo Yu %*Finding Collisions in the Full SHA-1 %f/crypto/cdl4htgtjabkopsmb3qw1eiq9v7renlk.pdf %m1a513b9b8583d8fe282b0d8a0d7aa329 %ccrypto %@Cynthia Dwork,Moni Naor,Hoeteck Wee %*Pebbling and Proofs of Work %f/crypto/ipwdx9pjy2lcfdenfsacvuzogit4mx1k.pdf %m2b21526de3dd81918eed0487358b31f6 %ccrypto %@Krzysztof Pietrzak %*Composition Does Not Imply Adaptive Security %f/crypto/tk01hb6icqr9afvjedgow2xudaxvnpib.pdf %m7654cdfeb81116cad5726f91b8c35178 %ccrypto %@R. Granger,F. Vercauteren %*On the Discrete Logarithm Problem on Algebraic Tori %f/crypto/uiaz5ts2fpoxf8vkoze1atshju4iwnrv.pdf %m6e3e37d7c3de2412c527b54eceb58135 %ccrypto %@Alexei Myasnikov,Vladimir Shpilrain,Alexander Ushakov %*A Practical Attack on a Braid Group Based Cryptographic Protocol %f/crypto/twfwc61goz7uiceltnysqkprzqb4kfhm.pdf %mee412473986a6da39b76c13957c1e4ab %ccrypto %@Yi Lu,Willi Meier,Serge Vaudenay %*The Conditional Correlation Attack: A Practical Attack on Bluetooth Encryption %f/crypto/5jvdnhzibvs3atu1jckcdr7l0ngyyaeu.pdf %m1393107c4e5b9cace17697eb9fe41ac3 %ccrypto %@Rafael Pass,abhi shelat %*Unconditional Characterizations of Non-interactive Zero-Knowledge %f/crypto/4mgwapmfkohetqcif1pdkq9ebhr0sixn.pdf %me9815731115254f873a56eb6908960c2 %ccrypto %@Joël Alwen,Giuseppe Persiano,Ivan Visconti %*Impossibility and Feasibility Results for Zero Knowledge with Public Keys %f/crypto/zptdh9gruyr6egyjtzsac1x2oi80nefn.pdf %m3d076e4f27cc02332631bb939d98ee41 %ccrypto %@Marc Fischlin %*Communication-Efficient Non-interactive Proofs of Knowledge with Online Extractors %f/crypto/sdmawfxdepmky46hionx8gqoytuaf207.pdf %m3b8869e3442583c3a2973c3931b06099 %ccrypto %@Jan Camenisch,Anna Lysyanskaya %*A Formal Treatment of Onion Routing %f/crypto/2jgzalv04izbqd5xhlrmhdcax78puc6n.pdf %mea261c98e689d00d003335b6f5329b2c %ccrypto %@Kun Peng,Colin Boyd,Ed Dawson %*Simple and Efficient Shuffling with Provable Correctness and ZK Privacy %f/crypto/urfx14akmulgqqetog6whbjzcznvh05c.pdf %m67885c236d135446213eb8432cdd4611 %ccrypto %@Michel Abdalla,Mihir Bellare,Dario Catalano,Eike Kiltz,Tadayoshi Kohno,Tanja Lange,John Malone-Lee,Gregory Neven,Pascal Paillier,Haixia Shi %*Searchable Encryption Revisited: Consistency Properties, Relation to Anonymous IBE, and Extensions %f/crypto/ozov0kiksxjzlucpt3qxlstya6ymf5ag.pdf %m94fa98df4b25365da2493e5795b58076 %ccrypto %@Rafail Ostrovsky,William E. Skeith %*Private Searching on Streaming Data %f/crypto/1timuo9qv08dqaskl6fwutrhfronbspw.pdf %m994824533fd456a0b352f2932252371f %ccrypto %@Lea Kissner,Dawn Song %*Privacy-Preserving Set Operations %f/crypto/k6hqfybemg7bs9ndxtctu0ujjkznwdp8.pdf %meb6815a6522e321ac458a7144ab7834e %ccrypto %@Dan Boneh,Craig Gentry,Brent Waters %*Collusion Resistant Broadcast Encryption with Short Ciphertexts and Private Keys %f/crypto/ynestfzb2waiu6cln80oswmklhc3fo4z.pdf %m23f86d904067de6219bb562b05118ced %ccrypto %@Jung Yeon Hwang,Dong Hoon Lee,Jongin Lim %*Generic Transformation for Scalable Broadcast Encryption Schemes %f/crypto/761xihvrtiyjwqua8bp5vdgch3mzexqf.pdf %m67d2cc488a0d02e4ec7e69aca3906445 %ccrypto %@Ari Juels,Stephen A. Weis %*Authenticating Pervasive Devices with Human Protocols %f/crypto/7dkwlvup0on5zmxqahr3ysihegbi9pn4.pdf %m64b594e02c20f11b26c01ead3746ad73 %ccrypto %@Serge Vaudenay %*Secure Communications over Insecure Channels Based on Short Authenticated Strings %f/crypto/yps29oegebiijvj3qru7kszxfo6fghdm.pdf %m101d7099bca386cc7c00813cc25157f2 %ccrypto %@Ronald Cramer,Vanesa Daza,Ignacio Gracia,Jorge Jiménez Urroz,Gregor Leander,Jaume Martí-Farré,Carles Padró %*On Codes, Matroids and Secure Multi-party Computation from Linear Secret Sharing Schemes %f/crypto/npi6gd1z9yqzh0pw5restxbeg7fcqldc.pdf %m86dd069860a1fc6f69a09384e00ecb9c %ccrypto %@Ronald Cramer,Serge Fehr,Martijn Stam %*Black-Box Secret Sharing from Primitive Sets in Algebraic Number Fields %f/crypto/exrobq5qvyn2tuzseg19dyiahwxto0ka.pdf %m4b8ac4ed5324a3cf6f3d79667592cde8 %ccrypto %@Boaz Barak,Ran Canetti,Yehuda Lindell,Rafael Pass,Tal Rabin %*Secure Computation Without Authentication %f/crypto/mef79onw6zfh8jrgx1mlwepdtoyiuvga.pdf %m7ea4ee9dc53e1e28a291a6f2a3e62aa0 %ccrypto %@Ivan Damgård,Yuval Ishai %*Constant-Round Multiparty Computation Using a Black-Box Pseudorandom Generator %f/crypto/pdakerstlg5hpy0quc2fu6krzycobqno.pdf %m028daab08a9e0177a18cc9ef40c5c64a %ccrypto %@Omer Barkol,Yuval Ishai %*Secure Computation of Constant-Depth Circuits with Applications to Database Search Problems %f/crypto/ok751taqvayjlhlszgrsx3hnerpo8cib.pdf %me44cd1dd9ce3b02ebc033ad18244dd88 %ccrypto %@Alexandra Boldyreva,Marc Fischlin %*Analysis of Random Oracle Instantiation Scenarios for OAEP and Other Practical Schemes %f/crypto/ma2zhlsul8qydkapwnii9406zf7kn5jf.pdf %m311549fef641a19b2b3824c8b5046b5d %ccrypto %@Jean-Sébastien Coron,Yevgeniy Dodis,Cécile Malinaud,Prashant Puniya %*Merkle-Damgård Revisited: How to Construct a Hash Function %f/crypto/gludnybzaihqxce4oiscr9u3zvmwe6yd.pdf %m74b6398e5e6f0b2abbe17c80fd6aa1bc %ccrypto %@Yevgeniy Dodis,Roberto Oliveira,Krzysztof Pietrzak %*On the Generic Insecurity of the Full Domain Hash %f/crypto/vtypjbxu3em1gkbffrunpz54szhoical.pdf %m44c447e4df70ddf2689669889e3c42e5 %ccrypto %@Stefan Wolf,Jürg Wullschleger %*New Monotones and Lower Bounds in Unconditional Two-Party Computation %f/crypto/uzx1pj0lozvgodbfrsvcw5m6rt8ukahj.pdf %mf3abdc6b13690255f6ea314969744343 %ccrypto %@Thomas Holenstein,Renato Renner %*One-Way Secret-Key Agreement and Applications to Circuit Polarization and Immunization of Public-Key Encryption %f/crypto/0stndix738waoqkvcp2xtgzlwz6vyqns.pdf %mf0c92d283e90f34a77c0a6650c15765f %ccrypto %@Ivan Damgård,Thomas Brochmann Pedersen,Louis Salvail %*A Quantum Cipher with Near Optimal Key-Recycling %f/crypto/qcmj8zzfiplndtil9hswkvr7rhyejc1q.pdf %mfb4c130baa8f1065fdcdb6c553c95399 %ccrypto %@Benoît Chevallier-Mames %*An Efficient CDH-Based Signature Scheme with a Tight Security Reduction %f/crypto/8szbmrdjrktbyzmnlel4vc9fotiuwk5u.pdf %me5d02f8dcad2e9390bc1fdea5c657b08 %ccrypto %@Mihir Bellare,Krzysztof Pietrzak,Phillip Rogaway %*Improved Security Analyses for CBC MACs %f/crypto/kbwdzleih5wptvz2cc3qrosodbxgjks8.pdf %mc600f5721818eef0fa05f093ef634f2d %ccrypto %@Hugo Krawczyk %*HMQV: A High-Performance Secure Diffie-Hellman Protocol %f/crypto/xmwkivdb3neih0lo6kagwsqyf2ntjpd1.pdf %me3eca82b08b518ec32563238909c2b63 %ccrypto %@Alex Biryukov,Christophe De Cannière,Michaël Quisquater %*On Multiple Linear Approximations %f/crypto/bjc1shayxdjudr20rfmt3hegsou8wqyl.pdf %m2446444c1c3738eb9d60675affaa9ec5 %ccrypto %@Nicolas T. Courtois %*Feistel Schemes and Bi-linear Cryptanalysis %f/crypto/qwygrorwtcbl5dzhpxuehga4inu9lmo0.pdf %m29a995175d46c7e945af86c817d50c80 %ccrypto %@Dan Boneh,Xavier Boyen,Hovav Shacham %*Short Group Signatures %f/crypto/qvdxg61grucokhw3jyqmlab5pzewy0sc.pdf %m56b09f1c579f5acf4924be8e35d0aab1 %ccrypto %@Jan Camenisch,Anna Lysyanskaya %*Signature Schemes and Anonymous Credentials from Bilinear Maps %f/crypto/lq9mo567fw4hucgytmssijfapzla3nkr.pdf %m46c83d56485e64330db513df0450ba32 %ccrypto %@Thomas Holenstein,Ueli Maurer,Johan Sjödin %*Complete Classification of Bilinear Hard-Core Functions %f/crypto/fcnz2ut93rlg0nl4mycgh5xftpkivwa6.pdf %md2cbd498c128c96b407abe5d66376402 %ccrypto %@Jacques Patarin %*Security of Random Feistel Schemes with 5 or More Rounds %f/crypto/y8t2hjpkupvswqxvfb0gmskic3gd6z49.pdf %m48566578932af6b09cbafb798b929363 %ccrypto %@Katsuyuki Okeya,Katja Schmidt-Samoa,Christian Spahn,Tsuyoshi Takagi %*Signed Binary Representations Revisited %f/crypto/3jgquvvjs1wmf0libn8gxtohsda9erct.pdf %mfc42d7e6c828c83eb341904ee6497e69 %ccrypto %@Michael Scott,Paulo S. L. M. Barreto %*Compressed Pairings %f/crypto/5nuteismfhjxw8u0b1ikzxerljhvggma.pdf %md499c8ec082fdca05b987d46429f2bb7 %ccrypto %@Marten van Dijk,David Woodruff %*Asymptotically Optimal Communication for Torus-Based Cryptography %f/crypto/bufh01tdyi85avx6jrnznswgr49lecp7.pdf %m3ca08e7f94f59e05feb130ef5112c005 %ccrypto %@Craig Gentry %*How to Compress Rabin Ciphertexts and Signatures (and More) %f/crypto/4zrukhgi0mytjvwq2asbj6crtfnd9ecb.pdf %m1037509c7e56a69147b94065671f0c84 %ccrypto %@Qi Cheng %*On the Bounded Sum-of-Digits Discrete Logarithm Problem in Finite Fields %f/crypto/pjrgccvqsxg0yeliaznmxtpobdkj1wel.pdf %m92f3e0a95286acf95d3449073594fb92 %ccrypto %@Alexander May %*Computing the RSA Secret Key Is Deterministic Polynomial Time Equivalent to Factoring %f/crypto/nwo9dxrzuwchf2miz3foba0grikqtchl.pdf %m6d170c81b1f8611595d8321957c9fe34 %ccrypto %@Rosario Gennaro %*Multi-trapdoor Commitments and Their Applications to Proofs of Knowledge Secure Under Concurrent Man-in-the-Middle Attacks %f/crypto/wljumysunkzber4ydgq6iq3g5fn8ittk.pdf %me224e5cfe204831bcddd61311231a3c1 %ccrypto %@Giovanni Di Crescenzo,Giuseppe Persiano,Ivan Visconti %*Constant-Round Resettable Zero Knowledge with Concurrent Soundness in the Bare Public-Key Model %f/crypto/y0axgmq2hjrnbjcqzelmfl8i7thg49vo.pdf %m65464bd4bb6e33978cfcae82a183556b %ccrypto %@Ivan Damgård,Serge Fehr,Louis Salvail %*Zero-Knowledge Proofs and String Commitments Withstanding Quantum Attacks %f/crypto/rhe8rojizfysc9lququzj1nmif6wt2nl.pdf %mb495ccfb649511cf3f5f2eae12542a51 %ccrypto %@Mihir Bellare,Adriana Palacio %*The Knowledge-of-Exponent Assumptions and 3-Round Zero-Knowledge Protocols %f/crypto/ltjb50pdwvfrkhacgomm31xbiav6sw2k.pdf %med3fc8f035c763dc51a961158ab45876 %ccrypto %@Eli Biham,Rafi Chen %*Near-Collisions of SHA-0 %f/crypto/zy31lfsbego6omanj7lepxf8dxq0u2qu.pdf %m363b206a642ae3dd78e8e1823adf18f1 %ccrypto %@Antoine Joux %*Multicollisions in Iterated Hash Functions. Application to Cascaded Constructions %f/crypto/wrifcegmnkchaplsx53tnqygeyzlumxr.pdf %m7f0f2c8cc53979126c9ce23761b5e5e6 %ccrypto %@Masayuki Abe,Serge Fehr %*Adaptively Secure Feldman VSS and Applications to Universally-Composable Threshold Cryptography %f/crypto/qw4fznexxlru6ymt9pbvi3bycahsftg8.pdf %meecc72eef6cad99318186c7acba0e174 %ccrypto %@Jonathan Katz,Rafail Ostrovsky %*Round-Optimal Secure Two-Party Computation %f/crypto/piygmtr8dymnwsegs4o9pucliw2od036.pdf %m555f2f1724cebe41f3d00e3510fcbcc4 %ccrypto %@Susan Landau %*Security, Liberty, and Electronic Communications %f/crypto/zvu6amijb7wbz2ovuxtjfrf0cgt8ep4d.pdf %mbdd5baa14636b21d8ce1803855104ea7 %ccrypto %@Håvard Molland,Tor Helleseth %*An Improved Correlation Attack Against Irregular Clocked and Filtered Keystream Generators %f/crypto/si6uypxmdxksv1gbegmbdro9fztaeqnk.pdf %m7385fc7fd1fbdbab1de65c6af15fc881 %ccrypto %@Philip Hawkes,Gregory G. Rose %*Rewriting Variables: The Complexity of Fast Algebraic Attacks on Stream Ciphers %f/crypto/gushjnms7uj5k4f6qkavtx8c39ycydwr.pdf %m6b9aee644e1d7681f753cabf29edf7ec %ccrypto %@Yi Lu,Serge Vaudenay %*Faster Correlation Attack on Bluetooth Keystream Generator E0 %f/crypto/vrlbgu1dsmmkjyr6l7gnvcpxwuwffhda.pdf %m999e4bed10f23e895cd05abd1d67c3ea %ccrypto %@Kaoru Kurosawa,Yvo Desmedt %*A New Paradigm of Hybrid Encryption Scheme %f/crypto/0pvqjoabxivryrathfzdmlumi3fdocnk.pdf %m84707ad82cfaad3044affba9a7f3ae7e %ccrypto %@Dan Boneh,Xavier Boyen %*Secure Identity Based Encryption Without Random Oracles %f/crypto/plpnxuezeaodvjalqhgmohr5dbwmnk0c.pdf %m324836d3bfea38364ca23aafb383bd7b %ccrypto %@Tal Moran,Ronen Shaltiel,Amnon Ta-Shma %*Non-interactive Timestamping in the Bounded Storage Model %f/crypto/rqu3weoxht7anyzifusetvxmjs19kcbk.pdf %m77021ae124749ec7d55765a065dfadee %ccrypto %@Dario Catalano,David Pointcheval,Thomas Pornin %*IPAKE: Isomorphisms for Password-Based Authenticated Key Exchange %f/crypto/b6t52lqwgksrjo9eafyfpzy1kidem4uc.pdf %m51c573b3feaae737e9bc307d778e5e16 %ccrypto %@Yevgeniy Dodis,Rosario Gennaro,Johan Håstad,Hugo Krawczyk,Tal Rabin %*Randomness Extraction and Key Derivation Using the CBC, Cascade and HMAC Modes %f/crypto/1lnxg9pa47lkvuehghycjw3q0yrr6dmi.pdf %mfc59edfd00a70bfb790dd3e27f4ed359 %ccrypto %@Michael T. Goodrich,Jonathan Z. Sun,Roberto Tamassia %*Efficient Tree-Based Revocation in Groups of Low-State Devices %f/crypto/jnklfdhc5vbqmdatoirppflxvq1skywj.pdf %m5bcf867ceda14bbb74cf6dc4d1121092 %ccrypto %@Cynthia Dwork,Kobbi Nissim %*Privacy-Preserving Datamining on Vertically Partitioned Databases %f/crypto/sei54xd3ia92zoljgubaskvyq8hfx0wc.pdf %m515ecf2d183133395fffb007ee00c5ff %ccrypto %@K. Srinathan,Arvind Narayanan,C. Pandu Rangan %*Optimal Perfectly Secure Message Transmission %f/crypto/cmq1yfcmsb7d65ooh3jvwuy8pqlguijx.pdf %m689e92f5fcd05c68a417861f324561be %ccrypto %@Matthias Fitzi,Stefan Wolf,Jürg Wullschleger %*Pseudo-signatures, Broadcast, and Multi-party Computation from Correlated Randomness %f/crypto/sr2usqiflhe5tnucin6a8vdofy39mgzc.pdf %md888014e1d222af3d43e32a7d245a236 %ccrypto %@Adi Shamir,Eran Tromer %*Factoring Large Numbers with the TWIRL Device %f/crypto/zlhdtoja65u1csvx2uc9s4p380ovrftg.pdf %m3e95249dc70a64bdf50342b2368ae0ac %ccrypto %@Johannes Blömer,Alexander May %*New Partial Key Exposure Attacks on RSA %f/crypto/7elcdb3uvm54txhnk2o1ik8uqgipgazs.pdf %mf55ac49ac4d33636000c71f86416d860 %ccrypto %@Jean-Charles Faugère,Antoine Joux %*Algebraic Cryptanalysis of Hidden Field Equation (HFE) Cryptosystems Using Gröbner Bases %f/crypto/6eusxg7umf8aq4hwxkp9nerjoc10vmyv.pdf %m01ff7b31468b0ddb114109599ce59ae4 %ccrypto %@Salil P. Vadhan %*On Constructing Locally Computable Extractors and Cryptosystems in the Bounded Storage Model %f/crypto/4t5bd6xwizlztmqrp0p1jonggkad37vf.pdf %mb86e95cbf9cffbf646b38b22d543a7fe %ccrypto %@Renato Renner,Stefan Wolf %*Unconditional Authenticity and Privacy from an Arbitrarily Weak Secret %f/crypto/uzw0pgotvjpkfblr9ohtdrq76usawbi4.pdf %m52469cc8b60ccf170d7a7c65086ad87e %ccrypto %@Moni Naor %*On Cryptographic Assumptions and Challenges %f/crypto/qeszo4lk9sz8rvkjcibt5nncqdejpyf7.pdf %m6b8e79efe743fecc43db9a8262d9a34f %ccrypto %@Jonathan Katz,Moti Yung %*Scalable Protocols for Authenticated Group Key Exchange %f/crypto/wwqdhsbv7coo6tzeur3gluip2njl8hyq.pdf %mba150a8fa28724e94320aa765afae4fb %ccrypto %@Jan Camenisch,Victor Shoup %*Practical Verifiable Encryption and Decryption of Discrete Logarithms %f/crypto/z1qqpjixzmvfer4oc0sngn3h7amyw52b.pdf %m4066fb22100d74035add44602fd4451d %ccrypto %@Yuval Ishai,Joe Kilian,Kobbi Nissim,Erez Petrank %*Extending Oblivious Transfers Efficiently %f/crypto/j5e1ofiaadsh9yxmkthrgz2ljnd0cnty.pdf %m5b0bfa568f72568e5a900277c1ff65df %ccrypto %@Frederik Armknecht,Matthias Krause %*Algebraic Attacks on Combiners with Memory %f/crypto/j5y4csb39xvqznouomgvqgptfu8lfmrw.pdf %mfb90abdc88d044c9dd4a8a57b77e4fc3 %ccrypto %@Nicolas T. Courtois %*Fast Algebraic Attacks on Stream Ciphers with Linear Feedback %f/crypto/1tvhjbylifgz0w5eeru3qiouqprkvdn2.pdf %m60d5c713d6d98c7113f848938ec5840a %ccrypto %@Alex Biryukov,Christophe De Cannière,Gustaf Dellkrantz %*Cryptanalysis of Safer++ %f/crypto/mjxkc5fw4ke3solmhrvjdoyvi8lrugqg.pdf %m5ddec44b32deca5b84d1529731907355 %ccrypto %@Jung Hee Cheon,Byungheup Jun %*A Polynomial Time Algorithm for the Braid Diffie-Hellman Conjugacy Problem %f/crypto/dzpb3topnrqag8gk9esjo7rzmv1lbwci.pdf %mb5522e0b624b3833aed1b980eedba0f5 %ccrypto %@Nick Howgrave-Graham,Phong Q. Nguyen,David Pointcheval,John Proos,Joseph H. Silverman,Ari Singer,William Whyte %*The Impact of Decryption Failures on the Security of NTRU Encryption %f/crypto/tnkjd98huwaglcb4sja3pfiomfy1w7zr.pdf %m506fc98a2345abdd014456d8fd3a7d70 %ccrypto %@Ivan Damgård,Jesper Buus Nielsen %*Universally Composable Efficient Multiparty Computation from Threshold Homomorphic Encryption %f/crypto/ti29tc4wqn0al68zlvhyrhzjafmivcex.pdf %m5ba01ced51eea45d92117eae873dbd86 %ccrypto %@Ran Canetti,Tal Rabin %*Universal Composition with Joint State %f/crypto/joaff1phcvzmcxhkoeejnu9ywi2tqk36.pdf %m11c434650196e9a10d2a7ab29e4a09e5 %ccrypto %@Daniele Micciancio,Salil P. Vadhan %*Statistical Zero-Knowledge Proofs with Efficient Provers: Lattice Problems and More %f/crypto/6zobrtnopdwimysj3f4env1lqtdagfrk.pdf %m0387e88581b51580900ab3da3220a957 %ccrypto %@Boaz Barak,Shien Jin Ong,Salil Vadhan %*Derandomization in Cryptography %f/crypto/8ks2jlxfuqmigetnhx3h9rrps4vojclp.pdf %m480944bcd75cf45a28e187c8b91dc191 %ccrypto %@Rafael Pass %*On Deniability in the Common Reference String and Random Oracle Model %f/crypto/opldkxvy7ecbr8ngtawwehh5j9zu0spc.pdf %me269a443552408f388627effcd4569bc %ccrypto %@Qi Cheng %*Primality Proving via One Round in ECPP and One Iteration in AKS %f/crypto/co4avxp9nhy6grzehatwzcvqmtq8jo0k.pdf %mc6de4e2efaf64f7ef616b6d436d4c834 %ccrypto %@Karl Rubin,Alice Silverberg %*Torus-Based Cryptography %f/crypto/5dprflywogpbzzir40xxkgbahqlkiu9m.pdf %me27f6d8cd59136b2ab12824ae317afeb %ccrypto %@Yuichi Komano,Kazuo Ohta %*Efficient Universal Padding Techniques for Multiplicative Trapdoor One-Way Permutation %f/crypto/kqixagke4t5qbxhjygfdlrcpn1a6b2yl.pdf %me7f4a2aeafc3c87f5e83094076ee4f5d %ccrypto %@Xavier Boyen %*Multipurpose Identity-Based Signcryption %f/crypto/rtakchivgsxl3ebjsoqqwf6p2toadbhn.pdf %mbe5e99587845517ddd9a122d4cf66298 %ccrypto %@Hugo Krawczyk %*SIGMA: The ‘SIGn-and-MAc’ Approach to Authenticated Diffie-Hellman and Its Use in the IKE Protocols %f/crypto/tuq4ghp7oj0bkzv8aa9dtpsreif2obq6.pdf %m5887f55ec9c0cfc87d30a71d46f60e23 %ccrypto %@Cynthia Dwork,Andrew Goldberg,Moni Naor %*On Memory-Bound Functions for Fighting Spam %f/crypto/4h3lf1dkx80t7frrvnzzqhsclibcuo6j.pdf %mfabb1dfd8cbf05b2fc967e4994b3a081 %ccrypto %@Niv Buchbinder,Erez Petrank %*Lower and Upper Bounds on Obtaining History Independence %f/crypto/wgcx7oyuiuwyhjtzpfkvt3n6qjermbfi.pdf %m64f77bebe6fea82e0ed7da4eacd6a0f0 %ccrypto %@Yuval Ishai,Amit Sahai,David Wagner %*Private Circuits: Securing Hardware against Probing Attacks %f/crypto/gwimh0od8ctvbtul54sfubix6pk1rn7a.pdf %m5106ed979e0187c652bfeb386c2989f9 %ccrypto %@Shai Halevi,Phillip Rogaway %*A Tweakable Enciphering Mode %f/crypto/omtucqaxleujpovcid4q2807gymfbsgw.pdf %m3ba6bb4909a55eea390d3a3745a8aaf1 %ccrypto %@Matthew Cary,Ramarathnam Venkatesan %*A Message Authentication Code Based on Unimodular Matrix Groups %f/crypto/guvioelpqcpxkcbsbiayt3q0ewzx6jsd.pdf %m9c916302cd4b6ac683c6c94aa49f0838 %ccrypto %@Jacques Patarin %*Luby-Rackoff: 7 Rounds Are Enough for 2n(1 − ε) Security %f/crypto/pgstubl7yjh9fr3qzc5tanofecaek0gh.pdf %me46c0b70e9300bab5ec4b4502ecab8d0 %ccrypto %@Omer Horvitz,Virgil Gligor %*Weak Key Authenticity and the Computational Completeness of Formal Encryption %f/crypto/bimbl8kudz0la5gd3cvjxn6qpfoocs2w.pdf %m9c332d237938e194338871c3b54fd64c %ccrypto %@Jonathan Herzog,Moses Liskov,Silvio Micali %*Plaintext Awareness via Key Registration %f/crypto/0d1omhbjrdygwyop5vsu6nitpc9k2cne.pdf %m1ec9c4c354e1483130c03e61a855b686 %ccrypto %@Ran Canetti,Hugo Krawczyk,Jesper B. Nielsen %*Relaxing Chosen-Ciphertext Security %f/crypto/bleqmgkyxovnkhq09dip3rchnbx47tzc.pdf %m2aa7416e47563735a21319b30918f9a3 %ccrypto %@Brice Canvel,Alain Hiltgen,Serge Vaudenay,Martin Vuagnoux %*Password Interception in a SSL/TLS Channel %f/crypto/sjy1xpvkwfqizs2khd3rrxi7jhyo0l5b.pdf %m034741ea66f16193a27fd2c6302adee9 %ccrypto %@Elad Barkan,Eli Biham,Nathan Keller %*Instant Ciphertext-Only Cryptanalysis of GSM Encrypted Communication %f/crypto/zdafvclmark2wlqgxkhvzy86buioxtce.pdf %ma0e8bb1581dd325c14d2bbc5035ef457 %ccrypto %@Philippe Oechslin %*Making a Faster Cryptanalytic Time-Memory Trade-Off %f/crypto/wh7mz8eo4sd3f56ovdpvjniqhk1euul9.pdf %m372974615f49fc14bc2436cc90ad4087 %ccrypto %@Sean Murphy,Matthew J.B. Robshaw %*Essential Algebraic Structure within the AES %f/crypto/ktrdoiygevrs1phhtmf0oljkzc427bep.pdf %me39c111fb0ff1b23e582b7f993eab30f %ccrypto %@Antoine Joux,Gwenaëlle Martinet,Frédéric Valette %*Blockwise-Adaptive Attackers Revisiting the (In)Security of Some Provably Secure Encryption Modes: CBC, GEM, IACBC %f/crypto/rveyjnsn2mzvmbkawf4dbuu0j98cl3ep.pdf %me2e816f723375c3db2369c99f835ab49 %ccrypto %@Moses Liskov,Ronald L. Rivest,David Wagner %*Tweakable Block Ciphers %f/crypto/u9o5cns8zjovhtgyxdzbrxhegnfta02f.pdf %m137d305adb25c525bf7ed8ef9f37cd20 %ccrypto %@Dani Halevy,Adi Shamir %*The LSD Broadcast Encryption Scheme %f/crypto/wxq3uzpqdh5yeivjegao2ltp4cjdwms9.pdf %madc1c4591b2254212584b836d66635d2 %ccrypto %@Jan Camenisch,Anna Lysyanskaya %*Dynamic Accumulators and Application to Efficient Revocation of Anonymous Credentials %f/crypto/s7uwf0mbm6n9cqidlyhi1j3na52opcvg.pdf %m40030f7ddb140f2d6070d93f06e79f6a %ccrypto %@Nicholas J. Hopper,John Langford,Luis von Ahn %*Provably Secure Steganography %f/crypto/4mxvmqsnhllgz6htic1joypvtua3wbus.pdf %mbc892ac4e63977e8be842b5285e26cf1 %ccrypto %@Jacques Stern,David Pointcheval,John Malone-Lee,Nigel P. Smart %*Flaws in Applying Proof Methodologies to Signature Schemes %f/crypto/jil9t1qxem6vrlisepgtmvxgnfurb2do.pdf %m6c9060f2a0f7f6047b7e92a25660c3e1 %ccrypto %@Jesper Buus Nielsen %*Separating Random Oracle Proofs from Complexity Theoretic Proofs: The Non-committing Encryption Case %f/crypto/xeif0c17uy9zgwxbuvyagrao5fdcirmh.pdf %mddb21b29f778dead268461fc3c186a9f %ccrypto %@Jakob Jonsson,Burton S. Kaliski %*On the Security of RSA Encryption in TLS %f/crypto/f7q205pd6rotckybgbleqhp4siiuegsm.pdf %md178a6efac49d5211deb80203a7ed1a2 %ccrypto %@Ran Canetti,Hugo Krawczyk %*Security Analysis of IKE’s Signature-Based Key-Exchange Protocol %f/crypto/h3q0xeaf9xjydmzrjuuswodtl67vb8n5.pdf %m36f355aea8eee4f92faa913efed4719b %ccrypto %@Mihir Bellare,Adriana Palacio %*GQ and Schnorr Identification Schemes: Proofs of Security against Impersonation under Active and Concurrent Attacks %f/crypto/4ltbx30yi6osiheqbvtvcynkjzgfamar.pdf %m7c3ab6c9f45943bfc1b9da0ecb53dca5 %ccrypto %@Rosario Gennaro,Yuval Ishai,Eyal Kushilevitz,Tal Rabin %*On 2-Round Secure Multiparty Computation %f/crypto/zque7m9conawvghy2ajtdpbn5yiixwek.pdf %m3bc234572b260143564251cddf12c8fb %ccrypto %@Markus Bläser,Andreas Jakoby,Maciej Liśkiewicz,Bodo Siebert %*Private Computation — k-Connected versus 1-Connected Networks %f/crypto/xmfeba6oyfp3ettbgpxguw8jjdv7h1iw.pdf %mcc114257b7f1d25aba560c47f88f351f %ccrypto %@Phong Q. Nguyen,David Pointcheval %*Analysis and Improvements of NTRU Encryption Paddings %f/crypto/xaj9o2ildmksqnuggpsb0zw4cvwahtok.pdf %m0ce0784f7936109b462b62e4f1e283e2 %ccrypto %@Jean-Sébastien Coron,Marc Joye,David Naccache,Pascal Paillier %*Universal Padding Schemes for RSA %f/crypto/8ay6lmkehsurx7wdogbpp4s0cibzn9cq.pdf %m626b8c09520a5f24e73abbd7407551ab %ccrypto %@Alexander May %*Cryptanalysis of Unbalanced RSA with Small CRT-Exponent %f/crypto/ugb95sjxtgw6wmho1yslrrchnvaf2knd.pdf %md81823ae2364cb84dc11a29c985cacbd %ccrypto %@Chi-Jen Lu %*Hyper-encryption against Space-Bounded Adversaries from On-Line Strong Extractors %f/crypto/f1jepzdqqgpcclo4elfmo8uk03zmtwsv.pdf %mf4f870502c1f3c6429be9de74a3e19a3 %ccrypto %@Ronald Cramer,Serge Fehr %*Optimal Black-Box Secret Sharing over Arbitrary Abelian Groups %f/crypto/q37sou05glrbvej4uxdpskn1owirapcd.pdf %m143e994529a49a3193cfbacf439e5a30 %ccrypto %@David Wagner %*A Generalized Birthday Problem %f/crypto/s31io4aempunily85c9gkm2qctrdpavt.pdf %m4dd0ccaf9860dc4c0b2efe39f06d9dd3 %ccrypto %@Ilya Mironov %*(Not So) Random Shuffles of RC4 %f/crypto/subbhkzonldv9rdjm6cepr8mjesz5wqc.pdf %m3385aac9a6b161021509aed950481ddf %ccrypto %@John Black,Phillip Rogaway,Thomas Shrimpton %*Black-Box Analysis of the Block-Cipher-Based Hash-Function Constructions from PGV %f/crypto/fucxmipvrq5pibtwzlu9zsynok1ct7sj.pdf %m74b5cfa2c43e395af0ead444d1f91ffe %ccrypto %@Karl Rubin,Alice Silverberg %*Supersingular Abelian Varieties in Cryptology %f/crypto/ixsrfu8ukltppdrbndghmho9jlzfjb6y.pdf %md6ece94305dea005d509645cded0c1ef %ccrypto %@Paulo S. L. M. Barreto,Hae Y. Kim,Ben Lynn,Michael Scott %*Efficient Algorithms for Pairing-Based Cryptosystems %f/crypto/wlzq5nugyv0rscimdbdtglefht3n2yxr.pdf %m555193c6ad98d921ee400f675f279539 %ccrypto %@Frederik Vercauteren %*Computing Zeta Functions of Hyperelliptic Curves over Finite Fields of Characteristic 2 %f/crypto/v8uhgpdqdi67acvxktanf0lox4ebgmhj.pdf %mf1c4ecc1a780e96f154b091f88614cb7 %ccrypto %@Philip MacKenzie,Thomas Shrimpton,Markus Jakobsson %*Threshold Password-Authenticated Key Exchange %f/crypto/xsdgz08bncajokv7oay1lf9imh6jrmqs.pdf %mfd1831bff1b70379af5e124cf36f3fb6 %ccrypto %@Jesper Buus Nielsen %*A Threshold Pseudorandom Function Construction and Its Applications %f/crypto/3ekh0my2lqajsfrhnseuytcxop7qucgg.pdf %mfcc984d32c4816639d337c662a5d96e9 %ccrypto %@Joy Algesheimer,Jan Camenisch,Victor Shoup %*Efficient Computation Modulo a Shared Secret with Application to the Generation of Shared Safe-Prime Products %f/crypto/vo7ja0b6yejhz5ucg13lkfnp9tgq4ats.pdf %m7d6247f4bda8855010a31f794cc0b8f8 %ccrypto %@Wen-Ching W. Li,Mats Näslund,Igor E. Shparlinski %*Hidden Number Problem with the Trace and Bit Security of XTR and LUC %f/crypto/uh4stswx5jybokclah0pdfbz81ke2ocv.pdf %m68f2462ba9e81c21aa2a0cdd049a0102 %ccrypto %@Ivan Damgåard,Jesper Buus Nielsen %*Expanding Pseudorandom Functions; or: From Known-Plaintext Security to Chosen-Plaintext Security %f/crypto/gu9l4ukdvzyt7i2hbcitvhjrspfnkcy5.pdf %m9d0d52ccf3c61cc51fef1ae05c44e63c %ccrypto %@Emmanuel Bresson,Jacques Stern,Michael Szydlo %*Threshold Ring Signatures and Applications to Ad-hoc Groups %f/crypto/oqlu2fmclcxbgwny5satkox3j9pd61jr.pdf %mc5f53f3a829621ea5eea1d2108f34619 %ccrypto %@Moni Naor %*Deniable Ring Authentication %f/crypto/ngrz9ydbsoj2eauqlre0tm8bpftfdvhj.pdf %mc42a2fd31d19351dadab8cd28c77540d %ccrypto %@Gene Itkis,Leonid Reyzin %*SiBIR: Signer-Base Intrusion-Resilient Signatures %f/crypto/bhgppgjh1f8tmw2qowemubzqresksn7o.pdf %meae9bf5383ea4fae87fb350f85d0a6ae %ccrypto %@Don Coppersmith,Shai Halevi,Charanjit Jutla %*Cryptanalysis of Stream Ciphers with Linear Masking %f/crypto/8ndgf3pzkebwrurvo0k4qx5slg9n72jh.pdf %mf450d51438797b7bd05cfc1527e755d8 %ccrypto %@Palash Sarkar %*The Filter-Combiner Model for Memoryless Synchronous Stream Ciphers %f/crypto/yabrsaw8d60kxll1egqfumdiwcoy5fuc.pdf %m5897b685278cacf7d71f501e626ffc0c %ccrypto %@Claude Carlet %*A Larger Class of Cryptographic Boolean Functions via a Study of the Maiorana-McFarland Construction %f/crypto/dluxbvptca8q9j3r2nwpzmkygrsmbuey.pdf %mccc9ee8804d2153239b06127d8d7faff %ccrypto %@Fehr Serge,Maurer Ueli %*Linear VSS and Distributed Commitments Based on Secret Sharing and Pairwise Checks %f/crypto/e9hqimmcxoa8u3dkj1cw7blrptzzhpdi.pdf %m13d33d6a01807c6a37bde244db5a0b62 %ccrypto %@Ivan Damgård,Jesper Buus Nielsen %*Perfect Hiding and Perfect Binding Universally Composable Commitment Schemes with Constant Expansion Factor %f/crypto/yaoihbrizq6sjtopusjadny5tkg9cmr8.pdf %m500ff47ff4a7ca2add1b839f7fb0ca5a %ccrypto %@Anna Lysyanskaya %*Unique Signatures and Verifiable Random Functions from the DH-DDH Separation %f/crypto/cwbyx2jgqkcqtzufa5hp7yn0xnmowivz.pdf %mfcd559c741b133241011bdad6f8804fa %ccrypto %@Jean-Sébastien Coron %*Security Proof for Partial-Domain Hash Signature Schemes %f/crypto/5i0ajmb6kxczfd34egg7v9fukc1yrqli.pdf %m305829401ba717a3241b6c4f0133d510 %ccrypto %@Boaz Barak,Oded Goldreich,Rusell Impagliazzo,Steven Rudich,Amit Sahai,Salil Vadhan,Ke Yang %*On the (Im)possibility of Obfuscating Programs %f/crypto/2ozlps79mq8gcyjgcjdbbwro3xuwiahq.pdf %me9013d3ddbcae53377a62289304cd9b5 %ccrypto %@Ran Canetti,Marc Fischlin %*Universally Composable Commitments %f/crypto/rufxigtblpuk6oerdjv0c254qm9c3lt7.pdf %mfd2594838622f6b8e318283f57aeecd0 %ccrypto %@Dalit Naor,Moni Naor,Jeff Lotspiech %*Revocation and Tracing Schemes for Stateless Receivers %f/crypto/vt45jexicp68ar9ganmou3wzhfoecnky.pdf %m17d62bf4f10f61bc219af6597a126b73 %ccrypto %@Aggelos Kiayias,Moti Yung %*Self Protecting Pirates and Black-Box Traitor Tracing %f/crypto/cmditvqfephbyusylwqartinevzbsca4.pdf %m48f64e3d075a0086c5fdae52919f25f2 %ccrypto %@Matthias Fitzi,Juan A. Garay,Ueli Maurer,Rafail Ostrovsky %*Minimal Complete Primitives for Secure Multi-party Computation %f/crypto/p47u5odgvajml2zchtz6xkbnegrwvi3q.pdf %m958e6f0cdee26c5b412e40b6a6f93184 %ccrypto %@Martin Hirt,Ueli Maurer %*Robustness for Free in Unconditional Multi-party Computation %f/crypto/p8t5srqwmzgytoh6cqiknncxoa4dmpfd.pdf %m749d3c307a63fdc4832759be44ee8d62 %ccrypto %@Ronald Cramer,Ivan Damgård %*Secure Distributed Linear Algebra in a Constant Number of Rounds %f/crypto/novjv78agceofwzrnqi3bcj5rum40pyl.pdf %mb757614e012b7c0ade1f2f4412faed38 %ccrypto %@Philip MacKenzie,Michael K. Reiter %*Two-Party Generation of DSA Signatures %f/crypto/k5abmznoxvcwf2psgbrls3gpth4mqilc.pdf %mace2762cf23a2a161a13cfc634638ba4 %ccrypto %@Yan Zong Ding %*Oblivious Transfer in the Bounded Storage Model %f/crypto/dqiyf4snlosaphhomx25j9t0ukqwcc3m.pdf %m68db7666757a61c2c572feeb2511f8ff %ccrypto %@Yehuda Lindell %*Parallel Coin-Tossing and Constant-Round Secure Two-Party Computation %f/crypto/agdtxau2rxeofjmrvpgzqk8ylhcy1mic.pdf %mb544e028b9e7ae167594a0496789bd68 %ccrypto %@Robert P. Gallant,Robert J. Lambert,Scott A. Vanstone %*Faster Point Multiplication on Elliptic Curves with Efficient Endomorphisms %f/crypto/qlx3xkhy0tvc4sbevnwphomnyjurlpdu.pdf %mdfadaa15273b56897e3367fb6f2fa592 %ccrypto %@Dan Boneh,Igor E. Shparlinski %*On the Unpredictability of Bits of the Elliptic Curve Diffie-Hellman Scheme %f/crypto/as97iytju3lxflwjirqabxkzgfzdsrec.pdf %m3613b62fb96a141a0e91549ffa2f3fac %ccrypto %@Dan Boneh,Matt Franklin %*Identity-Based Encryption from the Weil Pairing %f/crypto/vir2o7aqredjh9namztobwjdfeckbxzc.pdf %m5fd9df7f03f910776266c77c8487f7ae %ccrypto %@James Manger %*A Chosen Ciphertext Attack on RSA Optimal Asymmetric Encryption Padding (OAEP) as Standardized in PKCS #1 v2.0 %f/crypto/d02py3brzzca1tg5y7svhwrnc6jiomf9.pdf %mc983180fd88bb2b8fdb64eeff7cde5cd %ccrypto %@Victor Shoup %*OAEP Reconsidered %f/crypto/51hrfn4ezakxibpgi7wcls2sjvcpmkae.pdf %m0f57636c1d245c00668b55bac6ad2635 %ccrypto %@Eiichiro Fujisaki,Tatsuaki Okamoto,David Pointcheval,Jacques Stern %*RSA-OAEP Is Secure under the RSA Assumption %f/crypto/2ldpu0z4cvnljxeo8haspcfbagwjwmmx.pdf %m23f2e80b5d9992c2e456b1e5e2209458 %ccrypto %@Dan Boneh %*Simplified OAEP for the RSA and Rabin Functions %f/crypto/0anj5wc7eqkvkp1satdh32xuooldgl9r.pdf %mfb844652fc0750bf1e4b83d7a5d1f2b2 %ccrypto %@Mihir Bellare,Alexandra Boldyreva,Lars Knudsen,Chanathip Namprempre %*Online Ciphers and the Hash-CBC Construction %f/crypto/tsjuymrqgtzivf8sjdhn4l7356rqbygw.pdf %m8efeb5d92d8cbac05663430fb105c0a6 %ccrypto %@Hugo Krawczyk %*The Order of Encryption and Authentication for Protecting Communications (or: How Secure Is SSL?) %f/crypto/0z1ycpokmwoef3g2rv84anuvfbqsxe9d.pdf %m80ec0cc618a283d0d421c67a5dda2341 %ccrypto %@Gene Itkis,Leonid Reyzin %*Forward-Secure Signatures with Optimal Signing and Verifying %f/crypto/eh6cbng42b9r7slhootmilqvm3k5ziud.pdf %me4cf97ed6d24a7d457ee0dbbb253f118 %ccrypto %@Adi Shamir,Yael Tauman %*Improved Online/Offline Signature Schemes %f/crypto/8b3g54i20eozwodbvl9za7dchhysenjn.pdf %mfa95b552215a90e0d55ac69244c01c91 %ccrypto %@Jun Furukawa,Kazue Sako %*An Efficient Scheme for Proving a Shuffle %f/crypto/zymk3jurqxwswjfz59eyhtah4xivrcsa.pdf %m24ed53bc89fffd1102596467e5f6375a %ccrypto %@Jan Camenisch,Anna Lysyanskaya %*An Identity Escrow Scheme with Appointed Verifiers %f/crypto/iblasjgf8c4apky9vzmlk2euq1idy6go.pdf %mb57762db8c3d78557fd273e03be1c738 %ccrypto %@Oded Goldreich,Yehuda Lindell %*Session-Key Generation Using Human Passwords Only %f/crypto/ukf9h5pjyigrocs0qzzg7fwe68lxrhbp.pdf %m5802021bcc54ac443ba8eb618ef0741e %ccrypto %@Eric Brier,Christophe Clavier,Jean-Sébastien Coron,David Naccache %*Cryptanalysis of RSA Signatures with Fixed-Pattern Padding %f/crypto/btd9obln04qywgagx3pcjt1hkeifyurm.pdf %m087c37505262c05fd101843cbe1fdf4c %ccrypto %@Jovan D. Golić %*Correlation Analysis of the Shrinking Generator %f/crypto/ckpldmfsuofzbbje9e2raas4xx3hrtnq.pdf %mdb7104c62635dcfd6740b13425032312 %ccrypto %@Jung Hee Cheon %*Nonlinear Vector Resilient Functions %f/crypto/xzespklxcgekorhfr1wtpdclq6ijw3ao.pdf %m191e0783f0e18360069346a2b48a75c5 %ccrypto %@Seong-Hun Paeng,Kil-Chan Ha,Jae Heon Kim,Seongtaek Chee,Choonsik Park %*New Public Key Cryptosystem Using Finite Non Abelian Groups %f/crypto/bgdea7zv0bpdhmxcxjwkpf6ov1ynozsi.pdf %m60cb58c890b3843be33cc65ea750e7b0 %ccrypto %@Eonkyung Lee,Sang Jin Lee,Sang Geun Hahn %*Pseudorandomness from Braid Groups %f/crypto/d5lexopstizqub1jyve967r0onw2bhfd.pdf %m0934aa6998fca85e2571b43feb938836 %ccrypto %@Ronald Cramer,Ivan Damgård,Serge Fehr %*On the Cost of Reconstructing a Secret, or VSS with Optimal Reconstruction Phase %f/crypto/p2ifluu56itaqn3fbxjkrdbqgvaswovh.pdf %m35e4257ab3cd8baa639e28982b46b5db %ccrypto %@Christian Cachin,Klaus Kursawe,Frank Petzold,Victor Shoup %*Secure and Efficient Asynchronous Broadcast Protocols %f/crypto/cwp4nps1umaetqvtulqsghnf6a2ikzvk.pdf %m6a574b424d7638cfbd17608cf3bb61d0 %ccrypto %@Silvio Micali,Leonid Reyzin %*Soundness in the Public-Key Model %f/crypto/uijeklleoxq7fv0vjc6cddykxhyawph2.pdf %m2237bb0590bd5d988a2e06118dd56513 %ccrypto %@Alfredo De Santis,Giovanni Di Crescenzo,Rafail Ostrovsky,Giuseppe Persiano,Amit Sahai %*Robust Non-interactive Zero Knowledge %f/crypto/ql4ojtl6ebdujan7p9kvxcr3hn10s5vt.pdf %m1906c8cf0e1c3202702caab33446b603 %ccrypto %@Arjen K. Lenstra,Eric R. Verheul %*The XTR Public Key System %f/crypto/wlerpw8zgxjcq0x5azynvok2jadu1cfe.pdf %m54fdfa3e99ec122e1d3abae632a45ac1 %ccrypto %@Éliane Jaulmes,Antoine Joux %*A Chosen-Ciphertext Attack against NTRU %f/crypto/sehmpdwaufzazcrnbugvoq67pbeh5n3o.pdf %m26bc1d0fb7274bd78b99140c95dbed18 %ccrypto %@Yehuda Lindell,Benny Pinkas %*Privacy Preserving Data Mining %f/crypto/tsebergysmdlwizkrz9f7xlotaf1xquu.pdf %mdca9dea879e5cde77b995f1265c91d23 %ccrypto %@Amos Beimel,Yuval Ishai,Tal Malkin %*Reducing the Servers Computation in Private Information Retrieval: PIR with Preprocessing %f/crypto/xgnqtreg8jluts6ud4rceq5znhcxadfy.pdf %me1b74943c3da638e19af7412d89511c2 %ccrypto %@Yevgeniy Dodis,Silvio Micali %*Parallel Reducibility for Information-Theoretically Secure Computation %f/crypto/8jtgfojqhauvexuh5eo1407ypbwzi2cv.pdf %m567143f8afa7ce43356b3f7fb4f77444 %ccrypto %@Christian Cachin,Jan Camenisch %*Optimistic Fair Secure Computation %f/crypto/vokbal2pqmbrkuzcwjuyq1xowjvgp9ia.pdf %m2981d1ce13ca14e645c392d07f1f4915 %ccrypto %@Yevgeniy Dodis,Shai Halevi,Tal Rabin %*A Cryptographic Solution to a Game Theoretic Problem %f/crypto/qmviu8np9lfkirgujjcrt7zeaxdlybv2.pdf %m84e79acf25955a73e2eea85eb0d94c95 %ccrypto %@Ingrid Biehl,Bernd Meyer,Volker Müller %*Differential Fault Attacks on Elliptic Curve Cryptosystems %f/crypto/mfa9ijq58ds7javlrknpwurmlzhsgoi2.pdf %m083fd822168654a1dd7b6b2637eac594 %ccrypto %@Tatsuaki Okamoto,Keisuke Tanaka,Shigenori Uchiyama %*Quantum Public-Key Cryptosystems %f/crypto/viwnhjcrgo0lwf9mjpkz3dmhus2kc4nt.pdf %m92914f7363fb6613d05a6b83e836b7fa %ccrypto %@Ki Hyoung Ko,Sang Jin Lee,Jung Hee Cheon,Jae Woo Han,Ju-sung Kang,Choonsik Park %*New Public-Key Cryptosystem Using Braid Groups %f/crypto/8ewwkcpxbdr0uujf9lod6xcslh2mng17.pdf %m671e9489f039ef41274a755248b87b09 %ccrypto %@Don Coppersmith,Lars R. Knudsen,Chris J. Mitchell %*Key Recovery and Forgery Attacks on the MacDES MAC Algorithm %f/crypto/owk62ucgxs871nrevlmiewdahzzjtsl5.pdf %m27e68986dd0696f368792d0fdff9d8aa %ccrypto %@John Black,Phillip Rogaway %*CBC MACs for Arbitrary-Length Messages: The Three-Key Constructions %f/crypto/g49kopgaeh1cyzmfeybtk6pfonsd5b0j.pdf %mf3e0cabd51273446f01897e551dc7cdf %ccrypto %@Michael Semanko %*L-collision Attacks against Randomized MACs %f/crypto/m1msja3l4skro75ebfunbgxk8vdzof0p.pdf %m6275db5034f122b43258ddcf0af09b36 %ccrypto %@Jean-Sébastien Coron %*On the Exact Security of Full Domain Hash %f/crypto/7b15dacamk2yircwpnnxk8jpq64uxioy.pdf %mfc660f94054d2b59873e99538fca92d3 %ccrypto %@Dan Boneh,Moni Naor %*Timed Commitments %f/crypto/bwqzozwqh8pd41edx9r6gglk7j2ucumy.pdf %m7025c5f78f10879751ecbf606dccb909 %ccrypto %@Giuseppe Ateniese,Jan Camenisch,Marc Joye,Gene Tsudik %*A Practical and Provably Secure Coalition-Resistant Group Signature Scheme %f/crypto/fxh3fvoz04ltx7ic6k1smmked9twz5ur.pdf %ma83760e9ac67b7fed60ea6fe489f7e2f %ccrypto %@Masayuki Abe,Tatsuaki Okamoto %*Provably Secure Partially Blind Signatures %f/crypto/yic7kehsp5zwj0rqm38xlglu2dpdfjgf.pdf %meaa2b4ba2c2fa67f4ef08ce00dd0ddd0 %ccrypto %@Rainer Steinwandt,Markus Grassl,Willi Geiselmann,Thomas Beth %*Weaknesses in the SL2( \mathbb{F}_{2^n } ) Hashing Scheme %f/crypto/wdoh81szlrxmf4cpsioekqcqpez9nayy.pdf %m11bb1fb871bbfc040938e8ba780b7c68 %ccrypto %@Thomas Johansson,Fredrik Jönsson %*Fast Correlation Attacks through Reconstruction of Linear Polynomials %f/crypto/guqfhrt3zkl0q8tcmskidy2gex4hopjw.pdf %m6c06bee2171c2a19b7cb267f235e244c %ccrypto %@Reihaneh Safavi-Naini,Yejing Wang %*Sequential Traitor Tracing %f/crypto/xgyebfo5hyqwb61tjm3kixoq7czprpec.pdf %ma5a16df0a5a9a4a052158945e175bd8f %ccrypto %@Juan A. Garay,Jessica Staddon,Avishai Wool %*Long-Lived Broadcast Encryption %f/crypto/5cvgui3cysudjs9mn0gb64ai1whnewop.pdf %mf180d09d03cf1a40c7970f723bec446e %ccrypto %@Martín Abadi %*Taming the Adversary %f/crypto/ownq4wuikshr3yl9npj8mpead5acv0mf.pdf %m3ebc294702f0793c32455e45885cf2ed %ccrypto %@Anand Desai %*The Security of All-or-Nothing Encryption: Protecting against Exhaustive Key Search %f/crypto/ntzpntdfkazwufmvkbeoi42y8v9xa0wp.pdf %m5666375c4bd1c678f3a5008e2078e5a9 %ccrypto %@Zulfikar Ramzan,Leonid Reyzin %*On the Round Security of Symmetric-Key Cryptographic Primitives %f/crypto/jmx8gk4cfxh5y0v7zasilro9rj2dtshb.pdf %mc0d48ebb89f232589f5e989398d16bde %ccrypto %@Anand Desai %*New Paradigms for Constructing Symmetric Encryption Schemes Secure against Chosen-Ciphertext Attack %f/crypto/nlnv7y3c1fimqlfcaowpsrbgzbyoek9t.pdf %m7feacc4c2e9909e66a64f8e947cfb386 %ccrypto %@Marc Fischlin,Roger Fischlin %*Efficient Non-malleable Commitment Schemes %f/crypto/pkqcu7pkzxdlaacvugmi9nribyw5th60.pdf %m94a4558657e3453abf3f585993180a87 %ccrypto %@Ivan Damgård,Jesper Buus Nielsen %*Improved Non-committing Encryption Schemes Based on a General Complexity Assumption %f/crypto/mu8jkcy4e7hszbxp1fwezdldtqqrkgvu.pdf %m8d8eb84d8a244640ffe80689b129e888 %ccrypto %@Alon Rosen %*A Note on the Round-Complexity of Concurrent Zero-Knowledge %f/crypto/bfmfm9wquyro4hyxgvnz8jgvexd3c7hp.pdf %me51770077bbd5140222878c8b3aeece4 %ccrypto %@Rosario Gennaro %*An Improved Pseudo-random Generator Based on Discrete Log %f/crypto/bjya5ng4gwc1zsol3nvijkdila06bhdz.pdf %m97a6d40febe12ef8fcf0f7d31855fb62 %ccrypto %@Nicolas Gisin,Stefan Wolf %*Linking Classical and Quantum Key Agreement: Is There “Bound Information”? %f/crypto/jv3gzcudylsmdiyohn49wprub5ab7tsp.pdf %mdce69ba8ed3949480ee1f3eac7b1b106 %ccrypto %@Muxiang Zhang,Agnes Chan %*Maximum Correlation Analysis of Nonlinear S-boxes in Stream Ciphers %f/crypto/dhf7lmccxgr8wttowuzyhgm342rlpfv1.pdf %m40b4afb40e75533a3d3c3bc8379f3099 %ccrypto %@Palash Sarkar,Subhamoy Maitra %*Nonlinearity Bounds and Constructions of Resilient Boolean Functions %f/crypto/kdln71qiw5e3xgbgtu4rmwz9ckir8f2h.pdf %m02cd174db8f6137197107dd17c961890 %ccrypto %@Jürgen Bierbrauer,Holger Schellwat %*Almost Independent and Weakly Biased Arrays: Efficient Constructions and Cryptologic Applications %f/crypto/ytzsc8econ1exgkam6jukhpynqr573a2.pdf %m06137b48dc3211d644d59e444a947672 %ccrypto %@Jean-Sébastien Coron,David Naccache,Julien P. Stern %*On the Security of RSA Padding %f/crypto/b5ynxopwtm0a4gbuqjdl7nicezzikqes.pdf %mfd9a2a341003b0881b2fd727ad0806ec %ccrypto %@Aviad Kipnis,Adi Shamir %*Cryptanalysis of the HFE Public Key Cryptosystem by Relinearization %f/crypto/tkuy451k7wwojehq8i9psdrpsa3zdeci.pdf %ma7dd3af3c022a47c8ab72076e3b4f2cb %ccrypto %@Phong Nguyen,Jacques Stern %*The Hardness of the Hidden Subset Sum Problem and Its Cryptographic Implications %f/crypto/odeirlqb8z4usmtnqxh9ugrwwp7zs0fk.pdf %m097c4b098db36828af1bb9a8aff6d706 %ccrypto %@Ueli Maurer %*Information-Theoretic Cryptography %f/crypto/zkrj1wdwot4ldkjhpexoga8zmm5balnv.pdf %md20d2d80a96c0fcb4b1775045133b217 %ccrypto %@Yonatan Aumann,Michael O. Rabin %*Information Theoretically Secure Communication in the Limited Storage Space Model %f/crypto/ouv2c6nxpwhmvrhr4t7jzafwdi3ysag9.pdf %mb9090df7912ad0887afc247eb02850f4 %ccrypto %@Amos Beimel,Tal Malkin,Silvio Micali %*The All-or-Nothing Nature of Two-Party Secure Computation %f/crypto/vyh0tz6nmpxqjiadfcmez2piu1vt8gfl.pdf %me4ef1396fe70e8abe4fc7d6ca95f23e5 %ccrypto %@Ran Canetti,Rosario Gennaro,Stanisław Jarecki,Hugo Krawczyk,Tal Rabin %*Adaptive Security for Threshold Cryptosystems %f/crypto/dwumsnjzcakvh29nra1ybpdxto7fhgos.pdf %m85f15ab9e9fb6539bf0e2d17c28157b4 %ccrypto %@Niv Gilboa %*Two Party RSA Key Generation %f/crypto/ajm7yzeuq1suarncd9pnhxqkywgb8plf.pdf %m4b721ef8258f771a4277c5153ea37d01 %ccrypto %@Masayuki Abe %*Robust Distributed Multiplication without Interaction %f/crypto/feuaupcqvkje5mlgydhscbwl24h7jnd6.pdf %m6e71ef944dc2f4f8a944ecc4cb7b7e6d %ccrypto %@Berry Schoenmakers %*A Simple Publicly Verifiable Secret Sharing Scheme and Its Application to Electronic Voting %f/crypto/s4ygdzviojql1xm8ewua2mtesg0qnrdb.pdf %m855796b5a5cf43a581820fd6672a3494 %ccrypto %@Lars R. Knudsen,M. J. B. Robshaw,David Wagner %*Truncated Differentials and Skipjack %f/crypto/m5isklvh0p6fhbs2mlyuvxnptawqidu3.pdf %m488a3b74ffd38cecf7736435f0806dfe %ccrypto %@Thomas Johansson,Fredrik Jönsson %*Fast Correlation Attacks Based on Turbo Code Techniques %f/crypto/60k8xefq2ytgcqlaj4o7pmuvx9zw3vji.pdf %m0437d09c54d0cc03c9047c192200524c %ccrypto %@Subhamoy Maitra,Palash Sarkar %*Highly Nonlinear Resilient Functions Optimizing Siegenthaler’s Inequality %f/crypto/nmggft0e5ha9zo43dndlbczy2pkmewss.pdf %m56397d06573994201f1e4206b9cce81b %ccrypto %@J. Black,S. Halevi,H. Krawczyk,T. Krovetz,P. Rogaway %*UMAC: Fast and Secure Message Authentication %f/crypto/tnhsm8dqozyufp9giwlbad5icahvnq60.pdf %m6d23c02b08b2939eafdba14ce86ee2e4 %ccrypto %@Mark Etzel,Sarvar Patel,Zulfikar Ramzan %*Square Hash: Fast Message Authentication via Optimized Universal Hash Functions %f/crypto/f8ctlz7yuwmixaz34pbgdcqklrgenoup.pdf %mb2344727d5c657fcf1ea1e947fe64ba4 %ccrypto %@Jee Hea An,Mihir Bellare %*Constructing VIL-MACs from FIL-MACs: Message Authentication under Weakened Assumptions %f/crypto/zi39ktagnq5vywpvhsnehjxe0rqclsux.pdf %m122e1c86aa3df41dfb93a2bb99101ea8 %ccrypto %@Mihir Bellare,Oded Goldreich,Hugo Krawczyk %*Stateless Evaluation of Pseudorandom Functions: Security Beyond the Birthday Barrier %f/crypto/tpuef5yhadozyhngjdvwfmalvklbs6xi.pdf %m9296ffd4a1a671ea57c3fccd572625e7 %ccrypto %@Phong Nguyen %*Cryptanalysis of the Goldreich-Goldwasser-Halevi Cryptosystem from Crypto ’97 %f/crypto/zf1dcecpgs4tpr6g7mbblyihojr98huq.pdf %m665b1d262a526d987bedeaede76e2a02 %ccrypto %@Don Coppersmith %*Weakness in Quaternion Signatures %f/crypto/pfzg2tm6widkusxloxtbsw0ryy9bpeei.pdf %mea7dd003f280cb6ab7b3cc5de71b4194 %ccrypto %@Ye Ding-Feng,Lam Kwok-Yan,Dai Zong-Duo %*Cryptanalysis of “2R” Schemes %f/crypto/ox4iq82yewolayzmcd9tusehvpknbivh.pdf %m5f35af11472bdc77642c1b215430045e %ccrypto %@Dan Boneh,Glenn Durfee,Nick Howgrave-Graham %*Factoring N = prq for Large r %f/crypto/k7a1t38zpaemxoqgywmesthcxpivg6r5.pdf %m521d7c044a8dd3691e3dc2543483a066 %ccrypto %@Dan Boneh,Matthew Franklin %*An Efficient Public Key Traitor Tracing Scheme %f/crypto/vsonm80jxuic7ox4rdcpbzjftl5wbhia.pdf %m7ea27b914b3b84331c8a75940b4befef %ccrypto %@Amos Fiat,Tamir Tassa %*Dynamic Traitor Tracing %f/crypto/khmicfjybadrpxyo1vbsut56n0otzgza.pdf %mc703846a158b425eabf9ac5c363990cc %ccrypto %@Eli Gafni,Jessica Staddon,Yiqun Lisa Yin %*Efficient Methods for Integrating Traceability and Broadcast Encryption %f/crypto/lqqo4uapixag8cbw0vnwyxfzephtck9g.pdf %mceb11ae739f915081a6ca26bd8e06bc2 %ccrypto %@Paul Kocher,Joshua Jaffe,Benjamin Jun %*Differential Power Analysis %f/crypto/7g80sgipao2e4vtmz1rjf5luohsnkxwd.pdf %me3324770af83d3282f7d311b193bfa5d %ccrypto %@Suresh Chari,Charanjit S. Jutla,Josyula R. Rao,Pankaj Rohatgi %*Towards Sound Approaches to Counteract Power-Analysis Attacks %f/crypto/lcc70tj542qaftnhvuev1wrga3ozdbi6.pdf %m6947b522209ca50a0d15ee82dce4e9c6 %ccrypto %@Jan Camenisch,BRICS,Markus Michels %*Separability and Efficiency for Generic Group Signature Schemes %f/crypto/gqkh5mj8repe0fzhsuwoud197bbogawp.pdf %mbffd091fd481df99cdded9360a422409 %ccrypto %@Mihir Bellare,Sara K. Miner %*A Forward-Secure Digital Signature Scheme %f/crypto/ndpzov5pb9s2ugxzl1ywfuihtkebmvmq.pdf %md4fdcd0c385f67ca497b47fce643e878 %ccrypto %@Juan A. Garay,Markus Jakobsson,Philip MacKenzie %*Abuse-Free Optimistic Contract Signing %f/crypto/tuuczpgxitoijv2rewmklq3ncasw57fh.pdf %m22e6a9fb987d6a250d6534cf81e43b28 %ccrypto %@Oded Goldreich,Amit Sahai,Salil Vadhan %*Can Statistical Zero Knowledge Be Made Non-interactive? or On the Relationship of SZK and NISZK %f/crypto/cygelxndzofjmrs8xwab3lnpq95i6dep.pdf %m220f7a6d24359c82dd815f2892a7170b %ccrypto %@Giovanni Di Crescenzo,Rafail Ostrovsky %*On Concurrent Zero-Knowledge with Pre-processing %f/crypto/hlsvmituafzorjpceyfuvw3yjbqdsggx.pdf %m6551b67a703ef67f0922ac81a6d617db %ccrypto %@Victor Boyko %*On the Security Properties of OAEP as an All-or-Nothing Transform %f/crypto/7rdqymvxwe59qhspuyefjfrbksjzxton.pdf %mf54cb7297914af52d4162e2f0c71a672 %ccrypto %@Mihir Bellare,Amit Sahai %*Non-malleable Encryption: Equivalence between Two Notions, and an Indistinguishability-Based Characterization %f/crypto/hiadp3mvrs9bh2tgfdcb1joeai5lxjly.pdf %me29a5a2298f3934534788c8b9b7f65a7 %ccrypto %@Eiichiro Fujisaki,Tatsuaki Okamoto %*Secure Integration of Asymmetric and Symmetric Encryption Schemes %f/crypto/op5axmpwedba3jniq1s28h6cv4qjg0zg.pdf %m0d636f1fdefbf00ba1a0c2eca8b593e4 %ccrypto %@Tomas Sander,Amnon Ta-Shma %*Auditable, Anonymous Electronic Cash %f/crypto/hbbax2qzhrfuq73f4m19ns05iyd6oclp.pdf %m64d20e0b178b3c6acd0c1de1dcad8add %ccrypto %@Moni Naor,Benny Pinkas %*Oblivious Transfer with Adaptive Queries %f/crypto/swicl5ep8nagmbjmlb7ant1kofhyvxoz.pdf %m6653436e8c8847ef8f79ce0e9aca113d %ccrypto %@Niv Gilboa,Yuval Ishai %*Compressing Cryptographic Resources %f/crypto/wmqr1j9gdepnioapuy67ke5lsqbmohux.pdf %m4794611ed531c79b7e645d795e10716b %ccrypto %@Ravi Kumar,Sridhar Rajagopalan,Amit Sahai %*Coding Constructions for Blacklisting Problems without Computational Assumptions %f/crypto/wgyjocazpid1fkcdeg7vqmtr5pxnolw3.pdf %m098cb2b1d178106712b3f2bc2bd36397 %ccrypto %@R. Poovendran,J. S. Baras %*An Information Theoretic Analysis of Rooted-Tree Based Secure Multicast Key Distribution Schemes %f/crypto/eziqjjovbt1fp7b5w9ymlkpu0xikxzqt.pdf %m4bc9540ffbc1cb43214682b23fe0f604 %ccrypto %@Daniel Bleichenbacher %*Chosen ciphertext attacks against protocols based on the RSA encryption standard PKCS #1 %f/crypto/vfhbiqoovkkbfz4lwta9yejlw8gd6c1j.pdf %m4269937bcca21ba5d8d1e723735c66e4 %ccrypto %@Ronald Cramer,Victor Shoup %*A practical public key cryptosystem provably secure against adaptive chosen ciphertext attack %f/crypto/gcdieowuqbxmnpvtz9h0rasozsmdkftc.pdf %mdc6baaf2f8d7e183df452c45f323c63e %ccrypto %@Mihir Bellare,Anand Desai,David Pointcheval,Phillip Rogaway %*Relations among notions of security for public-key encryption schemes %f/crypto/lzxpnclc2ho8tuejdmdfny6wuarjbvok.pdf %me4fadc840c005c3b95cdf1011925d215 %ccrypto %@Steven M. Bellovin %*Cryptography and the internet %f/crypto/ljsfejagibpukkyh62ivnte9p1qf5sv3.pdf %m1606afd2b7f1b3ceb0ec231570c25f57 %ccrypto %@Florent Chabaud,Antoine Joux %*Differential collisions in SHA-0 %f/crypto/eytcp24neirwhxhofmoarsulpzdwkbg6.pdf %m6cd430c8dd412a63f76010c758cb10cd %ccrypto %@Alex Biryukov,Eyal Kushilevitz %*From differential cryptanalysis to ciphertext-only attacks %f/crypto/gfuqsrypi8edcnr9jidvmzfx7veox24t.pdf %md4497ef67a190c9f6827eee2822b1f6f %ccrypto %@Tal Rabin %*A simplified approach to threshold and proactive RSA %f/crypto/bylzkzuahaq8rj19ejsphfxk3wd2gnc0.pdf %m8e45f49543a402054415c6b4da4c3c06 %ccrypto %@Dario Catalano,Rosario Gennaro %*New efficient and secure protocols for verifiable signature sharing and other applications %f/crypto/iksb7qbok9zvz2gr0ijadftfnt1o5wyc.pdf %m839aeba284f59643b71922c9701ff8a9 %ccrypto %@Matthias Fitzi,Martin Hirt,Ueli Maurer %*Trading correctness for privacy in unconditional multi-party computation %f/crypto/76hfupvxadg9pmzwdscjtyzbetigo82y.pdf %m21715b97e7b34a13bef9aaea67fcee15 %ccrypto %@William Aiello,Sachin Lodha,Rafail Ostrovsky %*Fast digital identity revocation %f/crypto/gtifqdpvj9jz5nmelrwy6hyxsalc7xak.pdf %m3471771a53009a09e0da5e186908402f %ccrypto %@Oded Goldreich,Birgit Pfitzmann,Ronald L. Rivest %*Self-delegation with controlled propagation — or — What if you lose your laptop %f/crypto/6pt5y0qvrnnpzcjtwh2idlhkacgkfsif.pdf %m5fa3a0005a74219247b59e4665046135 %ccrypto %@Joe Kilian,Erez Petrank %*Identity escrow %f/crypto/rnmwcu16dgyukbhmrtc4i79apgizxwqh.pdf %m5166ed2cdd30f6fc5de91a3c37d657d5 %ccrypto %@Charanjit S. Jutla %*Generalized birthday attacks on unbalanced Feistel networks %f/crypto/ixgloqzg1exfliqebwzvumv9hmrh4asp.pdf %m13453c40cd7585f6f6711b25e15517c9 %ccrypto %@Takeshi Shimoyama,Toshinobu Kaneko %*Quadratic relation of S-box and its application to the linear attack of full round DES %f/crypto/fcoqausuvejgbq8nznp3y7t9t6ekoaxg.pdf %me379cefe36fc55f50326566ffbd6030e %ccrypto %@Thomas Jakobsen %*Cryptanalysis of block ciphers with probabilistic non-linear relations of low degree %f/crypto/uiqljwddayc6km25evm0rwtbnbslx1ys.pdf %m459da8270183d5a2ca185db8125aae52 %ccrypto %@Phong Nguyen,Jacques Stern %*Cryptanalysis of the Ajtai-Dwork cryptosystem %f/crypto/82kxbv1rffv3alje4iq6c0qm5zxhtejm.pdf %m08ad218d3ea45a21af8529e96f60a2a4 %ccrypto %@Serge Vaudenay %*Cryptanalysis of the Chor-Rivest cryptosystem %f/crypto/q8s3botzuwmbnaysqrcxuphfknhdw7te.pdf %m06a526b2d506f34511e5107d85b3925b %ccrypto %@Aviad Kipnis,Adi Shamir %*Cryptanalysis of the oil and vinegar signature scheme %f/crypto/8zj3hf6uzkipmpyo4ei2xl7h5v1cbjrf.pdf %mf6ba8cdce3d7b82f4b2b0e4c27d3a573 %ccrypto %@Moni Naor,Omer Reingold %*From unpredictability to indistinguishability: A simple construction of pseudo-random functions from MACs %f/crypto/h8sapm25zj6xnbokipldtgwrstedqvko.pdf %m7787d57e533147e0c3b2d5b75dba91cb %ccrypto %@Mihir Bellare,Shai Halevi,Amit Sahai,Salil Vadhan %*Many-to-one trapdoor functions and their relation to public-key cryptosystems %f/crypto/jknqhxm1oam87zp6jiklzd9ht2xdu0fu.pdf %mc55c9008dc54620c215484629096e4cb %ccrypto %@Yonatan Aumann,Michael O. Rabin %*Authentication, enhanced security and error correcting codes %f/crypto/tint1qrh9fy5so2cxagwupghn8ljvkio.pdf %mca9c007538c45dd1602a409efba0112c %ccrypto %@Sarvar Patel,Ganapathy S. Sundaram %*An efficient discrete log pseudo random generator %f/crypto/ooyphsrjlzghdtkvsiz9wr2ynulgkm5w.pdf %me2e16bbd129a93857d54e5c27953163c %ccrypto %@Tsuyoshi Takagi %*Fast RSA-type cryptosystem modulo pkq %f/crypto/ao1snaq3r7nks0bguierdfdkbvc4ztex.pdf %me251f4bf93167c5b1b9c1b6cca8260d7 %ccrypto %@Neal Koblitz %*An elliptic curve implementation of the finite field digital signature algorithm %f/crypto/z47pomakersnxujh51flbqjkg8epltd2.pdf %mde091c27d2a41d4e60cf5c8b3b0c584e %ccrypto %@Louis Salvail %*Quantum bit commitment from a physical assumption %f/crypto/h2pdgxatsvkyv64bhgfs9ccqj5y3uzao.pdf %m1db4745a8306b822e0eabeb952a5f4be %ccrypto %@Kazuo Ohta,Tatsuaki Okamoto %*On concrete security treatment of signatures derived from identification %f/crypto/sdxltc3dvrkmxi5twupp6ae0jf481vgm.pdf %mda04ea4a1a73cd63c32f7e74c2e33af4 %ccrypto %@Chris Hall,David Wagner,John Kelsey,Bruce Schneier %*Building PRFs from PRPs %f/crypto/n4wpe2vefbxsgktazq93wjmzfbimh1ln.pdf %m610479c2faad8ed233301f9710877672 %ccrypto %@W. Aiello,M. Bellare,G. Di Crescenzo,R. Venkatesan %*Security amplification by composition: The case of doubly-iterated, ideal ciphers %f/crypto/st3whxrcjlktfvps07wzqjxyki8gron1.pdf %m57c6edf5b246f447cd3fb9602e128c85 %ccrypto %@Satoshi Hada,Toshiaki Tanaka %*On the existence of 3-round zero-knowledge protocols %f/crypto/p5vw9rnlk3x1zqaw8ktpnafodmgqmv6r.pdf %m0973ad3f35a07691160ed3c89733f0ab %ccrypto %@Ronald Cramer,Ivan Damgård %*Zero-knowledge proofs for finite field arithmetic, or: Can zero-knowledge be for free? %f/crypto/vg8nx12fmiahqskjovu54ydrzozbcpu3.pdf %m59f91b4046f53dfbbd772bbbf2c6db7c %ccrypto %@Cynthia Dwork,Amit Sahai %*Concurrent zero-knowledge: Reducing the need for timing constraints %f/crypto/8rhpda53i0rfcvuukdecvzstg94njqxl.pdf %m8bca56f03e2932618d21df4b7ce8f91b %ccrypto %@Damian Weber,Thomas Denny %*The solution of McCurley's discrete log challenge %f/crypto/1zs9oxb3sqhkqodp2cij85zfhktgfyav.pdf %m5ced1d7b78e8d546da72d79b2af4dfdc %ccrypto %@Daniel V. Bailey,Christof Paar %*Optimal extension fields for fast arithmetic in public-key algorithms %f/crypto/mhjofvvk0pg2tib1u5cqywldo9wkmc4r.pdf %m33555b8ce67bb591111b40776356ea47 %ccrypto %@Ahto Buldas,Peeter Laud,Helger Lipmaa,Jan Villemson %*Time-stamping with binary linking schemes %f/crypto/i3fbl4dtzmonig6apcrd0sxzsqv7unmx.pdf %m32404fa5f7a724ada1fcbbd05e29c4df %ccrypto %@Moni Naor,Benny Pinkas %*Threshold traitor tracing %f/crypto/fruolpa2v5qotswf1mhikd9yjazg3n6x.pdf %m17f5f1088ab51246cda678d4b19e0ad1 %ccrypto %@Mikael Goldmann,Mats NÄslund %*The complexity of computing hard core predicates %f/crypto/a6fedilyauqc1wxwokdvbmsp4rrxthhj.pdf %m87245da5083cd7c09d4f37e9461e5ecb %ccrypto %@Eiichiro Fujisaki,Tatsuaki Okamoto %*Statistical zero knowledge protocols to prove modular polynomial relations %f/crypto/odwnvbsuiehb1mkenrfw5tlia4l9sqtp.pdf %mc4761a014745cb3a8233ff540925adef %ccrypto %@Giovanni Di Crescenzo,Tatsuaki Okamoto,Moti Yung %*Keeping the SZK-verifier honest unconditionally %f/crypto/xpufyqwkjdru5q92nelcggw0ybktrhmi.pdf %m5cd37d65ca13effe89eef728e4089e63 %ccrypto %@Oded Goldreich %*On the foundations of modern cryptography %f/crypto/uxala9zcimn6w51g7mos2wivrkpedt0n.pdf %mdc9c50955161ece596f6b30b9d644982 %ccrypto %@Donald Beaver %*Plug and play encryption %f/crypto/qc04llsmp1wkj72abpnhey3vv86du5yn.pdf %me63193d2c047b0e469d6a2d8c0ba0e1a %ccrypto %@Rein Canetti,Cynthia Dwork,Moni Naor,Rafail Ostrovsky %*Deniable Encryption %f/crypto/e9shlbmm3ueozx0nicq1jntvgtrgpjfv.pdf %m6640aab81ff19a63f18c0e9b03ad86f0 %ccrypto %@Oded Goldreich,Shafi Goldwasser,Shai Halevi %*Eliminating decryption errors in the Ajtai-Dwork Cryptosystem %f/crypto/z5yuqqunngmktisrl8o9bjp7wcatkogf.pdf %m4e4e19bb9b3f0df755da29cd8581dd88 %ccrypto %@Oded Goldreich,Shafi Goldwasser,Shai Halevi %*Public-key cryptosystems from lattice reduction problems %f/crypto/tiuhvdmqezy7s6xzkljrcufp1bmckgg5.pdf %m15c16ea6cfe6c20c6181b3d46f9c25fa %ccrypto %@Rosario Gennaro,Hugo Krawczyk,Tal Rabin %*RSA-based undeniable signatures %f/crypto/8kwn59hrizormz70tbqacquj3gywxuve.pdf %mce5290e31bf65c089a8d4a0e70402d51 %ccrypto %@Ari Juels,Michael Luby,Rafail Ostrovsky %*Security of blind digital signatures %f/crypto/qkndxglaybeohkoh58wjipgrbcxjf4vp.pdf %m23ae216a661135329216c9b0b9814e20 %ccrypto %@Yuliang Zheng %*Digital signcryption or how to achieve cost(signature & encryption) ≪ cost(signature) + cost(encryption) %f/crypto/pxck65gkwzumtraxhf4fsarpewoo3bte.pdf %mf9caf84d07aa4dbbadfe3aba8a400795 %ccrypto %@Rosario Gennaro,Pankaj Rohatgi %*How to sign digital streams %f/crypto/ucmjn9grrg35iylzjimkswhvvw401obt.pdf %m5f66fbc4b3a629f1acacdcd0b4a64f39 %ccrypto %@Phong Nguyen,Jacques Stern %*Merkle-Hellman revisited: A cryptanalysis of the Qu-Vanstone cryptosystem based on group factorizations %f/crypto/0zksqvtlx54wodgfiyedskf6uiapapvo.pdf %mc027ee8815f7488651d5961e1de1b271 %ccrypto %@Thomas A. Berson %*Failure of the McEliece public-key cryptosystem under message-resend and related-message attack %f/crypto/u1qlwgxnvoxhkr4tkryv9qb0iabwdsee.pdf %m892b4ed555562f015deef5a57c2f4ff6 %ccrypto %@Jean -FranÇois Misarsky %*A multiplicative attack using LLL algorithm on RSA signatures with redundancy %f/crypto/bcd4ufp7v96vsrxgwgbycwjjfpaso2er.pdf %mbc3d82a2c60b1fca583c53afb8d7e0e7 %ccrypto %@D. Bleichenbacher %*On the security of the KMOV public key cryptosystem %f/crypto/4hcvagcktdm3hbqwtyzibm7uod0erlav.pdf %m7d8a312bf50c7e00dd8d426888d7c302 %ccrypto %@Adam Young,Moti Yung %*The prevalence of kleptographic attacks on discrete-log based cryptosystems %f/crypto/kuwxfvichnmod5q0bhfasrxqtjgaeb7v.pdf %m064a5971e67e41f3c3e5792727f62c83 %ccrypto %@Mihir Bellare,Shafi Goldwasser,Daniele Micciancio %*“Pseudo-random” number generation within cryptographic algorithms: The DDS case %f/crypto/lt1euozvb5pqbxs7cijfkws2oufcdzga.pdf %m4edc2ac7f6ca75ffd367f50e73d3dd85 %ccrypto %@Christian Cachin,Ueli Maurer %*Unconditional security against memory-bounded adversaries %f/crypto/mhj32eptdr9cwa5kygjovnhxp0dzb84g.pdf %me665391a925f074dc832ad4b3536ad88 %ccrypto %@Ueli Maurer,Stefan Wolf %*Privacy amplification secure against active adversaries %f/crypto/ier7uthv5xhjkvf8ouqmaaclwsgbmypz.pdf %m988fc8d29fcb49b26ce72c985f8101f7 %ccrypto %@Moni Naor,Benny Pinkas %*Visual authentication and identification %f/crypto/in2mkxzzh90pbvy6fevooirtqcpa3jr8.pdf %me164c51a3e9614f627dd676d716e7fb0 %ccrypto %@Gilles Brassard %*Quantum information processing: The good, the bad and the ugly %f/crypto/9khmufu5sntoyy0pxlmxqihwczljrdat.pdf %mb6dd2772afce762ac66799055f687a4c %ccrypto %@Jorge Guajardo,Christof Paar %*Efficient algorithms for elliptic curve cryptosystems %f/crypto/tzfhwdf6p214rq7e3arwkbioyl5snlt0.pdf %m0507bacb54a3ba7446e668948d51d9ab %ccrypto %@Jerome A. Solinas %*An improved algorithm for arithmetic on a family of elliptic curves %f/crypto/jl3avbus7p8ekzukxhriyddfahww5eox.pdf %m77d186df4d648a5af9793ae888e9c555 %ccrypto %@Tsuyoshi Takagi %*Fast RSA-type cryptosystems using n-adic expansion %f/crypto/o4vs6cb2uzcn7wtpkil51adm03grpbyk.pdf %mb64eae356bebb6da10d64dce2c5f7290 %ccrypto %@Johannes Buchmann,Sachar Paulus %*A one way function based on ideal arithmetic in number fields %f/crypto/cqdxu0r83agtglzlijsncd9v5fnx1kpf.pdf %m11f75256bfd9037aabe1c89e11507630 %ccrypto %@Shlomi Dolev,Rafail Ostrovsky %*Efficient anonymous multicast and reception %f/crypto/3xjs1loelrzfawut7ovdi4ptyhk6vbpg.pdf %me956b28b963f7778e23f4d2a6359a838 %ccrypto %@Jan Camenisch,Markus Stadler %*Efficient group signature schemes for large groups %f/crypto/z0olulgiyrfnje1vpkskpcm4rtq5dtyj.pdf %mcb205c8a0f53f2603cec8e9930f5a141 %ccrypto %@Dan Boneh,Matthew Franklin %*Efficient generation of shared RSA keys %f/crypto/u9rzsahxi7mzvndgo0bwlycsvtbjydr4.pdf %mf0eabbb9a65c60a226459c48d5dfc759 %ccrypto %@Yair Frankel,Peter Gemmell,Philip D. MacKenzie,Moti Yung %*Proactive RSA %f/crypto/bzyo0vukagcyqw3d9kxfu2ozrtvsdgli.pdf %m49f2be3402ac01ce1a2f9d699f19af2f %ccrypto %@Ran Canetti %*Towards realizing random oracles: Hash functions that hide all partial information %f/crypto/1diqo73p2len9tlhwu4ktzsfmgyacv5s.pdf %m6a8326f133be518f78dc760c652a04e5 %ccrypto %@Mihir Bellare,Phillip Rogaway %*Collision-Resistant hashing: Towards making UOWHFs practical %f/crypto/mp1wetkjogwfbtlvviusqxqoaufzbrj0.pdf %m8a5824c98a90e522200a4201a8d4ee45 %ccrypto %@Lars Knudsen,Bart Preneel %*Fast and secure hashing based on codes %f/crypto/mci6octqgkrlq0vfabyzsrdplanm1due.pdf %meb8d8fba151a552217114d2acb3251c3 %ccrypto %@Jovan Dj. Golić,Renato Menicocci %*Edit distance correlation attack on the alternating step generator %f/crypto/kneupbfv8wx3arzwmq0z5bijl7p6ulsg.pdf %m7f34cc4b82eb7eaf511a5c4b901de497 %ccrypto %@Eli Biham,Adi Shamir %*Differential fault analysis of secret key cryptosystems %f/crypto/3xmgvlsm2inztuvoqudgspew8pickax4.pdf %md615c974da83d73045793deb4f306501 %ccrypto %@David Wagner,Bruce Schneier,John Kelsey %*Cryptanalysis of the cellular message encryption algorithm %f/crypto/dqnca5won6fqelmosxbbckrvr4wuyzis.pdf %m9089666b824a00a44f884f165eb842e2 %ccrypto %@Mihir Bellare,Ran Canetti,Hugo Krawczyk %*Keying Hash Functions for Message Authentication %f/crypto/oci5ytbpnv2dqifzc8gkx7pe9kejyhfm.pdf %ma78f2c9edb5b33790db7859df9c3d852 %ccrypto %@M. Atici,D. R. Stinson %*Universal Hashing and Multiple Authentication %f/crypto/3itdn7hcl2gv4um5mljh1jk8wzfrny9u.pdf %m7032e90ad3c1d6a8c029046897808f7a %ccrypto %@Tor Helleseth,Thomas Johansson %*Universal Hash Functions from Exponential Sums over Finite Fields and Galois Rings %f/crypto/gnp4yxlq1a3ibqdoaydtp8ojrwfihmcj.pdf %me0902b8a86188a4e34ad7b31f1836415 %ccrypto %@Jacques Patarin %*Asymmetric Cryptography with a Hidden Monomial %f/crypto/htkoyozsqxwqb67hwmfbujxvi4dtea0k.pdf %m34d4888272b4462d71a2d3b8d7085020 %ccrypto %@Daniel R. Simon %*Anonymous Communication and Anonymous Cash %f/crypto/ps4ukliqgw3ejchpd7tsye2rzbzcqfak.pdf %ma5d9700bb6562982c5528f420fca4d04 %ccrypto %@Susan K. Langford %*Weaknesses in Some Threshold Cryptosystems %f/crypto/dszae58gjjb1gexfay6us0ibnwuktchl.pdf %m2c401d5fb3dca511ced18001afe90fe6 %ccrypto %@Serge Vaudenay %*Hidden Collisions on DSS %f/crypto/0jmgncsieg8o4hxko9puqvkzcmvwyzhl.pdf %md39019d1b94ce638282fb9e754d6e05d %ccrypto %@Adam Young,Moti Yung %*The Dark Side of “Black-Box” Cryptography or: Should We Trust Capstone? %f/crypto/fyqrbqomzglcauai4xxpkhpzytdt67cr.pdf %mb67015a361c40eaac7bd6026380293b0 %ccrypto %@Paul C. Kocher %*Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems %f/crypto/tcqesqkrr12ufjn8iw5xzpvm0skaozbg.pdf %me88ae3f621aefde6f5a75e3544af6c38 %ccrypto %@Mats Näslund %*All Bits in ax + b mod p are Hard %f/crypto/k5jhz1sfeurhblcvcxn8oqyymj730gpw.pdf %mdfeba89f159d98fa53a82dd99f997fd7 %ccrypto %@Dan Boneh,Ramarathnam Venkatesan %*Hardness of Computing the Most Significant Bits of Secret Keys in Diffie-Hellman and Related Schemes %f/crypto/4accezsflg9qmnf0nuzrvkarvhjmhix6.pdf %m67a03eb259f51b91aeab02543de2e6f6 %ccrypto %@C. P. Schnorr %*Security of 2t-Root Identification and Signatures %f/crypto/avwzd8kosepku740vl2bjxqozrxmd1is.pdf %mee3cf85422d0158f1191ea2ff8975cee %ccrypto %@Rosario Gennaro,Stanisław Jarecki,Hugo Krawczyk,Tal Rabin %*Robust and Efficient Sharing of RSA Functions %f/crypto/ked5rhznn8dqgkwvomfpfcjxqacmulyt.pdf %mb82b2c58eb732485054b1d5df8dfd24d %ccrypto %@Ronald Cramer,Ivan Damgård %*New Generation of Secure and Practical RSA-Based Signatures %f/crypto/i2uurkqkpgyvpaodc0bzxjldtsq5oej4.pdf %m9f821145c72a48c504419a4dfc055ef0 %ccrypto %@Markus Jakobsson,Moti Yung %*Proving Without Knowing: On Oblivious, Agnostic and Blindfolded Provers %f/crypto/84synf2lgkicaovah5utdyspotbl61rj.pdf %mf5bc7a90c2fed15fcdd7fb9e8baf2911 %ccrypto %@Shai Halevi,Silvio Micali %*Practical and Provably-Secure Commitment Schemes from Collision-Free Hashing %f/crypto/2qc9pow3rwrz5fobitdymy64knxu7cak.pdf %m02a7218dec0b269e00ead9ab246c3703 %ccrypto %@Lars R. Knudsen,Willi Meier %*Improved Differential Attacks on RC5 %f/crypto/afkspfehavk5e2qjyxowlu1c7mnm48o6.pdf %md60ebe7c23ce4fd41b36abd35417d694 %ccrypto %@Paul C. van Oorschot,Michael J. Wiener %*Improving Implementable Meet-in-the-Middle Attacks by Orders of Magnitude %f/crypto/t29c1i3axozvwhnwrn4ufdfhcaeqmxrs.pdf %mfae5620a323c3b7a38dce1067f20fab6 %ccrypto %@John Kelsey,Bruce Schneier,David Wagner %*Key-Schedule Cryptanalysis of IDEA, G-DES, GOST, SAFER, and Triple-DES %f/crypto/xjevjpurbwdm0mcso6ichlz3graszak1.pdf %m171e49c0e175f2727d0cb466e4a3b3b0 %ccrypto %@Joe Kilian,Phillip Rogaway %*How to Protect DES Against Exhaustive Key Search %f/crypto/si7dt9vgrlqkkre0juywbcldhomzfpgy.pdf %m80d76b7bbfa9befad4c8bcb321acdd30 %ccrypto %@Ueli M. Maurer,Stefan Wolf %*Diffie-Hellman Oracles %f/crypto/j5hffinrw4dnlqmi8ebxmruboy032kss.pdf %m16e5a7dc17777b641149523784b01718 %ccrypto %@Dan Boneh,Richard J. Lipton %*Algorithms for Black-Box Fields and their Application to Cryptography %f/crypto/rdshcx17tcel4ypjiaemwwzv02tnpbzx.pdf %m20512e3135bcd943bf1db8f68c0ac757 %ccrypto %@Antoon Bosselaers,René Govaerts,Joos Vandewalle %*Fast Hashing on the Pentium %f/crypto/b7iag0txmkdfzlc2gexdmsv3yancozuj.pdf %m9b34636566eb6a6b8cc352acdde2bafe %ccrypto %@Victor Shoup %*On Fast and Provably Secure Message Authentication Based on Universal Hashing %f/crypto/tldj7kivchnxjpxyfs98nequr60kzmbg.pdf %m237e4a6112fc93ec2eaab11b629e1dd7 %ccrypto %@R. J. Hughes,G. G. Luther,G. L. Morgan,C. G. Peterson,C. Simmons %*Quantum Cryptography over Underground Optical Fibers %f/crypto/ppgfbd0jb1hswwjnygrvkdux9nev8lct.pdf %mc0f8741584a0d28a0486629dcffde11d %ccrypto %@Dominic Mayers %*Quantum Key Distribution and String Oblivious Transfer in Noisy Channels %f/crypto/o5ki7herhbuwycmqkfslawpgjoy6umad.pdf %m2d63139024a8272aff7f857ab06dff0b %ccrypto %@James L. Massey,Shirlei Serconek %*Linear Complexity of Periodic Sequences: A General Theory %f/crypto/9iqjni1rzoyn0jtawkrpocxudmetblvu.pdf %m8d1093a9085f3ec7aad4250c6bca71ee %ccrypto %@Paul Camion,Anne Canteaut %*Generalization of Siegenthaler Inequality and Schnorr-Vaudenay Multipermutations %f/crypto/ioelmqg0lnbv1mastzp5k46cows7uzuf.pdf %md9c1cf2ccdb22fff2a1aa91c76dae3cb %ccrypto %@Carlo Blundo,Luiz A. Frota Mattos,Douglas R. Stinson %*Trade-offs Between Communication and Storage in Unconditionally Secure Schemes for Broadcast Encryption and Interactive Key Distribution %f/crypto/m4rtyn2cke8gpimhpq9zdwdvuukojfqt.pdf %m40f9f3af8e2d4ea950bb48de65090053 %ccrypto %@Stefan Droste %*New Results on Visual Cryptography %f/crypto/xwjliolifuedvcgzsrrj7pnb6h4tum25.pdf %ma927c65c246a1ded1c631cb2961c493a %ccrypto %@Bart Preneel,Paul C. van Oorschot %*MDx-MAC and Building Fast MACs from Hash Functions %f/crypto/cfs0euzfarl5xo7sephxvow3pilbguyw.pdf %m1396d937f6cfa2b6e72bccf4dd2d5865 %ccrypto %@Mihir Bellare,Roch Guérin,Phillip Rogaway %*XOR MACs: New Methods for Message Authentication Using Finite Pseudorandom Functions %f/crypto/l8op6cnvsutyzqcerd54kzfwytnghhml.pdf %m441590ed53ca29629626983bd1306902 %ccrypto %@Phillip Rogaway %*Bucket Hashing and its Application to Fast Message Authentication %f/crypto/xozylcs2ybrn0amg9kexluphfptsen4v.pdf %m5db0ebaa75e349beb5052d1aa8bd2438 %ccrypto %@Richard Schroeppel,Hilarie Orman,Sean O’Malley,Oliver Spatscheck %*Fast Key Exchange with Elliptic Curve Systems %f/crypto/sz4slrw5mrjb8piwojc90zfn7v1niyue.pdf %m86d780e7fcb940b29d3b9f7bd54cfe15 %ccrypto %@Philippe Béguin,Jean-Jacques Quisquater %*Fast Server-Aided RSA Signatures Secure Against Active Attacks %f/crypto/xedjcbszygljhmhygf5tnmwbwe8p0roi.pdf %m4d0043aec945b1abac4480ab985ce797 %ccrypto %@Chae Hoon Lim,Pil Joong Lee %*Security and Performance of Server-Aided RSA Computation Protocols %f/crypto/ljw2my71nphdz65c3adks8trhse4tifg.pdf %m598b8a2f3cc96b683be089c7f50caec9 %ccrypto %@Shai Halevi %*Efficient Commitment Schemes with Bounded Sender and Unbounded Receiver %f/crypto/veqechr4ls0p3pkn6iz1ifrqgboamb85.pdf %m04cafbb2903dce19a5d606d9f2a76418 %ccrypto %@Donald Beaver %*Precomputing Oblivious Transfer %f/crypto/4tkyi85wgwmn1qx9vrs27bpoqaycrtmi.pdf %m2d7788d911c4e61744ae2a1738395bc6 %ccrypto %@Claude Crépeau,Jeroen van de Graaf,Alain Tapp %*Committed Oblivious Transfer and Private Multi-Party Computation %f/crypto/kn68oyxlhpsr1olc0urmcyvvdqwqwag4.pdf %ma4fae032f6f099fa8bb7b51a5fe80f19 %ccrypto %@Dominic Mayers %*On the Security of the Quantum Oblivious Transfer and Key Distribution Protocols %f/crypto/xsth156kcajcikh7udq2nawuyz0meoig.pdf %m7ef7dca4030453136664222bd91b3345 %ccrypto %@Thorsten Theobald %*How to Break Shamir’s Asymmetric Basis %f/crypto/oy1l4gcwju9uslhdnvfaq75rdvazbgyr.pdf %me11b975c697fe0fed352969602dcdc97 %ccrypto %@Sang-Joon Park,Sang-Jin Lee,Seung-Cheol Goh %*On the Security of the Gollmann Cascades %f/crypto/5jd1hzyxfkggvultznq49mbt7abspcwe.pdf %mca7c4b268b39fdc94eb5059d31a12906 %ccrypto %@Kazuo Ohta,Shiho Moriai,Kazumaro Aoki %*Improving the Search Algorithm for the Best Linear Expression %f/crypto/nsicdsitu1v9jzchhvdk5jgzr6pxafpb.pdf %m67f51557934d684c893266f667d39c7f %ccrypto %@Burton S. Kaliski,Yiqun Lisa Yin %*On Differential and Linear Cryptanalysis of the RC5 Encryption Algorithm %f/crypto/8zg54fdqakjocvxjrehalvhtg2upyxml.pdf %m9b87f4dfc1d45e1ccbc5780a9e07d50b %ccrypto %@Silvio Micali,Ray Sidney %*A Simple Method for Generating and Sharing Pseudo-Random Functions, with Applications to Clipper-like Key Escrow Systems %f/crypto/rspyqyoqnvmae5t6c9gpihg8bfzzsx0h.pdf %m44dffa75ec2f3d8bc5acf278b97e1235 %ccrypto %@Arjen K. Lenstra,Peter Winkler,Yacov Yacobi %*A Key Escrow System with Warrant Bounds %f/crypto/yogbqmtdqxf6idv8hfzjgba2rn5wwoue.pdf %m6a1a0ab977f56f5ef223ba0d0f615ce1 %ccrypto %@Joe Kilian,Tom Leighton %*Fair Cryptosystems, Revisited %f/crypto/yhqcfrt4tzip6zg0julxh5macebsdmfo.pdf %m021c8292d488f05a386598f4ac9e97c6 %ccrypto %@Yair Frankel,Moti Yung %*Escrow Encryption Systems Visited: Attacks, Analysis and Designs %f/crypto/yxa651jsfpvtjlg7wpuyqbmvhiwtsmor.pdf %m2549c204cb18cf7c7e7acecbd52020ad %ccrypto %@Ross Anderson,Roger Needham %*Robustness Principles for Public Key Protocols %f/crypto/acdqnipl98reskod5gbwuphkef1tqmgo.pdf %m88101f467f1f4ea722a2266f56cf7d93 %ccrypto %@Jacques Patarin %*Cryptanalysis of the Matsumoto and Imai Public Key Scheme of Eurocrypt’88 %f/crypto/oycd0xl2hprhzb6jpzeamt7kslma5r4w.pdf %m75d510f6abe9987f08713e86d4f10340 %ccrypto %@Andrew Klapper,Mark Goresky %*Cryptanalysis Based on 2-Adic Rational Approximation %f/crypto/pmlrexlypjsvx7bcq98ynkth6uoszkvn.pdf %m42e5cc0d6a40743b87c433275fcd0cf0 %ccrypto %@Lars R. Knudsen %*A Key-schedule Weakness in SAFER K-64 %f/crypto/crwz0qtmauabk9ki2e1lbhhtufpnfy6y.pdf %m5492af0361c38b3d228cafd18b9b62c3 %ccrypto %@Yair Frankel,Moti Yung %*Cryptanalysis of the Immunized LL Public Key Systems %f/crypto/wxpahv1k3tsdcymt2jdchak8zbgsonrn.pdf %m7d211ed38bdc845679c06d6416dcd543 %ccrypto %@Ronald Cramer,Ivan Damgård %*Secure Signature Schemes based on Interactive Protocols %f/crypto/d0pgcqrmtqgvlojiaouyxkspkvwwzabf.pdf %m4633ef29312dfb3a85a4599bfae00ec7 %ccrypto %@Joe Kilian %*Improved Efficient Arguments %f/crypto/wqhjznsfvdibxhz081jcc9qbre5yxund.pdf %mc94038134d96b0712198139497dc8665 %ccrypto %@Ivan Damgård,Oded Goldreich,Tatsuaki Okamoto,Avi Wigderson %*Honest Verifier vs Dishonest Verifier in Public Coin Zero-Knowledge Proofs %f/crypto/pbcszkg035j8yzgmijyaludt4x6wveal.pdf %m0ae5cb0bd67b4b2a050778f7ac164373 %ccrypto %@Amir Herzberg,Stanisław Jarecki,Hugo Krawczyk,Moti Yung %*Proactive Secret Sharing Or: How to Cope With Perpetual Leakage %f/crypto/idjgzrrpvegpuh37fjo89cwznlnsfc4q.pdf %m5d61956921b3f0c714f897ead5d2afc7 %ccrypto %@Amos Beimel,Benny Chor %*Secret Sharing with Public Reconstruction %f/crypto/7olaxhmgufylvdnmucbftskzpq36r9ik.pdf %m36f934ce463e51db241c8d59fcb0de43 %ccrypto %@G. R. Blakley,G. A. Kabatianski %*On General Perfect Secret Sharing Schemes %f/crypto/hcmjsr8k6eptf9nyebiouhkcf5pgadz4.pdf %m409f364374f9c2494988b66eb757f5cf %ccrypto %@Bruce Dodson,Arjen K. Lenstra %*NFS with Four Large Primes: An Explosive Experiment %f/crypto/rftxj3wa9c1nsiasbvqnmlzpgkf6qdm4.pdf %mbffe7be2a550682bca6c45e087ed22a9 %ccrypto %@Daniel Bleichenbacher,Wieb Bosma,Arjen K. Lenstra %*Some Remarks on Lucas-Based Cryptosystems %f/crypto/gkntotqxxsrmw60icwmrjlp59dphvhzj.pdf %mef58f009073ba9e4cb6dcf258446dd01 %ccrypto %@Susan K. Langford %*Threshold DSS Signatures without a Trusted Party %f/crypto/ak3muwipyl92dhr1mne4izlot0rfgcbs.pdf %m8e76148b2c5ad0c07e29cb0398fda2dc %ccrypto %@Kaoru Kurosawa,Satoshi Obana,Wakaha Ogata %*t-Cheater Identifiable (k, n) Threshold Secret Sharing Schemes %f/crypto/drlieobvxswgcyj0wmp5a9fi3aenkr16.pdf %m7ece653d565bc68d0ff24e4a73d6db7e %ccrypto %@Dan Boneh,Richard J. Lipton %*Quantum Cryptanalysis of Hidden Linear Functions %f/crypto/cwlu0fqmreh9xf8sn47xv3pbkzivyek1.pdf %m5498b67987d8a88d93e0650ccd06618b %ccrypto %@Tatsuaki Okamoto %*An Efficient Divisible Electronic Cash Scheme %f/crypto/yb6gnw9ug8viyhp2kp5itcodrqsdmauc.pdf %mfc9c7914f5f31852fe1d8ca1448a5ffe %ccrypto %@Dan Boneh,James Shaw %*Collusion-Secure Fingerprinting for Digital Data %f/crypto/ia5tkr42vmdwyjchvqn1xitfcug6xzrs.pdf %m5e9624dcac30e1795f994ca3fdee31e5 %ccrypto %@Mitsuru Matsui %*The First Experimental Cryptanalysis of the Data Encryption Standard %f/crypto/jaym0rkxexyre4hp6vu3i85qotfd1ozl.pdf %mb0248ac236e4bb962ac3d1592d226287 %ccrypto %@Kazuo Ohta,Kazumaro Aoki %*Linear Cryptanalysis of the Fast Data Encipherment Algorithm %f/crypto/nsi5fwe1zufcq6ctkyyvlbh9rt8j2gw0.pdf %m8acc2f24d45b529d90df386aa1b56993 %ccrypto %@Susan K. Langford,Martin E. Hellman %*Differential-Linear Cryptanalysis %f/crypto/uelfpatbe0y3stuckjwqnqr27kcomdbm.pdf %m050b5ba689eb3981de74cc12f3818d02 %ccrypto %@Burton S. Kaliski,M. J. B. Robshaw %*Linear Cryptanalysis Using Multiple Approximations %f/crypto/ypn3tgigbscmo82pycvd4nqlkel5h0o6.pdf %m37e2ee4f71874b08ca3f6aff721e9eb7 %ccrypto %@Jean-Pierre Tillich,Gilles Zémor %*Hashing with SL2 %f/crypto/iilynrosb9hf1e35k6zaltro7wzpsv2j.pdf %mea1dc16b7e609a082bfe1d49e50442fd %ccrypto %@Jinhui Chao,Kazuo Tanada,Shigeo Tsujii %*Design of Elliptic Curves with Controllable Lower Boundary of Extension Degree for Reduction Attacks %f/crypto/c1k8jgvum5cztr9nfgkajbyyblhiowux.pdf %md972a09a67ee5f7f7ec46b5ff2718c47 %ccrypto %@Ingrid Biehl,Johannes Buchmann,Christoph Thiel %*Cryptographic Protocols Based on Discrete Logarithms in Real-quadratic Orders %f/crypto/pkghm8q9bomasrz21djxyz0f6uuthqpn.pdf %mf5d2f15144d0a3b19c9a756927e6a4f1 %ccrypto %@Tatsuaki Okamoto %*Designated Confirmer Signatures and Public-Key Encryption are Equivalent %f/crypto/kj4c6dpg0ofudw5yyzgbaivcklphv9jx.pdf %me3b77f85c52545aa0195c0efb24b516d %ccrypto %@Daniel Bleichenbacher,Ueli M. Maurer %*Directed Acyclic Graphs, One-way Functions and Digital Signatures %f/crypto/he42z10wljxwtd86mbqujffk7syatvcc.pdf %m2733b190d9c38fdce0446e1ad37f805a %ccrypto %@Olivier Delos,Jean-Jacques Quisquater %*An Identity-Based Signature Scheme with Bounded Life-Span %f/crypto/i8nosoitpukaqjzcc7wkyg91062xgqrn.pdf %mf4e4644f4cc1a5df9659dad3a7a4a44e %ccrypto %@Chae Hoon Lim,Pil Joong Lee %*More Flexible Exponentiation with Precomputation %f/crypto/6hqujjyfymc5etlaz4xowe73kiaiwvbv.pdf %m437537faa911896b40982d164ac4fce3 %ccrypto %@Tamás Horváth,Spyros S. Magliveras,Tran van Trung %*A Parallel Permutation Multiplier for a PGM Crypto-chip %f/crypto/xdad8vzken7lig3melyvfsgiqhsut0um.pdf %md5b6aff1f36f953fc7beeaa459b9ddfb %ccrypto %@Don Davis,Ross Ihaka,Philip Fenstermacher %*Cryptographic Randomness from Air Turbulence in Disk Drives %f/crypto/wwvyhahk10olgveu4ng9ydxbpf3iknsz.pdf %ma70009eb91e1e69c039f5a36d89ab9c8 %ccrypto %@Christian Gehrmann %*Cryptanalysis of the Gemmell and Naor Multiround Authentication Protocol %f/crypto/jvhzvytqia5mzgwuoekax4gi21c3o9hs.pdf %m06d062e0381655aad1255c88ed81fb7d %ccrypto %@Hugo Krawczyk %*LFSR-based Hashing and Authentication %f/crypto/szbit6g2sc01eekp7jtxlwfdagdlhyvb.pdf %m02f886ff950bba01f59c93e58e27762c %ccrypto %@Kaoru Kurosawa %*New Bound on Authentication Code with Arbitration %f/crypto/pbryq97ltj0lsfycw1rtkqggk25nsw6u.pdf %maca136fd3f54502bef8476c99afc92f3 %ccrypto %@Carlo Blundo,Alfredo De Santis,Giovanni Di Crescenzo,Antonio Giorgio Gaggia,Ugo Vaccaro %*Multi-Secret Sharing Schemes %f/crypto/ah7yt5s98u3ojcbpvxzlcysgwzv0otkm.pdf %m2a4fccfc8971b99a84919c46fa1696fb %ccrypto %@Jacques Stern %*Designing Identification Schemes with Keys of Short Size %f/crypto/defahbio2nhlmqnpgcwf5kzvubmiaqy1.pdf %m3810c9ea5cfe67fe007376782f5ebad0 %ccrypto %@Ronald Cramer,Ivan Damgård,Berry Schoenmakers %*Proofs of Partial Knowledge and Simplified Design of Witness Hiding Protocols %f/crypto/xnpfjwqnmubsv0dzwaybjoqo4cpe92s7.pdf %med0b416b2188bec46ced7572f28b1752 %ccrypto %@Toshiya Itoh,Yuji Ohta,Hiroki Shizuya %*Language Dependent Secure Bit Commitment %f/crypto/kg5tauyxrhg2ehxm7vpneiyv1zwqljdb.pdf %m474b7135708ddc84b1d31e4274b70418 %ccrypto %@Marc Girault,Jacques Stern %*On the length of cryptographic hash-values used in identification schemes %f/crypto/9q427wamoz6vgvr0kknpbxjdhytjewyp.pdf %meda0e7d6703cb1e231491a2b4cd2a6b3 %ccrypto %@Mihir Bellare,Oded Goldreich,Shafi Goldwasser %*Incremental Cryptography: The Case of Hashing and Signing %f/crypto/w5cy2qn4uzlhzsps3lgfkkrxumcgb8xe.pdf %mf5d2f628471137ac0005938a40314e80 %ccrypto %@Cynthia Dwork,Moni Naor %*An Efficient Existentially Unforgeable Signature Scheme and its Applications %f/crypto/h2apnwhxazju38b9cezsjodigf16nfyr.pdf %m3d7a140ca82000f49cfe3da78bb10694 %ccrypto %@Jürgen Bierbrauer,K. Gopalakrishnan,D. R. Stinson %*Bounds for Resilient Functions and Orthogonal Arrays %f/crypto/uqbfnuwhxlhiygrjc4evdasntvcwbqkr.pdf %mf251beb8f226bbec28e3892d2ee66ec1 %ccrypto %@Benny Chor,Amos Fiat,Moni Naor %*Tracing Traitors %f/crypto/rjhsduzg6yfau3cmomrw0ntbakqbz4vk.pdf %mcdc4f1676d897c958b823cefdb7fe13e %ccrypto %@Ueli M. Maurer %*Towards the Equivalence of Breaking the Diffie-Hellman Protocol and Computing Discrete Logarithms %f/crypto/wzwhdhr9aeeli5pfqvguxd3t8cjbmgx2.pdf %m8f6c1a2ceacf42b86f0af38aed30dbd0 %ccrypto %@Preda Mihailescu %*Fast Generation of Provable Primes Using Search in Arithmetic Progressions %f/crypto/birpqanxi3qg029zuvkjlvw6on5ctk8o.pdf %md3721a35cf6e991553fd1dc12c78ed22 %ccrypto %@Don Coppersmith %*Attack on the Cryptographic Scheme NIKS-TAS %f/crypto/jjugqncfiiucd7vo0sy5nwmlhkw6qszp.pdf %mdb090cef9ce1d4b0348e0e3adf0311e2 %ccrypto %@Mike Burmester %*On the Risk of Opening Distributed Keys %f/crypto/8anbivfuyuprclqnw63r1ek7ld24qgt0.pdf %m4b90ba10ed94aadf6bf196a7927ab933 %ccrypto %@Th. Beth,D. E. Lazic,A. Mathias %*Cryptanalysis of Cryptosystems based on Remote Chaos Replication %f/crypto/jkz7gwhjtlcn42alxuees0for1piuobw.pdf %mfa90c893933df8625a45cabe18df2fb9 %ccrypto %@James L. Massey,Shirlei Serconek %*A Fourier Transform Approach to the Linear Complexity of Nonlinearly Filtered Sequences %f/crypto/a7ocj8kj5q6ha2dvtnh3cnlx1zeybipu.pdf %m2e903199ef6d0d7f66f6ecb0fd368622 %ccrypto %@Mihir Bellare,Joe Kilian,Phillip Rogaway %*The Security of Cipher Block Chaining %f/crypto/hkio6j5pwfzekqfdou0c4qjv19utya8h.pdf %m37a8235054117c240629915045bf28e7 %ccrypto %@Henri Gilbert,Pascal Chauvaud %*A Chosen Plaintext Attack of the 16-round Khufu Cryptosystem %f/crypto/1sfdyxtkbcsnpewtdf67qw5eruplzajq.pdf %m6f91425fb4ed9ce316e0b94e0aaa5ff0 %ccrypto %@Yukiyasu Tsunoo,Eiji Okamoto,Tomohiko Uyematsu %*Ciphertext Only Attack for One-way function of the MAP using One Ciphertext %f/crypto/i0fvuraujstos3wynod61mmfvqhj5c94.pdf %m20ecbf5ee478f99424956585fe62a7a1 %ccrypto %@Jennifer Seberry,Xian-Mo Zhang,Yuliang Zheng %*Pitfalls in Designing Substitution Boxes %f/crypto/egupwaqxoomrljfkkp7bm2hyvqlrt4bz.pdf %m68ec891a07fecc3cb60af6b39860bf51 %ccrypto %@Eyal Kushilevitz,Adi Rosén %*A Randomness-Rounds Tradeoff in Private Computation %f/crypto/hp87m53cxe9zokc2inastybdvaozgwld.pdf %mcec09dbd7774b5cc7c23f8ce2b238120 %ccrypto %@Kazue Sako,Joe Kilian %*Secure Voting Using Partially Compatible Homomorphisms %f/crypto/duawpowuqsxhq81gtf3rhixtmk95azj4.pdf %mcc9607df5a7726ec02c29ea9f0e9dfb5 %ccrypto %@Ran Canetti,Amir Herzberg %*Maintaining Security in the Presence of Transient Faults %f/crypto/yqybmh5nkaxl0gavzxkdeqgfwpjij9so.pdf %mab64eaad0dda4bf723bd0a6776eeeaf9 %ccrypto %@Adi Shamir %*Efficient Signature Schemes Based on Birational Permutations %f/crypto/nsvxu9jgc16lehvdnzttrm2f03rkiefy.pdf %mffe66680950b1c1f450c0ef5ff897bd6 %ccrypto %@Jacques Stern %*A new identification scheme based on syndrome decoding %f/crypto/3wtpuzuv7nvi80gmjfhrdshmtrsaclx1.pdf %m4389e5d4ee2e37fb53b755d1b25767ee %ccrypto %@Don Coppersmith,Hugo Krawczyk,Yishay Mansour %*The Shrinking Generator %f/crypto/hhtclrxdzl7iemcpamffwyr1nqt3bgo6.pdf %m803553518bba0e3c13aeb11bd4814858 %ccrypto %@Richard Taylor %*An Integrity Check Value Algorithm for Stream Ciphers %f/crypto/pknd8egdzqmjiotyfqfnzsuuxby57l06.pdf %maa9d38750e739386b4b6e6d7fc8ba238 %ccrypto %@Jennifer Seberry,Xian-Mo Zhang,Yuliang Zheng %*Nonlinearly Balanced Boolean Functions and Their Propagation Characteristics %f/crypto/ids1vyhj0zeif4eggj9pl6qzounxbycs.pdf %m733bf3b6401da0d71664c3f70f38ed22 %ccrypto %@Toshiya Itoh,Masafumi Hoshi,Shigeo Tsujii %*A Low Communication Competitive Interactive Proof System for Promised Quadratic Residuosity %f/crypto/d8bakg4fgkxhhrlfz6du70m3rxj1yzlq.pdf %md5330f4cfd50ace0946b9c8df366c87c %ccrypto %@A. De Santis,G. Di Crescenzo,G. Persiano %*Secret Sharing and Perfect Zero Knowledge %f/crypto/nxwpiuoea9ufbmg67pycklldjztssrqe.pdf %m028e8b035ca2ca8bf92eee3258476ca2 %ccrypto %@Yonatan Aumann,Uriel Feige %*One Message Proof Systems with Known Space Verifiers %f/crypto/kzidlmd9q1b2yv0lo6w3ppgecxcua7is.pdf %m09829889f1de6b9f65e63209376c442c %ccrypto %@Ivan B. Damgård %*Interactive Hashing can Simplify Zero-Knowledge Protocol Design Without Computational Assumptions %f/crypto/ao7cmwykqo0fihnqssju46ezl1invck2.pdf %m19a2d5f748facaad7f4439516662f085 %ccrypto %@C. Blundo,A. Cresti,A. De Santis,U. Vaccaro %*Fully Dynamic Secret Sharing Schemes %f/crypto/q0riy25jkg6tmrxl9q1apuk7v83avhzp.pdf %ma6336a8b19b8058e1c0cc6a85c6e1077 %ccrypto %@Wen-Ai Jackson,Keith M. Martin,Christine M. O’Keefe %*Multisecret Threshold Schemes %f/crypto/7bvgo9sixej1yrswzk2ifn0op6dmylvg.pdf %mc74327b121daa34b0fc9c26bf410967c %ccrypto %@Hugo Krawczyk %*Secret Sharing Made Short %f/crypto/vt9xseyuzxqcidzlw4thdwcivhmnbpra.pdf %m4c9ae08cd3abf00b313a52f230a74e58 %ccrypto %@Leonard M. Adleman,Jonathan DeMarrais %*A Subexponential Algorithm for Discrete Logarithms over All Finite Fields %f/crypto/j9bnif782rhdoeqg1xapym3mzupjywnv.pdf %m296997fca33ad13e5b551e261e142331 %ccrypto %@J. Buchmann,J. Loho,J. Zayer %*An implementation of the general number field sieve %f/crypto/0he5ufo1yxjdua3nmxzgitepkzvpiccw.pdf %mcc7f5cdbf49f754fa81630ff2d78b735 %ccrypto %@T. Denny,B. Dodson,A. K. Lenstra,M. S. Manasse %*On the factorization of RSA-120 %f/crypto/okehpge4ilqmciuzvnwdr1ygbj9dth8s.pdf %m018cd4502ac9a68fccbeb27bf4255ece %ccrypto %@Antoon Bosselaers,René Govaerts,Joos Vandewalle %*Comparison of three modular reduction functions %f/crypto/umt59jtspcl2xue3qyf7hqsdwazpcod6.pdf %m263e1e4b77e1fd92b1175fe848bacd3b %ccrypto %@Ishai Ben-Aroya,Eli Biham %*Differential Cryptanalysis of Lucifer %f/crypto/uodw6egbm3sllv05jdxkg7i1tpbp4uqz.pdf %mf02c732bfeaf9c8baf6a8a9d8bc17b5b %ccrypto %@Kazuo Ohta,Mitsuru Matsui %*Differential Attack on Message Authentication Codes %f/crypto/eca9g70eu5xfljfohprxhdmzorkncwbi.pdf %m608788c1fa469a0be19e9d8f67be4f27 %ccrypto %@Bart Preneel,Marnix Nuttin,Vincent Rijmen,Johan Buelens %*Cryptanalysis of the CFB mode of the DES with a reduced number of rounds %f/crypto/dsgt9uxy3ahiy6porfz724kq5ubf0han.pdf %m9334a40b79a7c1199fa73d9e1d68db7f %ccrypto %@Joan Daemen,René Govaerts,Joos Vandewalle %*Weak Keys for IDEA %f/crypto/8mtjwq2jmophz1yxeubkbtxuigga0kdi.pdf %mf9d220fbf795790eee4c973587a95436 %ccrypto %@Mihir Bellare,Phillip Rogaway %*Entity Authentication and Key Distribution %f/crypto/note6li19djfgmsrq7qhafzl3z50iuxs.pdf %mc39342762336a10998c40e5243197079 %ccrypto %@Ivan B. Damgård,Torben P. Pedersen,Birgit Pfitzmann %*On the Existence of Statistically Hiding Bit Commitment Schemes and Fail-Stop Signatures %f/crypto/plspfwdnhcacskorizjd4fxmm5klwqgv.pdf %mac40df2d84ec98b212df9f881a5bce3a %ccrypto %@Matthew Franklin,Stuart Haber %*Joint Encryption and Message-Efficient Secure Computation %f/crypto/3itb4hekxxbjsno1ahmdau2jnqrcy9ft.pdf %mf4a327e9fd2a3bfd55ba74a2b13ca82f %ccrypto %@Avrim Blum,Merrick Furst,Michael Kearns,Richard J. Lipton %*Cryptographic Primitives Based on Hard Learning Problems %f/crypto/4y8kzfvxpxg2uoaealdfuqsnyecikrdh.pdf %m953bf9f20407ed6d48a870b985241e6e %ccrypto %@Niels Ferguson %*Extensions of Single-term Coins %f/crypto/4ebfrq8bkstd0szpojunwoml1gn9vrcx.pdf %m5de7cfe3161d12b0b049f64b844ba234 %ccrypto %@Stefan Brands %*Untraceable Off-line Cash in Wallet with Observers %f/crypto/gadhdbqnjiwxzow6kqjecvubkgu8otn0.pdf %m8bfe8bd632f2b5ce789485e385a8a194 %ccrypto %@Claude Crépeau,Joe Kilian %*Discreet Solitary Games %f/crypto/6erokvkfxpi4znaubgc9lbhwtg1hyoey.pdf %m19dd388b02828bf7ba6cb1fc2f3a2dea %ccrypto %@Jürgen Bierbrauer,Thomas Johansson,Gregory Kabatianskii,Ben Smeets %*On Families of Hash Functions via Geometric Codes and Concatenation %f/crypto/7qwteuy2vrafzwb31d0zccpu8xxesgab.pdf %maa6ff53af9e63d185dd34b6cf2787861 %ccrypto %@Thomas Johansson %*On the Construction of Perfect Authentication Codes that Permit Arbitration %f/crypto/n1tdenziogqiyfdjmekxsmhj538tcwc0.pdf %m909abf0830bf560888e345f593db7130 %ccrypto %@Pete Gemmell,Moni Naor %*Codes for Interactive Authentication %f/crypto/r6mrljzy5jdhfye9nx8xbivlq2uqgcch.pdf %m880a497ec39c5ddfbe36f27709e0f313 %ccrypto %@Bart Preneel,René Govaerts,Joos Vandewalle %*Hash functions based on block ciphers: a synthetic approach %f/crypto/hxmhjo2vlgtwkimu3pkiwt4s09qpcr5b.pdf %m74381b8f344c372f312bec4f7b021341 %ccrypto %@Walter Hohl,Xuejia Lai,Thomas Meier,Christian Waldvogel %*Security of Iterated Hash Functions Based on Block Ciphers %f/crypto/vge9qra6bixzywungft3uzat71hoekcm.pdf %mff8900a0dc77e077836dc765dd8e556c %ccrypto %@Jaques Patarin,Pascal Chauvaud %*Improved Algorithms for the Permuted Kernel Problem %f/crypto/6vfghbkyxqbtpoici1k5omlafujpeg9l.pdf %m9022a25192fb293dee097b57d2f9c958 %ccrypto %@Luke O’Connor %*On the Distribution of Characteristics in Composite Permutations %f/crypto/atekovhf7jjvpiksoxql0qdcmbn5rc9x.pdf %m5663a63f38195bf3dd5dde8a68bd5260 %ccrypto %@Chuan-Ming Li,Tzonelih Hwang,Narn-Yih Lee %*Remark on the Threshold RSA Signature Scheme %f/crypto/9duai1fehlsawtrxzicd8f2gkbqbmvjz.pdf %m51f41ef52ef594f74b114f662978d39b %ccrypto %@Chae Hoon Lim,Pil Joong Lee %*Another Method for Attaining Security Against Adaptively Chosen Ciphertext Attacks %f/crypto/tdcviyuk0a6mbbno5wurlsrnqef83tac.pdf %mb9f94f574b1195d47d962732f8999bbb %ccrypto %@Don Coppersmith,Jacques Stern,Serge Vaudenay %*Attacks on the Birational Permutation Signature Schemes %f/crypto/rynqj1tvihbh4mu6tp3bwmcwiauddvqe.pdf %md6edfd32e2b8f06fb140bbb0f2331ef7 %ccrypto %@Amos Beimel,Benny Chor %*Interaction in Key Distribution Schemes %f/crypto/kjdeacxiq8pp0f3zyms1su4qdau6tcrv.pdf %ma6e8d0c6fd217251451b8f09c09f5b5b %ccrypto %@Tom Leighton,Silvio Micali %*Secret-Key Agreement without Public-Key Cryptography %f/crypto/fs2qblqdu4a01iwgpfrvzn5r3pik6mje.pdf %me1c44ea59d2b843cabc287b36dfc5a00 %ccrypto %@Amos Fiat,Moni Naor %*Broadcast Encryption %f/crypto/b6wkympwedgzhrymhdgtvispfbjc9fl2.pdf %me47c22d09828b211a30ccb0eb39010bd %ccrypto %@Jurjen N. E. Bos,David Chaum %*Provably Unforgeable Signatures %f/crypto/ajsyoqftejqtvmdguxioye2xs5mrd7nr.pdf %m6d4b6786ab07e8c4999254a2b60c58f2 %ccrypto %@Eugène van Heijst,Torben Pryds Pedersen,Birgit Pfitzmann %*New Constructions of Fail-Stop Signatures and Lower Bounds %f/crypto/surkeqhcimxgsyuazdwivfzwpe0a3jjg.pdf %m7f76576228dcc2811a8dbf7da8fb1dc4 %ccrypto %@Tatsuaki Okamoto %*Provably Secure and Practical Identification Schemes and Corresponding Signature Schemes %f/crypto/gfqeadfv9tsxl5un1yjahqw6roc0hmb3.pdf %m115c8fead0874cef1057ab6ced12da04 %ccrypto %@Tatsuaki Okamoto,Atsushi Fujioka,Eiichiro Fujisaki %*An Efficient Digital Signature Scheme Based on an Elliptic Curve over the Ring Zn %f/crypto/qtdnik5cfgsxmvwsh6dz0jur21izwymb.pdf %m1d37216ff01d25f4eaedb26cdb2fc528 %ccrypto %@Daniel M. Gordon %*Designing and Detecting Trapdoors for Discrete Log Cryptosystems %f/crypto/es0pdozfp2qkxsunbhg8gijtaiwx5jec.pdf %md9d48fe4b9de8470ab7ffb19bc66183e %ccrypto %@Miles E. Smid,Dennis K. Branstad %*Response to Comments on the NIST Proposed Digital Signature Standard %f/crypto/a6zjpkotxe2ky3wclp9bvz0mmdbi1ave.pdf %me169664e11076699bc9521dfe63daa8b %ccrypto %@David Chaum,Torben Pryds Pedersen %*Wallet Databases with Observers %f/crypto/uliefgk65huoawsxzp7nqktiaczd4v2o.pdf %ma84831e5bf3d6cf069726434e120e1e9 %ccrypto %@Rafael Hirschfeld %*Making Electronic Refunds Safer %f/crypto/jt9zyy4siqzbmw02cdvtxprsjlu7me1b.pdf %m9f42a99a5365a96fa52ac111192dca32 %ccrypto %@Silvio Micali %*Fair Public-Key Cryptosystems %f/crypto/zothrdqbaesiqpvkxfgbemngwhvfuxcu.pdf %m0219c9812367261c7bfcd700b65eadd3 %ccrypto %@Cynthia Dwork,Moni Naor %*Pricing via Processing or Combatting Junk Mail %f/crypto/pgsjyfaoorqxhpjw9dn4mbqiyhst2cx8.pdf %m639281d417391972cd57a417e29787e5 %ccrypto %@C. Blundo,A. De Santis,L. Gargano,U. Vaccaro %*On the Information Rate of Secret Sharing Schemes %f/crypto/9gqkx4vn1jzfyudoemo0p8ildnrfa3uj.pdf %mc71253b5bd59939d9a0f66ee18db285c %ccrypto %@D. R. Stinson %*New General Lower Bounds on the Information Rate of Secret Sharing Schemes %f/crypto/wdik9ugvx8oqcztmdpephx1yy27nq3ul.pdf %m37ee72de100ceef2cb09864ddbb5e058 %ccrypto %@Amos Beimel,Benny Chor %*Universally Ideal Secret Sharing Schemes %f/crypto/3jcgrf7ikkgl0dabmuuqyw4nehtiawyn.pdf %md51610246c028e263003ed52648923f1 %ccrypto %@Moni Naor,Rafail Ostrovsky,Ramarathnam Venkatesan,Moti Yung %*Perfect Zero-Knowledge Arguments for NP Can Be Based on General Complexity Assumptions %f/crypto/my6qt2quovjaxicxpwsdow31eg5uam0g.pdf %m10a380f68961c3febcd3726306a567ab %ccrypto %@Cynthia Dwork,Uri Feige,Joe Kilian,Moni Naor,Muli Safra %*Low communication 2-prover zero-knowledge proofs for NP %f/crypto/kd5kup4cxhq1ozegie9jom8wbxby2np3.pdf %m683de6232224ece2b632f401c801e32c %ccrypto %@Shafi Goldwasser,Rafail Ostrovsky %*Invariant Signatures and Non-Interactive Zero-Knowledge Proofs are Equivalent %f/crypto/c8vwfr0vrutczxuanhkg2gopnipxsi3j.pdf %md2bd93830ee9b07794bcc89c42235873 %ccrypto %@Kouichi Sakurai,Toshiya Itoh %*On the Discrepancy between Serial and Parallel of Zero-Knowledge Protocols %f/crypto/ru9bys8jlqz3kdvwt5hglonbzjotyaf6.pdf %medb391944bde3672d63fe05ef0a9f142 %ccrypto %@M. Sivabalan,S. E. Tavares,L. E. Peppard %*On the Design of SP Networks from an Information Theoretic Point of View %f/crypto/dxngkw5t4qx6os0nilvwpqub3yruehek.pdf %m1815d7b9e6bdd644974b2aa2ff77194f %ccrypto %@C. Carlet %*Partially-bent functions %f/crypto/vb7cmxwk4o1nfor2letyiu5ednu9shwi.pdf %m531af842df1daa68d8348840b833a65a %ccrypto %@Yuliang Zheng,Jennifer Seberry %*Practical Approaches to Attaining Security against Adaptively Chosen Ciphertext Attacks %f/crypto/u319cossnikikeubbvpj2dwq4fxtj5nv.pdf %m866f8cc58d4fac418e3c34bededc3ff4 %ccrypto %@Thierry Baritaud,Mireille Campana,Pascal Chauvaud,Henri Gilbert %*On the Security of the Permuted Kernel Identification Scheme %f/crypto/yjo58bnlkramzpodbwegjr6fzcvvu24q.pdf %mdfe83f1bc1eabb2f6bb8e7782704c85c %ccrypto %@Daniel M. Gordon,Kevin S. McCurley %*Massively Parallel Computation of Discrete Logarithms %f/crypto/0gtcqscbuoxgfrjblzhrpiyymnufzldj.pdf %ma403f0b8ef4cda1b195f82ce2a9e491f %ccrypto %@René Peralta %*A Quadratic Sieve on the n-Dimensional Cube %f/crypto/cfvnvyjn5oowb7q9qrlc0xisuzdepa3w.pdf %m0b90b62b7aba288c0bb07bdbd0148d9a %ccrypto %@Willi Meier,Othmar Staffelbach %*Efficient Multiplication on Certain Nonsupersingular Elliptic Curves %f/crypto/wgranuqpvlorf9tf6lcoxj3kjpim4gve.pdf %mce61b7182b13181fe51c365dcef58566 %ccrypto %@Kenji Koyama,Yukio Tsuruoka %*Speeding up Elliptic Cryptosystems by Using a Signed Binary Window Method %f/crypto/mqtzoishvu0bn9oexevj2ghf4pydpk58.pdf %mb5bf5bfb1418132f9486115063371b2f %ccrypto %@Jørgen Brandt,Ivan Damgård %*On Generation of Probable Primes by Incremental Search %f/crypto/uboxlho78ucnfdrmp3sh1waceypgztaw.pdf %mbfac9d98e983e1d5a8531f9035f4b1c3 %ccrypto %@Michael Fellows,Neal Koblitz %*Kid Krypto %f/crypto/8vuhwawrajzkuhgtscmnndtxo53ij9qv.pdf %m8e8d07cc051d8cd8a680678154bc7bc0 %ccrypto %@Mihir Bellare,Oded Goldreich %*On Defining Proofs of Knowledge %f/crypto/bjmdlvn23wvqjtepfdbhqkkyziswcxco.pdf %m918b906abbb911fab40b8faf565aa1e9 %ccrypto %@Amir Herzberg,Michael Luby %*Public Randomness in Cryptography %f/crypto/umjf4bcoszrd05suwlzw3pe6nvlx2h8k.pdf %ma1bef95b8c881537ab5cd24903e74aad %ccrypto %@Alexander Russell %*Necessary and Sufficient Conditions for Collision-Free Hashing %f/crypto/ipajrg8vwxicdbye49o2haveu1l3djsu.pdf %md12ad243cba1ea076f1f3f381052ee49 %ccrypto %@Mihir Bellare,Moti Yung %*Certifying Cryptographic Tools: The Case of Trapdoor Permutations %f/crypto/eel3cfsnv7osnc6zjrjk2hv9fpwxzr1l.pdf %me6985d0debcad0d8e74bc1320f6fac31 %ccrypto %@Ueli M. Maurer %*Protocols for Secret Key Agreement by Public Discussion Based on Common Information %f/crypto/uzao5hgksdkposwjvfa6v1y3d7eftqqe.pdf %m0c43f49c2da0785262f932463134782a %ccrypto %@Carlo Blundo,Alfredo De Santis,Amir Herzberg,Shay Kutten,Ugo Vaccaro,Moti Yung %*Perfectly-Secure Key Distribution for Dynamic Conferences %f/crypto/qilczfonnswijjbtcv23ah1pum0atrrd.pdf %ma79fbe7ea314beb80651557924d11cbd %ccrypto %@Eli Biham,Adi Shamir %*Differential Cryptanalysis of the Full 16-round DES %f/crypto/jfxymweh5bvask9vtscpfo3enbrgdkqy.pdf %mb884e88827e571dbf570dc36a8a95d79 %ccrypto %@Lars Ramkilde Knudsen %*Iterative Characteristics of DES and s2-DES %f/crypto/9fqcibos6nizqludwj7x0pwme1z4fmjc.pdf %mc75d354f0e48c7d4610b696228272ee1 %ccrypto %@Keith W. Campbell,Michael J. Wiener %*DES is not a Group %f/crypto/7xj3djvncbcos0eupv2rpufowairx19g.pdf %ma7eab15dabdac50655c5a97c2cae298b %ccrypto %@Hans Eberle %*A High-speed DES Implementation for Network Applications %f/crypto/shlqcodjiz9frye4plcsgvuq6fh08yrn.pdf %m48c78c8e26dcc4e6c36ed056b9911360 %ccrypto %@Bob Blakley,G. R. Blakley,A. H. Chan,J. L. Massey %*Threshold Schemes with Disenrollment %f/crypto/e69yckp8skh24fhvtpyqvlrrojcdmgsw.pdf %m91241126808ee60b77cebac969784313 %ccrypto %@Yair Frankel,Yvo Desmedt,Mike Burmester %*Non-existence of homomorphic general sharing schemes for some key spaces %f/crypto/2zqamlvotefpuxpjs3zdribwdgc8ove4.pdf %m93de5a37772e2233bd74e30ec133ae3f %ccrypto %@Lein Harn,Hung-Yu Lin %*An l-Span Generalized Secret Sharing Scheme %f/crypto/qkthyndvx4mpefuoov0lhajwi3mdrz8b.pdf %m7fb7adfba41ddeae401ca2ac89e833fa %ccrypto %@Kaisa Nyberg,Lars Ramkilde Knudsen %*Provable Security Against Differential Cryptanalysis %f/crypto/gwflfv2raqhs4g5uvx9sp7601tykbynd.pdf %mb9bb84ff15f9174b11e144629ca6fcb1 %ccrypto %@Peter C. Wayner %*Content-Addressable Search Engines and DES-like Systems %f/crypto/1xewkrgl0psbyu6b4dzhydkejifmlmov.pdf %m8e6b22290e9020637c70040a4a461c71 %ccrypto %@Serge Vaudenay %*FFT-Hash-II is not yet Collision-free %f/crypto/rfw3t5cm6f0gdstixujypkvlqg4aazpr.pdf %m6c4b9cd759af02bf21e0c3dbcdd3121e %ccrypto %@M. Abadi,M. Burrows,B. Lampson,G. Plotkin %*A Calculus for Access Control in Distributed Systems %f/crypto/xdbqp1o92hwmonl6y8gkrir03jcnbvjg.pdf %m3499676775bfd62881dc596f6824aee8 %ccrypto %@Marie-Jeanne Toussaint %*Deriving the Complete Knowledge of Participants in Cryptographic Protocols %f/crypto/7rehmuunq0sjzdk3brdmnh28pck1aqti.pdf %m8ae7dfc337b9c910f728446ebedc68ff %ccrypto %@Ray Bird,Inder Gopal,Amir Herzberg,Phil Janson,Shay Kutten,Refik Molva,Moti Yung %*Systematic Design of Two-Party Authentication Protocols %f/crypto/fvmlb8k9cjapozwh1cedq4ajigou0unx.pdf %me52873300739daddc79215c16a69c519 %ccrypto %@D. R. Stinson %*Combinatorial characterizations of authentication codes %f/crypto/xnslj9p2w7ds5b3rh8byvymqzc4ukwkx.pdf %m1ca17324e022e10cc9ad552ccd9b00d2 %ccrypto %@D. R. Stinson %*Universal hashing and authentication codes %f/crypto/poqcyfbhnniuzegalkdctjvlaxdo2twr.pdf %me1fa54b66578da12aba76c3bc3f544e1 %ccrypto %@P. Camion,C. Carlet,P. Charpin,N. Sendrier %*On Correlation-immune functions %f/crypto/vmtdh1jo7eb58b3aqfglhtkcspszp0yu.pdf %mc527829e6d8afdf02e96c1ff072b7d46 %ccrypto %@R. M. Capocelli,A. De Santis,L. Gargano,U. Vaccaro %*On the Size of Shares for Secret Sharing Schemes %f/crypto/ulpzsgmwiljyaqq0zc5nyd3h9fkewkhb.pdf %m95815b4a7e8ea2d5abc38a126c5ad64f %ccrypto %@Cynthia Dwork %*On Verification in Secret Sharing %f/crypto/cdjthuotsayxfnq40vrzijmabmd5rig1.pdf %maa7984590291872cde02baeb0e0d66cd %ccrypto %@Torben Pryds Pedersen %*Non-Interactive and Information-Theoretic Secure Verifiable Secret Sharing %f/crypto/mcwx9tbzvbfryo6duzhji4n27lgasrn1.pdf %mf60909ce606ba5fedc7059a175f14ab0 %ccrypto %@Michael J. Fischer,Rebecca N. Wright %*Multiparty Secret Key Exchange Using a Random Deal of Cards %f/crypto/qcecy4wwxl8koqszvdxv1t5aujr3y7kt.pdf %m1c6d36fa943f615f75cf356c921617d6 %ccrypto %@Eli Biham,Adi Shamir %*Differential Cryptanalysis of Snefru, Khafre, REDOC-II, LOKI and Lucifer %f/crypto/oymhwgoigblf6rvqczsjtftnkkdc90hw.pdf %m7de9de96cc5b6b4b0f4b80fe825bbf5c %ccrypto %@Anne Tardy-Corfdir,Henri Gilbert %*A Known Plaintext Attack of FEAL-4 and FEAL-6 %f/crypto/adxogyhjslm5ixfsorhzue1p04tcnrt6.pdf %me628011bce7c83ebeabbc772434186b0 %ccrypto %@Hikaru Morita,Kazuo Ohta,Shoji Miyaguchi %*A switching closure test to analyze cryptosystems %f/crypto/jmsfe5qfvl0txvcocdx87ypdhuhrugnj.pdf %mf44d30604656bf0119c32013f8447501 %ccrypto %@Bert den Boer,Antoon Bosselaers %*An Attack on the Last Two Rounds of MD4 %f/crypto/go7wil5fqomblj3iuxcy1vnk0esxgpzw.pdf %mc9183c70ab7a2793fa6a3b0515db7b33 %ccrypto %@Yeow Meng Chee,Antoine Joux,Jacques Stern %*The Cryptanalysis of a New Public-Key Cryptosystem based on Modular Knapsacks %f/crypto/ibgpctf2jfyllzrawug0o5m6siuadk8h.pdf %m1b068194e10167c2c8273b31cf72ace7 %ccrypto %@Dror Lapidot,Adi Shamir %*A One-Round, Two-Prover, Zero-Knowledge Protocol for NP %f/crypto/94vwndbptkxmofxhjz6yciq3ghv0gio5.pdf %mc17a22b4f27716980f4d0ff7023de820 %ccrypto %@Joe Kilian,Ronitt Rubinfeld %*Interactive Proofs with Space Bounded Provers %f/crypto/9gurikti51dpe8nzd6kxqjmsaszowol0.pdf %m7e442ff64ce6107a8762503d5ad82c16 %ccrypto %@Shang-Hua Teng %*Functional Inversion and Communication Complexity %f/crypto/newsrnjdsmbji3ioubm9qxhf1y52t07v.pdf %me5cfba51e54ad4b7f69874f55438d0f1 %ccrypto %@Steven Rudich %*The Use of Interaction in Public Cryptosystems. %f/crypto/ac71gthnnspqk5w0rytgixl3kujmocyo.pdf %m654214348980ac15c204fb234b6f091b %ccrypto %@Kenji Koyama,Ueli M. Maurer,Tatsuaki Okamoto,Scott A. Vanstone %*New Public-Key Schemes Based on Elliptic Curves over the Ring Zn %f/crypto/tkhifxmp0orhpdfacoszwa4g6cubzw1n.pdf %m2c3c1671f462f489141ffbe3baa10451 %ccrypto %@Tatsuaki Okamoto,Kouichi Sakurai %*Efficient Algorithms for the Construction of Hyperelliptic Cryptosystems %f/crypto/qicjyqfvurablpdc4oe3xsgtl7m8vo2e.pdf %m8a53edab4ee56d40ce1c4466d9726b45 %ccrypto %@Neal Koblitz %*CM-Curves with Good Cryptographic Properties %f/crypto/gnlxzm02jmdcxptcvrfuz47rbyb5v93y.pdf %m0c6815462f09113f307003f66560e7db %ccrypto %@Shigeo Tsujii,Jinhui Chao %*A New ID-Based Key Sharing System %f/crypto/c9nizkflg2xtkysthm1proudb0qagzil.pdf %m454aee4547591f23b72879cb3bd65a2b %ccrypto %@Michael Luby %*Pseudo-random Generators from One-way Functions %f/crypto/l1p4f7agoe0njsxucmr2bc6ftj3mehio.pdf %m8fde56e7e4013886007144956d22d4ea %ccrypto %@Jacques Patarin %*New Results on Pseudorandom Permutation Generators Based on the Des Scheme %f/crypto/58grbqte4plwhialneigrnsd39hvyj12.pdf %m9dbeb89b7d378388bbaa75d01295cd5a %ccrypto %@Colin D. Walter %*Faster Modular Multiplication by Operand Scaling %f/crypto/d1jniadf4wfiyhkok5eqsextsj0vzbuc.pdf %m2f410148299428f2b9513512047b064a %ccrypto %@Tatsuaki Okamoto,Kazuo Ohta %*Universal Electronic Cash %f/crypto/eu09z8jngf6dl7smhycmavpd4hykrosg.pdf %m783a19c88ab7dad7e1d8d1549ef42ec2 %ccrypto %@Birgit Pfitzmann,Michael Waidner %*How to Break and Repair a “Provably Secure” Untraceable Payment System %f/crypto/ezevnr35uo2j0osy1lqmmufx4dvzikqg.pdf %m46425461086b7e11eb512dab3084d746 %ccrypto %@Charles H. Bennett,Gilles Brassard,Claude Crépeau,Marie-Hélène Skubiszewska %*Practical Quantum Oblivious Transfer %f/crypto/ek3kc2yyiqpruhm57wdvzsnfdn8gqj6x.pdf %m8b9958b55f4cdf6420e94766d289a917 %ccrypto %@Albert G. Broscius,Jonathan M. Smith %*Exploiting Parallelism in Hardware Implementation of the DES %f/crypto/zxqb0lo9lgbyqt6uc5mjz7w2osteah1n.pdf %mbc944e98486134271a1e19c8578ae708 %ccrypto %@Donald Beaver %*Foundations of Secure Interactive Computing %f/crypto/ey9wqgvnckmbycjiv5ffs0rpgxdi61te.pdf %m97960dba0f41aba46b32d61017b459d5 %ccrypto %@Silvio Micali,Phillip Rogaway %*Secure Computation %f/crypto/iodze6hejpdgsyrnmbp7cm9af0huxwu8.pdf %mcf58bfda400ee1f1ad46300e04cbc40e %ccrypto %@Kenneth R. Iversen %*A Cryptographic Scheme for Computerized General Elections %f/crypto/vx57lltz0i2ya4nend6ssuja1bmkw3ig.pdf %m446c23859749c84c58ad10eb6a71b2b0 %ccrypto %@Donald Beaver %*Efficient Multiparty Protocols Using Circuit Randomization %f/crypto/g47jfberssem3yizrfwwuhmkpx0ahovt.pdf %mb7ea53dce5aaec97e1eb23814b310df0 %ccrypto %@Charles Rackoff,Daniel R. Simon %*Non-Interactive Zero-Knowledge Proof of Knowledge and Chosen Ciphertext Attack %f/crypto/a5ebgpox8ndy7kmiq3hz2xaumnle0ocf.pdf %m1d2efe3e7422b40952bd35e78b2ddae1 %ccrypto %@Ivan Damgård %*Towards Practical Public Key Systems Secure Against Chosen Ciphertext attacks %f/crypto/jifhvhgldn5vg73c1uqibatpcu8daf6p.pdf %m8ca9e0dfd2fcf437affd903e4f8eacb1 %ccrypto %@Yvo Desmedt,Yair Frankel %*Shared generation of authenticators and signatures %f/crypto/rqc5rcaxeupzjjm9mnhs3lbxd6p7tiy1.pdf %m5c71869e2fd48cf7ddb365091555d064 %ccrypto %@David Chaum,Eugène van Heijst,Birgit Pfitzmann %*Cryptographically Strong Undeniable Signatures, Unconditionally Secure for the Signer %f/crypto/bncg8uvfod6kq27o3wi9mgxleajtzcjf.pdf %mcdea45623b17dcc9673133cee37be42a %ccrypto %@Eli Biham,Adi Shamir %*Differential Cryptanalysis of DES-like Cryptosystems %f/crypto/wdgkfscozboumzumntn30ywyfphhglrx.pdf %m4a81c0f4c3c5549d5b4bb9f945abe725 %ccrypto %@Henri Gilbert,Guy Chassé %*A Statistical Attack of the FEAL-8 Cryptosystem %f/crypto/tt3yzxxev6uspniodyfia7brzsjqm9ww.pdf %mc3710401f4984abe7cbe359e468ec9b4 %ccrypto %@Gilles Brassard,Claude Crépeau %*Quantum Bit Commitment and Coin Tossing Protocols %f/crypto/tknwsqaivkafe4czqgrtgboyd2m1nxu3.pdf %md3364c63edff2b7e665e16df93809c7f %ccrypto %@D. Beaver,J. Feigenbaum,J. Kilian,P. Rogaway %*Security with Low Communication Overhead %f/crypto/bgizytvcpkrfqtjrwdoca63iv0wsgenm.pdf %mbb9e4baa9c0f381e497e0d633d920e1f %ccrypto %@Shafi Goldwasser,Leonid Levin %*Fair Computation of General Functions in Presence of Immoral Majority %f/crypto/unt78lcbndwigbxohmacqljufzave43g.pdf %mdba3df1ab21cdc6a8e1d8ea8bab6c67a %ccrypto %@Gilles Brassard,Moti Yung %*One-Way Group Actions %f/crypto/i5pitg42eftkdsuv3zb7olfnhjzrxlrm.pdf %m79c6a39ef464475422f9139e0e0335a4 %ccrypto %@B. A. LaMacchia,A. M. Odlyzko %*Solving Large Sparse Linear Systems Over Finite Fields %f/crypto/isgrbclwc1ael6xkys5ye8nknpqzmpwa.pdf %m12eff3a48a67fac03062fae53beab3a9 %ccrypto %@Johannes Buchmann,Stephan Düllmann %*On the Computation of Discrete Logarithms in Class Groups %f/crypto/mrj0rmvxydwlcsowep7axjq2hdbn94sg.pdf %m0755f85aa84f1e8eeeda3f7b4d5d6149 %ccrypto %@Chih-Chwen Chuang,James George Dunham %*Matrix Extensions of the RSA Algorithm %f/crypto/9hdchifxn4k5312y8bpsimwgqejqlrmd.pdf %m07e9281a990efb44ebaf5aeeb724995f %ccrypto %@Neal Koblitz %*Constructing Elliptic Curve Cryptosystems in Characteristic 2 %f/crypto/kdgbn5xashp3vtrqx0utcdywm4fohejq.pdf %m558b984ec89e9384af33954d82aa92a4 %ccrypto %@Thomas Beth,Yvo Desmedt %*Identification Tokens — or: Solving The Chess Grandmaster Problem %f/crypto/5slg2x9xeepqzunbq1ywl7dcbkzyvwfm.pdf %mdbdf620d3db310ce9234833f8211e871 %ccrypto %@Yvo Desmedt,Moti Yung %*Arbitrated Unconditionally Secure Authentication Can Be Unconditionally Protected against Arbiter’s Attacks %f/crypto/6knx3x8yk7pgrclsyaebdt9ze1foupjz.pdf %m6d319e210f5c022e46fabcce5ec119ce %ccrypto %@Joan Boyar,David Chaum,Ivan Damgård,Torben Pedersen %*Convertible Undeniable Signatures %f/crypto/f2oz4tywvb5gqfdkgmmtyl36h8nxeceq.pdf %ma9ab1914955704dd847ea99817386e29 %ccrypto %@David Chaum,Sandra Roijakkers %*Unconditionally-Secure Digital Signatures %f/crypto/rholdqadigqkbzkxeapm049bvy3l76rx.pdf %m8fb387f7ff5f6eeaab2b484ce14b426a %ccrypto %@Gustavus J. Simmons %*Geometric Shared Secret and/or Shared Control Schemes %f/crypto/jrnm2ugat3dpxkyocv4kbvjxdloszh1t.pdf %meed1d88ad8d24dd054b1320e74206820 %ccrypto %@E. F. Brickell,D. R. Stinson %*Some Improved Bounds on the Information Rate of Perfect Secret Sharing Schemes %f/crypto/y0cxu5zmaqotj7mkbsjvzdhiulvx3yrw.pdf %m002b98e65b72cd7170992a664cc4a8db %ccrypto %@Silvio Micali,Tal Rabin %*Collective Coin Tossing Without Assumptions nor Broadcasting %f/crypto/mpfdvoz51ctoi7ge2wxebcj9qpstayhi.pdf %m17af3ff756a9fb26f3a8f0c7a774a41f %ccrypto %@Yacov Yacobi %*A Key Distribution “Paradox” %f/crypto/lm2gf0nqzrphkbwecsckuvnpr8x45ejq.pdf %m94e417d12e7cce835f09a745af52c2aa %ccrypto %@Walter Fumy,Michael Munzert %*A Modular Approach to Key Distribution %f/crypto/pz1eyin8dkzbk9uyemqfu7wmsvdjs3gv.pdf %m9e54c4b8cdd1cd3b42c4422698000e67 %ccrypto %@Yuliang Zheng,Tsutomu Matsumoto,Hideki Imai %*Structural Properties of One-Way Hash Functions %f/crypto/dvwg5udw6of3voyupl4m2qqcxrfgcazk.pdf %m2ab059e56f856eadd5963127cc368045 %ccrypto %@Ronald L. Rivest %*The MD4 Message Digest Algorithm %f/crypto/5e0gnfewy3zzuxtgylubci9mhom4fwlp.pdf %mc492dc3d8cd3c35bbd93a3f5d7ab57a1 %ccrypto %@J. Kilian %*Achieving Zero-Knowledge Robustly %f/crypto/kjc18oxqq6jpr5fnfpy4lgsxi9k0h3ts.pdf %m6887c8125cefb3ea1beea6d2a8630575 %ccrypto %@Donald Beaver,Joan Feigenbaum,Victor Shoup %*Hiding Instances in Zero-Knowledge Proof Systems %f/crypto/txplltgdns5q3mbjri4ycjwp9kah82fg.pdf %m6ef6b686507c0b71d48feb3ede01a07e %ccrypto %@Kaoru Kurosawa,Shigeo Tsujii %*Multi-Language Zero Knowledge Interactive Proof Systems %f/crypto/nvenfry5g92wtxh3bufuwy8tia0zbdlc.pdf %md381b21f16e068569821c762587ff122 %ccrypto %@Dror Lapidot,Adi Shamir %*Publicly Verifiable Non-Interactive Zero-Knowledge Proofs %f/crypto/gfe3sitxgx07vjhh1omu58tcrnwuydb6.pdf %m48bda13ead781639311a0bab9e18db06 %ccrypto %@Alfredo De Santis,Moti Yung %*Cryptographic Applications of the Non-Interactive Metaproof and Many-prover Systems %f/crypto/dsnu6e8ichwzzo2nd3r7pm5civjwqsu1.pdf %m91fd38c9d59a7196a3125f2b29a1b171 %ccrypto %@J. Kilian %*Interactive Proofs with Provable Security against Honest Verifiers %f/crypto/ek52nn4gcdyplqywvk6bz0gjjtih9qtx.pdf %m12184b99a9e7bb537743d3f16deead72 %ccrypto %@A. W. Schrift,A. Shamir %*On the Universality of the Next Bit Test %f/crypto/u0d6vbqcgyitaxohin9hvjpclp5aeowu.pdf %m17b39de3c776dec276038b50fa0174a9 %ccrypto %@Ueli M. Maurer %*A Universal Statistical Test for Random Bit Generators %f/crypto/cn5lty6pbsx4wo80gec2qsruh7jvrzei.pdf %m47bd7e667334b44a17d5dd427dda28e2 %ccrypto %@James L. McInnes,Benny Pinkas %*On the Impossibility of Private Key Cryptography with Weakly Random Keys %f/crypto/z3qbc7e2iajvqsfxefnkgmrjumoc84id.pdf %m138083c54190828c049d172ad07b2208 %ccrypto %@Stuart Haber,W. Scott Stornetta %*How to Time-Stamp a Digital Document %f/crypto/ztc4gszixbontmbw9iwhac5jyf8ah60k.pdf %m8a203490925011836dd7a1612e89b545 %ccrypto %@Tatsuaki Okamoto,Kazuo Ohta %*How to Utilize the Randomness of Zero-Knowledge Proofs %f/crypto/cet7qzwv0yudwin2sxp8frc5zoebxkhp.pdf %mc15d66a4dd25f7da8f99dcce8d4c8540 %ccrypto %@Ralph C. Merkle %*Fast Software Encryption Functions %f/crypto/b3lzzutiox4quywjjgrcwbl7tn9didvf.pdf %mddd25dfcc9b131a1730d533fb338ad03 %ccrypto %@Dominique de Waleffe,Jean-Jacques Quisquater %*CORSAIR: A Smart Card for Public Key Cryptosystems %f/crypto/atvco3uxslqv1zlfnk0g4akofhsbwgnp.pdf %mfccb58d2bfbe401e5ecf7e243a9d0a4a %ccrypto %@Kireeti Kompella,Leonard Adleman %*Fast Checkers for Cryptography %f/crypto/2vq5xbunf4hljgrq93owyg7tfecikvsd.pdf %m0d3585ceef1cac16431faceaf76a3084 %ccrypto %@Richard Cleve %*Complexity Theoretic Issues Concerning Block Ciphers Related to D.E.S. %f/crypto/93bmteplgqhj2kwqnocldg0srbwtkenu.pdf %me96bc8c4a096d30f70b771e9eb02c3e3 %ccrypto %@Thomas W. Cusick,Michael C. Wood %*The Redoc II Cryptosystem %f/crypto/bionbliqy0cgta25vep3mofjnsjdkght.pdf %m69776ee30e9a2a30730f5290073974ee %ccrypto %@Kwangjo Kim,Tsutomu Matsumoto,Hideki Imai %*A Recursive Construction Method of S-boxes Satisfying Strict Avalanche Criterion %f/crypto/yi3i2pokgreavmcnzqwsphyrglucdebt.pdf %m9a7fa0755e224da04a924d0b95f0a01e %ccrypto %@Paul C. van Oorschot %*A Comparison of Practical Public-Key Cryptosystems based on Integer Factorization and Discrete Logarithms %f/crypto/bhc0hvokowigpjcfilwren26nrav58eq.pdf %mccf4424297cf44684e1b662afce7f97a %ccrypto %@Kenji Koyama,Routo Terada %*Nonlinear Parity Circuits and their Cryptographic Applications %f/crypto/4tjhl5ycv8yknjne7hrspoiddvaqcw06.pdf %m4dfb285b76c9a1eb317c7d20ba85561c %ccrypto %@Othmar Staffelbach,Willi Meier %*Cryptographic Significance of the Carry for Ciphers Based on Integer Addition %f/crypto/ybj2vaxkwmlpsttbkrn54hce0gzuyioc.pdf %mdca76d39271cfd7a6070dd16790b40a6 %ccrypto %@B. A. LaMacchia,A. M. Odlyzko %*Computation of Discrete Logarithms in Prime Fields %f/crypto/al0hfx9l7hno3mnrabwyrv1u8ej4ivq5.pdf %mcd16a91b59003999b2a392fc96250f2d %ccrypto %@Shimon Even %*Systolic Modular Multiplication %f/crypto/y1vhf7egkkqs8fndwirgw053zbxlmajp.pdf %m8be2fe168c506b1e37e83c0d29c4e974 %ccrypto %@Ronald L. Rivest %*Finding Four Million Large Random Primes %f/crypto/ysc4ne0opyg6qldaunw2catvfezmbmoj.pdf %m96ce6d06973a9e2198f2077af463e67f %ccrypto %@Shoji Miyaguchi %*The FEAL Cipher Family %f/crypto/phyfdt57fbluznvkaureyqoxkbgeoqc6.pdf %m3defa00981250583b403ea67fcef0c00 %ccrypto %@Yacov Yacobi %*Discrete-Log With Compressible Exponents %f/crypto/nf3rzvsj0yrmwxjkaedlthpmg1v69iwt.pdf %medbbe3abf194938d67c37d8601daa075 %ccrypto %@David Kahn %*Keying the German Navy’s Enigma %f/crypto/na2ljcnxitkr6w3lhkphcygmrmdqvu5f.pdf %mda3cf7a946f10d902f06be7a24a3c66b %ccrypto %@Yvo G. Desmedt %*Making Conditionally Secure Cryptosystems Unconditionally Abuse-Free in a General Context %f/crypto/kpcwpwg7q8k9ogichibyfemrxadjtmf6.pdf %mc22f531666fa7da6463ee168a3c1e98f %ccrypto %@Ivan Bjerre Damgård %*On the Existence of Bit Commitment Schemes and Zero-Knowledge Proofs %f/crypto/rsjney2hc5dfptv1hlwat3wb0rskqoxy.pdf %m8f1aeadeef997dd1743f81188bd52acb %ccrypto %@Russell L. Brand %*Problems with the Normal Use of Cryptography for Providing Security on Unclassified Networks %f/crypto/yweqpvibaq0msxfkamd7duitwh5rcnpj.pdf %m18761c935ffe25bb5fc65ca75f89a399 %ccrypto %@John T. Kohl %*The use of Encryption in Kerberos for Network Authentication %f/crypto/revxlqizptdswxglkw0iduma8o13s4jc.pdf %ma999e6f307983a0249619f1a0d3707fe %ccrypto %@David C. Feldmeier,Philip R. Karn %*UNIX Password Security - Ten Years Later %f/crypto/8moxie1stfcrupkarawjdhxsmnj3qzfy.pdf %m9fc2efbe09c74642fd629183365c5b89 %ccrypto %@Jonathan M. Smith %*Practical Problems with a Cryptographic Protection Scheme %f/crypto/r5yj1t7uxenloybmkzhamrcsidwpgwzt.pdf %md3fe82f6ca2a17168cbfdc9b08e81aa9 %ccrypto %@Paul Barrett,Raymond Eisele %*The Smart Diskette A Universal User Token and Personal Crypto-Engine %f/crypto/x8f2lnp9e3tlurgj4pbaa7hqcyibdh16.pdf %m244730add25be39fc75b8a72207f220c %ccrypto %@Agnes Hui Chan,Richard A. Games %*On the Quadratic Spans of Periodic Sequences %f/crypto/ie1a8qmj4lzatm963qtckbrsnlxye5gv.pdf %m6d1fbc048f1be90551d6204c99d4bb1e %ccrypto %@Cees J. A. Jansen,Dick E. Boekee %*The Shortest Feedback Shift Register That Can Generate A Given Sequence %f/crypto/jnsd7q62ts0h3hukwyq4gfpc9r5lmibm.pdf %me8c1715ae1fd5451254f3d7f68d61230 %ccrypto %@Ueli M. Maurer,James L. Massey %*Perfect Local Randomness in Pseudo-random Sequences %f/crypto/emazea4pnvkkp5cyotbo8ui3f9rh6w2u.pdf %md5e510c1880571ab029675f3359cf8f2 %ccrypto %@Oded Goldreich,Hugo Krawczyk %*Sparse Pseudorandom Distributions %f/crypto/ikmnvxfajzzsrp23wfwu6lghxa9nd5bq.pdf %mddf47e79a29113f2a6ec7293ec911a77 %ccrypto %@Moni Naor %*Bit Commitment Using Pseudo-Randomness %f/crypto/o7xvjfb3gyv8twrmqpabzg2uri0akcel.pdf %ma09d3269843bcc296f6e131dd7b476d8 %ccrypto %@Hugo Krawczyk %*How to Predict Congruential Generators %f/crypto/7h9cb8zwn0tmrnolajsdqbd31f4i6eyg.pdf %m50ca9ec22a02bb30e443c7001b8aea64 %ccrypto %@Bart Preneel,Antoon Bosselaers,René Govaerts,Joos Vandewalle %*A Chosen Text Attack on The Modified Cryptographic Checksum Algorithm of Cohen and Huang %f/crypto/u8cvzihks2qngxzxwdymyja6lqb4hro9.pdf %m7b48ddeb38e8099784d80899e9d425e3 %ccrypto %@Amos Fiat %*Batch RSA %f/crypto/8n5sqlsuzy6rz0kkp1ooejetg7g3nvhy.pdf %m094e94f78184b337c455d15d0a111238 %ccrypto %@Andreas Bender,Guy Castagnoli %*On the Implementation of Elliptic Curve Cryptosystems %f/crypto/zbfa8msliw5g0uqrsaudizpdkhcvt9vt.pdf %ma7d5e46574220743930a50fa726f5790 %ccrypto %@Mihir Bellare,Shafi Goldwasser %*New Paradigms for Digital Signatures and Message Authentication Based on Non-Interactive Zero Knowledge Proofs %f/crypto/nihry2cu73ouvl6hgc1msbdetxaqfmbi.pdf %me4b9ace3503e803fce73ba7d670326ae %ccrypto %@David Chaum,Hans van Antwerpen %*Undeniable Signatures %f/crypto/qpj2n31lehbccv0qfmmtezntvhogdpxy.pdf %m952a75bfebe2c70b28ea5e57aca17498 %ccrypto %@Ralph C. Merkle %*A Certified Digital Signature %f/crypto/9hwfnjvoe4ciqrzx6rwduv8kupc5lfz3.pdf %m4790798eb1285da94815783e807cd49a %ccrypto %@C. P. Schnorr %*Efficient Identification and Signatures for Smart Cards %f/crypto/haoxenth6n9efki3j2bztyauq40usplo.pdf %m484276343fc7b0d49140fc2099f28656 %ccrypto %@Marijke De Soete,Jean-Jacques Quisquater,Klaus Vedder %*A signature with shared verification scheme %f/crypto/xyin7ecrk6m3myzl0ha1b9pv5jv2iqdr.pdf %m8c50deb8dc0787753caa2537bd086934 %ccrypto %@Shimon Even,Oded Goldreich,Silvio Micali %*On-Line/Off-Line Digital Signatures %f/crypto/edkha5cpgqpmqizdoxwlguxk8h9ajyy2.pdf %ma4cfa48d48316b7ef5711b7fd7d8abd6 %ccrypto %@Ernest F. Brickell,Daniel M. Davenport %*On the Classification of Ideal Secret Sharing Schemes %f/crypto/kqbwmrv17dvbyuxehf3sgoqhrzmfigjj.pdf %mdc0620d03f1d54ab9214bc4eec7981b1 %ccrypto %@Benny Chor,Eyal Kushilevitz %*Secret Sharing Over Infinite Domains %f/crypto/mbb0xumcejwgdzxisz98qnfrklypq6id.pdf %m06c056f6d9dd1b1bd09f8c2f4649d4b6 %ccrypto %@Yvo Desmedt,Yair Frankel %*Threshold cryptosystems %f/crypto/6nlgd2tmbaeyfic1wojx7jv3zercg5ws.pdf %md1fcf52b89360126d001e206c8335680 %ccrypto %@Gerald C. Chick,Stafford E. Tavares %*Flexible Access Control with Master Keys %f/crypto/mu1vg3jd76lwbkvhyyn4rakioizfzxas.pdf %m45d2b6f41e7db9bbd9754125a1c3b5c1 %ccrypto %@Makoto Tatebayashi,Natsume Matsuzaki,David B. Newman %*Key Distribution Protocol for Digital Mobile Communication Systems %f/crypto/iapm06ysugd5arvbxnlteod4pk9svctb.pdf %mde918d109311717416f58acfc8722b15 %ccrypto %@Johannes A. Buchmann,Hugh C. Williams %*A key exchange system based on real quadratic fields Extended abstract %f/crypto/6id3q8dhlbesmman0rg7efkwy1xgh4uk.pdf %mbc5b9103a6c5fb6c3d4dc90aa7108656 %ccrypto %@Y. Yacobi,Z. Shmuely %*On Key Distribution Systems %f/crypto/dz4apt8o9zfvl5uapb6jmovqii0ktmwk.pdf %m7459eea4aad085315e64ae1d99a1bccd %ccrypto %@Ruth Nelson,John Heimann %*SDNS Architecture and End-to-end Encryption %f/crypto/jmojxyvt1fuqwbyhsf8lkgpapci3exmd.pdf %mcc190ebc6880a3cedc3d88a92a2c4245 %ccrypto %@Ernest F. Brickell %*A Survey of Hardware Implementations of RSA %f/crypto/hxswriycg4fovuge0d9azblkppmfrnn7.pdf %m74cec291701cac9fa2c4c20ebc9021e9 %ccrypto %@P. A. Findlay,B. A. Johnson %*Modular Exponentiation Using Recursive Sums of Residues %f/crypto/wwmhlyqfexiju5zb6pe81ov3osslangt.pdf %m5740ce58c6d54469f304ad72d853cca1 %ccrypto %@Hikaru Morita %*A Fast Modular-multiplication Algorithm based on a Higher Radix %f/crypto/1hxzfm3y9cgevldwnqhi4uagpv056edj.pdf %m6c65819acb07e834309ab569c7a344e5 %ccrypto %@Jurjen Bos,Matthijs Coster %*Addition Chain Heuristics %f/crypto/ihlfyurxftanspzvhtsee7o6jl5310mx.pdf %m37876578999821f2165fd94462242b14 %ccrypto %@Jean-Jacques Quisquater,Jean-Paui Delescaille %*How easy is collision search. New results and applications to DES %f/crypto/tvoyoiguj8r4dvsw9q5kakfrzmxgxsca.pdf %madab9ea1889f43503b56613683a30c71 %ccrypto %@Ivan Bjerre Damgård %*A Design Principle for Hash Functions %f/crypto/c1xoh4edapncy0tlmbwuqlevak2wsgiz.pdf %m95fb54204c2e0db4c1de1ea27cb323c6 %ccrypto %@Ralph C. Merkle %*One Way Hash Functions and DES %f/crypto/ucyizj3vpb7kw0fqtnks64sxlw1zdaqx.pdf %m5b36a3289e58f7c48fdad0ba385ce7a5 %ccrypto %@Spyros S. Magliveras,Nasir D. Memon %*Properties of Cryptosystem PGM %f/crypto/mcqhlnstz1dnevtu7f3p5qoxmwasgzak.pdf %m79701379916a604d6453bc716e3d2fa3 %ccrypto %@Yuliang Zheng,Tsutomu Matsumoto,Hideki Imai %*On the Construction of Block Ciphers Provably Secure and Not Relying on Any Unproved Hypotheses %f/crypto/nswxlrajqqomnpiayu4sh1kj97fkexet.pdf %mc5c3f3d4130caa94188c0d2c2c80f6c9 %ccrypto %@Tatsuaki Okamoto,Kazuo Ohta %*Disposable Zero-Knowledge Authentications and Their Applications to Untraceable Electronic Cash %f/crypto/guk9nxod35bt0hon4bsqzd7i2el1xhje.pdf %m7dab3d7da012e67beaafda0ffcda830b %ccrypto %@Michael Ben-Or,Shafi Goldwasser,Joe Kilian,Avi Wigderson %*Efficient Identification Schemes Using Two Prover Interactive Proofs %f/crypto/sgk2rfhwcu6cloyntow04aki59mzrp3y.pdf %m41f6dbe3ecbc62bf264098208dff2b0f %ccrypto %@Joan Boyar,René Peralta %*On the concrete complexity of zero-knowledge proofs %f/crypto/qgerorwpixs9hf0yhpd6acbmi5v2jwem.pdf %m99db5208d88d00946564919c508e94eb %ccrypto %@U. Feige,A. Shamir %*Zero Knowledge Proofs of Knowledge in Two Rounds %f/crypto/deo4qonpvstixubtj9hc1sme7fn0gk5a.pdf %m3732ed5e4453db5fb2b3c409ae1cc281 %ccrypto %@Joe Kilian,Silvio Micali,Rafail Ostrovsky %*Minimum Resource Zero-Knowledge Proofs %f/crypto/iaxse8ft4rf3lplajbyvndm7yjtsbuxq.pdf %m464854142a8587957869bf84a3555831 %ccrypto %@Mihir Bellare,Silvio Micali %*Non-Interactive Oblivious Transfer and Applications %f/crypto/yzq5uw1abrzgenoxam94dcphvrs87icp.pdf %m733c4e1377ef7cb20b81d1b37caeaede %ccrypto %@Donald Beaver %*Multiparty Protocols Tolerating Half Faulty Processors %f/crypto/jsodcxzwywqpvtcgsk3fzbghei4yke8r.pdf %m8229246b5341582db6e4e0553e6dbea7 %ccrypto %@Richard Cleve %*Controlled Gradual Disclosure Schemes for Random Bits and Their Applications %f/crypto/8dzanolcp4ubqyh5it0cmxsu9zeyb12x.pdf %m908d55f374fe1b9a7d9a8c3dec452a1c %ccrypto %@Donald Beaver,Shaft Goldwasser %*Multiparty Computation with Faulty Majority %f/crypto/bf8q4ughjkcv5pt7sji2dzrsuadbxnwl.pdf %m0fe49a89d7baf8bb99585e3e5c758c01 %ccrypto %@David Chaum %*The Spymasters Double-Agent Problem %f/crypto/fd2noewps1gzvte3ym6xcsa9ajvb0ibz.pdf %me02cd815ceb3d0dd6261b0c0731d911c %ccrypto %@Mihir Bellare,Lenore Cowen,Shaft Goldwasser %*On the Structure of Secret Key Exchange Protocols %f/crypto/s8vdfluen3wchjvs0hdkg9ixj6qlik7m.pdf %m1bacfff492656efb26c08ee2b19280d6 %ccrypto %@Adi Shamir %*An Efficient Identification Scheme Based on Permuted Kernels (extended abstract) %f/crypto/c6rcps8wa5ns9k3bj7zeyglvyd4txxdp.pdf %m6498982189918e4eb5be44237f47c35f %ccrypto %@Rafail Ostrovsky %*An Efficient Software Protection Scheme %f/crypto/5zm1tofkv0cz6lawy4edklh3qxnrjsyb.pdf %mbaffe30eb45f47a2bd46891181f2719a %ccrypto %@Carlisle Adams,Stafford Tavares %*Good S-Boxes Are Easy To Find %f/crypto/tkm47zifhthlb1rrad2fneejxnbyvuoc.pdf %m20ac9b57b2c0c725a3970b1e0cd55b89 %ccrypto %@Steve R. White %*Covert Distributed Processing with Computer Viruses %f/crypto/rjgfo2wircqk3dx1ovy0hzz4ceg7xasp.pdf %m5fa93d54914b4accfab7964f71a4014a %ccrypto %@Wyn L Price %*Progress in Data Security Standardisation %f/crypto/ojksqqfb4jxiv6pndfpttlzurw0vzksx.pdf %mfa5236f11a830cf2d1bdb095da445d51 %ccrypto %@Shoji Miyaguchi %*The FEAL-8 Cryptosystem and a Call for Attack %f/crypto/suzgvbsobu9qjgd7fkfveym21cdahp6o.pdf %m73d627c0fcaf17750e6b517ffeada017 %ccrypto %@Jean-Jacques Quisquater,Myriam Quisquater,Muriel Quisquater,Michaël Quisquater,Louis Guillou,Marie Annick Guillou,Gaïd Guillou,Anna Guillou,Gwenolé Guillou,Soazig Guillou %*How to Explain Zero-Knowledge Protocols to Your Children %f/crypto/okewsccguih8x7vlmjehibpyfnm25sjf.pdf %md2bad3b98a3d88844fe252706f670c11 %ccrypto %@Claude Crépeau,Joe Kilian %*Weakening Security Assumptions and Oblivious Transfer %f/crypto/zlcbz3vfqswqjoemmdyot4u09xaeu1sn.pdf %mdd25e7deb0c8302eaabaa2a189d36e0c %ccrypto %@Russell Impagliazzo,Steven Rudich %*Limits on the Provable Consequences of One-way Permutations %f/crypto/wyb1ct7vunuxej6axmhi9sgfzror0qw3.pdf %m10a5e3e585f3d837ed7a6a525e764edf %ccrypto %@Josh Benaloh,Jerry Leichter %*Generalized Secret Sharing and Monotone Functions %f/crypto/ifqymvj4cn6uzn7ekphobrtsoeswxwlc.pdf %mb1ab3ab91aa1e6dff2ed36a8de9a3fa8 %ccrypto %@Michael Ben-Or,Oded Goldreich,Shafi Goldwasser,Johan Håstad,Joe Kilian,Silvio Micali,Phillip Rogaway %*Everything Provable is Provable in Zero-Knowledge %f/crypto/txd78pwfuuioyvhtghrvz4ar9aksbmcc.pdf %mb431bb3893cc6b1dc3cc9db86e0dcf81 %ccrypto %@Oded Goldreich,Eyal Kushilevitz %*A Perfect Zero-Knowledge Proof for a Problem Equivalent to Discrete Logarithm %f/crypto/ynu03sfjl52cto4qehmrudkmd7fxxigc.pdf %m070db471a32cb4789aab823d3765ea8a %ccrypto %@Cynthia Dwork,Larry Stockmeyer %*Zero-Knowledge With Finite State Verifiers %f/crypto/g8drfl9kibvacmk7utzyys25anivoqqn.pdf %m8789a81a2a4c3932c7086514e72607f7 %ccrypto %@Eric Bach %*Intractable Problems in Number Theory %f/crypto/php5gi8rnqwmyurjhtkozz2taex1sqac.pdf %m2626650738137ef9c946a6d2d1baf6be %ccrypto %@Neal Koblitz %*A Family of Jacobians Suitable for Discrete Log Cryptosystems %f/crypto/fzhikv27qpmu5zdytaov0i4byggxokse.pdf %mc554c20d03dc4a203c76fc7ced8a30cc %ccrypto %@Marc Girault,Philippe Toffin,Brigitte Vallée %*Computation of Approximate L-th Roots Modulo n and Application to Cryptography %f/crypto/owax1jyv3sodwpp5b7h6v9rtafybu2q8.pdf %m179c6e93cc0e9efbf3ab80f8cbb0ffb4 %ccrypto %@Johan van Tilburg %*On the McEliece Public-Key Cryptosystem %f/crypto/kmqut1we4gld6ofvsexbbxsri7cav58g.pdf %mf33746c7defbbfcd4de6de611d6b6de0 %ccrypto %@Michael Lucks %*A Constraint Satisfaction Algorithm for the Automated Decryption of Simple Substitution Ciphers %f/crypto/lgrdmkynwchyadnomt08ebuzzivhw4ui.pdf %m709d12902ff878ff38b0c759ede93c7b %ccrypto %@Oded Goldreich,Hugo Krawczyk,Michael Luby %*On the Existence of Pseudorandom Generators %f/crypto/injuxjtg4bynwl3ecoqf1pd9zkxarmkc.pdf %mbb0cfc9ebd2f967f8791d7e39c6dc2ef %ccrypto %@Ivan Bjerre Damgård %*On The Randomness of Legendre and Jacobi Sequences %f/crypto/qo4yvavpsxdu1p0hw6kdruazexlml2gf.pdf %m7ed7754a1eb73dcc710cea70426538ea %ccrypto %@S. Micali,C. P. Schnorr %*Efficient, Perfect Random Number Generators %f/crypto/4jbdydi9o0rkqghchvnipoyxvlgmq7k6.pdf %mc7a5145665105da7f70a5e390d0a5012 %ccrypto %@Mihir Bellare,Silvio Micali %*How To Sign Given Any Trapdoor Function %f/crypto/vtednjpcj6z9gsftwrifmkc3xoup7aou.pdf %m917faadf2732cf899af2da638f7872f5 %ccrypto %@Louis Claude Guillou,Jean-Jacques Quisquater %*A “Paradoxical” Indentity-Based Signature Scheme Resulting from Zero-Knowledge %f/crypto/sundt95zk2uhco76ox3vcyzir0gspmj1.pdf %m71b51a59dc8fb904f92679280441f6ce %ccrypto %@Kazuo Ohta,Taisuaki Okamoto %*A Modification of the Fiat-Shamir Scheme %f/crypto/k6okwpnctzgvdy7wlfpy8bx3srr1qeu9.pdf %m1140524137ebc4568a4f55c00e664794 %ccrypto %@Silvio Micali,Adi Shamir %*An Improvement of the Fiat-Shamir Identification and Signature Scheme %f/crypto/jpgam4ahwbtdbus0hzoefx3i5f1s8qpy.pdf %m2745f32627fa664782e4444e69080c7a %ccrypto %@Charles Rackoff %*A Basic Theory of Public and Private Cryptosystems %f/crypto/xciflntb7w9j3p2qsr5zvagg6w1ryhjo.pdf %m17a597bd373ff868d39e706536cfe777 %ccrypto %@Manuel Blum,Paul Feldman,Silvio Micali %*Proving Security Against Chosen Ciphertext Attacks %f/crypto/tnoamjrsjyvrobfc06mqv2w4facnthhz.pdf %m613386dfd3350ebefe43e728889bf139 %ccrypto %@Alfredo De Santis,Siluio Micali,Giuseppe Persiano %*Non-Interactive Zero-Knowledge with Preprocessing %f/crypto/yencb87zhpgydmg1wcpbfvsai6dnfamt.pdf %m976ed86a7499d8d236952fe681f8fc5b %ccrypto %@U. Feige,A. Shamir,M. Tennenholtz %*The Noisy Oracle Problem %f/crypto/q0adru76vcysg5rslgz4efzlnpkyomhn.pdf %mf217a353c83574775b501fef5628d759 %ccrypto %@Martín Abadi,Eric Allendert,Andrei Broder,Joan Feigenbaum,Lane A. Hemachandra %*On Generating Solved Instances of Computational Problems %f/crypto/mdxq7khbtbr62xawpejsz89qlt14vrhg.pdf %ma9cedeea7d57c4e136847a37f295bcb0 %ccrypto %@Marijke De Soete %*Bounds and Constructions for Authentication - Secrecy Codes with Splitting %f/crypto/mbtzmluswqf34cfvay8gpr2ns5ql1zua.pdf %md5acafc6e88333a7a74e4bb9aeee5024 %ccrypto %@David Chaum,Amos Fiat,Moni Naor %*Untraceable Electronic Cash %f/crypto/ywmupmxeld9ba5ckdjz4xl1yqnk6qjo8.pdf %mc0ce8e07d1189a9c4e3972664086c847 %ccrypto %@Ivan Bjerre Damgård %*Payment Systems and Credential Mechanisms with Provable Security Against Abuse by Individuals %f/crypto/rl5wz8taiyhfgmdvtip4osmj7a6k0huv.pdf %mfad224e0c67cac782681fba551f054a8 %ccrypto %@Ming-Deli A. Huang,Shang-Hua Teng %*A Universal Problem in Secure and Verifiable Distributed Computation %f/crypto/keeczitvdkfipowgmann4qz5bl6hrgpj.pdf %m127b2b08f20af648629c28cc13168701 %ccrypto %@Leonard M. Adleman %*An Abstract Theory of Computer Viruses %f/crypto/3lqg1odcy7rn2ufwtbcmgiitsbzjoavh.pdf %mf0adb214e48392634c620d0ac9d39394 %ccrypto %@Yvo Desmedt %*Abuses in Cryptography and How to Fight Them %f/crypto/srlilvbqwknyqnicjy4ak7trf06xfheh.pdf %ma1ee09cfac9a70e77952854f2818f4c9 %ccrypto %@Gustavus J. Simmons %*How to (Really) Share a Secret %f/crypto/x1qn7sycubv2yqkpm4hpag69htekow0l.pdf %m836013fbf0a3e426b837b306298d3cbc %ccrypto %@Réjane Forrié %*The Strict Avalanche Criterion: Spectral Properties of Boolean Functions and an Extended Definition %f/crypto/jshvo5gfnsxkdma6gpkayvew8b3u9jqo.pdf %m37f17605890a7af3d8c8919b5b770ea1 %ccrypto %@Kencheng Zeng,Minqiang Hung %*On the Linear Syndrome Method in Cryptanalysis %f/crypto/hmwkazsl793pzhdrju4ignjuvg81bdta.pdf %m2fd32501dc2df9a4bba8d203b07c7c3b %ccrypto %@Richard T. C. Kwok,Beale Maurice %*Aperiodic Linear Complexities of de Bruijn Sequences %f/crypto/imr41zvbfoyskju03wmg6kelpr5t7hgu.pdf %me3e67cbaf7ba5e919d9702b8c8222bb3 %ccrypto %@J. R. Sherwood,V. A. Gallo %*The Application of Smart Cards for Rsa Digital Signatures in a Network Comprising Both Interactive and Store-and-Forward Facilities %f/crypto/prv7mvgcitxk0zwm391hyqiuflzuts8n.pdf %m78444bba1354a52d49324e293ff61ff9 %ccrypto %@B. J. Herbison %*Developing Ethernet Enhanced-Security System %f/crypto/zn0orvfaocqs3mbzfk6msde8hyplrcqn.pdf %md4de850a84809a2d8c31447b4cbbf8a3 %ccrypto %@D. G. Steer,L. Strawczynski,W. Diffie,M. Wiener %*A Secure Audio Teleconference System %f/crypto/cwtnzomp5kzbjrcag7qkswriqayfmsy2.pdf %m051900be5a786f558ddd96fd4ebaaa22 %ccrypto %@Bert den Boer %*Diffie-Hellman is as Strong as Discrete Log for Certain Primes %f/crypto/2q0kakbvyatlxfw1o8wjiomcth4ruqip.pdf %m8855c42fb3154804f55626b5cd0b8f53 %ccrypto %@Tzonelih Hwang,T. R. N. Rao %*Secret Error-Correcting Codes (SECC) %f/crypto/6nbnzqb3rxhvfcrykts4og9fejpsvi70.pdf %m538733ba48f5caa5879b679a2f07978d %ccrypto %@E. F. Brickell,D. R. Stinson %*The Detection of Cheaters in Threshold Schemes %f/crypto/nakug1emopf43b2qybahwsldhtvi7djt.pdf %m5a6bf8667f2bc5cb31cd8b3931e1dd41 %ccrypto %@Stuart A. Kurtz,Stephen R. Mahaney,James S. Royer %*On the Power of 1-way Functions %f/crypto/jzignlarvxybfwbo867m21dmg4zsa3lk.pdf %mf3b8ad76acde3387aff54f2c84bbc6b9 %ccrypto %@Gilles Brassard,Ivan Bjerre Damgaard %*“Practical IP” ⊆ MA %f/crypto/xqmavab5nr2g8toczenmpyzugiytpw9d.pdf %m0b8caed6966a56b41822c3ee92751880 %ccrypto %@Jørgen Brandt,Ivan Damgård,Peter Landrock,Torben Pedersen %*Zero-Knowledge Authentication Scheme with Secret Key Exchange %f/crypto/zg1e2a3opyfuxmyf8jolhduseqn0dimp.pdf %m4e383b743fb342a718e2d8b701ccdfde %ccrypto %@Wyn L. Price %*Standards for Data Security — a Change of Direction %f/crypto/s23na6vgklyev9qul8rxyzkfjrihtob7.pdf %m3d54cc09b979cce7815812ea9c38aa4c %ccrypto %@Kåre Presttun %*Integrating Cryptography in ISDN %f/crypto/gtfmrsfzj67qel2wpbgp8qn5xo9w1tsd.pdf %m071865db80b8ffee57cd8a3d63c3c15f %ccrypto %@Yvo Desmedt,Claude Goutier,Samy Bengio %*Special Uses and Abuses of the Fiat-Shamir Passport Protocol (extended abstract) %f/crypto/sm5lgptr8yhkbynx02exjvlfqzwuwgza.pdf %m960e26f4dc31599dcf10324425cb9d79 %ccrypto %@Russell Impagliazzo,Moti Yung %*Direct Minimum-Knowledge Computations (Extended Abstract) %f/crypto/pz7fzkvhrxk3d4ficqsoqjxw1a8yn5bv.pdf %m5472aa3bb1eb011d4610d5c850a081c7 %ccrypto %@Alfredo De Santis,Silvio Micali,Giuseppe Persiano %*Non-Interactive Zero-Knowledge Proof Systems %f/crypto/gzistlobjfnxkqlvqayje2ps4h8dk5ww.pdf %mc13465d36c5933f9cef7b1267836fbfe %ccrypto %@Oded Goldrcich,Ronen Vainish %*How to Solve any Protocol Problem - An Efficiency Improvement (Extended Abstract) %f/crypto/ytzcmsnfqcap2ghq6ludduekmwaorijb.pdf %m5cc58a784f1ad3a3a03dd2925cc186f3 %ccrypto %@David Chaum,Ivan B. Damgård,Jeroen van de Graaf %*Multiparty Computations Ensuring Privacy of Each Party’s Input and Correctness of the Result %f/crypto/qopibma6vv9za7jwtoj81bkqe4hkyitx.pdf %m1c66ce566bde54586382928d8e8dd008 %ccrypto %@Yvo Desmedt %*Society and Group Oriented Cryptography: a New Concept %f/crypto/bkkj5v9czsrgy1yt3lwnrajvdtp8xhhf.pdf %m59833803542e5f00d3eacd789b11b979 %ccrypto %@Jeroen van de Graaf,Renė Peralta %*A Simple and Secure Way to Show the Validity of Your Public Key %f/crypto/xn3bfgc0wexi1z9jtcesbyq4rnkaim6o.pdf %m468132a17e190ad7912168ab84cd2125 %ccrypto %@Zvi Galil,Stuart Haber,Moti Yung %*Cryptographic Computation: Secure Fault-Tolerant Protocols and the Public-Key Model (Extended Abstract) %f/crypto/p4znj2omc0axzdumble5tfgg6s3s8qoa.pdf %m3ea37e1c77208c9d14bed0b5da1fb1ab %ccrypto %@Ernest F. Brickell,David Chaum,Ivan B. Damgård,Jeroen van de Graaf %*Gradual and Verifiable Release of a Secret (Extended Abstract) %f/crypto/jtddmqzjg3xnafrezivkagye4lmos9c5.pdf %m79dcdbc06e7ae636608b69838a45b960 %ccrypto %@Judy H. Moore %*Strong Practical Protocols %f/crypto/2uoy8picvogwsvl7gxqaajrj3l4w60zb.pdf %m4997bd86723f7e576ebba60f6c668e52 %ccrypto %@Tsutomu Matsumoto,Hideki Imai %*On the KEY PREDISTRIBUTION SYSTEM: A Practical Solution to the Key Distribution Problem %f/crypto/2kxlzwpcbxpdnjqvalysr5ksmoyd6ea3.pdf %mac3d94f621ca0ea2feec2041eefebd90 %ccrypto %@Eiji Okamoto %*Key Distribution Systems Based on Identification Information %f/crypto/q6hq85j7eoxlgrnj2xwv4wszmpagttzp.pdf %m43b91e1850dae35c8b128460814a114e %ccrypto %@Jean-Jacques Quisquater %*Secret Distribution of Keys for Public-Key Systems %f/crypto/toevzsiuoqnxhmzbjha7g9wwkmkyt8lr.pdf %m4c7909de5433cf9d19d48c93e82f6ecb %ccrypto %@Gustavus J. Simmons %*An Impersonation-Proof Identity Verification Scheme %f/crypto/rmyovxuxsteaojf6r27s10ciw3pnekgk.pdf %m7c37188bf2f3ddee7fcb470a61aa4b72 %ccrypto %@George I. Davida,Brian J. Matt %*Arbitration in Tamper Proof Systems %f/crypto/4pilwno1sagyakdytxhd608vetgi5ncu.pdf %m4b8bc394d2319f6ebf2ea353fc613656 %ccrypto %@Louis Guillou,Jean-Jacques Quisquater %*Efficient Digital Public-Key Signatures with Shadow %f/crypto/ucdiae1bqlqlrm7ks0froav2ewgfysb6.pdf %me9bfee0377100db08d77d9d80e54672f %ccrypto %@Carlisle M. Adams,Henk Meijer %*Security-Related Comments Regarding McEliece’s Public-Key Cryptosystem %f/crypto/suvgkcq4ttygehdvjhjpuwpa82xi6clb.pdf %m99a538fb3a4f3cd9c47094a122ab2961 %ccrypto %@J. M. DeLaurentis %*Components and Cycles of a Random Function %f/crypto/tmjgdqu2q5nvohbripl0npal3tkjozbg.pdf %m895766778fa4c19241fb362a5a597661 %ccrypto %@Frank A. Feldman %*Fast Spectral Tests for Measuring Nonrandomness and the DES %f/crypto/vvl3fwmji6gkseapznbk7yr8xthgu10h.pdf %m93c9241c6bf8d60623348f8a5c2ecf48 %ccrypto %@Jean-Jacques Quisquater,Jean-Paul Delescaille %*Other Cycling Tests for DES %f/crypto/pm01yeucrijzbanf7qdtz5tckoy283qx.pdf %mc2f10b7a695b7452ccafd0113cc5ff48 %ccrypto %@George I. Davida,Frank B. Dancs %*A Crypto-Engine %f/crypto/urjhg7l8dgtsqytqpbl9eiimpnjvdwz5.pdf %mc4ae73a66a11e91f1376fce3a58b640f %ccrypto %@Gustavus J. Simmons %*A Natural Taxonomy for Digital Information Authentication Schemes %f/crypto/ujpdvbg08kgr7clzlesykdy21bqnefwn.pdf %mf8aaac6aec19050f89e58bbc10415d4f %ccrypto %@Richard A. Kemmerer %*Analyzing Encryption Protocols Using Formal Verification Techniques (Extended Abstract) %f/crypto/ufg1oxde7c3j49y5vf2lgnzpskmmohqn.pdf %m39ba8e7ae8546f4b1c54d0ea26fb5142 %ccrypto %@G. R. Blakley,William Rundell %*Cryptosystems based on an analog of heat flow %f/crypto/zpsf3ycvdoelymw20pbusar6jb1mvt5u.pdf %m7f960163b3b36b3ec4c0be2275bf0d5c %ccrypto %@D. R. Stinson,S. A. Vanstone %*A Combinatorial Approach to Threshold Schemes %f/crypto/dnpuhv5xdhwmeq3lflekgkpcvmrytzb6.pdf %m1e1f550349d0546acad84b25897c7e44 %ccrypto %@Hatsukazu Tanaka %*A Realization Scheme for the Identity-Based Cryptosystem %f/crypto/a6tfu7n5qk10elw3rjhfpsnlxk8guvmg.pdf %m629d29ccda0a7a29061d3959fb17586e %ccrypto %@Claude Crépeau %*Equivalence Between Two Flavours of Oblivious Transfers %f/crypto/mefwmdhqjjabz2xkevhc0rkzsno5b6fu.pdf %m614feeee308fdf6442b490a0d1ac620d %ccrypto %@D. R. Stinson %*A construction for authentication / secrecy codes from certain combinatorial designs %f/crypto/rbjmr5s9xjyuanwzyinbohmh0vlwepd7.pdf %mef6df5f29d16f28a8b573f68ac45093f %ccrypto %@Ralph C. Merkle %*A Digital Signature Based on a Conventional Encryption Function %f/crypto/90r8qzavg4tlpolx3y6vsq7toihbguxn.pdf %mbbf98f8547b790d5253f9fa1ec9c995f %ccrypto %@Maurice P. Herlihy,J. D. Tygar %*How to Make Replicated Data Secure %f/crypto/qecmp8jolzhnxoxwh71ftkqal2rfbri6.pdf %m1f1a7992221c69c33eeba73b2c2b2319 %ccrypto %@Michael Luby,Charles Rackoff %*A Study of Password Security %f/crypto/hz2rwm71uehd9slbfrxtnkxbqvlc0g8i.pdf %mc169b2624b9c07ae9e2359850c5a6766 %ccrypto %@Yossi Matias,Adi Shamir %*A Video Scrambling Technique Based On Space Filling Curves (Extended Abstract) %f/crypto/yg8rsfycbcs4jt3juhklpaod257kmvrx.pdf %m18c1372e4ed681236290285d85c05b40 %ccrypto %@E. F. Brickell,P. J. Lee,Y. Yacobi %*Secure Audio Teleconference %f/crypto/57gaoznqsbcwmrhfqrvoygp1hx0iinwe.pdf %m5e62744fdb0b74c7286674a4b714d2f7 %ccrypto %@Yacov Yacobi %*Attack on the Koyama-Ohta Identity Based Key Distribution Scheme %f/crypto/wxfjxhdp75kyskcfb1vz2ogzyjeqiamw.pdf %m85da7132a51c807770a79bd840cec45b %ccrypto %@Walter Fumy %*On the F-function of FEAL %f/crypto/kvyiw1gbgmedsq7um9nfpy6ke0jnahj8.pdf %mbf3edd326dfdb48269d44dc6a104b778 %ccrypto %@K. C. Zeng,J. H. Yang,Z. T. Dai %*Patterns of Entropy Drop of the Key in an S-Box of the DES (Extended Abtract) %f/crypto/lkyv5tjd0t39qgckb1izf2uypocaxgpw.pdf %mf61388dffc890d40bc03f1e620a13612 %ccrypto %@René Struik,Johan van Tilburg %*The Rao-Nam Scheme is Insecure Against a Chosen-Plaintext Attack %f/crypto/qtlh3ge58gizq7jucphws0mkrwosfvzx.pdf %m3e6e212f7a964f0713ab0bd814f3a84b %ccrypto %@T. R. N Rao %*On Struik-Tilburg Cryptanalysis of Rao-Nam Scheme %f/crypto/yvml7kghb8xcq9acjegwr10e6ru2tino.pdf %m11faf286f6bf5d97c520359ed5dd05da %ccrypto %@Pierre Beauchemin,Gilles Brassard %*A Generalization of Hellman’s Extension of Shannon’s Approach to Cryptography (Abstract) %f/crypto/ubhgiawlectxwdhbuo91aq8v6spkjtgp.pdf %m3b1bcc1f2199da92db526d5f030a3817 %ccrypto %@David Chaum,Claude Crépeau,Ivan Damgård %*Multiparty Unconditionally Secure Protocols (Abstract) %f/crypto/oa6p5xvluest47jmwr9gocf1t2kfei3h.pdf %mdc1afe390a609d4d240755120469a6c8 %ccrypto %@E. F. Brickell,J. H. Moore,M. R. Purtill %*Structure in the S-Boxes of the DES (extended abstract) %f/crypto/thfxvghdj2b7ujzpoy16o8mi4ac9sb5e.pdf %m1442ce6ce1439f24881d343836b3b920 %ccrypto %@Judy H. Moore,Gustavus J. Simmons %*Cycle Structure of the DES with Weak and Semi-Weak Keys %f/crypto/outqcjgk2eyvbnocr5a7sgjtfxli0kvw.pdf %m35757c29c93353bef87121bd7894eea3 %ccrypto %@T. R. N. Rao,Kil-Hyun Nam %*Private-Key Algebraic-Coded Cryptosystems %f/crypto/qg7flocw4915yradknafblpzkwhu0xmn.pdf %m54a494e6dfae79665e12c00e73ca446c %ccrypto %@Wiebren de Jonge,David Chaum %*Some Variations on RSA Signatures & their Security %f/crypto/9mtylhnek3wybovfxx8gnc5mg1ajitqu.pdf %mb21106a12f15efe75a18ed7216b3f497 %ccrypto %@N. S. James,R. Lidl,H. Niederreiter %*Breaking the Cade Cipher %f/crypto/o0gnw7xh9zwnrg5pftus14yrvmcsjq8l.pdf %m24bc31c785613d90afa0836867e18b74 %ccrypto %@John J. Cade %*A Modification of a Broken Public-Key Cipher %f/crypto/fykm6ct9xr43jd1lcke07bsuuaowpqiy.pdf %mc9e9fe550c7ba2ac80ec6b50dfa2acd8 %ccrypto %@Burton S. Kaliski %*A Pseudo-Random Bit Generator Based on Elliptic Logarithms %f/crypto/esi6tdlj7wklsz1gxw8erhn5oi2pyfpx.pdf %m71ab7b1db7133b61467ca87841b76499 %ccrypto %@Oded Goldreich %*Two Remarks Concerning the Goldwasser-Micali-Rivest Signature Scheme %f/crypto/rdk8gbewhwmcb1xt5yz9ldl7fqscikva.pdf %m5c4911f3c497e6799d033f2cbb3a18bc %ccrypto %@Yvo Desmedt,Jean-Jacques Quisquater %*Public-key Systems Based on the Difficulty of Tampering (Is there a difference between DES and RSA?) %f/crypto/sclraekzpgwvqdfbyplh7qxhjayu2uwn.pdf %me6a4c31ebdc045c92063cb0272ec45a5 %ccrypto %@David Chaum,Jan-Hendrik Evertse %*A Secure and Privacy-Protecting Protocol for Transmitting Personal Information Between Organizations %f/crypto/aigu6uo1myaxk2fjppltjql0nvtkcszw.pdf %m644a204150a68582a85fa42410fec60d %ccrypto %@Oded Goldreich,Silvio Micali,Avi Wigderson %*How to Prove All NP Statements in Zero-Knowledge and a Methodology of Cryptographic Protocol Design (Extended Abstract) %f/crypto/dlqerwg0bmynhlepn2zuyipzkxfotj4b.pdf %md64947c26993fcf5805a55192a520032 %ccrypto %@Amos Fiat,Adi Shamir %*How To Prove Yourself: Practical Solutions to Identification and Signature Problems %f/crypto/hjuvm9fizsbtaqyjperxp7wocst56nub.pdf %m1ed5c255525327916ef6e93774be5840 %ccrypto %@David Chaum %*Demonstrating that a Public Predicate can be Satisfied Without Revealing Any Information About How %f/crypto/bmcwh3lovezann9u6pb1ake5qdry8chr.pdf %mb00c9c8981e8efc5f95b157b3a25a840 %ccrypto %@David Chaum,Jan-Hendrik Evertse,Jeroen van de Graaf,René Peralta %*Demonstrating Possession of a Discrete Logarithm Without Revealing it %f/crypto/7vsydimoyjx0rfofbjtepwap1hh8ekg5.pdf %m76cd73e370741d9671925c2625d7bf2f %ccrypto %@Josh Cohen Benaloh %*Cryptographic Capsules: A Disjunctive Primitive for Interactive Protocols %f/crypto/p8grklzx2wfvvwiidod4ns17pmzbcshq.pdf %m4b226d037f49d776471a1ce029fcc03c %ccrypto %@Gilles Brassard,Claude Crepeau %*Zero-Knowledge Simulation of Boolean Circuits %f/crypto/09lkbcntntmgwaoeijoyv7hjv5a46idr.pdf %m4fca6467d59b81d36495fe6de27873ec %ccrypto %@Gilles Brassard,Claude Crepeau,Jean-Marc Robert %*All-or-Nothing Disclosure of Secrets %f/crypto/4wtotp0sref5omkyl8nbhznbgvvsiufe.pdf %mf2803f16483617d51035a392a2acbe1b %ccrypto %@Claude Crépeau %*A zero-knowledge Poker protocol that achieves confidentiality of the players’ strategy or How to achieve an electronic Poker face %f/crypto/mnjxck7lzteiacfnlx8kas9gujpoho15.pdf %mfc5c448d8b4cfdaf1592ce9a98ca99b4 %ccrypto %@Josh Cohen Benaloh %*Secret Sharing Homomorphisms: Keeping Shares of a Secret Secret (Extended Abstract) %f/crypto/p0ieztl2udshs6fm3c49mtinrvewc8qx.pdf %m9338a7f0d11d79782303a19be842e27a %ccrypto %@Martin Tompa,Heather Woll %*How to Share a Secret with Cheaters %f/crypto/2q4la6kfez0x8zcxkqen5f3ry1pslgh7.pdf %m7179ee2c4514662bab35a4b0af19c8aa %ccrypto %@G. R. Blakley,R. D. Dixon %*Smallest Possible Message Expansion in Threshold Schemes %f/crypto/tju0fiigctyozm71wdvkljx2obbnrqxh.pdf %mdba876d0b13763a4214c913c3c088575 %ccrypto %@G. A. Orton,M. P. Roy,P. A. Scott,L. E. Peppard,S. E. Tavares %*VLSI implementation of public-key encryption algorithms %f/crypto/khcjov4vertpfuwbaja06gsynunrdze1.pdf %mc9ce74db96f2d35c587d9efc5ac66ef5 %ccrypto %@T. Beth,B. M. Cook,D. Gollmann %*Architectures for exponentiation in GF(2n) %f/crypto/nfnhsxrqgsd5gwp809zpifuhlkeaczj1.pdf %m82d3936c1d42134079dff7459a6f951a %ccrypto %@Paul Barrett %*Implementing the Rivest Shamir and Adleman Public Key Encryption Algorithm on a Standard Digital Signal Processor %f/crypto/uksi4dkdrqg20jfiwcvnnveyhq37myom.pdf %m0fdd69efc97767fc0e8b86cc552e3475 %ccrypto %@Robert R. Jueneman %*A High Speed Manipulation Detection Code %f/crypto/lacdhi4akb3beg6yqojsstiunmcy0ptd.pdf %m432bf8cf76c0f21192d3e44fa88227cd %ccrypto %@Ralph Gyoery,Jennifer Seberry %*Electronic Funds Transfer Point of Sale in Australia %f/crypto/hazzq38jrpsnmn2fmypxhi76jlvecvt5.pdf %m2305349187853b6e333195dc836ba077 %ccrypto %@Silvio Micali,Charles Rackoff,Bob Sloan %*The Notion of Security for Probabilistic Cryptosystems (Extended Abstract) %f/crypto/xmqybqgd6k2bepu9gejajx5k0ozdlsso.pdf %m1e4a90886537055f5434bb917588cdd7 %ccrypto %@Neal R. Wagner,Paul S. Putter,Marianne R. Cain %*Large-Scale Randomization Techniques %f/crypto/s2tv0wfof7mqly4bjribq3k9hchli6vn.pdf %m3bc4c3fcff370d15f4ec4626ef82500d %ccrypto %@Agnes Hui Chan,Richard A. Games %*On the Linear Span of Binary Sequences Obtained from Finite Geometries %f/crypto/veuimnq8bzsu6ojf3dswpalvtkh2bq9p.pdf %md7d975fee69a2bfa98565d453d91076d %ccrypto %@D. R. Stinson %*Some Constructions and Bounds for Authentication Codes %f/crypto/ghmni76db0g89vrafcojz4naiwumrxjy.pdf %mb5998af68b5cf14dd372f93540e7514d %ccrypto %@Oded Goldreich %*Towards a Theory of Software Protection (Extended Abstract) %f/crypto/w4ndpkoyoiermghbxuimtdjg78hcaky6.pdf %m487aa461b77d87e26f4b7760fd4b68e0 %ccrypto %@Pierre Beauchemin,Gilles Brassard,Claude Crépeau,Claude Goutier %*Two Observations on Probabilistic Primality Testing %f/crypto/m9ea4otvzhk3cebnig1tmyuhxsislx0p.pdf %m227934ea660f2197fcc659ae7f61f2e3 %ccrypto %@Stephen M. Matyas %*Public Key Registration %f/crypto/seswy2iygrfzaokbi3e1h5mdkfunxjla.pdf %m5a558a51cd93ca46bb673ce2e83ef80a %ccrypto %@Yvo Desmedt %*Is there an ultimate use of cryptography? (Extended Abstract) %f/crypto/4wydim9tqxmtze5c0hobagfub2kv3apd.pdf %meca6db145cc8505f8e2132e9639572be %ccrypto %@Louis C. Guillou,Michel Ugon %*Smart Card a Highly Reliable and Portable Security Device %f/crypto/ze5k8nrtejfdu9vhwulxb4bfpl6tshco.pdf %m06d60c8998f9d9a8a0732bf1d5ae7b67 %ccrypto %@Gordon Rankine %*Thomas — A Complete Single Chip RSA Device %f/crypto/5ismcg7rn648opjxa0jfvzpiots1vmda.pdf %m30a142495647e19a0468690a4e5ef943 %ccrypto %@Dennis Estes,Leonard M. Adleman,Kireeti Kompella,Kevin S. McCurley,Gary L. Miller %*Breaking the Ong-Schnorr-Shamir Signature Scheme for Quadratic Number Fields %f/crypto/1bqlneb8pnzxoc37dawitgjkuhcrxkho.pdf %m0ec01bc4764d99874b74a4a069d7f089 %ccrypto %@Don Coppersmith %*Another Birthday Attack %f/crypto/ditw4oihmyycoa6unkqge8rlun95es1b.pdf %m3ccd28d570e7c5bf0f665d7f40dc6058 %ccrypto %@Wiebren de Jonge,David Chaum %*Attacks on Some RSA Signatures %f/crypto/qz7uuhran65gasorwkx2knocdj3lil9w.pdf %m9d61c134f328436a35573dc1fa42fb89 %ccrypto %@Ernest F. Brickell,John M. DeLaurentis %*An Attack on a Signature Scheme Proposed by Okamoto and Shiraishi %f/crypto/dywhvqw2exanpby1k0oumjt3kudvhcfl.pdf %mcf875f739772a3ef6b515f71e2d0aee3 %ccrypto %@Gustavus J. Simmons %*A Secure Subliminal Channel (?) %f/crypto/bc7oalbwwg01fezp9ixyuzpfrahstqlr.pdf %mbe311a95962aadaea32a5a94a84b5712 %ccrypto %@Yvo Desmedt %*Unconditionally Secure Authentication Schemes and Practical and Theoretical Consequences %f/crypto/nocjhwwd2uxiqbettqp15yvflpa8d6hk.pdf %mf301b2d5f591813c59072d3de67f27d6 %ccrypto %@Shimon Even,Oded Goldreich,Adi Shamir %*On the Security of Ping-Pong Protocols when Implemented using the RSA (Extended Abstract) %f/crypto/j7asnihfeawwcz6pi3l12puqznmkeyqc.pdf %mf6ad648fe40ce2c0938c8ff7b494779b %ccrypto %@Claude Crépeau %*A Secure Poker Protocol that Minimizes the Effect of Player Coalitions %f/crypto/bmc27xslryydtvijfn1lkkthq4r0mupa.pdf %mf642989d65799caa3a09bba5020771cb %ccrypto %@Richard Berger,Sampath Kannan,René Peralta %*A Framework for the Study of Cryptographic Protocols %f/crypto/5f6yvczltdpsixmyk1wuqd3ml2jjagoz.pdf %mb18c1b2370a7d620038e1b475a7da9a1 %ccrypto %@Don Coppersmith %*Cheating at Mental Poker %f/crypto/f9zwxh4ua6vt7ahgnblyofj1q3sm52zn.pdf %mbe4e3c29c922ee0d5d3de6987aa41878 %ccrypto %@Whitfield Diffie %*Security for the DoD Transmission Control Protocol %f/crypto/qhciwtrk62dawpoxvv3jmkcf45angmoz.pdf %m8976676ff7cb1ff8046adff5e8a2faa8 %ccrypto %@Zvi Galil,Stuart Haber,Moti Yung %*Symmetric Public-Key Encryption %f/crypto/entqbtbgievj2szjdwsfycpymf8ilq5d.pdf %me5af576d295ef409a2b1fae1a1f97bc5 %ccrypto %@James R. Gosler %*Software Protection: Myth or Reality? %f/crypto/h9ojyptb06hjfcmz7ulesvdwagtdufpr.pdf %m0ea73d697c99a6c114042d23b2534e9e %ccrypto %@Amir Herzberg,Shlomit S. Pinter %*Public Protection of Software %f/crypto/7dxqhcpv2tyfrsavruojznhqbzmjbtio.pdf %m486ead0cd10612142c0b00d056452ee5 %ccrypto %@G. R. Blakley,C. Meadows,G. B. Purdy %*Fingerprinting Long Forgiving Messages %f/crypto/93md8bkcmsppx5sry2l0yi4fcegjv1lw.pdf %m46e103c5fcacb5c557b51528edd4c513 %ccrypto %@David Chaum,Jan-Hendrik Evertse %*Cryptanalysis of des with a Reduced Number of Rounds %f/crypto/a2m35wuig9by4jnvonlk1kw0rmeq6spp.pdf %m3998892f524e82612e971f4018d122ef %ccrypto %@Burton S. Kaliski,Ronald L. Rivest,Alan T. Sherman %*Is DES a Pure Cipher? (Results of More Cycling Experiments on DES) (Preliminary Abstract) %f/crypto/muovl24hskyax35scfu1gnrwpt6zezvx.pdf %me3596cfdac440c07459bda3e48511a3c %ccrypto %@T. E. Moore,S. E. Tavares %*A Layered Approach to the Design of Private Key Cryptosystems %f/crypto/mklofvyj97crs5gi1z4coxb2gdfvmtin.pdf %m38d8521eecb796f9caecb0e975173eb4 %ccrypto %@E. Okamoto,K. Nakamura %*Lifetimes of Keys in Cryptographic Key Management Systems %f/crypto/2dsm9uqia4e6elwdvb3g8xb0fyzkspjq.pdf %m48e891d958ca9bcf8caa9955fffdb919 %ccrypto %@Rainer A. Rueppel %*Correlation Immunity and the Summation Generator %f/crypto/k5sdn2ewqvtyfcplq1w3rvazekpzj70f.pdf %ma79595f4d18ee9e6425866163bba9775 %ccrypto %@T. Siegenthaler %*Design of Combiners to Prevent Divide and Conquer Attacks %f/crypto/weazy0ghub13gzxd2h9pk784vdikottl.pdf %m9ecce2c19104cf891624e1c107df0f62 %ccrypto %@Adi Shamir %*On the Security of DES %f/crypto/dap04hsbk9jlsmkvfcvie6um7ncj2or3.pdf %md8d0ecf33f9a33b7c03ff582bfd63aad %ccrypto %@G. R. Blakley %*Information theory without the finiteness assumption, II. Unfolding the DES %f/crypto/yqaydomgflx2anu5k1huijpkvtxz0wne.pdf %m9bcf322f8327a97e717047305f005365 %ccrypto %@Harriet Fell,Whitfield Diffie %*Analysis of a Public Key Approach Based on Polynomial Substitution %f/crypto/u6vxaroejorhdjzx3ki98ta1hpmugwy7.pdf %me7b01d7e9627689e8afd8aba884db175 %ccrypto %@Martin Kochanski %*Developing an RSA Chip %f/crypto/xl2wm3sfobv49folhtugrdv0tenipjyg.pdf %m8587eb133145b25e42e0cb4bae8d4ce1 %ccrypto %@H. C. Williams %*An M3 Public-Key Encryption Scheme %f/crypto/2svh4ougmjgd3siarcabplc86xnv5qfb.pdf %m745426858560d72b99870be873f55b17 %ccrypto %@V. Varadharajan %*Trapdoor Rings And Their Use In Cryptography %f/crypto/tqmwloj286c1drvb7pjzq9mitihpeac5.pdf %ma0a388fed1147f0a95af35e3bfd6d733 %ccrypto %@Taher ElGamal %*On Computing Logarithms Over Finite Fields %f/crypto/ksezg4j859oxubbmrnanilclfqs0dpto.pdf %m34a7812b81418fe9383c627d4cc91d07 %ccrypto %@Johan Hastad %*N Using RSA with Low Exponent in a Public Key Network %f/crypto/rlfwksjqver2gch0dxtdypzlzii57oas.pdf %m6830edfe9b8ca3dd4982c87c66e81ebf %ccrypto %@N. M. Stephens %*Lenstra’s Factorisation Method Based on Elliptic Curves %f/crypto/twlxurzwmvzg1378rmlsqyjhek45cjp9.pdf %m783229fa365d39b34691bc9eabcbc2af %ccrypto %@Victor S. Miller %*Use of Elliptic Curves in Cryptography %f/crypto/2kyzxpw46rniiede7glbhqusnzcku1vb.pdf %m72f83f016d91e205cb2d0c4becba70a6 %ccrypto %@Stephen Wolfram %*Cryptography with Cellular Automata %f/crypto/mdx7zidctcynlrj1walvor0hahut8qe3.pdf %maea2894f36f0a84a1c31ebfdad071bf0 %ccrypto %@J. H. Reif,J. D. Tygar %*Efficient Parallel Pseudo-Random Number Generation %f/crypto/62gslcziovrq1wbecopvzusmalyqnbd4.pdf %m4cc2ef47599e2cc8fa0bce182eea228b %ccrypto %@Michael Luby,Charles Rackoff %*How to Construct Pseudo-random Permutations from Pseudo-random Functions %f/crypto/smxbe8iffhapmr3ck7jnpeykdwl6vu0g.pdf %m12c849bc6a049f0cd8c582bd4a180cf7 %ccrypto %@Benny Chor,Oded Goldreich,Shafi Goldwasser %*The Bit Security of Modular Squaring given Partial Factorization of the Modulos %f/crypto/d6no3gt4eujcrwcuvhfbn2vjsrqopaak.pdf %m5ebd080821fefe45288a6eae990a0b5e %ccrypto %@Philippe Godlewski,Gerard D. Cohen %*Some Cryptographic Aspects of Womcodes %f/crypto/iwc4yldnkexo25tm0ltfrgpjqafxyowz.pdf %m15f99b7fd98f271d9b8758fa70b1db25 %ccrypto %@Charles H. Bennett,Gilles Brassard,Jean-Marc Robert %*How to Reduce your Enemy’s Information (extended abstract) %f/crypto/n3lwmbsvmnjt9dakjpeqvxh4xkepy2ug.pdf %ma6d96df51a4f298717c4e8a8f8dfb92a %ccrypto %@Joan Feigenbaum %*Encrypting Problem Instances %f/crypto/od2xeqj0uhlb8mrpypktfhmc1ngjiwyd.pdf %m3d3a26293064f8969e2415476e2c2953 %ccrypto %@Johan van Tilburg,Dick E. Boekee %*Divergence Bounds on Key Equivocation and Error Probability in Cryptanalysis %f/crypto/tdzwr9bgafiqshklxcbm8wos6l1y4frj.pdf %mca630df367a12c23d028678287cf7d8e %ccrypto %@Y. Desmedt,A. M. Odlyzko %*A chosen text attack on the RSA cryptosystem and some discrete logarithm schemes %f/crypto/qtjr2a4asv6bxdfetkgnyvlehdjccyup.pdf %m1136576573d25a90d66a29aa9d19968d %ccrypto %@A. F. Webster,S. E. Tavares %*On the Design of S-Boxes %f/crypto/i0xpdeklshunmpa623zrjwyzffynjkxm.pdf %m268e933e0888ef04ced27fa482641dd0 %ccrypto %@Don Coppersmith %*The Real Reason for Rivest’s Phenomenon %f/crypto/soecrqhgnmkiqfmlfwzj5txu2yy1wn7p.pdf %md2aaeb92c193529c3baf635f5e4c1bab %ccrypto %@Jean-Jacques Quisquater,Yvo Desmedt,Marc Davio %*The Importance of “Good” Key Scheduling Schemes (How to Make a Secure DES* Scheme with ≤ 48 Bit Keys?) %f/crypto/vo0ipdobxe4tpymxjiu1trw9zd5fgz2c.pdf %macc89eacf2cab15c66a86773c77f5ebf %ccrypto %@Willem Haemers %*Access Control at the Netherlands Postal and Telecommunications Services %f/crypto/4fxqig2d7omygql1nj8srbhl6ef0pzjo.pdf %md6b1dd482dfb95dcbe2a25e3483bbe90 %ccrypto %@S C Serpell,C B Brookson,B L Clark %*A Prototype Encryption System Using Public Key %f/crypto/ekyaso0vgkx953ic17vdpefx2pnrjgtu.pdf %m6b599c0889ce1f39d8b218ad70d20273 %ccrypto %@Taher ElGamal %*A Public Key Cryptosystem and a Signature Scheme Based on Discrete Logarithms %f/crypto/jnimcpqyn738uigwm4ldztkoeresa0fq.pdf %md692b218ebcd15efa76c4229c5028d60 %ccrypto %@Neal R. Wagner,Marianne R. Magyarik %*A Public-Key Cryptosystem Based on the Word Problem %f/crypto/quvfuabhaprn5zqnxwgmedkrf29kjtzo.pdf %m4bd50ee61ab87f3feb0893bf55ecec4a %ccrypto %@H. Ong,C. P. Schnorr,A. Shamir %*Efficient Signature Schemes Based on Polynomial Equations (preliminary version) %f/crypto/bwhftw76zpigcehsqm4zl9qka1ynx5ve.pdf %me80d745998c88f071fd62e121c4fd277 %ccrypto %@Adi Shamir %*Identity-Based Cryptosystems and Signature Schemes %f/crypto/utguvhw91jdp5n86recmlbotpqjqeawd.pdf %ma614fb1ba7088f3ff93a14bc3957430c %ccrypto %@Benny Chor,Ronald L. Rivest %*A Knapsack Type Public Key Cryptosystem Based On Arithmetic in Finite Fields (preliminary draft) %f/crypto/9nmdfqcfxenhh3gbgr2d8miyk47laxtu.pdf %m48bba4f83ad0c6c4bb900e602c7cc493 %ccrypto %@H. C. Williams %*Some Public-Key Crypto-Functions as Intractable as Factorization %f/crypto/opqk6ozunwesncjz9g2xfhy57l34iyqa.pdf %md331595e652c6b9fa2d3b356c4d77de4 %ccrypto %@I. F. Blake,R. C. Mullin,S. A. Vanstone %*Computing Logarithms in GF (2n) %f/crypto/rgunmnrhz1fkxpldbvlaso3vj5e4ic7g.pdf %m4dd6004057e2621a29c6097affb9d2f6 %ccrypto %@Burt S. Kaliski %*Wyner’s Analog Encryption Scheme: Results of a Simulation %f/crypto/23ql5uua0mebtxki9xnejlfmwhfhq14s.pdf %mc2034e534c29334fc6fc35869b4ade50 %ccrypto %@Su-shing Chen %*On Rotation Group and Encryption of Analog Signals %f/crypto/abuahcpygbenjfuqvspr49dw8qlvx3iy.pdf %m238621583cc28542282582bd2c044945 %ccrypto %@Albert C. Leighton,Stephen M. Matyas %*The History of Book Ciphers %f/crypto/iahkpgstfvyobvqr4j7lpcfhg23by9u8.pdf %m6968a39fd96af1f451f04f9454d5224f %ccrypto %@J. A. Davis,D. B. Holdridge %*An Update on Factorization at Sandia National Laboratories %f/crypto/k50g7pdkjrucaejgrlinps2hfdfyzxmb.pdf %m901167784bf099cee7d23766becfc944 %ccrypto %@R. C. Fairfield,A. Matusevich,J. Plany %*An LSI Digital Encryption Processor (DEP) %f/crypto/zbvsn01guzegsco5rp9e8uynjiji4oba.pdf %m0476de1071eb766a84649d061eb9db8e %ccrypto %@Marc Davio,Yvo Desmedt,Jo Goubert,Frank Hoornaert,Jean-Jacques Quisquater %*Efficient hardware and software implementations for the DES %f/crypto/evhq76mjbxdjcik9t3yevxmqch82tu0y.pdf %m5635a827284db907fc60e387d2523991 %ccrypto %@Frank Hoornaert,Jo Goubert,Yvo Desmedt %*Efficient hardware implementation of the DES %f/crypto/v7c8sw9ofqd6lm1kandrz4y2lqiuvftk.pdf %mdc96b74ccbeb038f76a635628b468fef %ccrypto %@Norman Proctor %*A Self-Synchronizing Cascaded Cipher System with Dynamic Control of Error Propagation %f/crypto/w76xcmtvl1iep5scysix02vzz8pmqajy.pdf %m3e19357b7715f3beabe41d06f0657257 %ccrypto %@Umesh V. Vazirani,Vijay V. Vazirani %*Efficient and Secure Pseudo-Random Number Generation (Extended Abstract) %f/crypto/ejyzkxkgovd5rtgq2qxpsojnw1d0f8lb.pdf %me404c88e28a879f9b382ed602ea0c9b6 %ccrypto %@R. C. Fairfield,R. L. Mortenson,K. B. Coulthart %*An LSI Random Number Generator (RNG) %f/crypto/fi0kpczyyhmtbmxvsh6ufwvgb4oqs2an.pdf %mf2863bb5673329c4f61be64bede2b4d9 %ccrypto %@S. C. Kothari %*Generalized Linear Threshold Scheme %f/crypto/1ojvwc7byramav4rxttbkeoqs952k8dl.pdf %mfc896d563942a1d40d3d7dcefab6a093 %ccrypto %@G. R. Blakley,Catherine Meadows %*Security of Ramp Schemes %f/crypto/ndgj9rqonufsh6u0tb8zwctyspeydeaw.pdf %mab8de69f539c757b11b5bc0f7d0246fe %ccrypto %@Selim G. Akl,Henk Meijer %*A Fast Pseudo Random Permutation Generator With Applications to Cryptology %f/crypto/y4pf0dkvtru586aj9srwsoithluoncpe.pdf %m2e230548c5b047319fbfd0c9ba8797c4 %ccrypto %@Oded Goldreich,Shafi Goldwasser,Silvio Micali %*On the Cryptographic Applications of Random Functions (Extended Abstract) %f/crypto/dg5ckovpqaexqifnlghw9wfbn1uztryo.pdf %m24d34ef3f9ef1db6c36686063011cdc4 %ccrypto %@Manuel Blum,Shafi Goldwasser %*An Efficient Probabilistic Public-Key Encryption Scheme Which Hides All Partial Information %f/crypto/qfjrx6g1hebkdfckxaztsvpnublhv9p8.pdf %m6d5c90ee730ab85dcfcf811af114ffe9 %ccrypto %@Benny Chor,Oded Goldreich %*RSA/Rabin least significant bits are \tfrac{1} {2} + \tfrac{1} {{poly \left( {\log N} \right)}} secure (Extended Abstract) %f/crypto/kvbl79pnmaiijn0p52tc86xcav1jozhu.pdf %mdf14a91e0c41e24c05dde49445a71878 %ccrypto %@G. R. Blakley %*Information Theory without the Finiteness Assumption, I: Cryptosystems as Group-Theoretic Objects %f/crypto/xfmt7apfzjkl1b4josp2iocg5szbal0i.pdf %m8f73993480488431cca5f632f7a3cefb %ccrypto %@Alan G. Konheim %*Cryptanalysis of Adfgvx Encipherment Systems %f/crypto/gh6wsteubwcp01dqziajvozb74y3fdck.pdf %m44600ad42bf9bae7a5bdf24d964f5f10 %ccrypto %@Ernest F. Brickell %*Breaking Iterated Knapsacks %f/crypto/gygiysli2wfpxmj68bzmcrvjw3eefurz.pdf %mb8535516435b6cf83cdddf15350a3914 %ccrypto %@Yvo Desmedt,Jean-Jacques Quisquater,Marc Davio %*Dependence of output on input in DES: Small avalanche characteristics %f/crypto/sfhrrfnkemaw5ljod3gz1dtu0aecqq8o.pdf %m057a1c218ebdc7460a8fcb60f07b1e07 %ccrypto %@J. A. Reeds,J. L. Manferdelli %*Des has no Per Round Linear Factors %f/crypto/m3yw2u1x9butiokgd5lg7rjzyxcqwbtj.pdf %mdd2f9b1ecee87f8be956eba72f96aeb7 %ccrypto %@Donald Watts Davies %*A Message Authenticator Algorithm Suitable for a Mainframe Computer %f/crypto/vqkqgjnicprme4hcntb7psmz93alutda.pdf %m2c7a89b73e4ba5de45087d81f2ad901a %ccrypto %@Henry Beker,Michael Walker %*Key Management for Secure Electronic Funds Transfer in a Retail Environment %f/crypto/cmvkpwvmyjsbdul95xznn6fhrhlgri4o.pdf %mec12d191963ca7cd71db52ddda807d16 %ccrypto %@Gustavus J. Simmons %*Authentication Theory/Coding Theory %f/crypto/nxzqiuqodsihsg45hb69ed2ljcmp3yfa.pdf %meb776d5feb5c0ac185d28b68d742e3a7 %ccrypto %@David Chaum %*New Secret Codes Can Prevent a Computerized Big Brother %f/crypto/ahavdoki6tupx3iyhqrkyeq8ln4lbwmu.pdf %mdf16ee7cebc7fd8eba2c49716249383b %ccrypto %@Tom Tedrick %*Fair Exchange of Secrets (extended abstract) %f/crypto/awmq6w3ehtmxu4zsvypvkxjs0pi9bjor.pdf %me066c89db1194d2cd61536a42a1df457 %ccrypto %@Mordechai Yung %*Cryptoprotocols: Subscription to a Public Key, The Secret Blocking and The Multi-Player Mental Poker Game (extended abstract) %f/crypto/qxnibzmqzaad3x6rwmfldp045hwebv17.pdf %mfc5d4b8696eb8cb02667165cba9f09fa %ccrypto %@Steven Fortune,Michael Merritt %*Poker Protocols %f/crypto/e0mki1vptkfyowunudsaoqg3hqi9jjtv.pdf %mba5e54e3ebfca4c7aedb24f3c4674867 %ccrypto %@Shafi Goldwasser,Silvio Micali,Ronald L. Rivest %*A “Paradoxical” Solution to The Signature Problem %f/crypto/5okl01o8h2bhzuiv3ypnysw6jmuxefgg.pdf %mcb4a9feee00f44dea9d1c916d7083d90 %ccrypto %@A. K. Leung,S. E. Tavares %*Sequence Complexity as a Test for Cryptographic Systems %f/crypto/2iklypmxm8d53jqgvlowc6vdohaepnt1.pdf %m191778a2fa0dcc61d1561daa67153205 %ccrypto %@Charles H. Bennett,Gilles Brassard %*An Update on Quantum Cryptography %f/crypto/scul64glm07sjeudzvry32xhimepq5tx.pdf %mb9b387607f655886abed2399701c045d %ccrypto %@David Chaum %*How to Keep a Secret Alive %f/crypto/nj6oxfetcpqijdga0rml8ud23sq59gyk.pdf %m10c01c35ff8158fed5f567739d419aa5 %ccrypto %@Paul Kirchner,Pierre-Alain Fouque %*Revisiting Lattice Attacks on Overstretched NTRU Parameters %f/eurocrypt/96mgni8sdcgvqkj5w20of4h1lipkldze.pdf %m84d735bba0bcb2e4b5e778ce10026ce4 %ceurocrypt %@Jens Bauch,Daniel J. Bernstein,Henry de Valence,Tanja Lange,Christine van Vredendaal %*Short Generators Without Quantum Computers: The Case of Multiquadratics %f/eurocrypt/ztqq38esajyybbcixfnf40metgupa2lh.pdf %me9a7b3dff0094bbdaec78db4da1c4fca %ceurocrypt %@Jean-François Biasse,Thomas Espitau,Pierre-Alain Fouque,Alexandre Gélin,Paul Kirchner %*Computing Generator in Cyclotomic Integer Rings %f/eurocrypt/bjxhdv1xpwskruohjmqym837ficptwlo.pdf %m3a423425bb9ef044dbbff4e8cafb5792 %ceurocrypt %@Prabhanjan Ananth,Aayush Jain,Amit Sahai %*Robust Transforming Combiners from Indistinguishability Obfuscation to Functional Encryption %f/eurocrypt/4xiyznrlq8kalnzdrpsd1wchuvoe6taj.pdf %mea282e663f46d532f494d0ca0d31f677 %ceurocrypt %@Ilan Komargodski,Gil Segev %*From Minicrypt to Obfustopia via Private-Key Functional Encryption %f/eurocrypt/zl3mlorejcrghqhu7binxak9yo5zp04s.pdf %mba64c94e98a90ab27ff5327fcefec591 %ceurocrypt %@Prabhanjan Ananth,Amit Sahai %*Projective Arithmetic Functional Encryption and Indistinguishability Obfuscation from Degree-5 Multilinear Maps %f/eurocrypt/ucjvreubgmsx2xh05kpm8fn7yg4aidet.pdf %m81dcbfeeb7806137b49a06f621fee782 %ceurocrypt %@Thorsten Kleinjung,Claus Diem,Arjen K. Lenstra,Christine Priplata,Colin Stahlke %*Computation of a 768-Bit Prime Field Discrete Logarithm %f/eurocrypt/ogunm3tejzxdqte0ww8gb57lrxyojapp.pdf %mb6ff84d145ddd6afaf8d7d096bc509be %ceurocrypt %@Joshua Fried,Pierrick Gaudry,Nadia Heninger,Emmanuel Thomé %*A Kilobit Hidden SNFS Discrete Logarithm Computation %f/eurocrypt/fkjgwinlvpwzx79ttbhr1xd3arqegsic.pdf %m4444e274c914deacfbe27453ba51ed68 %ceurocrypt %@Peter Rindal,Mike Rosulek %*Improved Private Set Intersection Against Malicious Adversaries %f/eurocrypt/wexyq2h90tjscyinvoukmqvppflezia3.pdf %m218281a84c8540f5c0992ecdcf8fa68e %ceurocrypt %@Rafael Pass,Elaine Shi,Florian Tramèr %*Formal Abstractions for Attested Execution Secure Processors %f/eurocrypt/tdqn6sga0duv5xglw7rrup9ka1omyih4.pdf %m335a3b722beb37a9bd2734797f196d02 %ceurocrypt %@Vadim Lyubashevsky,Gregory Neven %*One-Shot Verifiable Encryption from Lattices %f/eurocrypt/kvqvxxwam7j9hdf10hsglezk5otjzr6n.pdf %mb0118c5c7f5fac931af9f672d9e91d08 %ceurocrypt %@Ronald Cramer,Léo Ducas,Benjamin Wesolowski %*Short Stickelberger Class Relations and Application to Ideal-SVP %f/eurocrypt/mmh3wpc8zcgq0xsyjivwoufjn5xdtbas.pdf %m292a9c47f13fd82b4882650cf1da0f0f %ceurocrypt %@Brandon Broadnax,Nico Döttling,Gunnar Hartung,Jörn Müller-Quade,Matthias Nagel %*Concurrently Composable Security with Shielded Super-Polynomial Simulators %f/eurocrypt/odsgyxwzkvupkdtxgayanb36zjq1rm42.pdf %m4ca2c771ab332ff888b9fd6c99f8206c %ceurocrypt %@Saikrishna Badrinarayanan,Dakshita Khurana,Rafail Ostrovsky,Ivan Visconti %*Unconditional UC-Secure Computation with (Stronger-Malicious) PUFs %f/eurocrypt/zinq6csejxuakmk2gnulqg8vjhfoery1.pdf %mac2c9da597eab373ee349ab0fb99f3fb %ceurocrypt %@Dan Boneh,Sam Kim,Hart Montgomery %*Private Puncturable PRFs from Standard Lattice Assumptions %f/eurocrypt/eomxjmacji64f0q1czflvvp7khqkba3x.pdf %m171043fe6a1c7d0081cc52f16a9b84f7 %ceurocrypt %@Ran Canetti,Yilei Chen %*Constraint-Hiding Constrained PRFs for NC^1 from LWE %f/eurocrypt/8fzk6es2oignip9qugnc31ubfatwxhca.pdf %ma420c9271850461e8478cd4180478fe5 %ceurocrypt %@Ronald Cramer,Ivan Damgård,Chaoping Xing,Chen Yuan %*Amortized Complexity of Zero-Knowledge Proofs Revisited: Achieving Linear Soundness Slack %f/eurocrypt/jhauqdftx8c3sl56kgiiazxzbc21bnho.pdf %mac914940e6b8e99ed927f4179a45a531 %ceurocrypt %@Payman Mohassel,Mike Rosulek,Alessandra Scafuro %*Sublinear Zero-Knowledge Arguments for RAM Programs %f/eurocrypt/x3lnotmilehgegidpq4fobucbm5qhf21.pdf %m63770326ee66ead98fea8a229a1b7d67 %ceurocrypt %@Gilles Barthe,François Dupressoir,Sebastian Faust,Benjamin Grégoire,François-Xavier Standaert,Pierre-Yves Strub %*Parallel Implementations of Masking Schemes and the Bounded Moment Leakage Model %f/eurocrypt/d8ospiyzf5bhq1tlijnsbapgetuywnfm.pdf %md665fbc4dee8b1a237f38f74809d9c6a %ceurocrypt %@Dahmun Goudarzi,Matthieu Rivain %*How Fast Can Higher-Order Masking Be in Software? %f/eurocrypt/sfcghfutpqwiakqb0m2zvsxwty8ru6r4.pdf %m430597336f369cf1754af33cedb94e59 %ceurocrypt %@Michel Abdalla,Romain Gay,Mariana Raykova,Hoeteck Wee %*Multi-input Inner-Product Functional Encryption from Pairings %f/eurocrypt/i2dazblwtzo7m8gcg1xjptpdshs94rqb.pdf %m92e889be6e42bc5fe8c1f8b18605aada %ceurocrypt %@Shashank Agrawal,Melissa Chase %*Simplifying Design and Analysis of Complex Predicate Encryption Schemes %f/eurocrypt/oekoqdqzt9u5mbvip8sc03afhk1n2cgp.pdf %m39203f2ff2ba17eee51c4024624dc16d %ceurocrypt %@David Kohel %*Twisted {\mu }_4-Normal Form for Elliptic Curves %f/eurocrypt/eujunqlfnw8kbaqlwzbaprhmd320sc4x.pdf %mdc7b311354d93c36d4bbe172f9448409 %ceurocrypt %@Craig Costello,David Jao,Patrick Longa,Michael Naehrig,Joost Renes,David Urbanik %*Efficient Compression of SIDH Public Keys %f/eurocrypt/g7xfzoa9cv81e4b2iuk0vdzqieptjkog.pdf %m49e559fa4c3bd0e3009f7ec1cfaa2387 %ceurocrypt %@Nir Bitansky,Huijia Lin,Omer Paneth %*On Removing Graded Encodings from Functional Encryption %f/eurocrypt/yh5papzskxqoof0ermdeyqvjwtmlzw69.pdf %m76d25c61cfe4aa502bb9831dc9291dc6 %ceurocrypt %@Shashank Agrawal,David J. Wu %*Functional Encryption: Deterministic to Randomized Functions from Simple Assumptions %f/eurocrypt/3ghvryjplw6ifk2e5ssat9ejvcbhk4xq.pdf %mb8526b07abe57c160e4eb6b36e222533 %ceurocrypt %@Yoshinori Aono,Phong Q. Nguyen %*Random Sampling Revisited: Lattice Enumeration with Discrete Pruning %f/eurocrypt/2lkhxxsorks0cu8j46grqiwetb9m3qbz.pdf %mfd1fb9b6f1099e4a1636fe98c9d0dc67 %ceurocrypt %@Martin R. Albrecht %*On Dual Lattice Attacks Against Small-Secret LWE and Parameter Choices in HElib and SEAL %f/eurocrypt/qqrhfa6g5xlpzwpc0ofvv1mldmjbyuyb.pdf %m8676becd437ca39b2ea8fe1b7133544a %ceurocrypt %@Atsushi Takayasu,Yao Lu,Liqiang Peng %*Small CRT-Exponent RSA Revisited %f/eurocrypt/eepncoirmlv1zu9tr0szbgdfvsh4y58u.pdf %m4e222cddfb79761cefcdf8374722e40c %ceurocrypt %@Elette Boyle,Niv Gilboa,Yuval Ishai %*Group-Based Secure Computation: Optimizing Rounds, Communication, and Computation %f/eurocrypt/l5figjzbeib3l02h1urdmsfx9yj6thnp.pdf %m835a99a9f7778fe2b4b454f2908edb61 %ceurocrypt %@Sanjam Garg,Susumu Kiyoshima,Omkant Pandey %*On the Exact Round Complexity of Self-composable Two-Party Computation %f/eurocrypt/4ghclutaqqzsf1f0ijywi5kxtwmob2yv.pdf %mde2db1e007fd35f44a624183597139ca %ceurocrypt %@Jun Furukawa,Yehuda Lindell,Ariel Nof,Or Weinstein %*High-Throughput Secure Three-Party Computation for Malicious Adversaries and an Honest Majority %f/eurocrypt/cc0im8okuwsvzbxtyaqdnjoresh4fjgq.pdf %m5481c393edcc1a35fdea5b5004760f42 %ceurocrypt %@Senyang Huang,Xiaoyun Wang,Guangwu Xu,Meiqin Wang,Jingyuan Zhao %*Conditional Cube Attack on Reduced-Round Keccak Sponge Function %f/eurocrypt/fj4qacgeyewstpi8j9lqnhb5sm6fkrcg.pdf %me6eb3f39104412d7365ef805045a2414 %ceurocrypt %@Lorenzo Grassi,Christian Rechberger,Sondre Rønjom %*A New Structural-Differential Property of 5-Round AES %f/eurocrypt/r6ft091htoc3galnlvdbbzindvqjqry4.pdf %ma3758fc92527992ada9624fd5a8e9e37 %ceurocrypt %@Geoffroy Couteau,Thomas Peters,David Pointcheval %*Removing the Strong RSA Assumption from Arguments over the Integers %f/eurocrypt/gck4gtp8dn9wry0eczqq1mjflmxp2hai.pdf %m8519e02e845d2073396adddda711d140 %ceurocrypt %@Yi Deng %*Magic Adversaries Versus Individual Reduction: Science Wins Either Way %f/eurocrypt/be5jzisfdahgnrvqx4i7obmy9ceuwvk1.pdf %m4a658505b51c68d656a8ae9ba26b4900 %ceurocrypt %@Viet Tung Hoang,Stefano Tessaro %*The Multi-user Security of Double Encryption %f/eurocrypt/mhq7baebnu3skojnwltramzfyizhx6pc.pdf %m121440f0c22c29ee9ed93f8d00b74c70 %ceurocrypt %@Pratik Soni,Stefano Tessaro %*Public-Seed Pseudorandom Permutations %f/eurocrypt/swtrwfcq4sbgguy1n8ieuzkljp69hdib.pdf %m797d1e02b12a0c15ea5124647a6b6812 %ceurocrypt %@Prabhanjan Ananth,Aloni Cohen,Abhishek Jain %*Cryptography with Updates %f/eurocrypt/cwo8jl5esgxhugmvy4vafnbzqtt3yziu.pdf %mba83daffac65333e5a112d1e2344c9c5 %ceurocrypt %@Yevgeniy Dodis,Siyao Guo,Jonathan Katz %*Fixing Cracks in the Concrete: Random Oracles with Auxiliary Input, Revisited %f/eurocrypt/hij16rupom4a5cnnztuadtxryfwwksyg.pdf %m573b61c38abca45e7b9a61e186187682 %ceurocrypt %@Paul Grubbs,Thomas Ristenpart,Yuval Yarom %*Modifying an Enciphering Scheme After Deployment %f/eurocrypt/soxolmiu0a7zvhgvq6zdeipxnptf93bs.pdf %mb0c85b14347a2674f0383352d786d808 %ceurocrypt %@Rishab Goyal,Venkata Koppula,Brent Waters %*Separating Semantic and Circular Security for Symmetric-Key Bit Encryption from the Learning with Errors Assumption %f/eurocrypt/zpfdzymuq2kmxh9vueqjwykcpie871bn.pdf %m6e418d68aed4793f66b1da32a28c4cf1 %ceurocrypt %@Mohammad Hajiabadi,Bruce M. Kapron %*Toward Fine-Grained Blackbox Separations Between Semantic and Circular-Security Notions %f/eurocrypt/mvzrlgkhq6pwxssk3z1igvfid2lu05bo.pdf %m947040e5624d6c65c1a35abe4ed5442e %ceurocrypt %@Nir Bitansky,Vinod Vaikuntanathan %*A Note on Perfect Correctness by Derandomization %f/eurocrypt/s03uqfl8dhboiokaxjrnuygzstxdlejc.pdf %m8468314575dc82133060b26fddebf325 %ceurocrypt %@Alessandro Chiesa,Matthew Green,Jingcheng Liu,Peihan Miao,Ian Miers,Pratyush Mishra %*Decentralized Anonymous Micropayments %f/eurocrypt/aqk4nypth95jcdrbgn0iuewqv7djv3mo.pdf %m461dbf84e69d154dd06a6c7741dfa79a %ceurocrypt %@Rafael Pass,Lior Seeman,Abhi Shelat %*Analysis of the Blockchain Protocol in Asynchronous Networks %f/eurocrypt/j89was0hpw2mquxlndm1gyxztcglf7hr.pdf %m76c3a931fc040c0785085cf61f2bb91e %ceurocrypt %@Joël Alwen,Jeremiah Blocki,Krzysztof Pietrzak %*Depth-Robust Graphs and Their Cumulative Memory Complexity %f/eurocrypt/60vw5nczvskmotqp9iykdt3w2coex8fs.pdf %m68ae5a72f67cd252c0ce1b6b76823982 %ceurocrypt %@Joël Alwen,Binyi Chen,Krzysztof Pietrzak,Leonid Reyzin,Stefano Tessaro %*Scrypt Is Maximally Memory-Hard %f/eurocrypt/6jit4zytlvupsqcfkpdeoyx7bimfwegk.pdf %m29e76d429efeffbc8fa58f9968a5f973 %ceurocrypt %@Gorjan Alagic,Alexander Russell %*Quantum-Secure Symmetric-Key Cryptography Based on Hidden Shifts %f/eurocrypt/ldpwfpf10asiwtxutjkm6v8nhyrqybde.pdf %md9b8e9d22c517ed31206ac2a0834afa7 %ceurocrypt %@Seny Kamara,Tarik Moataz %*Boolean Searchable Symmetric Encryption with Worst-Case Sub-linear Complexity %f/eurocrypt/bkjltpqdvbxpa0lmnetc2mzwgni81fks.pdf %m3f282de9da47ec5bb93bfc2f6f8a24cb %ceurocrypt %@Prabhanjan Ananth,Abhishek Jain,Amit Sahai %*Patchable Indistinguishability Obfuscation: i\mathcal {O} for Evolving Software %f/eurocrypt/ledsmjjg85xi0ttfpgsvhkcfnuz7mkq3.pdf %m69799670563311510aaca1ed738e5a54 %ceurocrypt %@Sanjam Garg,Omkant Pandey,Akshayaram Srinivasan,Mark Zhandry %*Breaking the Sub-Exponential Barrier in Obfustopia %f/eurocrypt/iadyejjzgs84ptnofogk3ds2uktq7w1b.pdf %m2d47578c1649cee476f8d256c1a9c3ac %ceurocrypt %@Yu Sasaki,Yosuke Todo %*New Impossible Differential Search Tool from Design and Cryptanalysis Aspects %f/eurocrypt/q7el0ih5drsab4foubpkcszna2vtmzry.pdf %mbb415e21669d84c9d9b760bd382a58a9 %ceurocrypt %@Kexin Qiao,Ling Song,Meicheng Liu,Jian Guo %*New Collision Attacks on Round-Reduced Keccak %f/eurocrypt/ozqnvmfk7wte4pimuokcejv0saibd85n.pdf %m087915ab4c6acfeb0d993cfdc410e308 %ceurocrypt %@Dan Boneh,Yuval Ishai,Amit Sahai,David J. Wu %*Lattice-Based SNARGs and Their Application to More Efficient Obfuscation %f/eurocrypt/uamgqddcwklefwv3bkcsetaopxjm20p9.pdf %mc5531c2953f1ab6c80be5883aca7697c %ceurocrypt %@Yilei Chen,Craig Gentry,Shai Halevi %*Cryptanalyses of Candidate Branching Program Obfuscators %f/eurocrypt/pdrqigwz7yqpmd5gox6skevnh3ut9efo.pdf %m0aae730c31ee818a038d535b4d14dea0 %ceurocrypt %@Serge Fehr,Louis Salvail %*Quantum Authentication and Encryption with Key Recycling %f/eurocrypt/ne3ifew58xp1hpmtjvfg0skhx7cbudau.pdf %mb001bed07c0b7025ca6f04c56fcfa00d %ceurocrypt %@Christopher Portmann %*Quantum Authentication with Key Recycling %f/eurocrypt/b0eixjhiflehkqkcq9db7vnacmoxrzpr.pdf %m263af9ef5db5079af0a1b121274415f0 %ceurocrypt %@André Chailloux,Anthony Leverrier %*Relativistic (or 2-Prover 1-Round) Zero-Knowledge Protocol for \mathsf {NP} Secure Against Quantum Adversaries %f/eurocrypt/rivfuan9ixg3d0wjku5yzqsgmeca1zb8.pdf %m9c192582cb526bb3124172685981889b %ceurocrypt %@Xiao Wang,Alex J. Malozemoff,Jonathan Katz %*Faster Secure Two-Party Computation in the Single-Execution Setting %f/eurocrypt/fxuoei2zar19uqll4tpghfr6md8vzxjh.pdf %m9f4d305e918df3af4cfe1db25c3327b3 %ceurocrypt %@Payman Mohassel,Mike Rosulek %*Non-interactive Secure 2PC in the Offline/Online and Batch Settings %f/eurocrypt/47ewdqj9imipfkdnbz3n6v2yxwgahblu.pdf %mc80a3a301ed28c478231ea6b08ba4e11 %ceurocrypt %@Xiong Fan,Chaya Ganesh,Vladimir Kolesnikov %*Hashing Garbled Circuits for Free %f/eurocrypt/s1pi0r2peic54qstfezvdmghuovdyjkb.pdf %m0263c9c4d1537304be48bad1b074c0c6 %ceurocrypt %@Dennis Hofheinz %*Adaptive Partitioning %f/eurocrypt/fwezp2v7c8m1tldhrcjbxepgwizqgqxl.pdf %mcd6f5d741a1995876aef5b4189efdded %ceurocrypt %@Felix Günther,Britta Hale,Tibor Jager,Sebastian Lauer %*0-RTT Key Exchange with Full Forward Secrecy %f/eurocrypt/quw3o6vc4ekbxdzirtk1gupyynop7fwe.pdf %mfd196345cdff879b20394223c178c1a8 %ceurocrypt %@Eli Ben-Sasson,Iddo Bentov,Alessandro Chiesa,Ariel Gabizon,Daniel Genkin,Matan Hamilis,Evgenya Pergament,Michael Riabzev,Mark Silberstein,Eran Tromer,Madars Virza %*Computational Integrity with a Public Random String from Quasi-Linear PCPs %f/eurocrypt/uvkhryuyxmgqelaoenj3wicgs16b4dko.pdf %mf6b7f76aabdef234d0b3fcae17b275b0 %ceurocrypt %@Amos Beimel,Yuval Ishai,Eyal Kushilevitz %*Ad Hoc PSM Protocols: Secure Computation Without Coordination %f/eurocrypt/96rekkmjsxlpihwttgdbhdysv74quv5w.pdf %m072c7f3f11933be3652e5d6eaef86421 %ceurocrypt %@Adi Akavia,Tal Moran %*Topology-Hiding Computation Beyond Logarithmic Diameter %f/eurocrypt/suone27galsfv90mrqe5tiawbyczy1dp.pdf %m65d7392933394982221e4887e76290fd %ceurocrypt %@Romain Gay,Dennis Hofheinz,Eike Kiltz,Hoeteck Wee %*Tightly CCA-Secure Encryption Without Pairings %f/eurocrypt/d4itqsaeu1rquxtg3ekdywbf780mjh2c.pdf %md074f9f6c825ccde2b45031bf38b14a8 %ceurocrypt %@Huijia Lin %*Indistinguishability Obfuscation from Constant-Degree Graded Encoding Schemes %f/eurocrypt/zy6veulcvgekpbxd8a5hhqi3nkxfcbus.pdf %medafcfd5ce739eb9cd3857d4e61f1beb %ceurocrypt %@Allison Bishop,Valerio Pastro,Rajmohan Rajaraman,Daniel Wichs %*Essentially Optimal Robust Secret Sharing with Maximal Corruptions %f/eurocrypt/vwxotfgpuz7qlujimawceb39bznrx8y0.pdf %mf83de4ed2dfa2b8ee36c497d873cf7d7 %ceurocrypt %@Peter Gaži,Stefano Tessaro %*Provably Robust Sponge-Based PRNGs and KDFs %f/eurocrypt/k2bpmtxsif7pugojwrbq8omhhvzatd9n.pdf %m0d3cf3ce78ca01247000956ec63b9236 %ceurocrypt %@Ran Canetti,Benjamin Fuller,Omer Paneth,Leonid Reyzin,Adam Smith %*Reusable Fuzzy Extractors for Low-Entropy Distributions %f/eurocrypt/na45yuzdepwdutx1ktkwqi9bghqb372f.pdf %m408a0aa0b390b3cb54d3f41127932233 %ceurocrypt %@Wouter Castryck,Ilia Iliashenko,Frederik Vercauteren %*Provably Weak Instances of Ring-LWE Revisited %f/eurocrypt/iywmtogq8dtu2sh0qlf9xk6bvfrjl4ej.pdf %m2e7a5d74a5cec1f3228ba4a96e60a0e2 %ceurocrypt %@Bin Zhang,Lin Jiao,Mingsheng Wang %*Faster Algorithms for Solving LPN %f/eurocrypt/wzdnb1htucg0orkm9wthxqxzsbvfypea.pdf %m3a30a28f6c084236329e6ef560ab3425 %ceurocrypt %@Bing Sun,Meicheng Liu,Jian Guo,Vincent Rijmen,Ruilin Li %*Provable Security Evaluation of Structures Against Impossible Differential and Zero Correlation Linear Cryptanalysis %f/eurocrypt/p43jgwsy2rntjx6ua09fqbnvoqiurcel.pdf %m0f5f11684ab381bfe516ead582b8096c %ceurocrypt %@Tyge Tiessen %*Polytopic Cryptanalysis %f/eurocrypt/rveim7tgh64rowniyfuptoblls1ynjmx.pdf %m1af474848d6ec39f49f494acb76b7697 %ceurocrypt %@François Durvaux,François-Xavier Standaert %*From Improved Leakage Detection to the Detection of Points of Interests in Leakage Traces %f/eurocrypt/hflmtsfhctdpe5qwa7wl93zodmnpbrk6.pdf %mf63790e70eeb9510a42789ac7ecf76bb %ceurocrypt %@Robert Granger,Philipp Jovanovic,Bart Mennink,Samuel Neves %*Improved Masking for Tweakable Blockciphers with Applications to Authenticated Encryption %f/eurocrypt/maxjeanbkqswfkwy654zr1pi8xlny7j3.pdf %ma7ba37291dce7e3ac260772de8f79e6c %ceurocrypt %@Léo Ducas,Damien Stehlé %*Sanitization of FHE Ciphertexts %f/eurocrypt/mujyqrcdtvosuw9f6yb70e8jpzhgaltg.pdf %m5cf0c1d74fbd7b6fe1ef25f4bc517416 %ceurocrypt %@Pierrick Méaux,Anthony Journault,François-Xavier Standaert,Claude Carlet %*Towards Stream Ciphers for Efficient FHE with Low-Noise Ciphertexts %f/eurocrypt/8l9tewkd2zobcvgxvdmcbhwprhknfiju.pdf %m1e541e1b33fc7b5f0ea98964b38b8735 %ceurocrypt %@Gaëtan Leurent %*Improved Differential-Linear Cryptanalysis of 7-Round Chaskey with Partitioning %f/eurocrypt/paoxdfs6q2sr8olg4yh7fvxrgvubwidt.pdf %m5834f20bdbd51d20262448192b344b42 %ceurocrypt %@Alex Biryukov,Léo Perrin,Aleksei Udovenko %*Reverse-Engineering the S-Box of Streebog, Kuznyechik and STRIBOBr1 %f/eurocrypt/x4srz8ig5gp6bloovqy3dqka9tphc0w2.pdf %m81a79b0c2cbd6edfbddca60d8f3f6c11 %ceurocrypt %@Joost Renes,Craig Costello,Lejla Batina %*Complete Addition Formulas for Prime Order Elliptic Curves %f/eurocrypt/nsrrf9qye8xp2hbd13vw6uehcn5gm0yb.pdf %mb07bfd9933f7cda828a6776ddbe4be29 %ceurocrypt %@Palash Sarkar,Shashank Singh %*New Complexity Trade-Offs for the (Multiple) Number Field Sieve Algorithm in Non-Prime Fields %f/eurocrypt/p1tbdxekxlzmufguz6qjloahkgwnwc4v.pdf %me026a61e37fdbd5cd1cb265cbcd91bf5 %ceurocrypt %@Marc Stevens,Pierre Karpman,Thomas Peyrin %*Freestart Collision for Full SHA-1 %f/eurocrypt/bvcdh4keinetajpsslf9mgo5jtg1xyxu.pdf %mdc0259a3a8e76c5e7e5dce4bb645215d %ceurocrypt %@Itai Dinur %*New Attacks on the Concatenation and XOR Hash Combiners %f/eurocrypt/cukolqr6eslydnv94fxye8uatjmwxocm.pdf %m6dd16b529a14e5268d8175efa89d3d59 %ceurocrypt %@Jung Hee Cheon,Pierre-Alain Fouque,Changmin Lee,Brice Minaud,Hansol Ryu %*Cryptanalysis of the New CLT Multilinear Map over the Integers %f/eurocrypt/awwemdaokinfpds3jlen07c4ruuqxyxb.pdf %m76df999617791a7ea9183fbf4f306cb6 %ceurocrypt %@Yupu Hu,Huiwen Jia %*Cryptanalysis of GGH Map %f/eurocrypt/dhves0kucm6pyebnojqfid7guk84za1t.pdf %m00886b7d377eba5471c8a79272dc7222 %ceurocrypt %@Mihir Bellare,Daniel J. Bernstein,Stefano Tessaro %*Hash-Function Based PRFs: AMAC and Its Multi-User Security %f/eurocrypt/xok1fzza5tljc6q7y2vmubnnvd3haidq.pdf %ma468a9c29f359e73f08cba5d1ec3395e %ceurocrypt %@Atul Luykx,Bart Preneel,Alan Szepieniec,Kan Yasuda %*On the Influence of Message Length in PMAC’s Security Bounds %f/eurocrypt/ezaqjbonk2mvaniliymxfc7ch690bhgo.pdf %m8ef3a17d94d1203fb2a1390a64218b46 %ceurocrypt %@Martin R. Albrecht,Kenneth G. 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Seth Terashima %*A Provable-Security Analysis of Intel’s Secure Key RNG %f/eurocrypt/zi3o5xisedknuex7b6huarjtph1vmjys.pdf %mb520bb75eb193a54c082605fccdced15 %ceurocrypt %@Yevgeniy Dodis,Chaya Ganesh,Alexander Golovnev,Ari Juels,Thomas Ristenpart %*A Formal Treatment of Backdoored Pseudorandom Generators %f/eurocrypt/p30vg1w2jyuhxsyhafantsjmu9bzkxkp.pdf %m3b6cafa625fdfa8885f3f49ff03985aa %ceurocrypt %@Razvan Barbulescu,Pierrick Gaudry,Aurore Guillevic,François Morain %*Improving NFS for the Discrete Logarithm Problem in Non-prime Finite Fields %f/eurocrypt/ltyptngpzak8uuloyqbhiajmcd5i1gwd.pdf %ma8573dc601b62ff15d7c72b9eedf24e7 %ceurocrypt %@Cécile Pierrot %*The Multiple Number Field Sieve with Conjugation and Generalized Joux-Lercier Methods %f/eurocrypt/u6kpagykqrhdgctaflbvwrwsn3dxmzy0.pdf %mf84d13d9e2e080ae04ba3e0b59e23e60 %ceurocrypt %@Alexandre Duc,Florian Tramèr,Serge Vaudenay %*Better Algorithms for LWE and LWR %f/eurocrypt/obuna8pjvsgf7xdt6etwliijqcn3exyu.pdf %mff489ecb2403767253f1eedeec46c79e %ceurocrypt %@Alexander May,Ilya Ozerov %*On Computing Nearest Neighbors with Applications to Decoding of Binary Linear Codes %f/eurocrypt/edni0j5fvms6rgcwwvy1s27i4e9gpaqu.pdf %m558cbc7402b5a143016acb0ab4ad05c6 %ceurocrypt %@Itai Dinur %*Cryptanalytic Time-Memory-Data Tradeoffs for FX-Constructions with Applications to PRINCE and PRIDE %f/eurocrypt/yo2xueta047idmbz5nsvcdkwpwlfomjk.pdf %md7463b9360e9a9c7499f3f91eeadd9ca %ceurocrypt %@Gregor Leander,Brice Minaud,Sondre Rønjom %*A Generic Approach to Invariant Subspace Attacks: Cryptanalysis of Robin, iSCREAM and Zorro %f/eurocrypt/ju9brdsepd1kb3fxqhzvtui24f0oa7m8.pdf %m8d8c653e7ce63ec75acb147ed844bfb9 %ceurocrypt %@Yosuke Todo %*Structural Evaluation by Generalized Integral Property %f/eurocrypt/qyycp6ezxf0kssiqlohxuaod3n8vcw4g.pdf %me57653d06da0eaefb318a701f11849d0 %ceurocrypt %@Achiya Bar-On,Itai Dinur,Orr Dunkelman,Virginie Lallemand,Nathan Keller,Boaz Tsaban %*Cryptanalysis of SP Networks with Partial Non-Linear Layers %f/eurocrypt/oxwiqy2jekcnztdyulazpawvgtmclfdg.pdf %m8f15b4271a5dcc06c8d83b9fd10b9ed3 %ceurocrypt %@Gaëtan Leurent,Lei Wang %*The Sum Can Be Weaker Than Each Part %f/eurocrypt/ebhe9fyivckfvl1r70nrtikaqulm6zsh.pdf %m314f373bc8ddc109e0040121f38b39f3 %ceurocrypt %@Daniel J. Bernstein,Daira Hopwood,Andreas Hülsing,Tanja Lange,Ruben Niederhagen,Louiza Papachristodoulou,Michael Schneider,Peter Schwabe,Zooko Wilcox-O’Hearn %*SPHINCS: Practical Stateless Hash-Based Signatures %f/eurocrypt/vyeusrlbxjrayqk1weth8db5uzjv2mga.pdf %m4f77d41f4d99873395160a40db39106c %ceurocrypt %@Alexandre Duc,Sebastian Faust,François-Xavier Standaert %*Making Masking Security Proofs Concrete %f/eurocrypt/bdygmxnr7akdtcolhuenyiasjwekqhxw.pdf %mad815dbdeb944c70fdd268267fd1d2bf %ceurocrypt %@Martin R. Albrecht,Christian Rechberger,Thomas Schneider,Tyge Tiessen,Michael Zohner %*Ciphers for MPC and FHE %f/eurocrypt/p0rcfeelulcqsojd7uvxwmki9i2dyxkm.pdf %mb35d143454b4af034db285e3da701021 %ceurocrypt %@Gilles Barthe,Sonia Belaïd,François Dupressoir,Pierre-Alain Fouque,Benjamin Grégoire,Pierre-Yves Strub %*Verified Proofs of Higher-Order Masking %f/eurocrypt/qocu85rlfsgsw3bzhkmtze9thxym4vda.pdf %m3f15362dc478a3ee47bb7ac3e5491d54 %ceurocrypt %@Josep Balasch,Sebastian Faust,Benedikt Gierlichs %*Inner Product Masking Revisited %f/eurocrypt/qvavffwjygzr396xmgeqj5ihnsl4tr7l.pdf %m2f3b3ec6d3c98d56ae6754bc48426740 %ceurocrypt %@Jung Hee Cheon,Damien Stehlé %*Fully Homomophic Encryption over the Integers Revisited %f/eurocrypt/x8oarvk9ctejvcxpufbbqp3zesw0l7qr.pdf %m1f2f385bdf81db5fd2de85d42bc61486 %ceurocrypt %@Koji Nuida,Kaoru Kurosawa %*(Batch) Fully Homomorphic Encryption over Integers for Non-Binary Message Spaces %f/eurocrypt/67exk0irrdvmn25cm4lbfxhsz3kgq89u.pdf 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Number of Computing Components Without Leak-Free Hardware %f/eurocrypt/lhn9r6tz5qbuejiskik1ajpunxwcxv7d.pdf %m12d57f2d7a4c26d63c85bb83167b969f %ceurocrypt %@Stefan Dziembowski,Sebastian Faust,Maciej Skorski %*Noisy Leakage Revisited %f/eurocrypt/8b2nxofeskrmltqc9igxnhk0hv3qdpy5.pdf %m73d751032e2873c93b823c55f96b68c5 %ceurocrypt %@Tore Kasper Frederiksen,Jesper Buus Nielsen,Claudio Orlandi %*Privacy-Free Garbled Circuits with Applications to Efficient Zero-Knowledge %f/eurocrypt/byzw5fciwq9d0ai21yuxuhvx8vhpko74.pdf %md2cc2a09003ed483ab9aac831c1f4739 %ceurocrypt %@Samee Zahur,Mike Rosulek,David Evans %*Two Halves Make a Whole %f/eurocrypt/moziknw4jlb5gq3tmdxa9vd1cvpa2wfi.pdf %m8f85192279924459e0bce8235d706c9e %ceurocrypt %@Jens Groth,Markulf Kohlweiss %*One-Out-of-Many Proofs: Or How to Leak a Secret and Spend a Coin %f/eurocrypt/czn0g25vf9bgwskhcrhv7le4lrukx8ip.pdf %md2a6744c98c6695787a27c5ce2f98635 %ceurocrypt %@Juan Garay,Aggelos Kiayias,Nikos Leonardos %*The Bitcoin Backbone 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McEliece over Quadratic Extensions %f/eurocrypt/ospgyokzlk1l8damxjicruejtf5iwcxa.pdf %m721797e65c6098fd5a8899f8b61d8c5f %ceurocrypt %@Jean-Charles Faugère,Louise Huot,Antoine Joux,Guénaël Renault,Vanessa Vitse %*Symmetrized Summation Polynomials: Using Small Order Torsion Points to Speed Up Elliptic Curve Index Calculus %f/eurocrypt/wvl8nlzkmezvxnfyjhujbegqco35tdq1.pdf %m5ea8d797fae9e46780c705d8951602ca %ceurocrypt %@Allison Lewko,Brent Waters %*Why Proving HIBE Systems Secure Is Difficult %f/eurocrypt/32jpwk8aug59s4wrueoqdsdfg7cfkj6n.pdf %mc55ef4b9158911418302631a47ca0daf %ceurocrypt %@Junzuo Lai,Robert H. Deng,Shengli Liu,Jian Weng,Yunlei Zhao %*Identity-Based Encryption Secure against Selective Opening Chosen-Ciphertext Attack %f/eurocrypt/rfkka8v6cb1uzq9mojneday4gibev5gp.pdf %m38c0960d737ec1ba63e7e7ace955fb06 %ceurocrypt %@Yevgeniy Dodis,Krzysztof Pietrzak,Daniel Wichs %*Key Derivation without Entropy Waste %f/eurocrypt/alndskyeo7qz3b0tnjwv49sv2cdxmypr.pdf %m2f74355cd59e4767c7d6ace8a57be2f9 %ceurocrypt %@Sebastian Faust,Pratyay Mukherjee,Daniele Venturi,Daniel Wichs %*Efficient Non-malleable Codes and Key-Derivation for Poly-size Tampering Circuits %f/eurocrypt/afotpew6qumsni0n2t7y3gcwzpbkedv9.pdf %m645349853f196a1a7d3f674ed6cc8d1a %ceurocrypt %@Dominique Unruh %*Revocable Quantum Timed-Release Encryption %f/eurocrypt/drgceoaxbu0nixfms8ywjhkc1vbnvil3.pdf %mb8f27ba61713beb06928a7074f00a011 %ceurocrypt %@Thomas Peyrin,Lei Wang %*Generic Universal Forgery Attack on Iterative Hash-Based MACs %f/eurocrypt/dkds4lqcwtrfuluheovna6qzj79bkw21.pdf %m786edd8941eb5227a8c5052a153e368e %ceurocrypt %@Céline Blondeau,Kaisa Nyberg %*Links between Truncated Differential and Multidimensional Linear Properties of Block Ciphers and Underlying Attack Complexities %f/eurocrypt/w7g1lc8tj5norqi9bfy0ujvecz32norp.pdf %m13252d0b8ef866b0da38df4f341c16e4 %ceurocrypt %@Craig Costello,Huseyin Hisil,Benjamin Smith %*Faster Compact Diffie–Hellman: Endomorphisms on the x-line %f/eurocrypt/mncyabevpwklhmsjogcstyeiuziqa9b5.pdf %m2b8f3335ac13dd252761c716a1d778c4 %ceurocrypt %@Susan Hohenberger,Amit Sahai,Brent Waters %*Replacing a Random Oracle: Full Domain Hash from Indistinguishability Obfuscation %f/eurocrypt/unwa1h5vpecfizasv8wokjol6ftqygrl.pdf %m2aeca38e9ebe8c2eecd722d3ee2414f8 %ceurocrypt %@Boaz Barak,Sanjam Garg,Yael Tauman Kalai,Omer Paneth,Amit Sahai %*Protecting Obfuscation against Algebraic Attacks %f/eurocrypt/tfluhybb1ahv5qmzqoec7s24gnakirr8.pdf %md66feaac4891a802a8bfed90a9c48bfe %ceurocrypt %@Adeline Langlois,Damien Stehlé,Ron Steinfeld %*GGHLite: More Efficient Multilinear Maps from Ideal Lattices %f/eurocrypt/bxdxcitnqjkenghjce8qpwbrkrslovws.pdf %ma14a1ba962391f8f76fcdedd2a305377 %ceurocrypt %@Chanathip Namprempre,Phillip Rogaway,Thomas Shrimpton %*Reconsidering Generic Composition %f/eurocrypt/i1grwbbfdytvleoj3wam90dcvexzshzp.pdf %m4f0dcc4a9377593d3e709cac2e3a9a46 %ceurocrypt %@Kazuhiko Minematsu %*Parallelizable Rate-1 Authenticated Encryption from Pseudorandom Functions %f/eurocrypt/5wqkrlbu1p3bpf462cfouxqzjrtml9wj.pdf %mecd2467654155464ffb03b824610bbd8 %ceurocrypt %@Ari Juels,Thomas Ristenpart %*Honey Encryption: Security Beyond the Brute-Force Bound %f/eurocrypt/pz8dguab1ydwijyf9sxlfesgtnhcohur.pdf %m080509cadca0e56a8d9c85e684b4d0f6 %ceurocrypt %@Ben Morris,Phillip Rogaway %*Sometimes-Recurse Shuffle %f/eurocrypt/2kxls6reyqvwxqiofjhgupebzbasc3uv.pdf %mc015ad9b24aa14db0330cab7cfdca158 %ceurocrypt %@Shan Chen,John Steinberger %*Tight Security Bounds for Key-Alternating Ciphers %f/eurocrypt/urbvdwonc50e7axupisfzv6ti3mkh1zt.pdf %m15763f6987a43e43d81462a5b7fc2e66 %ceurocrypt %@David Cash,Stefano Tessaro %*The Locality of Searchable Symmetric Encryption %f/eurocrypt/uftbqns0sbhniojamh7ojdvk8irtx2y3.pdf %m5ba4e94ca74512e8811fb60e79384c71 %ceurocrypt %@Himanshu Tyagi,Shun Watanabe %*A Bound for Multiparty Secret Key Agreement and Implications for a Problem of Secure Computing %f/eurocrypt/q1d5hoklnz8lvewg2hfdmjasxpu7iawb.pdf %ma8558e27050bd0bec9377bf129ddc407 %ceurocrypt %@Arash Afshar,Payman Mohassel,Benny Pinkas,Ben Riva %*Non-Interactive Secure Computation Based on Cut-and-Choose %f/eurocrypt/wlgb8vxen3foyar6dzomthixpcqk7l2v.pdf %ma691e7e31d298ab72c5d35ead4f1c8c5 %ceurocrypt %@Craig Gentry,Shai Halevi,Steve Lu,Rafail Ostrovsky,Mariana Raykova,Daniel Wichs %*Garbled RAM Revisited %f/eurocrypt/c41fpwdd2qft8shkrky9gjbubonrhgie.pdf %mf093460314dd31d1e94d771b5ff25753 %ceurocrypt %@Alexandre Duc,Stefan Dziembowski,Sebastian Faust %*Unifying Leakage Models: From Probing Attacks to Noisy Leakage. %f/eurocrypt/q791l5dwhpspgvg4jie8u0c6eannjzat.pdf %m520f95edbe2d45d04a3b9bc2cd4b2020 %ceurocrypt %@Jean-Sébastien Coron %*Higher Order Masking of Look-Up Tables %f/eurocrypt/xj1qhzu0imkw8ty9vuhesrjafnegdpvr.pdf %mc9452c69677d8e0abc465c091247cd9c %ceurocrypt %@François Durvaux,François-Xavier Standaert,Nicolas Veyrat-Charvillon %*How to Certify the Leakage of a Chip? %f/eurocrypt/k8wljrfdsivwyoceszgq2oibxal6ahdv.pdf %m8f03013d5a6cda829ec1d65423b9b238 %ceurocrypt %@Sanjam Garg,Divya Gupta %*Efficient Round Optimal Blind Signatures %f/eurocrypt/pnhvwcgaksugyf5idsj0tzoneixzf2hx.pdf %mb99a911634706650659b2d3974c2f142 %ceurocrypt %@Mihir Bellare,Sarah Meiklejohn,Susan Thomson %*Key-Versatile Signatures and Applications: RKA, KDM and Joint Enc/Sig %f/eurocrypt/ybzyg7lonhxfpcqamrldsv30tismhqex.pdf %mbe26c211fee4c6113f959346df2502df %ceurocrypt %@Benoît Libert,Thomas Peters,Marc Joye,Moti Yung %*Non-malleability from Malleability: Simulation-Sound Quasi-Adaptive NIZK Proofs and CCA2-Secure Encryption from Homomorphic Signatures %f/eurocrypt/hjmzuvslcnxowjpocl9kkuhvdmqgrybi.pdf %m9a97b723ac3979b8520133e9a59c8555 %ceurocrypt %@Dan Boneh,Craig Gentry,Sergey Gorbunov,Shai Halevi,Valeria Nikolaenko,Gil Segev,Vinod Vaikuntanathan,Dhinakaran Vinayagamurthy %*Fully Key-Homomorphic Encryption, Arithmetic Circuit ABE and Compact Garbled Circuits %f/eurocrypt/swzgldit0iv7w4bqedkcuflrbpsoknrj.pdf %m2db34a062d3f6c894b172c09aaa85daa %ceurocrypt %@Nuttapong Attrapadung %*Dual System Encryption via Doubly Selective Security: Framework, Fully Secure Functional Encryption for Regular Languages, and More %f/eurocrypt/v2mhilhebarfqantje1lkdvwzgu5s0s9.pdf %med8631373de20c25c459e6996e52b8b5 %ceurocrypt %@Shafi Goldwasser,S. Dov Gordon,Vipul Goyal,Abhishek Jain,Jonathan Katz,Feng-Hao Liu,Amit Sahai,Elaine Shi,Hong-Sheng Zhou %*Multi-input Functional Encryption %f/eurocrypt/stjdfpfy35nbg96ku0dcaheilxgmoiqw.pdf %m69dc82d9ec8ea49c8a1b764c8fa2744c %ceurocrypt %@Arno Mittelbach %*Salvaging Indifferentiability in a Multi-stage Setting %f/eurocrypt/lsawc7g5bm2atcwjszyunh0hx1i98vig.pdf %m59bff88c6c1f04e0704f24393ed3900d %ceurocrypt %@Melissa Chase,Sarah Meiklejohn %*Déjà Q: Using Dual Systems to Revisit q-Type Assumptions %f/eurocrypt/ftyqmzc26ckexxbsii80smge3pfv1rht.pdf %md04365274da36f700f6b6f84812efbd3 %ceurocrypt %@Niv Gilboa,Yuval Ishai %*Distributed Point Functions and Their Applications %f/eurocrypt/dkpaw9beszrqcqkv0mhgfttyc3y8in4u.pdf %m9f2253e4352cc7704bae0e085221b1f1 %ceurocrypt %@Daniel Kraschewski,Hemanta K. Maji,Manoj Prabhakaran,Amit Sahai %*A Full Characterization of Completeness for Two-Party Randomized Function Evaluation %f/eurocrypt/fhwldmwy7ctohs16kvaefaub5ixk4vdr.pdf %m3bb238128761666d6c77185e38db3db4 %ceurocrypt %@Juan A. Garay,Yuval Ishai,Ranjit Kumaresan,Hoeteck Wee %*On the Complexity of UC Commitments %f/eurocrypt/ks5upwihjczmlej168il7tkxrrymqwvn.pdf %m9a4cca07f8e48aeb0476418675a3c7ed %ceurocrypt %@Morten Dahl,Ivan Damgård %*Universally Composable Symbolic Analysis for Two-Party Protocols Based on Homomorphic Encryption %f/eurocrypt/gnvx8yec6hrthloks4ys39rimif0dbjz.pdf %mcf7c7177f3356fd20a6abd24ecc45245 %ceurocrypt %@Sanjam Garg,Craig Gentry,Shai Halevi %*Candidate Multilinear Maps from Ideal Lattices %f/eurocrypt/2jjmixzr7vyulfqrwvb9szcgohkioxag.pdf %m357b64b88e1028af859f0387d8431495 %ceurocrypt %@Nico Döttling,Jörn Müller-Quade %*Lossy Codes and a New Variant of the Learning-With-Errors Problem %f/eurocrypt/v8ab316wurgpqyhxgtl0bm97kjzwjdcq.pdf %m52f938bce1de286b04c45a38e435d16d %ceurocrypt %@Vadim Lyubashevsky,Chris Peikert,Oded Regev %*A Toolkit for Ring-LWE Cryptography %f/eurocrypt/7kyifoe3npcfle8sp1locdwkbztimqrg.pdf %m3f76255f1e8fc8192dad7c4be97ad140 %ceurocrypt %@Mark Lewko,Adam O’Neill,Adam Smith %*Regularity of Lossy RSA on Subdomains and Its Applications %f/eurocrypt/kvoihp9xxstveykgd5fn8l74jewdramc.pdf %m9ad41ed96dbdb40d16b9c7da10ea3b62 %ceurocrypt %@Marc Joye,Benoît Libert %*Efficient Cryptosystems from 2k-th Power Residue Symbols %f/eurocrypt/zsrwjrfi7hl4oleaukvneg32budj50nx.pdf %mf0d23d86ed57787c2b58d793ac2d88da %ceurocrypt %@Ananth Raghunathan,Gil Segev,Salil Vadhan %*Deterministic Public-Key Encryption for Adaptively Chosen Plaintext Distributions %f/eurocrypt/gs2wyfwexorazt6h85ul3ciej9mpb7ou.pdf %mca7f4ae4f7588d5ea9b66c46edebe983 %ceurocrypt %@Ryo Nishimaki %*How to Watermark Cryptographic Functions %f/eurocrypt/ug2rag6m4hesz51vfptobiqnaiyneldu.pdf %ma05525b8e68d7edccc5eb500bdc31740 %ceurocrypt %@Nicolas Veyrat-Charvillon,Benoît Gérard,François-Xavier Standaert %*Security Evaluations beyond Computing Power %f/eurocrypt/su1nqm3oyradkyjexgu2ahs4df6e7z5f.pdf %m28f7d3bcc8aedd005ac0610f03d049cd %ceurocrypt %@Emmanuel Prouff,Matthieu Rivain %*Masking against Side-Channel Attacks: A Formal Security Proof %f/eurocrypt/4xgudeaix6lcpsdeyfjbvjwuk27ghqoo.pdf %m053f4b702cfdb4f44047b0d0439e4529 %ceurocrypt %@Carmit Hazay,Adriana López-Alt,Hoeteck Wee,Daniel Wichs %*Leakage-Resilient Cryptography from Minimal Assumptions %f/eurocrypt/wjib6pcsvzncktymerrduqk2gq8in19m.pdf %mae5bf607c9abd6ed6c176d121ade8fca %ceurocrypt %@Antoine Joux %*Faster Index Calculus for the Medium Prime Case Application to 1175-bit and 1425-bit Finite Fields %f/eurocrypt/nw5yucllu8ytx9mposaaweg2h6iz7rdj.pdf %m80b2efaa9e1f2873e665e86a6e88bad3 %ceurocrypt %@Joppe W. Bos,Craig Costello,Huseyin Hisil,Kristin Lauter %*Fast Cryptography in Genus 2 %f/eurocrypt/jsrvoi9nkrwgua5lihyxvm7ahsn2bekw.pdf %m84727a6bc88356d9e9c751ebae9b8c57 %ceurocrypt %@Charles Bouillaguet,Pierre-Alain Fouque,Amandine Véber %*Graph-Theoretic Algorithms for the “Isomorphism of Polynomials” Problem %f/eurocrypt/qlhbrqkgs2zitlmstoybj0rg1ve96ucc.pdf %ma98acdbdbb0bcb709dfd61067c4d8736 %ceurocrypt %@Franck Landelle,Thomas Peyrin %*Cryptanalysis of Full RIPEMD-128 %f/eurocrypt/tplfhh4k18zg3m05slwzaxgdeqvqbkup.pdf %m80d766e78db7debf413dca1bc9f34a18 %ceurocrypt %@Marc Stevens %*New Collision Attacks on SHA-1 Based on Optimal Joint Local-Collision Analysis %f/eurocrypt/oric5eo40jhpvfutdbyv72a8iwfm61nx.pdf %m037d991c14cc7adbd4e1026398838bd6 %ceurocrypt %@Florian Mendel,Tomislav Nad,Martin Schläffer %*Improving Local Collisions: New Attacks on Reduced SHA-256 %f/eurocrypt/b7gws1py3gxourvjptm4rslal9u0nzbc.pdf %m14cd17b6e059c73ff104267ad7592c38 %ceurocrypt %@David Cash,Alptekin Küpçü,Daniel Wichs %*Dynamic Proofs of Retrievability via Oblivious RAM %f/eurocrypt/3slsxztb067aifh1wzy2rh9emotcvgky.pdf %m66ae920ead0b735b31ff0b814984766f %ceurocrypt %@Mihir Bellare,Sriram Keelveedhi,Thomas Ristenpart %*Message-Locked Encryption and Secure Deduplication %f/eurocrypt/nyvcyh73grl5cgzlet94o8iarndkfhtq.pdf %mf751c07a6219e0e97ce0a39582589b05 %ceurocrypt %@Guido Bertoni,Joan Daemen,Michaël Peeters,Gilles Van Assche %*Keccak %f/eurocrypt/qzig3rbfhpmlm2ydgti5z4fel7jcxand.pdf %m2c3650c2110f2d0ce5e5eaffae380bca %ceurocrypt %@Jung Hee Cheon,Jean-Sébastien Coron,Jinsu Kim,Moon Sung Lee,Tancrède Lepoint,Mehdi Tibouchi,Aaram Yun %*Batch Fully Homomorphic Encryption over the Integers %f/eurocrypt/ko0ypztfy9rwgk1woxb6vib7ilga5ecf.pdf %meb092263d2e67cb7851e31f8e734befc %ceurocrypt %@Dario Catalano,Dario Fiore %*Practical Homomorphic MACs for Arithmetic Circuits %f/eurocrypt/9s5kgbhpkudjtjhc7ntfesqwzmonrgvq.pdf %m824e00ad46d3a68a516d8b5ebc8142f6 %ceurocrypt %@Charalampos Papamanthou,Elaine Shi,Roberto Tamassia,Ke Yi %*Streaming Authenticated Data Structures %f/eurocrypt/h9rnmsokxvbek2ryjdsfn5xmzuyha0lu.pdf %ma5800ef211129c952648a18e70782ff2 %ceurocrypt %@Patrick Derbez,Pierre-Alain Fouque,Jérémy Jean %*Improved Key Recovery Attacks on Reduced-Round AES in the Single-Key Setting %f/eurocrypt/u7wb9rxusdceehlvzr0zmqxnwj6ygknf.pdf %m96167c002866272d57f06bc5dc3cd268 %ceurocrypt %@Céline Blondeau,Kaisa Nyberg %*New Links between Differential and Linear Cryptanalysis %f/eurocrypt/v2yeigkm8blvcnfzzxutq7q064obrkgl.pdf %me070fbaa72fd0e8f7fcb888a4091fcc6 %ceurocrypt %@Jooyoung Lee %*Towards Key-Length Extension with Optimal Security: Cascade Encryption and Xor-cascade Encryption %f/eurocrypt/exguqa8jmsypkpdzcvoiysovc5kluldm.pdf %m798b751e38028aef449d90b7c778ad29 %ceurocrypt %@Paul Baecher,Pooya Farshim,Marc Fischlin,Martijn Stam %*Ideal-Cipher (Ir)reducibility for Blockcipher-Based Hash Functions %f/eurocrypt/ymioxrtuafgj0hbzfdenkqhx9tjmwwd7.pdf %m13a3ea0f1975d20b2910de62bd5b1c47 %ceurocrypt %@Marc Fischlin,Nils Fleischhacker %*Limitations of the Meta-reduction Technique: The Case of Schnorr Signatures %f/eurocrypt/vxdfhpvq7oou2kygsr06jtuscynh4ep9.pdf %mbda0553c9215ab9e5dc3f63dc7cefd82 %ceurocrypt %@Florian Böhl,Dennis Hofheinz,Tibor Jager,Jessica Koch,Jae Hong Seo,Christoph Striecks %*Practical Signatures from Standard Assumptions %f/eurocrypt/dncykhe3xpcmi97hlj0zog2orsrqimu1.pdf %m0b981255ecd812b893cbf0f92403b97e %ceurocrypt %@Benny Applebaum,Yoni Moses %*Locally Computable UOWHF with Linear Shrinkage %f/eurocrypt/pimv6qy5unbcideopgra0ryskc2l4zst.pdf %mfd241f5fe3d13c40b25da28a2e82d97f %ceurocrypt %@Huijia Lin,Stefano Tessaro %*Amplification of Chosen-Ciphertext Security %f/eurocrypt/oaixutfb32odqyjnmwgl9rskhypsrgni.pdf %maad93aebcfb0a16dacab729cafa09843 %ceurocrypt %@Dennis Hofheinz %*Circular Chosen-Ciphertext Security with Compact Ciphertexts %f/eurocrypt/a4cf5b6zpjnhgyt89q7xgibmmizlvker.pdf %m678b6fcaa4dd73f05723628b3c28b466 %ceurocrypt %@Tore Kasper Frederiksen,Thomas Pelle Jakobsen,Jesper Buus Nielsen,Peter Sebastian Nordholt,Claudio Orlandi %*MiniLEGO: Efficient Secure Two-Party Computation from General Assumptions %f/eurocrypt/nictuejpblz37it2lwjxfo4q6soex5vd.pdf %m5a0308ca9d009d315716dff95c77984e %ceurocrypt %@Payman Mohassel,Saeed Sadeghian %*How to Hide Circuits in MPC an Efficient Framework for Private Function Evaluation %f/eurocrypt/eeq5hqmlc8g0ap6kjl1cw3br7xsiuv9d.pdf %me595d57b4bb8fd3a2db25d78b9c46d9d %ceurocrypt %@S. Dov Gordon,Tal Malkin,Mike Rosulek,Hoeteck Wee %*Multi-party Computation of Polynomials and Branching Programs without Simultaneous Interaction %f/eurocrypt/m27ucedbyxe0j8poqtirv6hsyfgn1xqv.pdf %mef44320c6ed578bfd9aadeca6190ba01 %ceurocrypt %@Dan Boneh,Mark Zhandry %*Quantum-Secure Message Authentication Codes %f/eurocrypt/zr4hauzmribff90xw2ijcp16pyaxseet.pdf %m2aaf6cb07a7180fb9f0ef4f60d3e982b %ceurocrypt %@Marco Tomamichel,Serge Fehr,Jędrzej Kaniewski,Stephanie Wehner %*One-Sided Device-Independent QKD and Position-Based Cryptography from Monogamy Games %f/eurocrypt/aiv0v7kr3zgcdbm9kbowom5dciwfze84.pdf %m7d6097aebb17591a1fd32a5e8cd4a7bb %ceurocrypt %@Rosario Gennaro,Craig Gentry,Bryan Parno,Mariana Raykova %*Quadratic Span Programs and Succinct NIZKs without PCPs %f/eurocrypt/labsectrjowystxgpumq8pijc02dlmvk.pdf %mf818b69a151b6b1f3c1366978433d6eb %ceurocrypt %@Stephanie Bayer,Jens Groth %*Zero-Knowledge Argument for Polynomial Evaluation with Application to Blacklists %f/eurocrypt/n9xceuclqgpvjk172ohahw0saivsfdig.pdf %m46bfe555b772ee0caccf966e4846676d %ceurocrypt %@Grégory Demay,Peter Gaži,Martin Hirt,Ueli Maurer %*Resource-Restricted Indifferentiability %f/eurocrypt/o4ia1lywqoklmpdvtnrb6nfsgf5yx7xc.pdf %m68a5c3e3d924ea24114298f2556c00dc %ceurocrypt %@Vipul Goyal,Abhishek Jain %*On Concurrently Secure Computation in the Multiple Ideal Query Model %f/eurocrypt/iczkxjlh384i2thjonuqtclsdkebywz5.pdf %m7d64dab58e66e5d47004eb2d8a42a991 %ceurocrypt %@Rafail Ostrovsky,Alessandra Scafuro,Ivan Visconti,Akshay Wadia %*Universally Composable Secure Computation with (Malicious) Physically Uncloneable Functions %f/eurocrypt/yyautlvl0rfihdtzfgnks6i1wepub8jo.pdf %mdceda0210b9964db0c35617a5e380a18 %ceurocrypt %@Steve Lu,Rafail Ostrovsky %*How to Garble RAM Programs? %f/eurocrypt/kfukchjvzolwm5poxqpintnlbytsrmag.pdf %m4e01799cda821c7b20679d129702d1d6 %ceurocrypt %@Antoine Joux %*A Tutorial on High Performance Computing Applied to Cryptanalysis %f/eurocrypt/yzkvp0uga7ihl5orznnjbedv4gdbxemw.pdf %mc78b9c97e7c92cec620c6ff3ed822bba %ceurocrypt %@Alfred Menezes %*Another Look at Provable Security %f/eurocrypt/zheixc8tte0wv6k12gdougpkdpiymhsf.pdf %md3d81825881f2d5886df3c84e96465e9 %ceurocrypt %@Antoine Joux,Vanessa Vitse %*Cover and Decomposition Index Calculus on Elliptic Curves Made Practical %f/eurocrypt/pycvbqdqv18r9mzotknh6kafsthidzx7.pdf %m949342d12e3ae61fc25078c68abaa1e2 %ceurocrypt %@Jean-Charles Faugère,Ludovic Perret,Christophe Petit,Guénaël Renault %*Improving the Complexity of Index Calculus Algorithms in Elliptic Curves over Binary Fields %f/eurocrypt/ixz0ntubj5qk6nll9dhrtxowpkgbr3yp.pdf %mdfdf7b7e875f91d439278fa25c16f3bd %ceurocrypt %@Andrey Bogdanov,Lars R. Knudsen,Gregor Leander,Francois-Xavier Standaert,John Steinberger,Elmar Tischhauser %*Key-Alternating Ciphers in a Provable Setting: Encryption Using a Small Number of Public Permutations %f/eurocrypt/8j3oshvjfrbbcn4flyd26uvg1qppn7t5.pdf %mea4206e59b5b5603fdc957e3f00055d6 %ceurocrypt %@Peter Gaži,Stefano Tessaro %*Efficient and Optimally Secure Key-Length Extension for Block Ciphers via Randomized Cascading %f/eurocrypt/kdf2cg5bsnojv7e4xvcdyemb8wiuk9oy.pdf %mf100d9bc74249677def1c584e8e6c451 %ceurocrypt %@Adam Groce,Jonathan Katz %*Fair Computation with Rational Players %f/eurocrypt/pgojfs7vtkfkmprlydireuxg5ntuh0a6.pdf %mf69b6682fc523abf995e9dc16a51eb8e %ceurocrypt %@Sanjam Garg,Vipul Goyal,Abhishek Jain,Amit Sahai %*Concurrently Secure Computation in Constant Rounds %f/eurocrypt/b1lwz3xmfrmobkenvlgttj9a6efnkpox.pdf %m17c974385836e5e8129882f8a697fa0a %ceurocrypt %@Tsz Hon Yuen,Sherman S. M. Chow,Ye Zhang,Siu Ming Yiu %*Identity-Based Encryption Resilient to Continual Auxiliary Leakage %f/eurocrypt/d8a45af9wibsht3wpjfscoelrytezgvz.pdf %m0b8496dc59e04e182751e6488e0bc6fc %ceurocrypt %@Dominique Unruh %*Quantum Proofs of Knowledge %f/eurocrypt/nllamzoj6nktmp9oub4sh1fypwturw8q.pdf %m34681b06a622b1f02ea96b18fff42036 %ceurocrypt %@Alessandra Scafuro,Ivan Visconti %*On Round-Optimal Zero Knowledge in the Bare Public-Key Model %f/eurocrypt/mmxdvrfl1ul0qb8gcpu9setwjixgodnn.pdf %m502b9f042035a51e62dedb43755808b6 %ceurocrypt %@Gene S. Kopp,John D. Wiltshire-Gordon %*Robust Coin Flipping %f/eurocrypt/a1f2w8gazjj3kr7h4bsytdpno9uvuerw.pdf %mf094f3e9dfaa5b39c976c5f0424f05ec %ceurocrypt %@Alfonso Cevallos,Serge Fehr,Rafail Ostrovsky,Yuval Rabani %*Unconditionally-Secure Robust Secret Sharing with Compact Shares %f/eurocrypt/svn7ef1fpdojxtvpcoksl5arhytmd6kh.pdf %m1b7e1de3acba577eb04f1f26f0cffd45 %ceurocrypt %@Dennis Hofheinz %*All-But-Many Lossy Trapdoor Functions %f/eurocrypt/xbni490sndfq7shvbuhlozcrwja5pf6a.pdf %mc60a275ac223d1ada59b475b8197d062 %ceurocrypt %@Mihir Bellare,Eike Kiltz,Chris Peikert,Brent Waters %*Identity-Based (Lossy) Trapdoor Functions and Applications %f/eurocrypt/zaott7bahyqdwciuy4mb6fgfvizg2xpp.pdf %m28fda46d938dac4d21309c12e2ad120f %ceurocrypt %@Hoeteck Wee %*Dual Projective Hashing and Its Applications — Lossy Trapdoor Functions and More %f/eurocrypt/k689luorvrialoq5euebdtcm30gzxqwg.pdf %m90337d19767457ae05923c643063ecb8 %ceurocrypt %@Stephanie Bayer,Jens Groth %*Efficient Zero-Knowledge Argument for Correctness of a Shuffle %f/eurocrypt/iqfwv4kpgyqwcn3x9bvd7s2ghczbsfi6.pdf %m2806680a981508b73c0bff52e63e94ab %ceurocrypt %@Melissa Chase,Markulf Kohlweiss,Anna Lysyanskaya,Sarah Meiklejohn %*Malleable Proof Systems and Applications %f/eurocrypt/paculk9rvml8jvdq1t2ex54oaezgswgc.pdf %m280a843ec65b6b63818085f04997956c %ceurocrypt %@Masayuki Abe,Kristiyan Haralambiev,Miyako Ohkubo %*Group to Group Commitments Do Not Shrink %f/eurocrypt/9ci02m6q8yxaezlqzpr14hcuub3watsg.pdf %m025eeda2533a4f14670cdf765e4d8399 %ceurocrypt %@Allison Lewko %*Tools for Simulating Features of Composite Order Bilinear Groups in the Prime Order Setting %f/eurocrypt/dxs1kvrumbfw04xzsqyt3fpheglrz9pj.pdf %mea3f665be8fd4e0e90a38808da12df60 %ceurocrypt %@Orr Dunkelman,Nathan Keller,Adi Shamir %*Minimalism in Cryptography: The Even-Mansour Scheme Revisited %f/eurocrypt/k4bymedzvph2opdl5ik8u0emxsor3jzc.pdf %m8ba6c8e906b1017fff98d5498a77a27d %ceurocrypt %@Yevgeniy Dodis,Eike Kiltz,Krzysztof Pietrzak,Daniel Wichs %*Message Authentication, Revisited %f/eurocrypt/rvy0wjzhgnpqobzsbnuu4mei9c7qaco6.pdf %mf60551f98ec52b168863cc1d236ddb55 %ceurocrypt %@Omkant Pandey,Yannis Rouselakis %*Property Preserving Symmetric Encryption %f/eurocrypt/yfx8ut5izlct3shmv9y7ljkobsgvk2we.pdf %m870787ff5868c6b3a9c080c76a2d6e4a %ceurocrypt %@Dmitry Khovratovich,Gaëtan Leurent,Christian Rechberger %*Narrow-Bicliques: Cryptanalysis of Full IDEA %f/eurocrypt/dwjyrqf8a9d35kntombueuz7thixz4r6.pdf %m414923b9edeb6380763dcf38d783c628 %ceurocrypt %@Yu Sasaki %*Cryptanalyses on a Merkle-Damgård Based MAC — Almost Universal Forgery and Distinguishing-H Attacks %f/eurocrypt/qkj1ww9kjtyb8yzelaihmcdnghxm2sru.pdf %m9975db6c8feb2e7ba3ebce931520b8e7 %ceurocrypt %@Amir Moradi %*Statistical Tools Flavor Side-Channel Collision Attacks %f/eurocrypt/f9iw5uetkfjz4mbyl21zjwlotxuy8bpg.pdf %mda879aed479ea3f73efed08099c43437 %ceurocrypt %@Jean-Sébastien Coron,David Naccache,Mehdi Tibouchi %*Public Key Compression and Modulus Switching for Fully Homomorphic Encryption over the Integers %f/eurocrypt/rotqet6zwjjipwv2gxdu5xysk3qpk8nz.pdf %m3036d376afbd90f33338c41869567b18 %ceurocrypt %@Craig Gentry,Shai Halevi,Nigel P. Smart %*Fully Homomorphic Encryption with Polylog Overhead %f/eurocrypt/uafifwhkjynx2opmhxy9s4rkebzlevst.pdf %mf2275a593cfb52844845ad06f9bf8ef2 %ceurocrypt %@Gilad Asharov,Abhishek Jain,Adriana López-Alt,Eran Tromer,Vinod Vaikuntanathan,Daniel Wichs %*Multiparty Computation with Low Communication, Computation and Interaction via Threshold FHE %f/eurocrypt/gm3dx5zqwciarvyhz7hoieeg8pf1ju4r.pdf %m6913ec2d3f2a68210b96e7b2b58fe7ef %ceurocrypt %@Yuanmi Chen,Phong Q. Nguyen %*Faster Algorithms for Approximate Common Divisors: Breaking Fully-Homomorphic-Encryption Challenges over the Integers %f/eurocrypt/zfqsrxdd0m19xl6ujmfl8nwuya5tp4en.pdf %m9e46abc0870cf861563a1adca55c1836 %ceurocrypt %@Anja Becker,Antoine Joux,Alexander May,Alexander Meurer %*Decoding Random Binary Linear Codes in 2n/20: How 1 + 1 = 0 Improves Information Set Decoding %f/eurocrypt/x20paobwvjzqzfk3t4uhmesxstweklr6.pdf %m8d9d23a220f55b46a6a46792eefefcb3 %ceurocrypt %@Saqib A. Kakvi,Eike Kiltz %*Optimal Security Proofs for Full Domain Hash, Revisited %f/eurocrypt/edurcgmp7n1dqum4nwwxseogijzr9fkl.pdf %m3e2864e26d7511f5c028e3442b286750 %ceurocrypt %@Yannick Seurin %*On the Exact Security of Schnorr-Type Signatures in the Random Oracle Model %f/eurocrypt/ubcn48crpesftwnjyvewtbxa0zs3pll6.pdf %m7129ba1d42c939c71aea5d399297286e %ceurocrypt %@Michel Abdalla,Pierre-Alain Fouque,Vadim Lyubashevsky,Mehdi Tibouchi %*Tightly-Secure Signatures from Lossy Identification Schemes %f/eurocrypt/z9njsyqwb1txl0gqvg4douwiaiz3balx.pdf %m98fb27eafac531b0735cb6d0ebcb00e1 %ceurocrypt %@Tatsuaki Okamoto,Katsuyuki Takashima %*Adaptively Attribute-Hiding (Hierarchical) Inner Product Encryption %f/eurocrypt/wqmv0uznqrfk5ke7ybaf2htzdt3wdclh.pdf %mc643f5065755078cc0e00374161652c7 %ceurocrypt %@Benoît Libert,Thomas Peters,Moti Yung %*Scalable Group Signatures with Revocation %f/eurocrypt/nr9ajepkwtx7mmfbadgtuzdq0hwc65yl.pdf %m9b4a855cd647871a57eb6e7aac4a29f5 %ceurocrypt %@Ilya Mironov,Omkant Pandey,Omer Reingold,Gil Segev %*Incremental Deterministic Public-Key Encryption %f/eurocrypt/eqhscnor2zlhgo3bempgjvtwq8vdl4ur.pdf %m5077be623eab79c1a4d5d5296643af3f %ceurocrypt %@Mihir Bellare,Rafael Dowsley,Brent Waters,Scott Yilek %*Standard Security Does Not Imply Security against Selective-Opening %f/eurocrypt/vjinucaz6brzcdiwr4skopjqly5gps2e.pdf %m7fb321e250ebe50a722f6db956cf599b %ceurocrypt %@Susan Hohenberger,Allison Lewko,Brent Waters %*Detecting Dangerous Queries: A New Approach for Chosen Ciphertext Security %f/eurocrypt/7bltknkufcbdwmga1qz26dxvieioa3r0.pdf %m754845aced98cb311defa1c0a2a4660e %ceurocrypt %@Alexandra Boldyreva,Jean Paul Degabriele,Kenneth G. Paterson,Martijn Stam %*Security of Symmetric Encryption in the Presence of Ciphertext Fragmentation %f/eurocrypt/ys2jzhvpzn9tgoamjgebakd6liwmorkd.pdf %mbbf3f99044e236a36078aec2a04eead5 %ceurocrypt %@Daniele Micciancio,Chris Peikert %*Trapdoors for Lattices: Simpler, Tighter, Faster, Smaller %f/eurocrypt/st96zqfqn3bumsyxjdoybtw8pcjvua2r.pdf %m2e1e80af322b240821664cd4e506c412 %ceurocrypt %@Abhishek Banerjee,Chris Peikert,Alon Rosen %*Pseudorandom Functions and Lattices %f/eurocrypt/iflzrp7bx5sv6jom1eqrkfnaahyuu0zm.pdf %md4b4071e3e4487d3aed069df44aee7d1 %ceurocrypt %@Vadim Lyubashevsky %*Lattice Signatures without Trapdoors %f/eurocrypt/j9sxi1zqyf7heid0rfptmak4ugupn5qk.pdf %m20cb9021811411cf4f781652ca1f9743 %ceurocrypt %@Ronald Cramer %*The Arithmetic Codex: Theory and Applications %f/eurocrypt/knhn53vrcwbdjcftzx8fvamhw0edlsze.pdf %mf735587b58b584b5196ff8aaf1660fda %ceurocrypt %@Phong Q. Nguyen %*Lattice Reduction Algorithms: Theory and Practice %f/eurocrypt/bmarmr4widz1tfsa2vbkxlqjpi7xjo90.pdf %mdbfb9147e018dd565fc44b3a3731dd1b %ceurocrypt %@Eike Kiltz,Krzysztof Pietrzak,David Cash,Abhishek Jain,Daniele Venturi %*Efficient Authentication from Hard Learning Problems %f/eurocrypt/ftawopng3jgk6ulikpvzy8yw7edq9b1d.pdf %m6404849128d0d8f6467a9ad91ccb61a0 %ceurocrypt %@Damien Stehlé,Ron Steinfeld %*Making NTRU as Secure as Worst-Case Problems over Ideal Lattices %f/eurocrypt/mmoyabwetck3ng9fldyhupztd5gaike7.pdf %mddc37b3d8c727d581181492f22e0bdeb %ceurocrypt %@Diego F. Aranha,Koray Karabina,Patrick Longa,Catherine H. Gebotys,Julio López %*Faster Explicit Formulas for Computing Pairings over Ordinary Curves %f/eurocrypt/hxlpatlfbw41dovwqkcnrptdizog590j.pdf %ma4b6e6162343555235199d52b2e4e4f2 %ceurocrypt %@Amir Moradi,Axel Poschmann,San Ling,Christof Paar,Huaxiong Wang %*Pushing the Limits: A Very Compact and a Threshold Implementation of AES %f/eurocrypt/ojw4szwh9gvh1clmfedk25ap0brsljmn.pdf %mca1f9a33f314517c81b5b9b5eac1267f %ceurocrypt %@Elette Boyle,Gil Segev,Daniel Wichs %*Fully Leakage-Resilient Signatures %f/eurocrypt/jzaws7bilceqtybktplajgenovrszhym.pdf %m43ee90c9008609b51abe88b038339a90 %ceurocrypt %@Mathieu Renauld,François-Xavier Standaert,Nicolas Veyrat-Charvillon,Dina Kamel,Denis Flandre %*A Formal Study of Power Variability Issues and Side-Channel Attacks for Nanoscale Devices %f/eurocrypt/c9yvyfzfigwt0izx43wcgu2atb7kldpo.pdf %m1467f1918bfa4d9b28f04c65b62f9412 %ceurocrypt %@Craig Gentry,Shai Halevi %*Implementing Gentry’s Fully-Homomorphic Encryption Scheme %f/eurocrypt/7pjuuexw3lth9opq1c2b0dyvhwndcbam.pdf %m1bb35af9e92fa981600162c1a0a2ae99 %ceurocrypt %@Dan Boneh,David Mandell Freeman %*Homomorphic Signatures for Polynomial Functions %f/eurocrypt/yjuzrhcmp59wde0l4i8xfmktdsexhn3b.pdf %ma63aa9a0d46c1662515085162baee008 %ceurocrypt %@Rikke Bendlin,Ivan Damgård,Claudio Orlandi,Sarah Zakarias %*Semi-homomorphic Encryption and Multiparty Computation %f/eurocrypt/uykrx7xmep4lswti5gcowlbuqtpoj3cs.pdf %mdbb3354cd74f1ffd30f61d24442c8699 %ceurocrypt %@Sven Schäge %*Tight Proofs for Signature Schemes without Random Oracles %f/eurocrypt/vqsup68x3enyhvsarw0cpjxetodahi5b.pdf %m7990ddf23acacda3c0255d3400dc6700 %ceurocrypt %@Dario Catalano,Dario Fiore,Bogdan Warinschi %*Adaptive Pseudo-free Groups and Applications %f/eurocrypt/ztdljlcuwvkyi75ggrf8xybeb93o0dim.pdf %m3b82f0e84f0bc297ef9344414c221377 %ceurocrypt %@Georg Fuchsbauer %*Commuting Signatures and Verifiable Encryption %f/eurocrypt/7ec0uphskglwbwqz2yybtvrzt3id5qcg.pdf %m35bf021efb2220e74ca1502b2da224a7 %ceurocrypt %@Niek J. Bouman,Serge Fehr %*Secure Authentication from a Weak Key, without Leaking Information %f/eurocrypt/g6cgjxeyl4h5qmksbjrpwr01ly9biohu.pdf %mded08acd65de70754de97d359a9ac917 %ceurocrypt %@Hadi Ahmadi,Reihaneh Safavi-Naini %*Secret Keys from Channel Noise %f/eurocrypt/g5ht2kvl6yzebjmpprsqweg4unwjooxf.pdf %mbfc08ae3c5d1244ab1e33eef93150cc0 %ceurocrypt %@Satoshi Obana %*Almost Optimum t-Cheater Identifiable Secret Sharing Schemes %f/eurocrypt/zxrhoylmd14jvwstfpeam6ngpi2ikg3n.pdf %m1cec491e37c0d64594546e3561d8e1e7 %ceurocrypt %@Gregor Leander %*On Linear Hulls, Statistical Saturation Attacks, PRESENT and a Cryptanalysis of PUFFIN %f/eurocrypt/ygbo4i79grwhxexlbtfkorufic8vac6p.pdf %m3ef69a790a703391e5740d25a4a5f4e4 %ceurocrypt %@Yevgeniy Dodis,John Steinberger %*Domain Extension for MACs Beyond the Birthday Barrier %f/eurocrypt/o1cqddavxgubt0yytzbi89mjkrn4h5fm.pdf %m1af77c83f4e001bb774583059d6d0d05 %ceurocrypt %@Pouyan Sepehrdad,Serge Vaudenay,Martin Vuagnoux %*Statistical Attack on RC4 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Rabin,Leonid Reyzin,Eran Tromer,Vinod Vaikuntanathan %*Protecting Circuits from Leakage: the Computationally-Bounded and Noisy Cases %f/eurocrypt/xfdj5pfgcwukqpj4ibnaxketmrca19wo.pdf %me2f3002751e91fb70460c3fce79321df %ceurocrypt %@S. Dov Gordon,Jonathan Katz %*Partial Fairness in Secure Two-Party Computation %f/eurocrypt/aiayzwt4mu2cesl9p7hjqebpwo6kvkiy.pdf %m664701049cc6bc573caa34fa2f750b3c %ceurocrypt %@Juan Garay,Clint Givens,Rafail Ostrovsky %*Secure Message Transmission with Small Public Discussion %f/eurocrypt/9kljy8qrifhumd5olubtngvmihswnpoa.pdf %m3d6b490b20df313c26d95260e366a9ed %ceurocrypt %@Marc Fischlin,Dominique Schröder %*On the Impossibility of Three-Move Blind Signature Schemes %f/eurocrypt/x2h9bzskjtmkryo0puzdvue1h3cxqygb.pdf %m0b060a1ae28c4ab676ca4f6878e6d974 %ceurocrypt %@Esther Hänggi,Renato Renner,Stefan Wolf %*Efficient Device-Independent Quantum Key Distribution %f/eurocrypt/gaex05zdyutksbqgsvm7nfj2qk3l8xdm.pdf %m9d6f160feddb10ac9cb06575d91b11f1 %ceurocrypt %@Nick Howgrave-Graham,Antoine Joux %*New Generic Algorithms for Hard Knapsacks %f/eurocrypt/x6kju2bglzsnegdejdh3otyavfcvq7io.pdf %m0eb2b36f8df0cb964dd7b472749d8448 %ceurocrypt %@Nicolas Gama,Phong Q. Nguyen,Oded Regev %*Lattice Enumeration Using Extreme Pruning %f/eurocrypt/qtlf7w0iyxucvgxwcdm2oyv5a8mqngaf.pdf %m9c625f3a429c0c0c45d07af119941d0b %ceurocrypt %@Jean-Charles Faugère,Ayoub Otmani,Ludovic Perret,Jean-Pierre Tillich %*Algebraic Cryptanalysis of McEliece Variants with Compact Keys %f/eurocrypt/rpayjshtygaogjw6ubi2ew0nlizqhc4m.pdf %mc3500ed440dff8d78ed076e99a2749ea %ceurocrypt %@Alex Biryukov,Orr Dunkelman,Nathan Keller,Dmitry Khovratovich,Adi Shamir %*Key Recovery Attacks of Practical Complexity on AES-256 Variants with up to 10 Rounds %f/eurocrypt/b5cuhgyzwnsdipx2r6zdlkaecvkf0b1m.pdf %mc3ab0e9a9fd4b9cd7739c4d29d38cdab %ceurocrypt %@Moti Yung %*Cryptography between Wonderland and Underland %f/eurocrypt/ew84phkjvbxycalbypzkiue5fdlswncf.pdf %m3d10925819be775a872b32727741e7e0 %ceurocrypt %@Alex Biryukov,Ivica Nikolić %*Automatic Search for Related-Key Differential Characteristics in Byte-Oriented Block Ciphers: Application to AES, Camellia, Khazad and Others %f/eurocrypt/90p3x1vl7czvsjkusrgjpilhgb56txyh.pdf %m51756474da4e36aca71855d9a6c596f8 %ceurocrypt %@Kenneth G. Paterson,Gaven J. Watson %*Plaintext-Dependent Decryption: A Formal Security Treatment of SSH-CTR %f/eurocrypt/ndiyucmfshxkgmnloq0oar9bhiexa8vj.pdf %m531b0b581049b69fc1d7dc4fe853202a %ceurocrypt %@Daniele Micciancio %*Computational Soundness, Co-induction, and Encryption Cycles %f/eurocrypt/vne3om8qaugojfc1d5h4ltpzylptia62.pdf %mb2ff41819e682c025f7fd620e0895578 %ceurocrypt %@Serge Fehr,Dennis Hofheinz,Eike Kiltz,Hoeteck Wee %*Encryption Schemes Secure against Chosen-Ciphertext Selective Opening Attacks %f/eurocrypt/urterlgc5vpsugkanisjffzbq69mj8wm.pdf %m2a1c8a92082814e246940a1a088c7a98 %ceurocrypt %@Tolga Acar,Mira Belenkiy,Mihir Bellare,David Cash %*Cryptographic Agility and Its Relation to Circular Encryption %f/eurocrypt/l4ktbwid0rszg318ghpyvweaccjmxsqf.pdf %m601a02bd18c277f9e6216958cf1c0ef1 %ceurocrypt %@Boaz Barak,Iftach Haitner,Dennis Hofheinz,Yuval Ishai %*Bounded Key-Dependent Message Security %f/eurocrypt/fmgqf24liq5ypgk60x3vvntuzt9s1rcm.pdf %mc54a9ccb6dae90a4e865491d7abcc2bd %ceurocrypt %@Ivan Damgård,Yuval Ishai,Mikkel Krøigaard %*Perfectly Secure Multiparty Computation and the Computational Overhead of Cryptography %f/eurocrypt/yoqkropf6ecjpxsnyz03ljhqastbcu12.pdf %mf1bccd29696bef7e4bb3e3b265ecbc1e %ceurocrypt %@Martin Hirt,Vassilis Zikas %*Adaptively Secure Broadcast %f/eurocrypt/fabxo7vh2vtw69imcgiasuqyhlpesdmw.pdf %ma36b122b2a986e7c55ea2bbc9cd1e8c0 %ceurocrypt %@Dominique Unruh %*Universally Composable Quantum Multi-party Computation %f/eurocrypt/4h3ftygzitjcuuxs5kyefbpargd9henz.pdf %m9a07544e7013aa14881eb94b622bcf01 %ceurocrypt %@Craig Gentry,Shai Halevi,Vinod Vaikuntanathan %*A Simple BGN-Type Cryptosystem from LWE %f/eurocrypt/yiwjlyi691gsr5xnkf7ofhzga8v2rqd0.pdf %mcab7fa713874f64f1bf3b1ad0f8881cb %ceurocrypt %@David Cash,Dennis Hofheinz,Eike Kiltz,Chris Peikert %*Bonsai Trees, or How to Delegate a Lattice Basis %f/eurocrypt/sa8hbpio1yerkjmkgfusvwet63vlc2zr.pdf %m5eca6fef954c27a11fe5ebafda82e9a9 %ceurocrypt %@Shweta Agrawal,Dan Boneh,Xavier Boyen %*Efficient Lattice (H)IBE in the Standard Model %f/eurocrypt/vkzn7ymujbpilo1ma0t2gkbipa9sjyer.pdf %mdfa2b98aeb6806f122463a94c2f48650 %ceurocrypt %@Jooyoung Lee,John Steinberger %*Multi-property-preserving Domain Extension Using Polynomial-Based Modes of Operation %f/eurocrypt/yau5spkbe7rhklqwi4gclmtxtnw6r8ag.pdf %m12ec922969b137c8fa7eefa3e53d0b11 %ceurocrypt %@John Steinberger %*Stam’s Collision Resistance Conjecture %f/eurocrypt/9n2xphbzmwcioqlpb8efvuynj7rr43ej.pdf %m4ed520a57d2f1cc8d5231fe5e01e8c5f %ceurocrypt %@Iftach Haitner,Thomas Holenstein,Omer Reingold,Salil Vadhan,Hoeteck Wee %*Universal One-Way Hash Functions via Inaccessible Entropy %f/eurocrypt/hqwwso6bhn7a0x1eidt5rtp9yjklcur3.pdf %mec0441cf8f5527392b83c3ea1aecfcde %ceurocrypt %@Rafael Pass,Hoeteck Wee %*Constant-Round Non-malleable Commitments from Sub-exponential One-Way Functions %f/eurocrypt/fn7enl1lj2t0h98pazr6ymkqfdwj4bxg.pdf %ma1113c2ea6ba3914033bc65d5f24df7b %ceurocrypt %@Susan Hohenberger,Brent Waters %*Constructing Verifiable Random Functions with Large Input Spaces %f/eurocrypt/fbhagkjr5mk3nc6ooqietqxmz9rtz2w0.pdf %m8c394639ada65b63fcd223b4035c52e8 %ceurocrypt %@Eike Kiltz,Payman Mohassel,Adam O’Neill %*Adaptive Trapdoor Functions and Chosen-Ciphertext Security %f/eurocrypt/rfd7liiehaqufyzysx8wuwkrnmsovghp.pdf %m9423d81f8704c9cea11c50e351f3d731 %ceurocrypt %@Mihir Bellare,Dennis Hofheinz,Scott Yilek %*Possibility and Impossibility Results for Encryption and Commitment Secure under Selective Opening %f/eurocrypt/9jlxq4oaupwuerijfxmodzste87agbvy.pdf %mc9bb4d36b6be10e80cbc095b1b888624 %ceurocrypt %@Divesh Aggarwal,Ueli Maurer %*Breaking RSA Generically Is Equivalent to Factoring %f/eurocrypt/8b75iwbjnxvuhjso1rekt9ym4efpcszg.pdf %m90c402556f2b8053ec0725fda870b9aa %ceurocrypt %@Vipul Goyal,Amit Sahai %*Resettably Secure Computation %f/eurocrypt/ajbxkzhwocwe518rk0yflqc3sxp9s7va.pdf %m313cda3bb382f728882495ad07b2c083 %ceurocrypt %@Chi-Jen Lu %*On the Security Loss in Cryptographic Reductions %f/eurocrypt/fdktp5wyqjyhsatr864xivgxnkv1zz90.pdf %m1aae615bd7ea50549e058360be444978 %ceurocrypt %@Praveen Gauravaram,Lars R. Knudsen %*On Randomizing Hash Functions to Strengthen the Security of Digital Signatures %f/eurocrypt/on0z3iw6y9c4yfgtbudimpjxenmsgfwv.pdf %ma6078d618440ef04f59f6dcff4271994 %ceurocrypt %@Lars R. Knudsen,Florian Mendel,Christian Rechberger,Søren S. Thomsen %*Cryptanalysis of MDC-2 %f/eurocrypt/exmdfnhcjok9wtaysetlmi0pbxfubzk2.pdf %mffeafbda0a23b7d23ce7b25133a0c43d %ceurocrypt %@Xiaoyun Wang,Hongbo Yu,Wei Wang,Haina Zhang,Tao Zhan %*Cryptanalysis on HMAC/NMAC-MD5 and MD5-MAC %f/eurocrypt/mkcuzf0n9yrsx3xarfblznj45kvtjyq2.pdf %md0b8bcb4bc227598e8e5b2d6aab9aeb2 %ceurocrypt %@Yu Sasaki,Kazumaro Aoki %*Finding Preimages in Full MD5 Faster Than Exhaustive Search %f/eurocrypt/5gw2lp1ypfqdsb4w3zbldon8uvhmmf0t.pdf %m807c7419128fb7b39224092d85b2f41d %ceurocrypt %@Qianhong Wu,Yi Mu,Willy Susilo,Bo Qin,Josep Domingo-Ferrer %*Asymmetric Group Key Agreement %f/eurocrypt/objvskrh8qr4ec7vsq6i9fwluhagexp1.pdf %mc2d6141e9a808915381a72121275ab83 %ceurocrypt %@Craig Gentry,Brent Waters %*Adaptive Security in Broadcast Encryption Systems (with Short Ciphertexts) %f/eurocrypt/ptwgxzpdx61qdesgbnqmrutlcmjnih5a.pdf %mdaaf500b9ca4f7d35cdb66126f9151dd %ceurocrypt %@Olivier Billet,Duong Hieu Phan %*Traitors Collaborating in Public: Pirates 2.0 %f/eurocrypt/1r3tk2ciuxbbvc5ayijfjt6zv9moeamx.pdf %m3f58b5468d696c3541b3d6d4520204af %ceurocrypt %@Bhavana Kanukurthi,Leonid Reyzin %*Key Agreement from Close Secrets over Unsecured Channels %f/eurocrypt/sqxtyxg1chbok6d9jg3qzikdp72hwui0.pdf %me554895ed9083412b15d51d0b05d720e %ceurocrypt %@Alexandra Boldyreva,Nathan Chenette,Younho Lee,Adam O’Neill %*Order-Preserving Symmetric Encryption %f/eurocrypt/qit0ge7kbooyifjswqc3wdtx1hp48uug.pdf %mb94b937c34e18b494000fc67e6045743 %ceurocrypt %@Kan Yasuda %*A Double-Piped Mode of Operation for MACs, PRFs and PROs: Security beyond the Birthday Barrier %f/eurocrypt/noqp29kxl65vzlakhvwamsm71s0ujii4.pdf %me5fa63672b255494bd97e07bb084f551 %ceurocrypt %@Guilhem Castagnos,Fabien Laguillaumie %*On the Security of Cryptosystems with Quadratic Decryption: The Nicest Cryptanalysis %f/eurocrypt/okzcawgtwde1xpaih2o0s6fcsq3jpgmb.pdf %m7576085dd97f257fea7391c55292318d %ceurocrypt %@Itai Dinur,Adi Shamir %*Cube Attacks on Tweakable Black Box Polynomials %f/eurocrypt/cwke3gilrfqn7y2zph8sximytdstjov4.pdf %m2cda090a2f3a497c0ab4984a1251dda4 %ceurocrypt %@Khaled Ouafi,Serge Vaudenay %*Smashing SQUASH-0 %f/eurocrypt/dhwqt1ahrbaklezvjylbd49g03ocntxi.pdf %ma9dc69965f744db2b67209ad9d851b27 %ceurocrypt %@Dennis Hofheinz,Eike Kiltz %*Practical Chosen Ciphertext Secure Encryption from Factoring %f/eurocrypt/qlz1orh43wazw6ppcsomxg7hifvcnxj0.pdf %m67510df084c91c31a81983a5370e0e02 %ceurocrypt %@Susan Hohenberger,Brent Waters %*Realizing Hash-and-Sign Signatures under Standard Assumptions %f/eurocrypt/5xhcn02yyffvwtgilrovbsm3tezads9e.pdf %mb893d1fbef62bc19ce6759bb38eb4b84 %ceurocrypt %@Jan Camenisch,Nishanth Chandran,Victor Shoup %*A Public Key Encryption Scheme Secure against Key Dependent Chosen Plaintext and Adaptive Chosen Ciphertext Attacks %f/eurocrypt/msnty876qvgifwaye3k2hlonfdk5bpxu.pdf %m55944ad29fb65714fc799a7d3ec4c30c %ceurocrypt %@Shafi Goldwasser %*Cryptography without (Hardly Any) Secrets ? %f/eurocrypt/7kuy3gkrgwyaswoiupaq8cql5sz1hefx.pdf %m8e91f991c6b7ba28e27b787168eb9854 %ceurocrypt %@Yevgeniy Dodis,Thomas Ristenpart,Thomas Shrimpton %*Salvaging Merkle-Damgård for Practical Applications %f/eurocrypt/zwkmv8a6qidggoaycrsjr9uo5xfui0zw.pdf %mf3df060ceb54a1c4829f189d96c616d0 %ceurocrypt %@Eike Kiltz,Krzysztof Pietrzak %*On the Security of Padding-Based Encryption Schemes – or – Why We Cannot Prove OAEP Secure in the Standard Model %f/eurocrypt/nb6yus4p1btftexlk5dxpjeznc0oh3fv.pdf %mc2737247932ac5c905fd74ef6580b5b6 %ceurocrypt %@Mihir Bellare,Thomas Ristenpart %*Simulation without the Artificial Abort: Simplified Proof and Improved Concrete Security for Waters’ IBE Scheme %f/eurocrypt/kreip173xwofltxbapcjvm6u9yvg8hzr.pdf %m8a14a8fffca401fa4ef4426c10200105 %ceurocrypt %@Jan Camenisch,Aggelos Kiayias,Moti Yung %*On the Portability of Generalized Schnorr Proofs %f/eurocrypt/kyp6o1yhftpv5fcirxuaoi8jcjwevwsz.pdf %m6f2e81cb7815f4e357b450c3cca10f78 %ceurocrypt %@François-Xavier Standaert,Tal G. Malkin,Moti Yung %*A Unified Framework for the Analysis of Side-Channel Key Recovery Attacks %f/eurocrypt/pwwvgm4uydzs7oglsnkhicxf15aeab6y.pdf %m9236de690eddc421205aa3c42126fc03 %ceurocrypt %@Krzysztof Pietrzak %*A Leakage-Resilient Mode of Operation %f/eurocrypt/cvlsdj7438uybcikpholrz1s0oh9rpvy.pdf %m6e15d52f79330878bcf17f463badb4c6 %ceurocrypt %@Daniel J. Bernstein,Tien-Ren Chen,Chen-Mou Cheng,Tanja Lange,Bo-Yin Yang %*ECM on Graphics Cards %f/eurocrypt/edfsthcbsuajdgmie7umrq6n94rvl5yy.pdf %mf35f7b7ae85e9513e530bb417f30fa87 %ceurocrypt %@Christophe Doche,David R. Kohel,Francesco Sica %*Double-Base Number System for Multi-scalar Multiplications %f/eurocrypt/qvnx1jbzew5ei6lfokmo7rzsp2cbdnvu.pdf %mebbc7441999a257e86376d0ea72def32 %ceurocrypt %@Steven D. Galbraith,Xibin Lin,Michael Scott %*Endomorphisms for Faster Elliptic Curve Cryptography on a Large Class of Curves %f/eurocrypt/cspebizn2hxiuar3rmyu0eht5gd9cx4v.pdf %m0f46a44b854d661b284afec26e839cef %ceurocrypt %@Takakazu Satoh %*Generating Genus Two Hyperelliptic Curves over Large Characteristic Finite Fields %f/eurocrypt/wxkdrlzfd2yjhtogqbtepjhr35ikx7mb.pdf %md623747662e58fed086590cb3b76630a %ceurocrypt %@Michel Abdalla,Dario Catalano,Dario Fiore %*Verifiable Random Functions from Identity-Based Key Encapsulation %f/eurocrypt/j7zbklpecqhgodluhemg8jtsq9xwb40z.pdf %m838ec44d5453f85b66701d521f5bc09b %ceurocrypt %@Céline Chevalier,Pierre-Alain Fouque,David Pointcheval,Sébastien Zimmer %*Optimal Randomness Extraction from a Diffie-Hellman Element %f/eurocrypt/ynjuskxrcezs7xgtogewbmi0z9rqwchi.pdf %mce7383a90ed2a4112404eee7a1cb209c %ceurocrypt %@Eike Kiltz,Krzysztof Pietrzak,Martijn Stam,Moti Yung %*A New Randomness Extraction Paradigm for Hybrid Encryption %f/eurocrypt/zwlocogqixhj18smzvbuhn9q2sevgxe0.pdf %m93e7b58a289f8ad59c37baf76394176c %ceurocrypt %@Sebastiaan Indesteege,Nathan Keller,Orr Dunkelman,Eli Biham,Bart Preneel %*A Practical Attack on KeeLoq %f/eurocrypt/mfrn6vnjshcgp5xu9gejvo7hkabpy2zl.pdf %mab7a82b2019d7ddeb0fa6042c7909b8a %ceurocrypt %@Pierre-Alain Fouque,Gilles Macario-Rat,Jacques Stern %*Key Recovery on Hidden Monomial Multivariate Schemes %f/eurocrypt/n87da6rt9scghbgfw2ln4hxuxfvyoz5m.pdf %m88d7d7aa40171c49cb4eda7e87b55cb6 %ceurocrypt %@Nicolas Gama,Phong Q. Nguyen %*Predicting Lattice Reduction %f/eurocrypt/tjmbh0ztj5vosrqxnxd8m7czc4puyygh.pdf %macebd216826a8fea3e28b7b909a0d921 %ceurocrypt %@Gregory Neven %*Efficient Sequential Aggregate Signed Data %f/eurocrypt/watjnsvcivgpywletdbpn3ohq7j2uadr.pdf %mfa06375c8747b5d31d6b9c6f33fa0d51 %ceurocrypt %@Daniel J. Bernstein %*Proving Tight Security for Rabin-Williams Signatures %f/eurocrypt/kdpobgrcw4en30yc1k6hi7lipumds2qm.pdf %mbde572034af34628bd0f0458b228b027 %ceurocrypt %@Rosario Gennaro,Shai Halevi,Hugo Krawczyk,Tal Rabin %*Threshold RSA for Dynamic and Ad-Hoc Groups %f/eurocrypt/3anc9aruostqi8wbx7hvuzehfnoglbtp.pdf %m2acb10c36fb553c83eb9cbbae003030c %ceurocrypt %@Dennis Hofheinz,Dominique Unruh %*Towards Key-Dependent Message Security in the Standard Model %f/eurocrypt/nqcgwa1ijo794yhy3usai5gjd2fmsclk.pdf %m3478d642c4e4193c789e1faaa3a9bdd6 %ceurocrypt %@David Cash,Eike Kiltz,Victor Shoup %*The Twin Diffie-Hellman Problem and Applications %f/eurocrypt/f1rkisjzmftek5doqyhv9xguzroeqwpc.pdf %m07e80d01571fd9573db041432a2c7354 %ceurocrypt %@Jonathan Katz,Amit Sahai,Brent Waters %*Predicate Encryption Supporting Disjunctions, Polynomial Equations, and Inner Products %f/eurocrypt/k83syjye0nw42gcbzlaqghekduznvsio.pdf %ma8d4332131311813b5f106f24092f2f4 %ceurocrypt %@Benjamin Smith %*Isogenies and the Discrete Logarithm Problem in Jacobians of Genus 3 Hyperelliptic Curves %f/eurocrypt/ub8x4ppcbny2oevoeadshdfgz0twq9xs.pdf %m8159037a6a8b2be9ffe37891f5bc0142 %ceurocrypt %@Guido Bertoni,Joan Daemen,Michaël Peeters,Gilles Van Assche %*On the Indifferentiability of the Sponge Construction %f/eurocrypt/b16olunrzmp9xwjgmxese8dbsw7pgflk.pdf %m2521b52732b75b51ec037ba60c1f04fc %ceurocrypt %@Yevgeniy Dodis,Krzysztof Pietrzak,Prashant Puniya %*A New Mode of Operation for Block Ciphers and Length-Preserving MACs %f/eurocrypt/5v0qutfy6i2ywxlvcuhaktw1xohdze9q.pdf %me7190d284af956580eb0bd6236f9f95f %ceurocrypt %@Phillip Rogaway,John Steinberger %*Security/Efficiency Tradeoffs for Permutation-Based Hashing %f/eurocrypt/19natsm4hpvbjogeqivccadw3yiuom7w.pdf %med2d65dc94a7b9d20726d7cebf1a3439 %ceurocrypt %@Lei Wang,Kazuo Ohta,Noboru Kunihiro %*New Key-Recovery Attacks on HMAC/NMAC-MD4 and NMAC-MD5 %f/eurocrypt/5ggti86pyz349ahcierrksbjzf2sblv7.pdf %m907524288e0a71f3bc3b3ada29571824 %ceurocrypt %@Jean-Pierre Tillich,Gilles Zémor %*Collisions for the LPS Expander Graph Hash Function %f/eurocrypt/rbjrfxzcalfj9vd5ckq0hwyltohm7iev.pdf %m10979463d3a951f299a69e16ddc02370 %ceurocrypt %@Elena Andreeva,Charles Bouillaguet,Pierre-Alain Fouque,Jonathan J. Hoch,John Kelsey,Adi Shamir,Sebastien Zimmer %*Second Preimage Attacks on Dithered Hash Functions %f/eurocrypt/sp4r7pxonkhbyhei2weo1iyfzqb8fklt.pdf %m6fb1edee6d3d111609aaff34c0984a58 %ceurocrypt %@Vipul Goyal,Payman Mohassel,Adam Smith %*Efficient Two Party and Multi Party Computation Against Covert Adversaries %f/eurocrypt/jzrwkd14afnxo3clbq0azgxgkpb5se72.pdf %m322ad654c6fc682363c76621f664691f %ceurocrypt %@Juan A. Garay,Rafail Ostrovsky %*Almost-Everywhere Secure Computation %f/eurocrypt/enxhbpf8wqaylk5jbikzmdd3v20wuptr.pdf %md16e4cc5fb5fb0aeee8ca8e83dd3e4b3 %ceurocrypt %@Kaoru Kurosawa,Kazuhiro Suzuki %*Truly Efficient 2-Round Perfectly Secure Message Transmission Scheme %f/eurocrypt/xk5xgn6bkfalwtcvyhjeta0gnpzcrqiz.pdf %m2946569f79d7515976ac032f1d730f11 %ceurocrypt %@Boaz Barak,Sharon Goldberg,David Xiao %*Protocols and Lower Bounds for Failure Localization in the Internet %f/eurocrypt/g8vwubrvqqdrjxsekotg35nyz209malf.pdf %m0a200c74e99a642bb7710cb4bec5ea5e %ceurocrypt %@Henri Gilbert,Matthew J. B. Robshaw,Yannick Seurin %*: Increasing the Security and Efficiency of %f/eurocrypt/pkqwdkhijlsfecabtyzeg7ilap1on2ds.pdf %m8394603f9206bc897b759e62a74a4c62 %ceurocrypt %@Jens Groth,Yuval Ishai %*Sub-linear Zero-Knowledge Argument for Correctness of a Shuffle %f/eurocrypt/mipafbvurlwanxdlveqwezjcbstd1gfo.pdf %m943b1103a72d5a503711b799c7ae02b1 %ceurocrypt %@Omkant Pandey,Rafael Pass,Amit Sahai,Wei-Lung Dustin Tseng,Muthuramakrishnan Venkitasubramaniam %*Precise Concurrent Zero Knowledge %f/eurocrypt/f6bmls5tyzhxar4u2gnch3xr0mnza7qp.pdf %m4a32a0999fdd6389756b38941dc7bfc5 %ceurocrypt %@Jens Groth,Amit Sahai %*Efficient Non-interactive Proof Systems for Bilinear Groups %f/eurocrypt/j73qdcwulnxgz6pt9gkndeixs1calryt.pdf %m5004121a83a80aff61d81b899b8cb608 %ceurocrypt %@Dario Catalano,Dario Fiore,Mariagrazia Messina %*Zero-Knowledge Sets with Short Proofs %f/eurocrypt/8jegdyqjrose7xmo0hcgn5fuywpluznk.pdf %md5947d1d156c59b93ca069a42e362230 %ceurocrypt %@Hao Chen,Ronald Cramer,Robbert de Haan,Ignacio Cascudo Pueyo %*Strongly Multiplicative Ramp Schemes from High Degree Rational Points on Curves %f/eurocrypt/nepsgj5uxqchz3rd8rv7weifznpwv2bl.pdf %m9514f4a3ac6b9d126b37079fd6a7b24f %ceurocrypt %@Ronald Cramer,Yevgeniy Dodis,Serge Fehr,Carles Padró,Daniel Wichs %*Detection of Algebraic Manipulation with Applications to Robust Secret Sharing and Fuzzy Extractors %f/eurocrypt/xz9beubyeiiw4olozrqt52fvymnjlhpk.pdf %md19f1c33e1da459804072ce88f2bd662 %ceurocrypt %@Ran Canetti,Ronny Ramzi Dakdouk %*Obfuscating Point Functions with Multibit Output %f/eurocrypt/pm7rbzjy6ncoyxvkfsql4ggpfwktdtw2.pdf %mc87563f73a745bcc0beef79503f15a42 %ceurocrypt %@Ivan Damgård,Jesper Buus Nielsen,Daniel Wichs %*Isolated Proofs of Knowledge and Isolated Zero Knowledge %f/eurocrypt/43kcfbxdxp1o0na9bikqt2tljmwjlqyo.pdf %m7430ef3f0a601ece6b41ae5e14bccbd3 %ceurocrypt %@Tal Moran,Gil Segev %*David and Goliath Commitments: UC Computation for Asymmetric Parties Using Tamper-Proof Hardware %f/eurocrypt/ihjyg4e598profchc2p7ysnqkvgoim0u.pdf %m8e1a7ba90a271323ccdf0bce027dbaf5 %ceurocrypt %@Nishanth Chandran,Vipul Goyal,Amit Sahai %*New Constructions for UC Secure Computation Using Tamper-Proof Hardware %f/eurocrypt/s9orzijbe7k4ynf38lumxjmqwaitpfc1.pdf %m56480cc8ce8b150a0540c059366db192 %ceurocrypt %@Marc Stevens,Arjen Lenstra,Benne de Weger %*Chosen-Prefix Collisions for MD5 and Colliding X.509 Certificates for Different Identities %f/eurocrypt/0jg1enirntdobzj7lcv8mv6lk4pshx3f.pdf %m6ab72ba350a003d0defbe97120b1ea55 %ceurocrypt %@Krzysztof Pietrzak %*Non-trivial Black-Box Combiners for Collision-Resistant Hash-Functions Don’t Exist %f/eurocrypt/2yimdougahedlw6ln08aszrcgpqkexbb.pdf %mf57f2580330ae685fd0bb0ab5b7a5b01 %ceurocrypt %@John P. Steinberger %*The Collision Intractability of MDC-2 in the Ideal-Cipher Model %f/eurocrypt/estisrv0mn8v3ykfwodxbgd9pqfrznce.pdf %m40769537bacf9a06eaaddeace19cb7fe %ceurocrypt %@Yehuda Lindell,Benny Pinkas %*An Efficient Protocol for Secure Two-Party Computation in the Presence of Malicious Adversaries %f/eurocrypt/vkdap0ln41sh9mj6bryzxzjfmldircet.pdf %m6bf177f715643a3ebf2c1a4c85dd20f5 %ceurocrypt %@David P. Woodruff %*Revisiting the Efficiency of Malicious Two-Party Computation %f/eurocrypt/wfkjzspg5auytvxgby1mmlr9rdokhuqe.pdf %m8e45964fe21ddf2b44c4f36f8f494d17 %ceurocrypt %@Stanisław Jarecki,Vitaly Shmatikov %*Efficient Two-Party Secure Computation on Committed Inputs %f/eurocrypt/4j9temqwa28b3yfjomrlwdsvg6bczvly.pdf %md1960def483811f44d1a57040d2e2c51 %ceurocrypt %@Jonathan Katz %*Universally Composable Multi-party Computation Using Tamper-Proof Hardware %f/eurocrypt/aiflwsb0rbifxwc1stymdluhqoeza8jt.pdf %m4d3e0d81d954a97223faa1ad1cbc944a %ceurocrypt %@Moti Yung,Yunlei Zhao %*Generic and Practical Resettable Zero-Knowledge in the Bare Public-Key Model %f/eurocrypt/eqpzvdonlnggyaifoc0hd31esv9lcaqj.pdf %mdb4d286f806b818a5332138245a673a0 %ceurocrypt %@Yi Deng,Dongdai Lin %*Instance-Dependent Verifiable Random Functions and Their Application to Simultaneous Resettability %f/eurocrypt/ekepwficldkr1ytnlr3upyois4xtdfz2.pdf %m3d9eb828107af52005dea382159a9522 %ceurocrypt %@Chun-Yuan Hsiao,Chi-Jen Lu,Leonid Reyzin %*Conditional Computational Entropy, or Toward Separating Pseudoentropy from Compressibility %f/eurocrypt/3ipbgl9qwsntzchhauwyjpacnkb47s0d.pdf %m0a4cc99a4fb866b26cd4c3710c9f0e8a %ceurocrypt %@Shien Jin Ong,Salil Vadhan %*Zero Knowledge and Soundness Are Symmetric %f/eurocrypt/w5qwoc9pg2yvdeusdtlu6z8kelh4gjvf.pdf %m737dc81fe8a0fb4aac267d6020ddc19c %ceurocrypt %@Xavier Boyen %*Mesh Signatures %f/eurocrypt/be0djhc4gjm9qhutrnwsrizs5filfpya.pdf %mf4458e2d0ca5bb59a71e74b31bf56b8a %ceurocrypt %@Thomas Ristenpart,Scott Yilek %*The Power of Proofs-of-Possession: Securing Multiparty Signatures against Rogue-Key Attacks %f/eurocrypt/fr97gvxbloeifqjag05nowmm2nh4bsc6.pdf %mc2b311d81d4dd151ba5c7ea468eff2e9 %ceurocrypt %@Jan Camenisch,Susan Hohenberger,Michael Østergaard Pedersen %*Batch Verification of Short Signatures %f/eurocrypt/yfhib0so9vdjbiwfk7qeolxpueswyl6z.pdf %ma52659dee247d7973d5103df0adbc74e %ceurocrypt %@Vivien Dubois,Pierre-Alain Fouque,Jacques Stern %*Cryptanalysis of SFLASH with Slightly Modified Parameters %f/eurocrypt/abtlaiyljk2eqxbswnmj03dut4hzopwu.pdf %m0b29a87e2b4bf33d6cbefab76c467347 %ceurocrypt %@Hongjun Wu,Bart Preneel %*Differential Cryptanalysis of the Stream Ciphers Py, Py6 and Pypy %f/eurocrypt/lnw0qahbq4tofus9xwvdcaged3cmpnj8.pdf %m69f5a31f56d1cb47ebb44f298ebcec61 %ceurocrypt %@Hao Chen,Ronald Cramer,Shafi Goldwasser,Robbert de Haan,Vinod Vaikuntanathan %*Secure Computation from Random Error Correcting Codes %f/eurocrypt/1t9y5jkrdgpucneq6sv7uwyfbohxadiw.pdf %m429920c076d54bc2e90fc9c70f12b65c %ceurocrypt %@Jonathan Katz,Chiu-Yuen Koo %*Round-Efficient Secure Computation in Point-to-Point Networks %f/eurocrypt/dhvqr4zz1xikprvjbl2kwet75nfmncub.pdf %mbf7b9067750a842a749bb3452e306e27 %ceurocrypt %@Ronald Cramer,Ivan Damgård,Robbert de Haan %*Atomic Secure Multi-party Multiplication with Low Communication %f/eurocrypt/hk7ii0abx6wltnhkbugzd5jgx3sflcao.pdf %mc3c7024cb8f84b48060d1f9e3fe1db21 %ceurocrypt %@Lorenz Minder,Amin Shokrollahi %*Cryptanalysis of the Sidelnikov Cryptosystem %f/eurocrypt/4emjpfybixoanzfitz9h0djrulcosr2k.pdf %maf381d1e4b9a3129eb78534be77bf064 %ceurocrypt %@Aurélie Bauer,Antoine Joux %*Toward a Rigorous Variation of Coppersmith’s Algorithm on Three Variables %f/eurocrypt/dh18zco6krhyyisal3mkbtnjxzefo4um.pdf %m76e3c00e8004bcb3298170fbdec7ef23 %ceurocrypt %@Andreas Enge,Pierrick Gaudry %*An L (1/3 + ε) Algorithm for the Discrete Logarithm Problem for Low Degree Curves %f/eurocrypt/vvfhhyd9apk6ul5bxdjtsjcmmu4b1q3k.pdf %m84eb602422750f87a8a747bbb3647877 %ceurocrypt %@Xavier Boyen %*General Ad Hoc Encryption from Exponent Inversion IBE %f/eurocrypt/qdkmmliqzsifakb5u3fwpjnzr9v06evg.pdf %mac9be31360be66be5fd6c55db62d11ec %ceurocrypt %@Ivan Damgård,Rune Thorbek %*Non-interactive Proofs for Integer Multiplication %f/eurocrypt/vw7uzuzjymg3podf9kepga6sqttd8cfb.pdf %mff85f36d038865132e287df6fe4b218f %ceurocrypt %@R. Granger,F. Hess,R. Oyono,N. Thériault,F. Vercauteren %*Ate Pairing on Hyperelliptic Curves %f/eurocrypt/zf37xbqorrfvc9iwgkmqapiljk0cteld.pdf %mfdb60ca48db08a11e3a3fe28be23e401 %ceurocrypt %@Oriol Farràs,Jaume Martí-Farré,Carles Padró %*Ideal Multipartite Secret Sharing Schemes %f/eurocrypt/xtuvaoukzkmvjfy8zmqnnlb7r91ociq6.pdf %m1022e5906f8b773120745184b3a43c28 %ceurocrypt %@Willi Geiselmann,Rainer Steinwandt %*Non-wafer-Scale Sieving Hardware for the NFS: Another Attempt to Cope with 1024-Bit %f/eurocrypt/fe4wrjpeusm6r3cfxolivkbwmkz71sxo.pdf %m0a49555643754c42b50f1af095e39b3f %ceurocrypt %@Sébastien Canard,Aline Gouget %*Divisible E-Cash Systems Can Be Truly Anonymous %f/eurocrypt/nf624rczjvmlxvjkdgcs93idhpeoerig.pdf %mdc671e3b75c35deef554a59de13d60a3 %ceurocrypt %@Ueli Maurer,Johan Sjödin %*A Fast and Key-Efficient Reduction of Chosen-Ciphertext to Known-Plaintext Security %f/eurocrypt/vixck7fwq0buemxetsuaph4spddrntio.pdf %m87f4611c57e216d6fd454a1011b70c68 %ceurocrypt %@Krzysztof Pietrzak,Johan Sjödin %*Range Extension for Weak PRFs; The Good, the Bad, and the Ugly %f/eurocrypt/ra5ysl9jtoczv64xiedzfvwibhenkg2m.pdf %m27912afa616aa85e09581a2e16330e12 %ceurocrypt %@Yevgeniy Dodis,Prashant Puniya %*Feistel Networks Made Public, and Applications %f/eurocrypt/ycxdkuvxzc8njo9v6r73nzpggptyefsq.pdf %m3e66ec9f54daada3d9607e35e744e246 %ceurocrypt %@Jürg Wullschleger %*Oblivious-Transfer Amplification %f/eurocrypt/q6sn7m30frdp9owznymylvgceqob1uwh.pdf %mad40d42be565c2df87c5e3d32cb9d9d5 %ceurocrypt %@Jan Camenisch,Gregory Neven,abhi shelat %*Simulatable Adaptive Oblivious Transfer %f/eurocrypt/ctn8w29roqs1gcv6bfabfhqz4iw5tmyl.pdf %md59720b42add988435f868db73890a01 %ceurocrypt %@Jung Hee Cheon %*Security Analysis of the Strong Diffie-Hellman Problem %f/eurocrypt/udcwgyfi9ubb10rjptpvf7eewsaxh84x.pdf %m94a0d0c4dbc6537ad2a0001cfd574aa9 %ceurocrypt %@Kenneth G. Paterson,Arnold K. L. Yau %*Cryptography in Theory and Practice: The Case of Encryption in IPsec %f/eurocrypt/atu2fh9rs8mcqiigxvedqkspelk76jzo.pdf %medb55d873149f6784f1dfe4305d1ccef %ceurocrypt %@Jean-Charles Faugère,Ludovic Perret %*Polynomial Equivalence Problems: Algorithmic and Theoretical Aspects %f/eurocrypt/t45a8xysz3zsmwuta106hcqorwile2df.pdf %mc2f64f637920fb5ab063b1cbb07f6f80 %ceurocrypt %@Vanessa Gratzer,David Naccache %*Alien vs. Quine, the Vanishing Circuit and Other Tales from the Industry’s Crypt %f/eurocrypt/rw9issdbk0tf8qrxvylukapmub46xo2f.pdf %ma9263decf3dbfedd789e2c30d61eab4e %ceurocrypt %@Ee-Chien Chang,Qiming Li %*Hiding Secret Points Amidst Chaff %f/eurocrypt/bn3i8zjrdyltvo15aph6dckhsmxufeze.pdf %me337abde2d96af077b835236376be6cc %ceurocrypt %@Jonathan Katz,Ji Sun Shin %*Parallel and Concurrent Security of the HB and HB +  Protocols %f/eurocrypt/rvuhgfxdtgcwqmo20tprcl4eqknzdxy9.pdf %m44e3139f825ecc99946284ce8b114e86 %ceurocrypt %@Tal Moran,Moni Naor %*Polling with Physical Envelopes: A Rigorous Analysis of a Human-Centric Protocol %f/eurocrypt/f51xz3ubkpmo6vwcnsy74ncl0itjrjpk.pdf %m4f9cd0e9d28eb8adfd1380ecd1da38e5 %ceurocrypt %@Côme Berbain,Henri Gilbert,Jacques Patarin %*QUAD: A Practical Stream Cipher with Provable Security %f/eurocrypt/kmwxcsm4nqpractknz7wv0uf6gro5tpu.pdf %m4cd0bc2fd4d2bbe1567e7579c248a278 %ceurocrypt %@Aline Gouget,Hervé Sibert %*How to Strengthen Pseudo-random Generators by Using Compression %f/eurocrypt/llurgj37dweno2vhzkt6gy1cz9pwsakh.pdf %mfce1cb9b986a294bfb9b638cf3566a6c %ceurocrypt %@Scott Contini,Arjen K. Lenstra,Ron Steinfeld %*VSH, an Efficient and Provable Collision-Resistant Hash Function %f/eurocrypt/5sqgm3tu96nyrpx2wlzgiovycipajh8a.pdf %m0b84ef379df15f8b672c6f2ec68dbc05 %ceurocrypt %@John Kelsey,Tadayoshi Kohno %*Herding Hash Functions and the Nostradamus Attack %f/eurocrypt/0cxzxmlvbw4fhamornvyrepbi2dtalgw.pdf %meec0055ba5dcb2c49a70de8b59f830fd %ceurocrypt %@Claude Crépeau,George Savvides %*Optimal Reductions Between Oblivious Transfers Using Interactive Hashing %f/eurocrypt/u7jivr2i4gmud9zvntspkkceqzdxmlwb.pdf %me2767eb8146d834c02f4dda3847f3d4c %ceurocrypt %@Stefan Wolf,Jürg Wullschleger %*Oblivious Transfer Is Symmetric %f/eurocrypt/sdvbtqyiujkx9pekxh6q0yo37cnl4wlc.pdf %m6b951df34a127cd80b47822324ace21b %ceurocrypt %@Nicolas Gama,Nick Howgrave-Graham,Phong Q. Nguyen %*Symplectic Lattice Reduction and NTRU %f/eurocrypt/ajutvxfrbxsh2mgrzchzsn3opegdjtvw.pdf %m91e3d5a24e27b9432676b81186be9d02 %ceurocrypt %@Antoine Joux,Reynald Lercier %*The Function Field Sieve in the Medium Prime Case %f/eurocrypt/y5hq3p0urxul2gfnrvyeimqto9dezgas.pdf %m170d5ae19f23da1447e1263de94a3940 %ceurocrypt %@Phong Q. Nguyen,Oded Regev %*Learning a Parallelepiped: Cryptanalysis of GGH and NTRU Signatures %f/eurocrypt/yzrml1er9a407cugnsit6thjfqdnz5wu.pdf %m410759e6cb856637be6644079814977e %ceurocrypt %@Alexander W. Dent %*The Cramer-Shoup Encryption Scheme Is Plaintext Aware in the Standard Model %f/eurocrypt/uqzmbe2prizkpjgo7mxoych4alnst9l6.pdf %m04510929bc161094e5d047e31b2a7eb7 %ceurocrypt %@Yuval Ishai,Manoj Prabhakaran,Amit Sahai,David Wagner %*Private Circuits II: Keeping Secrets in Tamperable Circuits %f/eurocrypt/yyiwluz4hqpsgu7pnv8oejsbmdrcrtmk.pdf %mb8a84f6489506009dd0bf32eeddc955c %ceurocrypt %@Krzysztof Pietrzak %*Composition Implies Adaptive Security in Minicrypt %f/eurocrypt/svlsit9perjwfhg2gbutkqp1r67bf38j.pdf %m8d8cb6163a8a603ff5ee86f857d9ac72 %ceurocrypt %@Jens Groth,Rafail Ostrovsky,Amit Sahai %*Perfect Non-interactive Zero Knowledge for NP %f/eurocrypt/coykmtupqig2h4znaksv1vajoe3yzbgf.pdf %m263216f74cd9ba1fdd997e325f3514b3 %ceurocrypt %@Kevin S. McCurley %*Language Modeling and Encryption on Packet Switched Networks %f/eurocrypt/dtvw6diqvnub04upzhgctsa8fmfkyeic.pdf %ma69d7ac6d93ba700e774705cffc65bfc %ceurocrypt %@Phillip Rogaway,Thomas Shrimpton %*A Provable-Security Treatment of the Key-Wrap Problem %f/eurocrypt/qtlhctzpgoqjmy1l2iwubdh5ug7f4ebm.pdf %m9926d6e5f54f61180433136e8cc5eb73 %ceurocrypt %@Ueli Maurer,Yvonne Anne Oswald,Krzysztof Pietrzak,Johan Sjödin %*Luby-Rackoff Ciphers from Weak Round Functions? %f/eurocrypt/fdpz4aecmoapxjoguhcwqb6ksxl1207n.pdf %m26093c1bd895293876e571eb76072bbc %ceurocrypt %@Mihir Bellare,Phillip Rogaway %*The Security of Triple Encryption and a Framework for Code-Based Game-Playing Proofs %f/eurocrypt/yfplvbg4me6jbh87ka0kgqiqat1rrsui.pdf %m1382805ea922a4eecdb360f77cfa08c0 %ceurocrypt %@Xavier Boyen,Brent Waters %*Compact Group Signatures Without Random Oracles %f/eurocrypt/grbk8tv71msq6d9xrehzcfoesymaygx4.pdf %m327ab36fcfd3957cad587b2f1f9b354a %ceurocrypt %@Craig Gentry %*Practical Identity-Based Encryption Without Random Oracles %f/eurocrypt/pipcc7lnsmw3nby5bd6rgejq1t8sihux.pdf %m2c1d2a86ec76670e1181e68cc958c44d %ceurocrypt %@Steve Lu,Rafail Ostrovsky,Amit Sahai,Hovav Shacham,Brent Waters %*Sequential Aggregate Signatures and Multisignatures Without Random Oracles %f/eurocrypt/jx8vdbxqljmpobscwyzkvkh1ggeilz6q.pdf %m251b3cb7f39bc38bc8818e8a9a1b696f %ceurocrypt %@Cynthia Dwork,Krishnaram Kenthapadi,Frank McSherry,Ilya Mironov,Moni Naor %*Our Data, Ourselves: Privacy Via Distributed Noise Generation %f/eurocrypt/a9n2omxtevqhrjwkqlddtn7zmsb4lgz6.pdf %m94461b06651b674c38d539782e72d955 %ceurocrypt %@Dennis Hofheinz,Jörn Müller-Quade,Dominique Unruh %*On the (Im-)Possibility of Extending Coin Toss %f/eurocrypt/uwtizqjcuyh6f4ewz9p2xgy7s1eqso5v.pdf %m01eb633079550153010c444d606b8e1f %ceurocrypt %@Berry Schoenmakers,Pim Tuyls %*Efficient Binary Conversion for Paillier Encrypted Values %f/eurocrypt/jxhdtwfyd3hsmslby2ktproirwjpncvb.pdf %m3248106950060310bf17d2fede13009e %ceurocrypt %@Claude Crépeau,George Savvides,Christian Schaffner,Jürg Wullschleger %*Information-Theoretic Conditions for Two-Party Secure Function Evaluation %f/eurocrypt/ktldd9kmbuhialvpnfn1rs0qsc8ogjxg.pdf %mbbf8a0a53f352520db968e85a8767bb3 %ceurocrypt %@Ivan Damgård,Kasper Dupont,Michael Østergaard Pedersen %*Unclonable Group Identification %f/eurocrypt/pnm92wxeyzo6g4iagbdsm7rj3zivyc0c.pdf %m5aac1e77d1f6b917c93962dae215b603 %ceurocrypt %@Dan Boneh,Amit Sahai,Brent Waters %*Fully Collusion Resistant Traitor Tracing with Short Ciphertexts and Private Keys %f/eurocrypt/goshizkeywxbvsqtfc0irvbannx8plcd.pdf %m7cb4572e2a88c120d47c33f066633f6d %ceurocrypt %@Jesús F. Almansa,Ivan Damgård,Jesper Buus Nielsen %*Simplified Threshold RSA with Adaptive and Proactive Security %f/eurocrypt/udofmhio2imnnxy30lkct5y9qs8fzzpx.pdf %m504a763df4fc0ca7fdc1a212c58ac240 %ceurocrypt %@Xiaoyun Wang,Xuejia Lai,Dengguo Feng,Hui Chen,Xiuyuan Yu %*Cryptanalysis of the Hash Functions MD4 and RIPEMD %f/eurocrypt/ttwjm2forxcnsbqayepq8no7ubvf1h5c.pdf %m1d77d3a8bdb6f614f829c0ac794ca00b %ceurocrypt %@Xiaoyun Wang,Hongbo Yu %*How to Break MD5 and Other Hash Functions %f/eurocrypt/v8cyaoxrqy93m7bwm4jzsagupilt2skn.pdf %m30e20568da4fe4443460aab68b1599a1 %ceurocrypt %@Eli Biham,Rafi Chen,Antoine Joux,Patrick Carribault,Christophe Lemuet,William Jalby %*Collisions of SHA-0 and Reduced SHA-1 %f/eurocrypt/xvh09j8le62czoovkirbmfcas1bpud4z.pdf %m2d36f92a2a46ef3d1a67f886c3cf5ccb %ceurocrypt %@Iftach Haitner,Omer Horvitz,Jonathan Katz,Chiu-Yuen Koo,Ruggero Morselli,Ronen Shaltiel %*Reducing Complexity Assumptions for Statistically-Hiding Commitment %f/eurocrypt/mryfqtmkgw96vjcqsbf8nvdzlo5t4uiw.pdf %mb94098b281635ab0351e3e7fe6f83c8f %ceurocrypt %@Yael Tauman Kalai %*Smooth Projective Hashing and Two-Message Oblivious Transfer %f/eurocrypt/ylmv59qg7xudp2ibqlnh3thbuipr0cnz.pdf %m00c349681aa98ff848d9211efdc49101 %ceurocrypt %@Danny Harnik,Joe Kilian,Moni Naor,Omer Reingold,Alon Rosen %*On Robust Combiners for Oblivious Transfer and Other Primitives %f/eurocrypt/btvy2g5ya7pq4m0cht8ad16ndhxguweo.pdf %m6183ea1e167dbfa5eb109ff1fc28d287 %ceurocrypt %@Brent Waters %*Efficient Identity-Based Encryption Without Random Oracles %f/eurocrypt/1b7dgrowhkfpuyepedlsj804zulmyjto.pdf %m00bebb64e29c3f466e39f885c1f21707 %ceurocrypt %@Masayuki Abe,Rosario Gennaro,Kaoru Kurosawa,Victor Shoup %*Tag-KEM/DEM: A New Framework for Hybrid Encryption and A New Analysis of Kurosawa-Desmedt KEM %f/eurocrypt/natkdbbm75v3nrocjivqpcp8gwffsyeh.pdf %me511e53a39a5cfc6d1075fdfbaa54a10 %ceurocrypt %@Xavier Boyen,Yevgeniy Dodis,Jonathan Katz,Rafail Ostrovsky,Adam Smith %*Secure Remote Authentication Using Biometric Data %f/eurocrypt/zsuplomxlvpy2w3ouqbhizi91gfjnnrb.pdf %m01051d3af2b76378832cab2e6a55384c %ceurocrypt %@Daniel J. Bernstein %*Stronger Security Bounds for Wegman-Carter-Shoup Authenticators %f/eurocrypt/pvicq4oiekwnsq0ymhz6rsgxaeofcb9j.pdf %m970808c414a0fabf7a050af769d0bacc %ceurocrypt %@Kaoru Kurosawa,Swee-Huay Heng %*3-Move Undeniable Signature Scheme %f/eurocrypt/bvdlmqagc48znkdswolt26ahx0vwp5ut.pdf %m5701c428e700098c32b3578f3380f438 %ceurocrypt %@Aggelos Kiayias,Moti Yung %*Group Signatures with Efficient Concurrent Join %f/eurocrypt/1loxb0839pkqsyvdrw5c7jzzahnesmpy.pdf %m7f8e13e64fbd50eb3aa324db816c068b %ceurocrypt %@Phong Q. Nguên,Damien Stehlé %*Floating-Point LLL Revisited %f/eurocrypt/s27efl4i6tqbonkcjpdiyjod8rvehkxa.pdf %m79076eb939bbb14cd6c42030d62dc299 %ceurocrypt %@Marten van Dijk,Robert Granger,Dan Page,Karl Rubin,Alice Silverberg,Martijn Stam,David Woodruff %*Practical Cryptography in High Dimensional Tori %f/eurocrypt/cn5yatimu0fzknupawirljdsbmy7se92.pdf %m5c6f33ded51eac97514569ec9e7771ae %ceurocrypt %@Johannes Blömer,Alexander May %*A Tool Kit for Finding Small Roots of Bivariate Polynomials over the Integers %f/eurocrypt/qgnih6xybk3jwkdfs5petmzv1vuo4m8a.pdf %m5e12f82f4e33e18922fda9b049437ea3 %ceurocrypt %@Akinori Kawachi,Takeshi Koshiba,Harumichi Nishimura,Tomoyuki Yamakami %*Computational Indistinguishability Between Quantum States and Its Cryptographic Application %f/eurocrypt/8jqluab7co2pfhxbwienafywqrcovy1g.pdf %m9fda0279a0f77ab587b6d60be24c4c3e %ceurocrypt %@Claude Crépeau,Daniel Gottesman,Adam Smith %*Approximate Quantum Error-Correcting Codes and Secret Sharing Schemes %f/eurocrypt/0mdb7pcrys58etkxwjsxt469pmnuhogi.pdf %maa603e107d955e6e35562fa9299a2204 %ceurocrypt %@Jan Camenisch,Susan Hohenberger,Anna Lysyanskaya %*Compact E-Cash %f/eurocrypt/8j3oyzkugqkhvrbslwmn2dv1ttx4dbom.pdf %m60ea97accfa2ed9f2a55a29c7a534803 %ceurocrypt %@Martin Hirt,Jesper Buus Nielsen,Bartosz Przydatek %*Cryptographic Asynchronous Multi-party Computation with Optimal Resilience %f/eurocrypt/ldzekaoszcx23l6pypnqnydxcu7v4t0q.pdf %m1b72604cc292dee035bea17bee11abb9 %ceurocrypt %@Pierre-Alain Fouque,Louis Granboulan,Jacques Stern %*Differential Cryptanalysis for Multivariate Schemes %f/eurocrypt/jqpbpsa8evolwqx4vrumyanh3fbkc5in.pdf %m0d62b825755eb18dd1000abbb0fd7e6f %ceurocrypt %@Ludovic Perret %*A Fast Cryptanalysis of the Isomorphism of Polynomials with One Secret Problem %f/eurocrypt/s36pnkpradgwoj4clw8tjxtsev1kyazf.pdf %m9399e1d2d405e6bf3d75ae02678c376a %ceurocrypt %@Matthias Ernst,Ellen Jochemsz,Alexander May,Benne de Weger %*Partial Key Exposure Attacks on RSA up to Full Size Exponents %f/eurocrypt/yes9qx05nnbswdtjmil6ozffv4c1qkgx.pdf %m90989dd4194f145da367c1f7dee996c9 %ceurocrypt %@Daniele Micciancio %*The RSA Group is Pseudo-Free %f/eurocrypt/s85vztklbqwrjrpm3zdlpg7w1xi0v6uf.pdf %mfb8b1082d083a9b714f54ba58fa1a797 %ceurocrypt %@Ran Canetti,Shai Halevi,Jonathan Katz,Yehuda Lindell,Phil MacKenzie %*Universally Composable Password-Based Key Exchange %f/eurocrypt/yp9qezfpkv3kcrliqroe0wgj2uzx6t7s.pdf %m10208268bbe1097eb299e16c114dd522 %ceurocrypt %@Melissa Chase,Alexander Healy,Anna Lysyanskaya,Tal Malkin,Leonid Reyzin %*Mercurial Commitments with Applications to Zero-Knowledge Sets %f/eurocrypt/d6nqlityr2sxaecvqhf9mubhk5osjipl.pdf %m779686019c54ac9756031696c84b979c %ceurocrypt %@Dan Boneh,Xavier Boyen,Eu-Jin Goh %*Hierarchical Identity Based Encryption with Constant Size Ciphertext %f/eurocrypt/afqi1sap6l42yornc5zlzvudgqdw9umb.pdf %mb098423130f7aa7c9830c601c80beef6 %ceurocrypt %@Amit Sahai,Brent Waters %*Fuzzy Identity-Based Encryption %f/eurocrypt/wizw7c41vd2vunpfrkobjyqhmyzqxe8g.pdf %m96623658198d308ab5dbae47d30f7695 %ceurocrypt %@John Kelsey,Bruce Schneier %*Second Preimages on n-Bit Hash Functions for Much Less than 2n Work %f/eurocrypt/fozc7sqizl8xbs6d4e0jru3dhnvgfptx.pdf %ma39780dbe117243f288eb20ec1b29698 %ceurocrypt %@Itsik Mantin %*Predicting and Distinguishing Attacks on RC4 Keystream Generator %f/eurocrypt/gcn7nfqtdii90uylumjqmbkx3r6skapl.pdf %ma7a92fa5de9b665278df41da0af55070 %ceurocrypt %@Eli Biham,Orr Dunkelman,Nathan Keller %*Related-Key Boomerang and Rectangle Attacks %f/eurocrypt/neao2hjk83l9iowphwzagubcbtp65vfv.pdf %m7b0b5c81de8d75e14099cf339af5bec9 %ceurocrypt %@John Black,Martin Cochran,Thomas Shrimpton %*On the Impossibility of Highly-Efficient Blockcipher-Based Hash Functions %f/eurocrypt/ekxyuu5hd0mqqpb8etonpvwjzxjsn7lf.pdf %m0066dc7203ec9d70604a05a09bb9814e %ceurocrypt %@Hervé Chabanne,Duong Hieu Phan,David Pointcheval %*Public Traceability in Traitor Tracing Schemes %f/eurocrypt/rhss9xqztzp7nn1vab6ipadky5dxmfct.pdf %m15aec1e6e09efa4538992a11c9f1b86b %ceurocrypt %@Nam-Su Jho,Jung Yeon Hwang,Jung Hee Cheon,Myung-Hwan Kim,Dong Hoon Lee,Eun Sun Yoo %*One-Way Chain Based Broadcast Encryption Schemes %f/eurocrypt/ujl5renpb96c3rtvuj7gkf1sgqpivihw.pdf %m0f91a983531c7002f6cedf92e49882ed %ceurocrypt %@Michael J. Freedman,Kobbi Nissim,Benny Pinkas %*Efficient Private Matching and Set Intersection %f/eurocrypt/ocwf5kaba9ryn2siyvzldfmxokj4ttce.pdf %m61c8e020db14f26aa5b9e61e09f46089 %ceurocrypt %@Benjamin Lynn,Manoj Prabhakaran,Amit Sahai %*Positive Results and Techniques for Obfuscation %f/eurocrypt/umnfyrw4zsofhbg0kpt6u7pqcxy8ighd.pdf %mdb825b5e2b71fcc72cce808b902f9913 %ceurocrypt %@Gagan Aggarwal,Nina Mishra,Benny Pinkas %*Secure Computation of the kth-Ranked Element %f/eurocrypt/nddwrwzubhgze16aybvmp4oak7jen8mc.pdf %m28a68d2213e8e0bded45378f84ad0fc4 %ceurocrypt %@Dan Boneh,Xavier Boyen %*Short Signatures Without Random Oracles %f/eurocrypt/gdynckfjb2zwi5emovs6bj8plihgdwnv.pdf %me0aaec9cf608e4f2344684c66625ceb8 %ceurocrypt %@Anna Lysyanskaya,Silvio Micali,Leonid Reyzin,Hovav Shacham %*Sequential Aggregate Signatures from Trapdoor Permutations %f/eurocrypt/p6jb0asuf7tynjobkehdneu2f5cwgc9v.pdf %m6a5e14195b8d255c101af76aab98f44f %ceurocrypt %@Ivan Damgård,Thomas Pedersen,Louis Salvail %*On the Key-Uncertainty of Quantum Ciphers and the Computational Security of One-Way Quantum Transmission %f/eurocrypt/p17h6iz3i5rg9pn04cecqwuuvdoxaxgs.pdf %m0ce58bb4a74bc39f875afeb0935ae271 %ceurocrypt %@Renato Renner,Stefan Wolf %*The Exact Price for Unconditionally Secure Asymmetric Cryptography %f/eurocrypt/ji0cxzwvxsvpg8u6yeqytoneldrnkk5m.pdf %meecb040e8ab67fa276fcc4322f9afaef %ceurocrypt %@Stefan Dziembowski,Ueli Maurer %*On Generating the Initial Key in the Bounded-Storage Model %f/eurocrypt/gibm4xzscky9arfnmft7cukwsjehpj3o.pdf %m68b42555ff4541384d1e28b3e26f8837 %ceurocrypt %@John Canny,Stephen Sorkin %*Practical Large-Scale Distributed Key Generation %f/eurocrypt/pslju5hy8fcykvcrdrsg1giqtfwl2mkb.pdf %m354487cdb24130821164588dee872409 %ceurocrypt %@Daniele Micciancio,Saurabh Panjwani %*Optimal Communication Complexity of Generic Multicast Key Distribution %f/eurocrypt/djel6hhcemp2tgr13ic9nlsyswvuvzno.pdf %m85f069275dd180b0a162884095cfc6ba %ceurocrypt %@Mihir Bellare,Alexandra Boldyreva,Adriana Palacio %*An Uninstantiable Random-Oracle-Model Scheme for a Hybrid-Encryption Problem %f/eurocrypt/aqa5xnpjgs9fvokmy03lhrgu2u6jwc71.pdf %m6aad995f3aff2d64b3b5cc315cb9e986 %ceurocrypt %@Steven Myers %*Black-Box Composition Does Not Imply Adaptive Security %f/eurocrypt/qne1hxjxyomvktfbcbqk2djs69vasrli.pdf %mb22c6b80442044c0bc38460c2b166025 %ceurocrypt %@Ran Canetti,Shai Halevi,Jonathan Katz %*Chosen-Ciphertext Security from Identity-Based Encryption %f/eurocrypt/krtwdf3hniqsox9szy8tfr5bn4azvq1h.pdf %m1db05624f8a4344d396cdb40e8e3ac84 %ceurocrypt %@Dan Boneh,Xavier Boyen %*Efficient Selective-ID Secure Identity-Based Encryption Without Random Oracles %f/eurocrypt/4bbkpeyaqj7thorf1xamjdc9yg8hmcuw.pdf %mae4bc4285224a1f5f9e4dff394db13ad %ceurocrypt %@Pierrick Gaudry,Éric Schost %*Construction of Secure Random Curves of Genus 2 over Prime Fields %f/eurocrypt/8kzuewn6m5sfvuv2hgfdk9hltjxritbn.pdf %m86de8acd726ddc2c8627672386bdb98d %ceurocrypt %@David Naccache,Nigel P. Smart,Jacques Stern %*Projective Coordinates Leak %f/eurocrypt/no2rtb0hijxiav3fomgetdc7vqpjgpnk.pdf %m900f81cdabd6023f9865cff6a0c9736a %ceurocrypt %@Mihir Bellare,Chanathip Namprempre,Gregory Neven %*Security Proofs for Identity-Based Identification and Signature Schemes %f/eurocrypt/0hmgc4awnzoimfdxvbzeqd5uqhpcy9sv.pdf %m9348068da217196a5c43bbb18265d64c %ceurocrypt %@Liqun Chen,Caroline Kudla,Kenneth G. Paterson %*Concurrent Signatures %f/eurocrypt/xlfiph5d2y4qrbmaotfzq87cpsewe9wu.pdf %mce9182774cea7a8e87500af32748acbb %ceurocrypt %@Tal Malkin,Satoshi Obana,Moti Yung %*The Hierarchy of Key Evolving Signatures and a Characterization of Proxy Signatures %f/eurocrypt/pxqwufnxoqzgyif6djvom4lcbtmbhvik.pdf %m5183604a4037cfd7ce349e09530afaad %ceurocrypt %@Luis von Ahn,Nicholas J. Hopper %*Public-Key Steganography %f/eurocrypt/elfyn0knemj2dq7bbslwiwijzyp3a9mh.pdf %m59dc13f3622b781614a4fe15b10666a5 %ceurocrypt %@Cynthia Dwork,Moni Naor,Omer Reingold %*Immunizing Encryption Schemes from Decryption Errors %f/eurocrypt/62ufjmhokicepgndm5f4hlwl0rnwttkv.pdf %m165561fea0ea2fec8bf38683997d77c0 %ceurocrypt %@Rosario Gennaro,Hugo Krawczyk,Tal Rabin %*Secure Hashed Diffie-Hellman over Non-DDH Groups %f/eurocrypt/lwuh0yb3bcjgamt2eh4eockafvryig8f.pdf %m97f78b9d6a6242842d5e1304ac766e21 %ceurocrypt %@Philip MacKenzie,Ke Yang %*On Simulation-Sound Trapdoor Commitments %f/eurocrypt/cb74ffvp1lqwzibu65ovys8eeu0ktkht.pdf %m6965cd708e9983d46743d6dba7cf287f %ceurocrypt %@Mihir Bellare,Tadayoshi Kohno %*Hash Function Balance and Its Impact on Birthday Attacks %f/eurocrypt/hevtm78r9bnscutlahsajyelkofndrzo.pdf %m2a9e5cc1f551e8baa225c952ef4bd7c7 %ceurocrypt %@Matthias Fitzi,Thomas Holenstein,Jürg Wullschleger %*Multi-party Computation with Hybrid Security %f/eurocrypt/dmvmbfai8c1njvk95thswanduzi32wyk.pdf %m8955e0a257651128ff0b2713dbb442a1 %ceurocrypt %@Yuval Ishai,Eyal Kushilevitz %*On the Hardness of Information-Theoretic Multiparty Computation %f/eurocrypt/ar9yvm8fpzzqj4nxu1dwfehs7k0evgxb.pdf %m57ed18122c511cfb49651a03d93b8529 %ceurocrypt %@Philippe Golle,Ari Juels %*Dining Cryptographers Revisited %f/eurocrypt/ua9smbkb7tiyoawjqdrrjehucz0dlzq4.pdf %m48c7a38d0afef04e77817394d281259b %ceurocrypt %@Willi Meier,Enes Pasalic,Claude Carlet %*Algebraic Attacks and Decomposition of Boolean Functions %f/eurocrypt/woihz49bypszfnr0tukf5pk2jmembvle.pdf %m2b8928ad142813509fe26bfd9cb3e343 %ceurocrypt %@Jean-Sébastien Coron %*Finding Small Roots of Bivariate Integer Polynomial Equations Revisited %f/eurocrypt/awlom9bihnizrejuzpfvq7ye4q8gnk6m.pdf %me86b4e6d3cddc08a9b2fda3137fb4e47 %ceurocrypt %@Dan Boneh,Giovanni Di Crescenzo,Rafail Ostrovsky,Giuseppe Persiano %*Public Key Encryption with Keyword Search %f/eurocrypt/ymzvdtrqkenofxcspdsxnyf7p2bho1wj.pdf %m0b2d1ba6c768c6118ca7c8416f1d9c12 %ceurocrypt %@Yevgeniy Dodis,Leonid Reyzin,Adam Smith %*Fuzzy Extractors: How to Generate Strong Keys from Biometrics and Other Noisy Data %f/eurocrypt/p5ew762bxftyuoxslwgvjdzng0ozbetr.pdf %m1185bbe72d018db401a6e23dc7bfa187 %ceurocrypt %@Michael Szydlo %*Merkle Tree Traversal in Log Space and Time %f/eurocrypt/fngjmyrjk29qzuepe5q8x1bw4mh3fap0.pdf %m2dea0b38c31e4c288f0838d914a4bc7f %ceurocrypt %@Phong Q. Nguyen %*Can We Trust Cryptographic Software? Cryptographic Flaws in GNU Privacy Guard v1.2.3 %f/eurocrypt/84nhlf7bweac2wsv95jugtkrkfsrompo.pdf %m0221bb2db2c71cc8fd9c2e013d314375 %ceurocrypt %@Aggelos Kiayias,Yiannis Tsiounis,Moti Yung %*Traceable Signatures %f/eurocrypt/oyveyfc6mzx4azwuhq0vkel7anlns8rb.pdf %mf11a26716c20a39bdd11533c7d3df3f8 %ceurocrypt %@Stanislaw Jarecki,Vitaly Shmatikov %*Handcuffing Big Brother: an Abuse-Resilient Transaction Escrow Scheme %f/eurocrypt/xjucoykt70mre6szektjygunbipb2oqg.pdf %m7111cf1ce9f82a98f500689889fe21e0 %ceurocrypt %@Yevgeniy Dodis,Aggelos Kiayias,Antonio Nicolosi,Victor Shoup %*Anonymous Identification in Ad Hoc Groups %f/eurocrypt/2nmgkgds3wt7ect5rwxqmriao0ybqfpj.pdf %m6a724573a4910aba4bd64cc1e8528a84 %ceurocrypt %@Antoine Joux %*Cryptanalysis of the EMD Mode of Operation %f/eurocrypt/qqr9garwxan3ubi2l5c4e0fnmp1vdkwc.pdf %mbf0c8076ea7b2da5cd9f491eb3940dbc %ceurocrypt %@Pascal Junod %*On the Optimality of Linear, Differential, and Sequential Distinguishers %f/eurocrypt/zplsfts6gq3koyvhep0vfa2rnxjobb7d.pdf %m85010c3b6ed4513f249b01c0703062aa %ceurocrypt %@Alex Biryukov,Christophe De Cannière,An Braeken,Bart Preneel %*A Toolbox for Cryptanalysis: Linear and Affine Equivalence Algorithms %f/eurocrypt/ixl2fbvkwsosw0tn3ei5jgpmxthvzyko.pdf %m8dd115cce4314d48798316a44a0bfcca %ceurocrypt %@Matthias Fitzi,Martin Hirt,Thomas Holenstein,Jürg Wullschleger %*Two-Threshold Broadcast and Detectable Multi-party Computation %f/eurocrypt/96vvh1snsp2mddnrof3j5ugumt7bzq8x.pdf %m357dad3562e2d677ff579406e57a9f3a %ceurocrypt %@Ran Canetti,Eyal Kushilevitz,Yehuda Lindell %*On the Limitations of Universally Composable Two-Party Computation without Set-up Assumptions %f/eurocrypt/tpnoinhfb1esdrbaggqu9i2xxswkytl6.pdf %m565cf7d53ee770d48d061306fb3ac6b3 %ceurocrypt %@Benny Pinkas %*Fair Secure Two-Party Computation %f/eurocrypt/t7guin5ybyxfaemmsucrlvpkbo6vrdcz.pdf %mc4e73cf7d7c9056224aa508a3e7e2704 %ceurocrypt %@Kris Gaj,Arkadiusz Orłowski %*Facts and Myths of Enigma: Breaking Stereotypes %f/eurocrypt/4xdisnfe9kdomj5ajxzy70qquptfwohu.pdf %m70c0aa180dc0f68ff4f3d55f5c5c7a62 %ceurocrypt %@Yunlei Zhao,Xiaotie Deng,C. H. Lee,Hong Zhu %*Resettable Zero-Knowledge in the Weak Public-Key Model %f/eurocrypt/wbthpoxrfopmuh16e7zb8ntzrq0i4gal.pdf %mafdd00adf4c6b932087746d5911e4d9a %ceurocrypt %@Daniele Micciancio,Erez Petrank %*Simulatable Commitments and Efficient Concurrent Zero-Knowledge %f/eurocrypt/9ldcufnerxaguxmbpmt1s7zvon8ksztc.pdf %mb59e210d28f42ed96f9c0f5d060bf57f %ceurocrypt %@Rafael Pass %*Simulation in Quasi-Polynomial Time, and Its Application to Protocol Composition %f/eurocrypt/rdpzrimjhycookykhaxwvm9w3n2bucsf.pdf %m97fcf6f14163180520b783b7148c79ec %ceurocrypt %@Juan A. Garay,Philip MacKenzie,Ke Yang %*Strengthening Zero-Knowledge Protocols Using Signatures %f/eurocrypt/odikzu56dy7ab0v9w3jxlstqgpnv4yfp.pdf %mf26980314d72a6d9ba0f5a80f4608ff5 %ceurocrypt %@Gustav Hast %*Nearly One-Sided Tests and the Goldreich-Levin Predicate %f/eurocrypt/6lx7y9muezyjviganog184xqbckbqizt.pdf %m681a3a1f4e8289057979e78350f58e4f %ceurocrypt %@Jonathan Katz %*Efficient and Non-malleable Proofs of Plaintext Knowledge and Applications %f/eurocrypt/h5hdsxgow1oq7ntv6waepqbg34vjrfc2.pdf %m88ee669f44c8a754f1fccd90a78656ff %ceurocrypt %@Daniel Augot,Matthieu Finiasz %*A Public Key Encryption Scheme Based on the Polynomial Reconstruction Problem %f/eurocrypt/wa0g7ncskxqdml6xbcignzoukrytdwq9.pdf %mde0581e1da0027afe4ed1d6e44d02100 %ceurocrypt %@Yehuda Lindell %*A Simpler Construction of CCA2-Secure Public-Key Encryption under General Assumptions %f/eurocrypt/ynsfrycbmqzon6ptd4zwjm753uhiavrl.pdf %m31dc2813f7e8c56f9f2a4a88c548f5b3 %ceurocrypt %@Ran Canetti,Shai Halevi,Jonathan Katz %*A Forward-Secure Public-Key Encryption Scheme %f/eurocrypt/wd5jxztyp6leyjf27uhi0z9rucmaxsk3.pdf %m6042b3184d477c143a665825bf4678d9 %ceurocrypt %@Craig Gentry %*Certificate-Based Encryption and the Certificate Revocation Problem %f/eurocrypt/okstlwam91nfbxgutbjymiexz28er5cc.pdf %mc704d83e701bc58e27bf903cacfdc80e %ceurocrypt %@Luis von Ahn,Manuel Blum,Nicholas J. Hopper,John Langford %*CAPTCHA: Using Hard AI Problems for Security %f/eurocrypt/mlpfskqeidozeqjk61w4zyfxoxg09ujd.pdf %mbf578cabc8d431ce82ac74ddb1ead45e %ceurocrypt %@Yevgeniy Dodis,Jee Hea An %*Concealment and Its Applications to Authenticated Encryption %f/eurocrypt/q6ywxa4tkhvsrcmkpxoizfjwgirz3jdq.pdf %m5f356d7aabd1aa3a432ad01ff3045e90 %ceurocrypt %@Patrik Ekdahl,Willi Meier,Thomas Johansson %*Predicting the Shrinking Generator with Fixed Connections %f/eurocrypt/hzwpx9p6tke0jdec1goqrs5riywfyubf.pdf %m2cb723b9bd897a0284564316a2ddaaf8 %ceurocrypt %@Nicolas T. Courtois,Willi Meier %*Algebraic Attacks on Stream Ciphers with Linear Feedback %f/eurocrypt/amzn0oviucyidgzrxkq5vmqeusasntjf.pdf %me11133783d986025c29d052a161ec8f3 %ceurocrypt %@Reynald Lercier,David Lubicz %*Counting Points on Elliptic Curves over Finite Fields of Small Characteristic in Quasi Quadratic Time %f/eurocrypt/w5tluz20dned6qhmyqefpvpgkm38x1wb.pdf %mcd6f3f7ff0ff6473d82dda8236a23b82 %ceurocrypt %@Florian Hess %*The GHS Attack Revisited %f/eurocrypt/poxrw4osqbhbde38gzfjxiydhacyfetw.pdf %ma74567aa989dd307babdbd2fcb90afe8 %ceurocrypt %@Mathieu Ciet,Tanja Lange,Francesco Sica,Jean-Jacques Quisquater %*Improved Algorithms for Efficient Arithmetic on Elliptic Curves Using Fast Endomorphisms %f/eurocrypt/nu03gqcvlutixytz5wminaoyvc27afhl.pdf %m83beda89d2712cc0e0fcbb0e4def49c0 %ceurocrypt %@Eu-Jin Goh,Stanisław Jarecki %*A Signature Scheme as Secure as the Diffie-Hellman Problem %f/eurocrypt/dqrzkvmj6lx3uxoclpi7hfgw5dbqzyt8.pdf %m5a43fc7e0e4658b019a5121bac82d4b6 %ceurocrypt %@Dan Boneh,Craig Gentry,Ben Lynn,Hovav Shacham %*Aggregate and Verifiably Encrypted Signatures from Bilinear Maps %f/eurocrypt/dptf2ychqaja09wiqkv38xrbexmeb7vd.pdf %m5bf65119e4fb3eebf1ea18281cc78f3c %ceurocrypt %@Michael Szydlo %*Hypercubic Lattice Reduction and Analysis of GGH and NTRU Signatures %f/eurocrypt/asg7rlzbxc3uxl1qbdvgwa2o4fij9new.pdf %ma4d6b108cf4ca890e419901d5da2624e %ceurocrypt %@Jacques Stern %*Why Provable Security Matters? %f/eurocrypt/vt51pimwudacgjzwofynshbhadke7gbi.pdf %m1322c3c77dbb08b90d22c2c62db2b1dc %ceurocrypt %@Pierre-Alain Fouque,Guillaume Poupard %*On the Security of RDSA %f/eurocrypt/hygbn6f1w3kdcuv2aruslpwqg7jsif8x.pdf %m5d21a2062e9ac190411406527f767fbf %ceurocrypt %@Eonkyung Lee,Je Hong Park %*Cryptanalysis of the Public-Key Encryption Based on Braid Groups %f/eurocrypt/5odk9xlqptj2szh3vbjikr8og7vnureb.pdf %m274fbc4a9978f2c161bdc1c8b20311b6 %ceurocrypt %@Mihir Bellare,Tadayoshi Kohno %*A Theoretical Treatment of Related-Key Attacks: RKA-PRPs, RKA-PRFs, and Applications %f/eurocrypt/ygtstl0mqhji5oa7spzlcnqzvkdeywrv.pdf %maa13bceed28a6589ca2e6838dbc2357a %ceurocrypt %@Mario Di Raimondo,Rosario Gennaro %*Provably Secure Threshold Password-Authenticated Key Exchange %f/eurocrypt/a1mdqjw3qcmgp2k7rsjn4ltzv5bgwnyi.pdf %m6bfd997751ee1518421dcd1c47e7629f %ceurocrypt %@Rosario Gennaro,Yehuda Lindell %*A Framework for Password-Based Authenticated Key Exchange %f/eurocrypt/zx4wgr0yejdh3skjpnq8bqfnvxpu2dzl.pdf %md05a44f1e4f08f0f02daa07980d61ed8 %ceurocrypt %@Ueli Maurer,Krzysztof Pietrzak %*The Security of Many-Round Luby-Rackoff Pseudo-Random Permutations %f/eurocrypt/tbylny1lrio6kzvhddeq7xtwphi9unrf.pdf %mafa73a8e826d488487845f21feaa5f79 %ceurocrypt %@Renato Renner,Stefan Wolf %*New Bounds in Secret-Key Agreement: The Gap between Formation and Secrecy Extraction %f/eurocrypt/x70sqy9urxgdftmqvlcnzsmwhuaoj63k.pdf %m37fb7385cdb6022ec9bde405c2666ce0 %ceurocrypt %@Jonathan Katz,Rafail Ostrovsky,Adam Smith %*Round Efficiency of Multi-party Computation with a Dishonest Majority %f/eurocrypt/hsrhr1qigoyycpea8qil3ck0fdz9tnj2.pdf %m0972a681f3121e3c033e9a487d3855e9 %ceurocrypt %@Ronald Cramer,Serge Fehr,Yuval Ishai,Eyal Kushilevitz %*Efficient Multi-party Computation over Rings %f/eurocrypt/o2met9uf1a4zzepqtcxcnj7loivng0ld.pdf %m419010dea1ac50f89c8404613a633b4f %ceurocrypt %@Mihir Bellare,Daniele Micciancio,Bogdan Warinschi %*Foundations of Group Signatures: Formal Definitions, Simplified Requirements, and a Construction Based on General Assumptions %f/eurocrypt/9v7gsrchu3udjnqjvofw1hzm2lsanptq.pdf %m060bfbfb4e406e6ca13ce86e609ac4c8 %ceurocrypt %@Rosario Gennaro,Daniele Micciancio %*Cryptanalysis of a Pseudorandom Generator Based on Braid Groups %f/eurocrypt/vzxcihp5lataj7g0d9qrobojl1feugsk.pdf %m81a850a12792692f257de56f39924cfd %ceurocrypt %@Sang Jin Lee,Eonkyung Lee %*Potential Weaknesses of the Commutator Key Agreement Protocol Based on Braid Groups %f/eurocrypt/efzehzsunx0donsjqrc8i4okgp27k6ig.pdf %m8e6c9c099024115d98e282ff380e9e4d %ceurocrypt %@Steven D. Galbraith,Florian Hess,Nigel P. Smart %*Extending the GHS Weil Descent Attack %f/eurocrypt/z8itwn6wdvntq2cugbq73fkerpspsofm.pdf %m3b230ee2f4b55008521fd137ee57163b %ceurocrypt %@Ronald Cramer,Victor Shoup %*Universal Hash Proofs and a Paradigm for Adaptive Chosen Ciphertext Secure Public-Key Encryption %f/eurocrypt/mpkq9pmzaec43y78vwtgf6clfnru1zbd.pdf %m16decec254d78565f0310b83e52bf39b %ceurocrypt %@Yevgeniy Dodis,Jonathan Katz,Shouhuai Xu,Moti Yung %*Key-Insulated Public Key Cryptosystems %f/eurocrypt/kcg3dsizp5hptcm96qu47vnjsxowv8m1.pdf %m91f5abca4eb776e0be5d3323e738c6e2 %ceurocrypt %@Jee Hea An,Yevgeniy Dodis,Tal Rabin %*On the Security of Joint Signature and Encryption %f/eurocrypt/yk5iq3sjzlphv2tkunobozad8ygxpew4.pdf %m73aa10468ac1835c65c3d493908712c4 %ceurocrypt %@Joan Daemen,Vincent Rijmen %*AES and the Wide Trail Design Strategy %f/eurocrypt/cvlgbq9dpjoui768pyecfg5djsf10nrh.pdf %m56e4c9d7f7777d4d4bb3d89b10e8378b %ceurocrypt %@Ueli Maurer %*Indistinguishability of Random Systems %f/eurocrypt/knpnyuxersadfc7z8ej0pukcytijwfq5.pdf %m8efd50907e3209ebe89dea42add909b0 %ceurocrypt %@Alexander Russell,Hong Wang %*How to Fool an Unbounded Adversary with a Short Key %f/eurocrypt/5j96roef0atzhubw13ywclai7vpskgrd.pdf %mc09130259858fe68f9458a33520113fe %ceurocrypt %@David P. Woodruff,Marten van Dijk %*Cryptography in an Unbounded Computational Model %f/eurocrypt/jmiqhd5vexqkbzmfyt1sg0el72uzpibj.pdf %m5af0370f2771e9ca3cf287fc1747dd31 %ceurocrypt %@Junko Nakajima,Mitsuru Matsui %*Performance Analysis and Parallel Implementation of Dedicated Hash Functions %f/eurocrypt/wfkaudebfeqvhm1pxwxgts2ani8rgj5k.pdf %m3b37fc53a4b5e28eaa381d2bfc6173bf %ceurocrypt %@John A. Clark,Jeremy L. Jacob %*Fault Injection and a Timing Channel on an Analysis Technique %f/eurocrypt/uveflrj2jbc6wvgoxaihhs7dtxqiotnp.pdf %me1f0422d3b4aaf42ec143c5774ce4d5a %ceurocrypt %@Young-Ho Park,Sangtae Jeong,Jongin Lim %*Speeding Up Point Multiplication on Hyperelliptic Curves with Efficiently-Computable Endomorphisms %f/eurocrypt/4aamskp3zme0fvtrbjogsvktyub2j5gn.pdf %m4ee53561fdacfbfca160bd742c070daa %ceurocrypt %@Philippe Chose,Antoine Joux,Michel Mitton %*Fast Correlation Attacks: An Algorithmic Point of View %f/eurocrypt/k1rqxmbh4licbjv5asd0d9nwftxj2cwg.pdf %md0dbe1639af95bf3a984c99959afcbe8 %ceurocrypt %@Matthias Krause %*BDD-Based Cryptanalysis of Keystream Generators %f/eurocrypt/6hcdtlmeqp82mhwrgvcdnfyosupjbz70.pdf %m17fbbf8ac7086cb021087e3d1a24d695 %ceurocrypt %@Jovan Dj. Golić,Vittorio Bagini,Guglielmo Morgari %*Linear Cryptanalysis of Bluetooth Stream Cipher %f/eurocrypt/9vurgdysklib1kemph534tpmzfcx80cl.pdf %m0d4c34df52bd9d7ba9281b9463bfb81e %ceurocrypt %@Ivan Damgård,Maciej Koprowski %*Generic Lower Bounds for Root Extraction and Signature Schemes in General Groups %f/eurocrypt/6sxmfwt3ipqvzcfghqyj2dubbl71hzoe.pdf %m9269d114ddafe9e1df88e92fb13d7493 %ceurocrypt %@Jean-Sébastien Coron %*Optimal Security Proofs for PSS and Other Signature Schemes %f/eurocrypt/0p6kiwlus93eobjmcaqzfdl5qxhzi7xv.pdf %mf7644f3b23e05c5d1254f11be1efe214 %ceurocrypt %@Henri Gilbert,Marine Minier %*Cryptanalysis of SFLASH %f/eurocrypt/6pubky0zxja5xtcejspymgiwgsm7kfvi.pdf %mbefa25c77185e6164e6dda731a0ff403 %ceurocrypt %@Craig Gentry,Mike Szydlo %*Cryptanalysis of the Revised NTRU Signature Scheme %f/eurocrypt/5qotqvbhzcy8ptu2glve6iu1xmgkf0km.pdf %m6d7341e02ef7a92c3a2bc86e6fb99dc3 %ceurocrypt %@Emmanuel Bresson,Olivier Chevassut,David Pointcheval %*Dynamic Group Diffie-Hellman Key Exchange under Standard Assumptions %f/eurocrypt/7age4jfg8bqkds9nihltxo6wpzhkxrvo.pdf %mdd4200fd1774e59ac16735de3478b862 %ceurocrypt %@Ran Canetti,Hugo Krawczyk %*Universally Composable Notions of Key Exchange and Secure Channels %f/eurocrypt/nzwjhxqoejr3rb95tksbvpuied20vspn.pdf %m853a0d8ec55ead56a262590c52b8954a %ceurocrypt %@Donald Beaver %*On Deniability in Quantum Key Exchange %f/eurocrypt/t4ak7oixm9dwbnu80u6rlcomztfvnepj.pdf %mee745be608f7ac34c7f58d05f7ae3c96 %ceurocrypt %@Anand Desai,Alejandro Hevia,Yiqun Lisa Yin %*A Practice-Oriented Treatment of Pseudorandom Number Generators %f/eurocrypt/dzajs2dsx6effwlitnp4l190amjykh8u.pdf %mb07675efd039427edb011a03d7856545 %ceurocrypt %@John Black,Phillip Rogaway %*A Block-Cipher Mode of Operation for Parallelizable Message Authentication %f/eurocrypt/wjl0gijr9ackhg5usplqmbq6tffcuder.pdf %ma25cd4317c7527ea9d93fe4bffac3b90 %ceurocrypt %@Stephen Kent %*Rethinking PKI: What’s Trust Got to Do with It? %f/eurocrypt/dgclrwi1lvqzmb9xcsepn2zgwj0ksbhp.pdf %m0a363a0d07d103d2b1aaf1fe206be10d %ceurocrypt %@Tal Malkin,Daniele Micciancio,Sara Miner %*Efficient Generic Forward-Secure Signatures with an Unbounded Number of Time Periods %f/eurocrypt/iawempuekqmuo6ta0s5xck13dcsrgyxt.pdf %md3d32832bba8aa95915acb93cd8401af %ceurocrypt %@Michel Abdalla,Jee Hea An,Mihir Bellare,Chanathip Namprempre %*From Identification to Signatures via the Fiat-Shamir Transform: Minimizing Assumptions for Security and Forward-Security %f/eurocrypt/6hi7rbwrdpfxmu9nmczfslhotbcqga50.pdf %me9a4049b11f94e64957364f0ed5e6e6f %ceurocrypt %@Junji Shikata,Goichiro Hanaoka,Yuliang Zheng,Hideki Imai %*Security Notions for Unconditionally Secure Signature Schemes %f/eurocrypt/5hpyockasaxnwizg2rqfzqoj8mv4in1m.pdf %m27008e9b80fe782d71227f4e7890fd8e %ceurocrypt %@Aggelos Kiayias,Moti Yung %*Traitor Tracing with Constant Transmission Rate %f/eurocrypt/8qogprw9asjq7zm4isvovhfrtyfid3zb.pdf %me9180460d8397a585694756e047e7fbf %ceurocrypt %@Jeremy Horwitz,Ben Lynn %*Toward Hierarchical Identity-Based Encryption %f/eurocrypt/yb0ad46gwflqiqmmelroieptugzusrvk.pdf %m4d9a5bfa35972795718ca458f46aa855 %ceurocrypt %@Matthias Fitzi,Nicolas Gisin,Ueli Maurer,Oliver von Rotz %*Unconditional Byzantine Agreement and Multi-party Computation Secure against Dishonest Minorities from Scratch %f/eurocrypt/ginyzqcwla7mumwxjsk5pqth2o8kcgrr.pdf %m782ca0bb08ba502846da4eef849d65a6 %ceurocrypt %@Yvo Desmedt,Yongge Wang %*Perfectly Secure Message Transmission Revisited %f/eurocrypt/8zdz0mngubpal7e2igjvqdrsso69mkux.pdf %mcc754a46aae77925ec1f8114eaeabdfd %ceurocrypt %@Anne Canteaut,Marion Videau %*Degree of Composition of Highly Nonlinear Functions and Applications to Higher Order Differential Cryptanalysis %f/eurocrypt/o8ijfatrveycd6kbulzetxykzxsqfnr1.pdf %m665d8286e7ad6271cfe7fb10613005e9 %ceurocrypt %@Serge Vaudenay %*Security Flaws Induced by CBC Padding — Applications to SSL, IPSEC, WTLS... %f/eurocrypt/ojav69zjdtimskhclquryuzx45rf3scy.pdf %mf072e23677f160e63881e19a39d2512f %ceurocrypt %@Frederik Vercauteren,Bart Preneel,Joos Vandewalle %*A Memory Efficient Version of Satoh’s Algorithm %f/eurocrypt/bru091eqplu4pnmkmyfzat2ogbcyxfj3.pdf %m0db2ee4f00cca7e15fca4ead660721e4 %ceurocrypt %@Mireille Fouquet,Pierrick Gaudry,Robert Harley %*Finding Secure Curves with the Satoh-FGH Algorithm and an Early-Abort Strategy %f/eurocrypt/op7fxq9umiw3jdhnvzv5gqar14oiestl.pdf %m348343c2619c01ac92c3942e91104a27 %ceurocrypt %@Nigel P. Smart %*How Secure Are Elliptic Curves over Composite Extension Fields? %f/eurocrypt/ymbnw4ct6yqxwzvvkds3f1sef9xoret5.pdf %m5c7bf5edba568cd920f6b8d9988c3e2b %ceurocrypt %@Giovanni Di Crescenzo,Jonathan Katz,Rafail Ostrovsky,Adam Smith %*Efficient and Non-interactive Non-malleable Commitment %f/eurocrypt/cbgh2umugezrcdxta0o8p5kk9yjisnlp.pdf %m92dc39a51b7d9a67908ea7048bc27284 %ceurocrypt %@Claude Crépeau,Frédéric Légaré,Louis Salvail %*How to Convert the Flavor of a Quantum Bit Commitment %f/eurocrypt/s4cqa8lnounjbbku0tsdexwa9oegrmzv.pdf %mab9afa3abfb999327ea43c9b8e432c77 %ceurocrypt %@Jonathan Katz,Steven Myers,Rafail Ostrovsky %*Cryptographic Counters and Applications to Electronic Voting %f/eurocrypt/n2vjxffyklz06ous1uwactviy7pgesn5.pdf %mbec22a085cae4e0afedb7093f727c9a8 %ceurocrypt %@Jan Camenisch,Anna Lysyanskaya %*An Efficient System for Non-transferable Anonymous Credentials with Optional Anonymity Revocation %f/eurocrypt/twa4vqpv9kmnnfsdk7mteqrhlc8d3xzr.pdf %m40ca7cdea7dc20d1be4b0ff546edad82 %ceurocrypt %@Bill Aiello,Yuval Ishai,Omer Reingold %*Priced Oblivious Transfer: How to Sell Digital Goods %f/eurocrypt/yxmidjp4racqf5o2uvx3ngttw8dri69z.pdf %me3831f07678d9dc930d0a7538882b09e %ceurocrypt %@Masayuki Abe %*A Secure Three-Move Blind Signature Scheme for Polynomially Many Signatures %f/eurocrypt/pg7tqazxro4md8hzjl9cirvk2mdeeqh5.pdf %m616b8d77acf7a21ea5d5999d5e033f0b %ceurocrypt %@Ivan Damgård,Maciej Koprowski %*Practical Threshold RSA Signatures without a Trusted Dealer %f/eurocrypt/3ppojnxdakt0vcjfgoir4xh8e9yy6zau.pdf %mf469a2490397f2952418c3fbf370ffb6 %ceurocrypt %@Ilya Mironov %*Hash Functions: From Merkle-Damgård to Shoup %f/eurocrypt/yzp9bmild7ovhe8kj4wndyetizxjctxf.pdf %mc072fb1496b39276b2c43b37b18feeae %ceurocrypt %@Craig Gentry %*Key Recovery and Message Attacks on NTRU-Composite %f/eurocrypt/bzbzyre42ijs8hjrumnaa7uwwtqepk9g.pdf %m82339e0dbbfea64e17f09414109e758a %ceurocrypt %@Eric R. Verheul %*Evidence that XTR Is More Secure than Supersingular Elliptic Curve Cryptosystems %f/eurocrypt/wp6sfyi9lfpdkqmc2r4qhg3zeattgvhn.pdf %m54c92e11c7b845d86b4a4b8129abfe4c %ceurocrypt %@Jeffrey Hoffstein,Jill Pipher,Joseph H. Silverman %*NSS: An NTRU Lattice-Based Signature Scheme %f/eurocrypt/mgnjfusghybokvcqddboktxlnsmtra51.pdf %m2d20fb3a64fbc9e1d469c70c280927cc %ceurocrypt %@Dario Catalano,Rosario Gennaro,Nick Howgrave-Graham %*The Bit Security of Paillier’s Encryption Scheme and Its Applications %f/eurocrypt/ounoxrjwwzls0ze4dvar7vhaif3qin2p.pdf %mc7d07055b48eeca65e25db9d9e031030 %ceurocrypt %@Ahmad-Reza Sadeghi,Michael Steiner %*Assumptions Related to Discrete Logarithms: Why Subtleties Make a Real Difference %f/eurocrypt/bjt9vxultghwrfkos8q1ln4bdusvedem.pdf %mb745b0cef57a23b4a3c614f67b4c2f0e %ceurocrypt %@Ran Canetti,Ivan Damgaard,Stefan Dziembowski,Yuval Ishai,Tal Malkin %*On Adaptive vs. Non-adaptive Security of Multiparty Protocols %f/eurocrypt/ia15xoqikm7rd8jfrwh6ce39v4bvyanz.pdf %m2c690eab71f4bb007190d1d6928ef25b %ceurocrypt %@Ronald Cramer,Ivan Damgård,Jesper B. Nielsen %*Multiparty Computation from Threshold Homomorphic Encryption %f/eurocrypt/7g0xkwcsvxzpsmjhef68kpzf2mnrgiyv.pdf %mf97e554b50aff1884bf45683e209c86e %ceurocrypt %@Yevgeniy Dodis,Amit Sahai,Adam Smith %*On Perfect and Adaptive Security in Exposure-Resilient Cryptography %f/eurocrypt/jtpv5qkmugeorgwu0hlixfv3ad7nbdlz.pdf %m166da3b7a72e3816c3e85322c08d5f55 %ceurocrypt %@Ulrich Kühn %*Cryptanalysis of Reduced-Round MISTY %f/eurocrypt/p3lnl9m2uiauoe8drwzm1f0nahp4yhv5.pdf %m7a0687c5e0e61c6d057ef1bc6999b7a9 %ceurocrypt %@Eli Biham,Orr Dunkelman,Nathan Keller %*The Rectangle Attack — Rectangling the Serpent %f/eurocrypt/3qsud6yynhdkxcmcjrvtuqor1z7lkwze.pdf %m2ee55111394c23684a5511e932c4a009 %ceurocrypt %@Steven Myers %*Efficient Amplification of the Security of Weak Pseudo-random Function Generators %f/eurocrypt/56qgvo7xsz4boqvftkhcuse1nyzjcg9d.pdf %m70ae3167b095f09297091a32eb50d768 %ceurocrypt %@Silvio Micali,Leonid Reyzin %*Min-round Resettable Zero-Knowledge in the Public-Key Model %f/eurocrypt/iykpg42m7sxe9wuclqtvrnwe5xgtnfdm.pdf %m81bbe17d7e309e88a525b098f5559722 %ceurocrypt %@Alex Biryukov,Adi Shamir %*Structural Cryptanalysis of SASAS %f/eurocrypt/ujy6opnwxzlbh8bfwvm12jtddi45mxok.pdf %meea93065d0a55e9e1dbb1c8831c3a7cc %ceurocrypt %@Amr M. Youssef,Guang Gong %*Hyper-bent Functions %f/eurocrypt/sfon62jhrfcyakzhxtjqgu0w5wmv8voc.pdf %m67689da40fe42250f5b29ddb4805abe8 %ceurocrypt %@Liam Keliher,Henk Meijer,Stafford Tavares %*New Method for Upper Bounding the Maximum Average Linear Hull Probability for SPNs %f/eurocrypt/ox1ayjnqfbolqvsdwifm93v7egykxzcd.pdf %md8d2ddb87e4c396cc8f3702bc55d0c50 %ceurocrypt %@Dan Boneh,Glenn Durfee,Matt Franklin %*Lower Bounds for Multicast Message Authentication %f/eurocrypt/yipx1gjxtc3d6s9rhfbepuwya5g47fvl.pdf %me35d4228e3cb8803c579eed2489241c2 %ceurocrypt %@Ran Canetti,Hugo Krawczyk %*Analysis of Key-Exchange Protocols and Their Use for Building Secure Channels %f/eurocrypt/kdzpqv9nfvohs1futnzw8hy374oiqmbd.pdf %m1b579e31b2ac0ed03642212bb6d8445d %ceurocrypt %@Jonathan Katz,Rafail Ostrovsky,Moti Yung %*Efficient Password-Authenticated Key Exchange Using Human-Memorable Passwords %f/eurocrypt/ls6fxww0ggeoj4ncfzoeqj18vlpnuzym.pdf %m4f43e22fdb73e05bc5e73555b053d995 %ceurocrypt %@Mihir Bellare,Marc Fischlin,Shafi Goldwasser,Silvio Micali %*Identification Protocols Secure against Reset Attacks %f/eurocrypt/ps0is7waly6crgbzz429uxcmmwqt3odg.pdf %m16dc0c05604457d5988aa17d7f8a0982 %ceurocrypt %@Jee Hea An,Mihir Bellare %*Does Encryption with Redundancy Provide Authenticity? %f/eurocrypt/wr5atdiwppvk92jqgb3ksfsxjgllzy7u.pdf %md4bcbdcff53172acbf3ef62ac64ce9c9 %ceurocrypt %@Charanjit S. Jutla %*Encryption Modes with Almost Free Message Integrity %f/eurocrypt/1zu2amkxmt0s5lvcdjxiubswr8ntejgv.pdf %m5b61325be0f95d43ff6908a0653bb29d %ceurocrypt %@Stefania Cavallar,Bruce Dodson,Arjen K. Lenstra,Walter Lioen,Peter L. Montgomery,Brian Murphy,Herman te Riele,Karen Aardal,Jeff Gilchrist,Gérard Guillerm,Paul Leyland,Jöel Marchand,François Morain,Alec Muffett,Chris and Craig Putnam,Paul Zimmermann %*Factorization of a 512-Bit RSA Modulus %f/eurocrypt/yodfgb37apjvdctywcfogat6jlkhw51q.pdf %m57ca94dd69f9444dac507f0d1b078af7 %ceurocrypt %@Pierrick Gaudry %*An Algorithm for Solving the Discrete Log Problem on Hyperelliptic Curves %f/eurocrypt/vbx7gafcd2wihxukteaqo46qrj1rj8st.pdf %m27bd39c474c42a94dd65f97bf86144f5 %ceurocrypt %@Arjen K. Lenstra,Adi Shamir %*Analysis and Optimization of the TWINKLE Factoring Device %f/eurocrypt/y3xud5au7z4owqnpgsncbo0hmt68itl9.pdf %m61ec11b85b59e2ac2de89aa4610c6dd7 %ceurocrypt %@Daniel Bleichenbacher,Phong Q. Nguyen %*Noisy Polynomial Interpolation and Noisy Chinese Remaindering %f/eurocrypt/874hts60lmcriv1oef5iph2jxmbwqzd3.pdf %m93a4b1d78179d1ab40e9f1bdc2c4d85c %ceurocrypt %@François Grieu %*A Chosen Messages Attack on the ISO/IEC 9796-1 Signature Scheme %f/eurocrypt/fadthg1uknigxw6cj2lksjvqp5imerrq.pdf %m9ff9a836b27ff63d3a9744ed40ebd730 %ceurocrypt %@Marc Girault,Jean-François Misarsky %*Cryptanalysis of Countermeasures Proposed for Repairing ISO 9796-1 %f/eurocrypt/8jbvsq7r39hk6mxrxunal1ggavczinyj.pdf %m3afa72d3a4b1b1c81f744487514ae783 %ceurocrypt %@Jean-Sébastien Coron,David Naccache %*Security Analysis of the Gennaro-Halevi-Rabin Signature Scheme %f/eurocrypt/hzjntadfwgcqxbjablwryms9mkvhgt3q.pdf %m9ed9c2c2ca55f5126bbbbacb80c0c2bc %ceurocrypt %@Michael Walker %*On the Security of 3GPP Networks %f/eurocrypt/a0l4ckbosmtr2flfmzhiv7kjntr65g3w.pdf %m80cd5e00d7c6497c63961516631bf613 %ceurocrypt %@Eyal Kushilevitz,Rafail Ostrovsky %*One-Way Trapdoor Permutations Are Sufficient for Non-trivial Single-Server Private Information Retrieval %f/eurocrypt/a8jsdnj1pw7ydbi4fqrnry2hl3sukiez.pdf %m19e8dfeab17cd01491ccf5bebabced0f %ceurocrypt %@Giovanni Di Crescenzo,Tal Malkin,Rafail Ostrovsky %*Single Database Private Information Retrieval Implies Oblivious Transfer %f/eurocrypt/jyfb51k04dnzoe9s6xtqgvwdsztmpauh.pdf %m50d7702c501468ebf97460bd90ce0959 %ceurocrypt %@Mihir Bellare,David Pointcheval,Phillip Rogaway %*Authenticated Key Exchange Secure against Dictionary Attacks %f/eurocrypt/mn9jcoa6r4zpkuy5f8wgthxm7cukvzn1.pdf %m792186e79446dda20c4ceaefa3b0934c %ceurocrypt %@Victor Boyko,Philip MacKenzie,Sarvar Patel %*Provably Secure Password-Authenticated Key Exchange Using Diffie-Hellman %f/eurocrypt/stjdsyt5olngi4f2mhhmw3dequkg1kyc.pdf %m3601651aaa89e817eb054ac196975323 %ceurocrypt %@Guillaume Poupard,Jacques Stern %*Fair Encryption of RSA Keys %f/eurocrypt/ttumekcaov5x1swpmf4apgero08yiqub.pdf %m8772840f2b4aa55c58260e74c696c296 %ceurocrypt %@Dario Catalano,Rosario Gennaro,Shai Halevi %*Computing Inverses over a Shared Secret Modulus %f/eurocrypt/j5chryrb6lvgxee9dndzfkkxhcv0uspt.pdf %m5e5f77e94d815572276690b974e441a0 %ceurocrypt %@Victor Shoup %*Practical Threshold Signatures %f/eurocrypt/je68rkcau0or7fi41usyqqdbzpnslvmy.pdf %m3bf19d22984d30a4fd60fa798938f547 %ceurocrypt %@Stanisław Jarecki,Anna Lysyanskaya %*Adaptively Secure Threshold Cryptography: Introducing Concurrency, Removing Erasures %f/eurocrypt/5hzw7b3tdagfa6onmntq02euscqpkcls.pdf %mf0a423ab9224d6e5424b5f684cecde63 %ceurocrypt %@Jan Camenisch,Markus Michels %*Confirmer Signature Schemes Secure against Adaptive Adversaries %f/eurocrypt/t1nysdr5w2cu3bkegqbs7tvefyfomic9.pdf %m0d2b8742d7c0daa79937424824148434 %ceurocrypt %@Mihir Bellare,Alexandra Boldyreva,Silvio Micali %*Public-Key Encryption in a Multi-user Setting: Security Proofs and Improvements %f/eurocrypt/lrhgsovmxqfet3h702tua4puywxa9zvw.pdf %m772ded185f04ee6b20ec88a1878f17e0 %ceurocrypt %@Victor Shoup %*Using Hash Functions as a Hedge against Chosen Ciphertext Attack %f/eurocrypt/rlcpquvejog6tk1dceuirpi39xbfnho0.pdf %mee0a47dd51de3c78e7e700ef12678521 %ceurocrypt %@Gilles Brassard,Norbert Lütkenhaus,Tal Mor,Barry C. Sanders %*Security Aspects of Practical Quantum Cryptography %f/eurocrypt/zxkspcbtqgnj024uhyaf6fmbadterhow.pdf %m716836bb0fc4ba5a2f4798c5a01a4103 %ceurocrypt %@Paul Dumais,Dominic Mayers,Louis Salvail %*Perfectly Concealing Quantum Bit Commitment from any Quantum One-Way Permutation %f/eurocrypt/q1lpteki9bc6nzwghsmydpte37s8r0lx.pdf %m235608656f65a180421388eff2221feb %ceurocrypt %@Ronald Cramer,Ivan Damgård,Ueli Maurer %*General Secure Multi-party Computation from any Linear Secret-Sharing Scheme %f/eurocrypt/u1gjijis9lzbpnarmthbr5oc3dfkp26l.pdf %m41fd522201327793390d806beec2cf28 %ceurocrypt %@Donald Beaver %*Minimal-Latency Secure Function Evaluation %f/eurocrypt/z6qsqjesdmjvvd1t80yex3bhibi2whfw.pdf %mce196db40d429e0763c6cfa56377d24a %ceurocrypt %@Ueli Maurer,Stefan Wolf %*Information-Theoretic Key Agreement: From Weak to Strong Secrecy for Free %f/eurocrypt/eo7yt1jnwevl5lxxp8uwbatkgc49aiuy.pdf %m4e1f6c14924f46ed3e6ba5dc69d4cc58 %ceurocrypt %@Jean-Sébastien Coron,Marc Joye,David Naccache,Pascal Paillier %*New Attacks on PKCS#1 v1.5 Encryption %f/eurocrypt/wukvblqfsehagt0cspi41ynmew6rdt29.pdf %m1b8f7235119f2390bd13b8c92fd6a618 %ceurocrypt %@Éliane Jaulmes,Antoine Joux %*A NICE Cryptanalysis %f/eurocrypt/ioncesfzjij7pklkxudwmv45tgbpyavm.pdf %me32cfb7c845afdab1a6d8ade9a9ed37a %ceurocrypt %@Nicolas Courtois,Alexander Klimov,Jacques Patarin,Adi Shamir %*Efficient Algorithms for Solving Overdefined Systems of Multivariate Polynomial Equations %f/eurocrypt/3g9nhnrom6pcq5fdkgjetvs7ikb10par.pdf %m948fa6fef83c3f6b50b992052bca1c33 %ceurocrypt %@Eli Biham %*Cryptanalysis of Patarin’s 2-Round Public Key System with S Boxes (2R) %f/eurocrypt/rfp4dzxbrehtcetliwnvk2b0qdug7jfw.pdf %mb1ca14d99c88aa82905f8ac99ee11a37 %ceurocrypt %@Anthony E Sale %*Colossus and the German Lorenz Cipher — Code Breaking in WW II %f/eurocrypt/stbnbjqypkf0ixn1yasgo2h6cwov7tuu.pdf %m6bbc6ab7b769c51b671338b9a81f3c3c %ceurocrypt %@Ivan Damgård %*Efficient Concurrent Zero-Knowledge in the Auxiliary String Model %f/eurocrypt/jme32il69ofrjzdycuxfpcgotyihw07m.pdf %m7b154150b8b4b810e107f7b7b9dfdee7 %ceurocrypt %@Fabrice Boudot %*Efficient Proofs that a Committed Number Lies in an Interval %f/eurocrypt/7vt0xgrygbfjvejtya23dcweoklas9kh.pdf %m3d07b22212a26480c79145ea58e76047 %ceurocrypt %@Victor Shoup %*A Composition Theorem for Universal One-Way Hash Functions %f/eurocrypt/zqjwg3ks4gaimcy9pn1hfxabncuexldj.pdf %meb865ed46c31838682d717d2ae5c2089 %ceurocrypt %@Ran Canetti,Yevgeniy Dodis,Shai Halevi,Eyal Kushilevitz,Amit Sahai %*Exposure-Resilient Functions and All-or-Nothing Transforms %f/eurocrypt/swhrfllbar4kek6imedb2pvt8igspjn0.pdf %m2c8894e60035a6148ddba1dbb434fe51 %ceurocrypt %@Stefan Lucks %*The Sum of PRPs Is a Secure PRF %f/eurocrypt/tw7cbvghcoerjzg9qzbax05184yw6tnn.pdf %m946075a888bd9204eb42cbf4455451cd %ceurocrypt %@Palash Sarkar,Subhamoy Maitra %*Construction of Nonlinear Boolean Functions with Important Cryptographic Properties %f/eurocrypt/aojb79elwjlvad1xprzshi2bu6nrockm.pdf %mf4d4e1b73d6b0208679585b5e3b22835 %ceurocrypt %@Anne Canteaut,Claude Carlet,Pascale Charpin,Caroline Fontaine %*Propagation Characteristics and Correlation-Immunity of Highly Nonlinear Boolean Functions %f/eurocrypt/aqpyzer6bg7gojwflbfzrdto54sj1yix.pdf %m3450a167a0d420949a0fe5b3844b7c3b %ceurocrypt %@Shinichi Kawamura,Masanobu Koike,Fumihiko Sano,Atsushi Shimbo %*Cox-Rower Architecture for Fast Parallel Montgomery Multiplication %f/eurocrypt/g6ltp20wezo8nvjqlbrtxfsjudhi13ze.pdf %m28ad1b5232b7a297d8fd1853d0060919 %ceurocrypt %@Martin Hirt,Kazue Sako %*Efficient Receipt-Free Voting Based on Homomorphic Encryption %f/eurocrypt/2xcgd9i7lbnvcv6ftqrpg4atjuwpswua.pdf %m9110746672951bf56362c7a6759284cc %ceurocrypt %@Yvo Desmedt,Kaoru Kurosawa %*How to Break a Practical MIX and Design a New One %f/eurocrypt/iendwqgu64fgjcfe8ztnbbyzxkwjxytr.pdf %m3b4d1add0641b0f938411f17f9d4d31b %ceurocrypt %@Anne Canteaut,Michaël Trabbia %*Improved Fast Correlation Attacks Using Parity-Check Equations of Weight 4 and 5 %f/eurocrypt/19paronwqu3tm7pdofaudbey8gtv0rix.pdf %m8b27974cde7b2411a0f41086aa036621 %ceurocrypt %@Alex Biryukov,David Wagner %*Advanced Slide Attacks %f/eurocrypt/6opd8esbqn10o45dcapnwxfceyvkr9u7.pdf %m14efae1480361c78c20d93926f4a155d %ceurocrypt %@Dan Boneh,Glenn Durfee %*Cryptanalysis of RSA with Private Key d Less than N0.292 %f/eurocrypt/zdinvlmye6a7vq0hf1sqbtygzkn3ux9w.pdf %m34eac6e3fc0c5c34a760763e64085136 %ceurocrypt %@Eli Biham,Alex Biryukov,Adi Shamir %*Cryptanalysis of Skipjack Reduced to 31 Rounds Using Impossible Differentials %f/eurocrypt/ruzlubkaobsfqjddwx309vat4gjmyq5i.pdf %md1df7cd19e9fdf99e48bc6ad37733c29 %ceurocrypt %@Wim Nevelsteen,Bart Preneel %*Software Performance of Universal Hash Functions %f/eurocrypt/t0lbmg8ukjgsxhk54qqcepwm3wvzidnr.pdf %m2917f086479d174e4caafa5d0e0d20f0 %ceurocrypt %@Yevgeniy Dodis,Silvio Micali %*Lower Bounds for Oblivious Transfer Reductions %f/eurocrypt/vwcnkutbjlxdolmhiorb19q05v4f6yry.pdf %m08d8d559dde3bc2c82496a42ac7dd640 %ceurocrypt %@Ivan Damgård,Joe Kilian,Louis Salvail %*On the (Im)possibility of Basing Oblivious Transfer and Bit Commitment on Weakened Security Assumptions %f/eurocrypt/exothlpkug2ltfzzw6icw0dqb8dosq1n.pdf %m6a09265d7209d07c54557cb716a8cfd6 %ceurocrypt %@Giovanni Di Crescenzo,Rafail Ostrovsky,Sivaramakrishnan Rajagopalan %*Conditional Oblivious Transfer and Timed-Release Encryption %f/eurocrypt/skpul7mvoxxteqd4f2fzwjoa6til1mib.pdf %m2d3205af7b0b229557ee53f7050d8a56 %ceurocrypt %@Ran Canetti,Shafi Goldwasser %*An Efficient threshold Public Key Cryptosystem Secure Against Adaptive Chosen Ciphertext Attack (Extended Abstract) %f/eurocrypt/uflgikrd5ypnzx2w9ewk0l4jysd1mtcf.pdf %ma6ec1f71a65c92c8e4b8c941554df45e %ceurocrypt %@Jan Camenisch,Markus Michels %*Proving in Zero-Knowledge that a Number is the Product of Two Safe Primes %f/eurocrypt/iolqyt8fdkmvehn6u2ixveqjkdp71xma.pdf %m50e41917150b6cfbadc150cf23fa0255 %ceurocrypt %@Rosario Gennaro,Shai Halevi,Tal Rabin %*Secure Hash-and-Sign Signatures Without the Random Oracle %f/eurocrypt/b5kuczqw2q4svo3ojmxnykaid81rameh.pdf %m9759627452fbd0afd07d5eeb15853467 %ceurocrypt %@Funda Ergun,Joe Kilian,Ravi Kumar %*A Note on the Limits of Collusion-Resistant Watermarks %f/eurocrypt/d4rq0g3uetpz9cixlfgtjofj16cdyon5.pdf %m3e94eec962b8c470506b42389fd081ab %ceurocrypt %@Birgit Pfitzmann,Ahmad-Reza Sadeghi %*Coin-Based Anonymous Fingerprinting %f/eurocrypt/qb3mjs4ppnaiardxctmz8isbjh9u6ryo.pdf %m9e9a9b9f3b10387418ecfbbd4a018477 %ceurocrypt %@Nigel P. Smart %*On the Performance of Hyperelliptic Cryptosystems %f/eurocrypt/tpshvkcar1gd8cxn9qwlxlbeboipyi2f.pdf %md740b1234c7c65bc9f9228769f60c199 %ceurocrypt %@Tetsutaro Kobayashi,Hikaru Morita,Kunio Kobayashi,Fumitaka Hoshino %*Fast Elliptic Curve Algorithm Combining Frobenius Map and Table Reference to Adapt to Higher Characteristic %f/eurocrypt/udz8xd1zmjs9mph3klsckhnvgwqrbqfb.pdf %m632fb7a04e0f3995fa49ffe584f68bfa %ceurocrypt %@Ryuichi Harasawa,Junji Shikata,Joe Suzuki,Hideki Imai %*Comparing the MOV and FR Reductions in Elliptic Curve Cryptography %f/eurocrypt/0rjuyet2ycwu5pgzwobdhk4oneipntj6.pdf %m266b8553d48a46a138fbdc541613cc0a %ceurocrypt %@Aviad Kipnis,Jacques Patarin,Louis Goubin %*Unbalanced Oil and Vinegar Signature Schemes %f/eurocrypt/f5tkd1yv7rnjacustjgm2bmxuoorhysf.pdf %m458848948713ad9b3b14a9e20f64d6ef %ceurocrypt %@Pascal Paillier %*Public-Key Cryptosystems Based on Composite Degree Residuosity Classes %f/eurocrypt/k24nkr3d0aezppaociyyunvcz5uttqmw.pdf %mfc6532c6230c86df381b369f29449c25 %ceurocrypt %@David Pointcheval %*New Public Key Cryptosystems Based on the Dependent-RSA Problems %f/eurocrypt/7cpjorlkqjmykx2bzg1hcmr4wptgtf5l.pdf %ma4fb7cec5e80f7e69897892d6eb58765 %ceurocrypt %@Serge Vaudenay %*Resistance Against General Iterated Attacks %f/eurocrypt/jcdieun6ubrf2xotbsezy04rp9dgypa7.pdf %m455ba20563c27769fddeb43d10176b49 %ceurocrypt %@Philip Hawkes,Luke O’Connor %*XOR and Non-XOR Differential Probabilities %f/eurocrypt/3r174dmjynpqo2agusi6eqjzmetclhfh.pdf %ma1c1543f45fee421e8cfe194c9b4229b %ceurocrypt %@Jung Hee Cheon,Seongtaek Chee,Choonsik Park %*S-boxes with Controllable Nonlinearity %f/eurocrypt/mg5jesyg4rfn3zyqt2uppvasevjhxdqf.pdf %m193db73f90d467cac917b64d6635c49f %ceurocrypt %@Rosario Gennaro,Stanisław Jarecki,Hugo Krawczyk,Tal Rabin %*Secure Distributed Key Generation for Discrete-Log Based Cryptosystems %f/eurocrypt/xebjhn27zcpsyo5blujgm4invmwfdpc0.pdf %mf90c1dba31e4c924489c8d10ed6930ee %ceurocrypt %@Ronald Cramer,Ivan Damgård,Stefan Dziembowski,Martin Hirt,Tal Rabin %*Efficient Multiparty Computations Secure Against an Adaptive Adversary %f/eurocrypt/vu1hp8i0urlmbc3tgy5fsda4xtr7ljqw.pdf %m5cff972cc07cc70816e272035981edf2 %ceurocrypt %@Moni Naor,Benny Pinkas,Omer Reingold %*Distributed Pseudo-random Functions and KDCs %f/eurocrypt/sp7wm5zaxqrrt6tfu30bzidlnxojcyo9.pdf %m4858aa6a1f4239d0c4cbd2e5f8dc34b9 %ceurocrypt %@Thomas Johansson,Fredrik Jönsson %*Improved Fast Correlation Attacks on Stream Ciphers via Convolutional Codes %f/eurocrypt/hylwvndjd2s13upkagcim7aetfvfh4gq.pdf %m1fdca7abb8a0aaf8a3de72a48e1dbe8d %ceurocrypt %@Lars R. Knudsen,Willi Meier %*Cryptanalysis of an Identification Scheme Based on the Permuted Perceptron Problem %f/eurocrypt/c8d0shwack231qfl4pixnt9dpbjve7mz.pdf %mfad1764134ebcb8060ec2ef0effcd7ef %ceurocrypt %@Luke O’Connor %*An Analysis of Exponentiation Based on Formal Languages %f/eurocrypt/kg0savtpixydcbux6hk51fhoqarm9pbv.pdf %md6bcc32c0b0f9601563329246b203a5b %ceurocrypt %@Takaaki Mizuki,Hiroki Shizuya,Takao Nishizeki %*Dealing Necessary and Sufficient Numbers of Cards for Sharing a One-Bit Secret Key (Extended Abstract) %f/eurocrypt/2op6caiuowgl4yeves8dhdb7mxtsnlyj.pdf %m5dc1bd18b234eef459fda244bf0574c6 %ceurocrypt %@Christian Cachin,Silvio Micali,Markus Stadler %*Computationally Private Information Retrieval with Polylogarithmic Communication %f/eurocrypt/i7cgrzywo649typmnegkwjvaesurxzhp.pdf %m94e030cf1a9313e1a6592b2e40121e99 %ceurocrypt %@Ransom Richardson,Joe Kilian %*On the Concurrent Composition of Zero-Knowledge Proofs %f/eurocrypt/y9vtgixckeuopbat41d50l6xueyzwrzc.pdf %m3166899297ac6c073806c5f0fa1f5728 %ceurocrypt %@Marc Fischlin %*Pseudorandom Function Tribe Ensembles Based on One-Way Permutations: Improvements and Applications %f/eurocrypt/sqcv95zmojkqaupepjvelgu3onatkw10.pdf %mac280c965444496dbbfb47ca6ce52f2b %ceurocrypt %@Yongge Wang,Yvo Desmedt %*Secure Communication in Broadcast Channels: The Answer to Franklin and Wright’s Question %f/eurocrypt/g3ubx4aovvrc9tkyefplyqojt728jhn6.pdf %ma14f5cea4439e35596f0f8b9c5940cf7 %ceurocrypt %@Ran Canetti,Tal Malkin,Kobbi Nissim %*Efficient Communication-Storage Tradeoffs for Multicast Encryption %f/eurocrypt/zdzolf7egjtyprvobw1mtkcsp54xnifs.pdf %m57ab6527ec2aa8fd7cda3046585c5711 %ceurocrypt %@Johan Borst,Lars R. Knudsen,Vincent Rijmen %*Two Attacks on Reduced IDEA %f/eurocrypt/wnervclbkltf1kn3mv7zz4gfjaaq5gd6.pdf %m4d710bd3a9b045d89a83bb25f933f8ae %ceurocrypt %@Thilo Zieschang %*Combinatorial Properties of Basic Encryption Operations %f/eurocrypt/cqykyxge4z298k6hfalblgpjoduvznqv.pdf %m44ec5f67712d5679d4d0b553893edd04 %ceurocrypt %@David Naccache,Jacques Stern %*A New Public-Key Cryptosystem %f/eurocrypt/wcdofiabdnr87lncvxq05utmblysrjhv.pdf %m49819467f359c473edfd38bd162f3694 %ceurocrypt %@Dan Boneh,Richard A. DeMillo,Richard J. Lipton %*On the Importance of Checking Cryptographic Protocols for Faults %f/eurocrypt/01davinoe29pr7ojiu6vlfsywyb8late.pdf %m62a013217ce961c09c031d43f5964e25 %ceurocrypt %@Don Coppersmith,Adi Shamir %*Lattice Attacks on NTRU %f/eurocrypt/eb5uvrmwcqdiemfjbpadsyp9x6ykqggn.pdf %m4d25e18f6b25638485f21a39efc6876b %ceurocrypt %@Adam Young,Moti Yung %*Kleptography: Using Cryptography Against Cryptography %f/eurocrypt/6kl4c5gejqoupjlqxtw1ztrrxmgm30ha.pdf %ma200b8abe9465c030139390979a4d30e %ceurocrypt %@Ronald Cramer,Ivan Damgård %*Fast and Secure Immunization Against Adaptive Man-in-the-Middle Impersonation %f/eurocrypt/rhnrx0gl8anqdjgs2di9yautp7it4uz6.pdf %maf707cc68afca69752bb7dba8539c20e %ceurocrypt %@Birgit Pfitzmann,Michael Waidner %*Anonymous Fingerprinting %f/eurocrypt/xjykbefptmuntoqr24qcylejgra5n0oh.pdf %me4eadddd4a80aba5f397ef67a7173be5 %ceurocrypt %@Ronald Cramer,Rosario Gennaro,Berry Schoenmakers %*A Secure and Optimally Efficient Multi-Authority Election Scheme %f/eurocrypt/p1l7zb9t6j5vyoexwte0fg34rgjlcidh.pdf %m53dbdd6905a46bb23461aeeefedadf77 %ceurocrypt %@Eric R. Verheul,Henk C. A. van Tilborg %*Binding ElGamal: A Fraud-Detectable Alternative to Key-Escrow Proposals %f/eurocrypt/9gljlery8o3uoqfkcfxapwgwd2zkhvim.pdf %m953adc2d2904c06003adb9eff405d922 %ceurocrypt %@Ross Anderson,Michael Roe %*The GCHQ Protocol and Its Problems %f/eurocrypt/dne61msbjy42vfvhdowtrqljlrtmaqop.pdf %m2ba9211d777c01451014b946d384e40d %ceurocrypt %@Thomas Johansson %*Bucket Hashing with a Small Key Size %f/eurocrypt/flmygrhnsg7wtzm6karxuy5hvcpsqx1b.pdf %m3b20efb417b5e20145d84be62b543591 %ceurocrypt %@Mihir Bellare,Daniele Micciancio %*A New Paradigm for Collision-Free Hashing: Incrementality at Reduced Cost %f/eurocrypt/wamjedgzz9y5kn2qpyo80qv4l3rrdlos.pdf %m1357c91fca718a3c6e871651f724f79a %ceurocrypt %@Christian Cachin %*Smooth Entropy and Rényi Entropy %f/eurocrypt/y5jv41qxukzawbrvlb9sectkn7qfgstg.pdf %madd17bfcfc02c378861be36efb7847ea %ceurocrypt %@Ueli Maurer %*Information-Theoretically Secure Secret-Key Agreement by NOT Authenticated Public Discussion %f/eurocrypt/knvboaetlbzklndia57z1yiqmrfpwypf.pdf %m618bfd417726ed9d05c7398ecd9d425d %ceurocrypt %@Jovan Dj. Golić %*Linear Statistical Weakness of Alleged RC4 Keystream Generator %f/eurocrypt/13ufjd795tqlxqrsocjvmwi8kizydyth.pdf %m17fa4ec8f2c4fc3faa252efee510f9ba %ceurocrypt %@Jovan Dj. Golić %*Cryptanalysis of Alleged A5 Stream Cipher %f/eurocrypt/wxehpx5yofpisdqon7lcyvkawjcj2f8i.pdf %mca316c0d0d9ec1e08e7c99b6359a659e %ceurocrypt %@Victor Shoup %*Lower Bounds for Discrete Logarithms and Related Problems %f/eurocrypt/c86ngwgab3rc9eaozq7zuybivi2jyswj.pdf %m09aa8ca6c900cdc60539af347370553f %ceurocrypt %@R. Fischlin,C. P. Schnorr %*Stronger Security Proofs for RSA and Rabin Bits %f/eurocrypt/4j7cyhqq98ean2sygfbowhrimexaflvj.pdf %mfcb34f4a3a7161425e20bc8a48746d69 %ceurocrypt %@Mihir Bellare,Markus Jakobsson,Moti Yung %*Round-Optimal Zero-Knowledge Arguments Based on Any One-Way Function %f/eurocrypt/wrsufzg3jtqd9150l6uiahncdzelokgk.pdf %m1fa04d1374eb6b89c4de7d115d14d02b %ceurocrypt %@Claude Crépeau %*Efficient Cryptographic Protocols Based on Noisy Channels %f/eurocrypt/qzsmfvc6pjqzytor9e4cbskyariblo8p.pdf %m5970475f7d3413909d7fe99bafb09209 %ceurocrypt %@Stefan Brands %*Rapid Demonstration of Linear Relations Connected by Boolean Operators %f/eurocrypt/yfajv0b8nmtouepeqrfccgx1bzw5xsi9.pdf %mdc8221337380d98593534756ab610e51 %ceurocrypt %@Gilles Brassard,Claude Crépeau %*Oblivious Transfers and Privacy Amplification %f/eurocrypt/3jwu82dmwbgjapv5m0kqg7uitflekxzc.pdf %m20135af8740ea4c78ccbb03a2d110ea6 %ceurocrypt %@Antoon Bosselaers,René Govaerts,Joos Vandewalle %*SHA: A Design for Parallel Architectures? %f/eurocrypt/waxhyvrfjwtdgk30b1ierklxtv7jn694.pdf %ma738f46f9f1771ca604f83cdead88408 %ceurocrypt %@Christof Paar,Pedro Soria-Rodriguez %*Fast Arithmetic Architectures for Public-Key Algorithms over Galois Fields GF((2n)m) %f/eurocrypt/u8posi4r3cjygtpbhqufdkwaligwojv9.pdf %m25f35205c8475e3c17acbb24636b7d6e %ceurocrypt %@Reynald Lercier %*Finding Good Random Elliptic Curves for Cryptosystems Defined over % MathType!MTEF!2!1!+- % feaafiart1ev1aaatCvAUfKttLearuqr1ngBPrgarmWu51MyVXgatC % vAUfeBSjuyZL2yd9gzLbvyNv2CaeHbd9wDYLwzYbItLDharyavP1wz % ZbItLDhis9wBH5garqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbb % L8F4rqqrFfpeea0xe9Lq-Jc9vqaqpepm0xbba9pwe9Q8fs0-yqaqpe % pae9pg0FirpepeKkFr0xfr-xfr-xb9adbaqaaeGaciGaaiaabeqaam % aaeaqbaaGcbaWefv3ySLgznfgDOjdarCqr1ngBPrginfgDObcv39ga % iyqacqWFfcVrdaWgaaWcbaGaeeOmaiZaaWbaaWqabeaaieGacqGFUb % GBaaaaleqaaaaa!496C! %f/eurocrypt/zgxknvgykyfqhl14quisaw7cbt32ms89.pdf %m0ff7f32d8203cc2bfafaff9ace40184e %ceurocrypt %@Marc Fischlin %*Incremental Cryptography and Memory Checkers %f/eurocrypt/kwr9jlofidzkqvx7tf21gb0qhxr8n4ht.pdf %m1c8672d531820aa1dbddf4e958572af9 %ceurocrypt %@Kaoru Kurosawa,Thomas Johansson,Douglas Stinson %*Almost k-wise Independent Sample Spaces and Their Cryptologic Applications %f/eurocrypt/ciwpiyfcsh5vl6k10pxe3godurnvzbx8.pdf %mf499806cfa3897cdd8b8b5f868ea4791 %ceurocrypt %@Claude Carlet %*More Correlation-Immune and Resilient Functions over Galois Fields and Galois Rings %f/eurocrypt/dhl78qdbaiqekcayjg25w9rfbmzuzhmi.pdf %m0dc48daf8cdd92d1548ac6c9091fd89b %ceurocrypt %@Kaoru Kurosawa,Takashi Satoh %*Design of SAC/PC(l) of Order k Boolean Functions and Three Other Cryptographic Criteria %f/eurocrypt/qi7wd1gbx95vjeyfo2s0mlc3zsnuxqmt.pdf %m2288fa6601e9cbe82a0d8baf9d3095bd %ceurocrypt %@Markus Jakobsson,Moti Yung %*Distributed “Magic Ink” Signatures %f/eurocrypt/ojwrp5zdv3tmp2bshvfhltkybui0af7j.pdf %ma7db1144a46f4759b072795bb22929be %ceurocrypt %@Jan Camenisch %*Efficient and Generalized Group Signatures %f/eurocrypt/jukde2kwfoy9du4gricjoxl8v157wpsl.pdf %m01a77e10abdecd9564637623d1cb36b5 %ceurocrypt %@Niko Barić,Birgit Pfitzmann %*Collision-Free Accumulators and Fail-Stop Signature Schemes Without Trees %f/eurocrypt/xeuturvmyxb3ml4o9g0nsrkhcvbczai1.pdf %m7924e0a58a6c2ca2fbf76175a0d9a28b %ceurocrypt %@Marc Girault,Jean-François Misarsky %*Selective Forgery of RSA Signatures Using Redundancy %f/eurocrypt/osvl1cweim6pnvxz30gmznsyfk9ir2uq.pdf %m6c5606a33b5509373aa4b230f6879f02 %ceurocrypt %@Don Coppersmith,Matthew Franklin,Jacques Patarin,Michael Reiter %*Low-Exponent RSA with Related Messages %f/eurocrypt/tvsu3vogybrdblfihm1io68y9x0n5eqa.pdf %maec3687999a88fa7e5b1391963931035 %ceurocrypt %@Daniel Bleichenbacher %*Generating EIGamal Signatures Without Knowing the Secret Key %f/eurocrypt/jytqcekd3tfgphfuoz9imn4ull5sbexw.pdf %m28d53583043e2dc1824fd7d44a2e4a0f %ceurocrypt %@Bart Preneel,Paul C. van Oorschot %*On the Security of Two MAC Algorithms %f/eurocrypt/hakhcuiomepy9xndjzbubqesa8gc7vjq.pdf %m5c671602300919aba62d3a860f501808 %ceurocrypt %@Jacques Patarin %*Hidden Fields Equations (HFE) and Isomorphisms of Polynomials (IP): Two New Families of Asymmetric Algorithms %f/eurocrypt/glnebzqht5uycbgdkrsmr2vn6iexcsyj.pdf %m67ce2c9a8257086da8c5cbcb56db9d4a %ceurocrypt %@Bernd Meyer,Volker Müller %*A Public Key Cryptosystem Based on Elliptic Curves over ℤ/nℤ Equivalent to Factoring %f/eurocrypt/rhs9mvadqn5zfpstdzwyqpynllx7u4kj.pdf %mcb04eceaac624eed36885fd7a41f8a15 %ceurocrypt %@Jörg Schwenk,Jörg Eisfeld %*Public Key Encryption and Signature Schemes Based on Polynomials over ℤn %f/eurocrypt/gnem098zhnupaucwg5tikwiq3hpejlfy.pdf %mf06bc8d946aeeee3c3d0062b1b37fa3c %ceurocrypt %@Ronald Cramer,Matthew Franklin,Berry Schoenmakers,Moti Yung %*Multi-Authority Secret-Ballot Elections with Linear Work %f/eurocrypt/7p4dqyro0zgnktksge13bjdymlbatcha.pdf %me8cb9b3b045f0a5b1a1b6a6f0cf98213 %ceurocrypt %@Birgit Pfitzmann,Matthias Schunter %*Asymmetric Fingerprinting %f/eurocrypt/smhuixjramf4vvg7nx3nsw2qo0dk6tj8.pdf %m0de4cf63b520e158bb0b3bc3913b4f87 %ceurocrypt %@Mike Burmester %*Homomorphisms of Secret Sharing Schemes: A Tool for Verifiable Signature Sharing %f/eurocrypt/s1wjbi2qrk7owx6sbqcpzmeyjv3hhk0a.pdf %m66938ad9a7d6e3aad72d61e992917ffd %ceurocrypt %@Simon R. Blackburn,Mike Burmester,Yvo Desmedt,Peter R. Wild %*Efficient Multiplicative Sharing Schemes %f/eurocrypt/ttw7jrknmhre12bm6on5duyjwqa4kghd.pdf %m9fb81e3bff006b1c3bb853c7d3091e92 %ceurocrypt %@Donald Beaver %*Equivocable Oblivious Transfer %f/eurocrypt/lscyxuvrgpwns5q021gvz3hiwrfuhe48.pdf %mf0c6b02bb88397a85a7b52aa67b431b8 %ceurocrypt %@Joan Boyar,René Peralta %*Short Discreet Proofs %f/eurocrypt/fdmuqa2ep9hc8bg46wxlsayifyk5wjth.pdf %m74e3f8f83c56e412a653fd5b69e817b7 %ceurocrypt %@Markus Jakobsson,Kazue Sako,Russell Impagliazzo %*Designated Verifier Proofs and Their Applications %f/eurocrypt/bxoumg9iyplsejhar3ca4k7ztj6pzi5q.pdf %m4cc5b6a3910ee5afcbd6a5882b13c607 %ceurocrypt %@Don Coppersmith %*Finding a Small Root of a Univariate Modular Equation %f/eurocrypt/lauzfsogm2ldhicgfeiwbjsq80ydv1e5.pdf %mf4964f3144e9b1a432d25a3ce960835b %ceurocrypt %@Seong-Min Hong,Sang-Yeop Oh,Hyunsoo Yoon %*New Modular Multiplication Algorithms for Fast Modular Exponentiation %f/eurocrypt/nbfgq9xwomlktrynjfuhdime3hd1207a.pdf %mf0c20876d97304bc61cbbb52e8acb75f %ceurocrypt %@Don Coppersmith %*Finding a Small Root of a Bivariate Integer Equation; Factoring with High Bits Known %f/eurocrypt/hcwujovfb9aeer7igdmfqyukyb24pl5l.pdf %m146016d4a678ff7bd0ad22f6103bac7d %ceurocrypt %@Markus Stadler %*Publicly Verifiable Secret Sharing %f/eurocrypt/lxrkui6hlbfhot2mns4c8badi3qv0qty.pdf %mec27b6a9531062fe618851b992f98300 %ceurocrypt %@Wakaha Ogata,Kaoru Kurosawa %*Optimum Secret Sharing Scheme Secure against Cheating %f/eurocrypt/jlpsam4rnkxod5c9ypz8dobwyewnmrs3.pdf %m2bfca5770cf8b8d8d49fd204e8d039b9 %ceurocrypt %@Keith Gibson %*The Security of the Gabidulin Public Key Cryptosystem %f/eurocrypt/dxtulye1ks4zrv6fnyiq9tjkcd2gscjz.pdf %mf8e666665664867390b891a340841adf %ceurocrypt %@Lars R. Knudsen,M. J. B. Robshaw %*Non-Linear Approximations in Linear Cryptanalysis %f/eurocrypt/twr5ixjaveph3k4yb6g17csnfobmc0o2.pdf %m79e5fb337002f43db66d39340e8c4e06 %ceurocrypt %@Lars R. Knudsen,Torben P. Pedersen %*On the Difficulty of Software Key Escrow %f/eurocrypt/mufreo8dac9lfappns1xg3l5nwswty0c.pdf %m814fad4d9d0c4d00127f0be87dec9c08 %ceurocrypt %@Jean-Bernard Fischer,Jacques Stern %*An Efficient Pseudo-Random Generator Provably as Secure as Syndrome Decoding %f/eurocrypt/abk7nx0l3lywd1icjzjufw2ocstv8ten.pdf %ma82e42259f7bacdbe2937231bcc11949 %ceurocrypt %@Andrew Klapper %*On the Existence of Secure Feedback Registers %f/eurocrypt/oxhyo7ntndmvwicgcejd6fjtkp4bexqa.pdf %mdc1e37a018a32cc7a35b5c8a2c3ee537 %ceurocrypt %@Jovan Dj. Golić %*Fast Low Order Approximation of Cryptographic Functions %f/eurocrypt/skdwoyh7t1ydmxrbun9fiopfmcn5lvjs.pdf %m0b0b7e51e567a75eae7659716cb4d02b %ceurocrypt %@Paul Camion,Anne Canteaut %*Construction of t-Resilient Functions over a Finite Alphabet %f/eurocrypt/dxdz2gyai9o0ascrrmvpvtolzwmqtkjn.pdf %m1d6bbef4989ad533dcbe69f9c2782daa %ceurocrypt %@Xian-Mo Zhang,Yuliang Zheng %*Auto-Correlations and New Bounds on the Nonlinearity of Boolean Functions %f/eurocrypt/s5rxbouhjukfgxjpqd8i2ckrmvny3tz0.pdf %mcc113154654e313ba5abda87f572ec62 %ceurocrypt %@William Aiello,Ramarathnam Venkatesan %*Foiling Birthday Attacks in Length-Doubling Transformations %f/eurocrypt/p6owxrmeah0gcn5kwlz8fvqut4b7hjud.pdf %m34d2094b0b163496f39e065a779eb322 %ceurocrypt %@Victor Shoup,Avi Rubin %*Session Key Distribution Using Smart Cards %f/eurocrypt/myuobxbhp7nvo3pgicqhns9vir46mfde.pdf %mbc9ac5aa2287a58d6e164f105d10a2d1 %ceurocrypt %@Paul C. van Oorschot,Michael J. Wiener %*On Diffie-Hellman Key Agreement with Short Exponents %f/eurocrypt/bzx5dily4qa0lnpc9gsdpeovjb83q6we.pdf %m2c7876588364dbcd0c6ff1a42cd0861a %ceurocrypt %@Victor Shoup %*On the Security of a Practical Identification Scheme %f/eurocrypt/k2jz37vf1lueiampnhxmgdw9k6oirryo.pdf %m0398f36a798ca5bd2c1611a18d088d7e %ceurocrypt %@Rosario Gennaro,Stanisław Jarecki,Hugo Krawczyk,Tal Rabin %*Robust Threshold DSS Signatures %f/eurocrypt/rfhux2wsgpg8djekb0lfyvtm37w9co6b.pdf %m15f52dd2a776a8d38f476cb96bd0366d %ceurocrypt %@Ivan Damgård,Torben Pedersen %*New Convertible Undeniable Signature Schemes %f/eurocrypt/57jigbm2aw0huvmvua6yqxkklf9l81qt.pdf %m9060e2418c093954acbf1cc31c6f4778 %ceurocrypt %@David Pointcheval,Jacques Stern %*Security Proofs for Signature Schemes %f/eurocrypt/icgdgj4xbwb9td8etqnve31kjyvq7y0o.pdf %mfe933bf9223db3ecb41e68fb04cc005f %ceurocrypt %@Mihir Bellare,Phillip Rogaway %*The Exact Security of Digital Signatures-How to Sign with RSA and Rabin %f/eurocrypt/topfxaa9xubhilhrcv17nmdczg3uzwkq.pdf %m2220f167d2370e432099c696a0f15661 %ceurocrypt %@C. P. Schnorr,H. H. Hörner %*Attacking the Chor-Rivest Cryptosystem by Improved Lattice Reduction %f/eurocrypt/ppjx38zwqcflktlmmcaenwxhyvvoyt2g.pdf %m5fa0ca5f4c9e9fe4709ccc433b976c58 %ceurocrypt %@Luke O’Connor %*Convergence in Differential Distributions %f/eurocrypt/nfzbs0r3qkitrjte5x1silwnuvm9g4az.pdf %m0a311cfe07b7337f6d035ea7dc15ec11 %ceurocrypt %@Carlo Harpes,Gerhard G. Kramer,James L. Massey %*A Generalization of Linear Cryptanalysis and the Applicability of Matsui’s Piling-up Lemma %f/eurocrypt/y7oddv0fyj6ms9rg5wbt4iuqceall3kh.pdf %md528629e30afa79241785288b8c99237 %ceurocrypt %@Lidong Chen,Torben P. Pedersen %*On the Efficiency of Group Signatures Providing Information-Theoretic Anonymity %f/eurocrypt/ovh3nfd2qmckvqgiylrinusegdp5cxm1.pdf %m098ac2849356cc78aad7e5ff52394f84 %ceurocrypt %@Matthew K. Franklin,Michael K. Reiter %*Verifiable Signature Sharing %f/eurocrypt/fk0xbtlybgismmzrikhacpfjypq1935g.pdf %m7f2c940ee48275b7477ca153265e9d8a %ceurocrypt %@Chae Hoon Lim,Pil Joong Lee %*Server(Prover/Signer)-Aided Verification of Identity Proofs and Signatures %f/eurocrypt/iomjqzxpmfyesdiyq1kapnurgkcx034h.pdf %m489e9391e19fb42cf9ce510548d381a4 %ceurocrypt %@Reynald Lercier,François Morain %*Counting the number of points on elliptic curves over finite fields: strategies and performances %f/eurocrypt/v7f0h9wvkkqsmzigu1emne8nbropoctj.pdf %m24e6e88a9638a724ec19444d5ee83cae %ceurocrypt %@Damian Weber %*An Implementation of the General Number Field Sieve to Compute Discrete Logarithms mod p %f/eurocrypt/ujbm4zw6txnlspquhbryiw3zfynmosvv.pdf %m994bac4c384e0f762507fec04fd4cb06 %ceurocrypt %@Peter L. Montgomery %*A Block Lanczos Algorithm for Finding Dependencies over GF(2) %f/eurocrypt/ohrtfirgndgfbjway0ckmzoxmxhev7ni.pdf %m685f949724486044ea14d01c42f4800e %ceurocrypt %@Birgit Pfitzmann,Matthias Schunter,Michael Waidner %*How to Break Another “Provably Secure” Payment System %f/eurocrypt/qhst2cekc6zawarbnjmtpl5fyo1z0mvu.pdf %m11f604ef490c9693839652c9e4d1fe19 %ceurocrypt %@Claude Crépeau,Louis Salvail %*Quantum Oblivious Mutual Identification %f/eurocrypt/grlxz4bpqukwqswflhjux0eogzomidvh.pdf %mf59f30498f23900759a2767f9b12903e %ceurocrypt %@Christian Gehrmann %*Secure Multiround Authentication Protocols %f/eurocrypt/k8lbdzyej13blnyqmsdfe5opzrwq0mjv.pdf %m0533877ef0a4cd1e8385083b3e9668ff %ceurocrypt %@Rosario Gennaro,Silvio Micali %*Verifiable Secret Sharing as Secure Computation %f/eurocrypt/fixru40koh2g6bwetngv9mdqbehckaao.pdf %mb5ffe30a35d108b68ea2f7cc8b1eb377 %ceurocrypt %@Wen-Ai Jackson,Keith M. Martin,Christine M. O’Keefe %*Efficient Secret Sharing Without a Mutually Trusted Authority %f/eurocrypt/kbneu4qcrtfaztbwcpjlv71x0nhdedsi.pdf %m91d3b312ed769c9943237f1153344e0e %ceurocrypt %@Philippe Béguin,Antonella Cresti %*General Short Computational Secret Sharing Schemes %f/eurocrypt/pnl7a8ivxzhjklyuqxg6mbnthd9ze2u5.pdf %me77f11949a3071dfdafa884421fca2c2 %ceurocrypt %@Markus Stadler,Jean-Marc Piveteau,Jan Camenisch %*Fair Blind Signatures %f/eurocrypt/qpxn1ry9db7cow2alzimksuh5r4fnfuy.pdf %m951595e2c7f4f2b1b3ddce7ef2acd846 %ceurocrypt %@Markus Jakobsson %*Ripping Coins for a Fair Exchange %f/eurocrypt/m7usvflnihq5ip6k3cjylgefekr9pas4.pdf %m076321fc5670b193c13d9a348eef4b32 %ceurocrypt %@Stefan Brands %*Restrictive Binding of Secret-Key Certificates %f/eurocrypt/4ue3trhwjokj98nndc7mrviyka2ybgz1.pdf %m3ee33f8e47f4a6d3e10ac4c09740fae6 %ceurocrypt %@Jovan Dj. Golić %*Towards Fast Correlation Attacks on Irregularly Clocked Shift Registers %f/eurocrypt/qanb9tlmsguj1hvbfxem2wghkckofjdl.pdf %m1a3449f9ead4aece58cd7c7543270c9b %ceurocrypt %@Andrew Klapper,Mark Goresky %*Large Period Nearly deBruijn FCSR Sequences %f/eurocrypt/wenxz4qsvrd2i7l8yzlmyu9qvoa3j5hj.pdf %m7820b5cdc6d53805bd98fd0489ea0fe1 %ceurocrypt %@Xian-Mo Zhang,Yuliang Zheng %*On Nonlinear Resilient Functions %f/eurocrypt/3aynsmnfqujrmejubr50tcvoztfdowkp.pdf %m861314ee520c7fdb1d7038d08eef1b2c %ceurocrypt %@Kaoru Kurosawa,Satoshi Obana %*Combinatorial Bounds for Authentication Codes with Arbitration %f/eurocrypt/1cu0cbqsefizewryrzxyjpas6vu3l5hw.pdf %m7c4d421b3006f23f18742322a0acd87b %ceurocrypt %@Hugo Krawczyk %*New Hash Functions for Message Authentication %f/eurocrypt/ml1evdykeb245iqn6ptjoblcsfraih3f.pdf %m34687d6ba2ba5059b8a70918c6696cc6 %ceurocrypt %@Jürgen Bierbrauer %*A2—codes from universal hash classes %f/eurocrypt/68tsjpdnrswkftv9qphohlufld1m0wia.pdf %m9aaf3baf449e7369a2ca5e064d0ecccb %ceurocrypt %@David Pointcheval %*A New Identification Scheme Based on the Perceptrons Problem %f/eurocrypt/xr3hmqctisnuf5mkce8fo2jltklndh64.pdf %m006982198a9fa99fdb66378a7a8d714e %ceurocrypt %@Kenji Koyama %*Fast RSA-type Schemes Based on Singular Cubic Curves y2 + axy ≡ x3 (mod n) %f/eurocrypt/ydlwa3rdbegpq0cf8vzueruyxho5s1ik.pdf %m2e8257a6be0b1f020754ac1b7705f0fc %ceurocrypt %@Kouichi Sakurai,Hiroki Shizuya %*Relationships among the Computational Powers of Breaking Discrete Log Cryptosystems %f/eurocrypt/z9ogdewfifbah48r0rlux6atjqob2dnj.pdf %mf7d5d94d9fb7071b13eaf0f872410774 %ceurocrypt %@Mats Näslund %*Universal Hash Functions & Hard Core Bits %f/eurocrypt/zdwbfqkjaacm25cn3qvnebp8mirxzis6.pdf %m57dbdffc1a33e3e082ff10939421bbd8 %ceurocrypt %@Giovanni Di Crescenzo %*Recycling Random Bits in Composed Perfect Zero-Knowledge %f/eurocrypt/xb4l8hgfqahkmcwu17nlg6pvs9dcktdb.pdf %mead3759b66151361e00f97925a121fad %ceurocrypt %@Chih-Hung Wang,Tzonelih Hwang,Jiun-Jang Tsai %*On the Matsumoto and Imai’s Human Identification Scheme %f/eurocrypt/rww5v8imvbh4gfe3kydlcyxht7lzp9po.pdf %m31febc5e41c82185415840aeafb08c02 %ceurocrypt %@Kazue Sako,Joe Kilian %*Receipt-Free Mix-Type Voting Scheme %f/eurocrypt/obqa9wty87ygfptljn4ulkssxi0jc2cd.pdf %ma8ef8d0c1644efaf37cfd124d2443e55 %ceurocrypt %@David Naccache,David M’raïhi,William Wolfowicz,Adina di Porto %*Are Crypto-Accelerators Really Inevitable? %f/eurocrypt/p0dlhms7edk52yqrk3fivzgiafbtocqp.pdf %mdb2efee1983cc3de35e1aebb69412079 %ceurocrypt %@Stefano D’Amiano,Giovanni Di Crescenzo %*Anonymous NIZK Proofs of Knowledge with Preprocessing %f/eurocrypt/4jxqsfvpdybkh3u6ksezxi90lcmocrfu.pdf %m52259037676ddccb89313ffa0e819140 %ceurocrypt %@Moni Naor,Adi Shamir %*Visual cryptography %f/eurocrypt/ozfa5j3xi6bq4pptyktlkzblmwh8s1nm.pdf %mafce49353d94d04d6d43aa77c49fad2a %ceurocrypt %@László Csirmaz %*The size of a share must be large %f/eurocrypt/7dfdecw9yoj8yt02kobzsgl6vwuqxz1m.pdf %mb4200ad2983cf4cef482f2f15eaccb81 %ceurocrypt %@Marten van Dijk %*A linear construction of perfect secret sharing schemes %f/eurocrypt/atmcg14d5iztcfsv9ukzoyg7apqewrjb.pdf %m43b9da0d5931276dd4d80b182f7c740b %ceurocrypt %@C. Blundo,A. Giorgio Gaggia,D. R. Stinson %*On the dealer's randomness required in secret sharing schemes %f/eurocrypt/kol219ei6frpseuk5rtadthzul4vbnqm.pdf %md932033647cd8f667e8fe7c82be6ce98 %ceurocrypt %@C. P. Schnorr,S. Vaudenay %*Black box cryptanalysis of hash networks based on multipermutations %f/eurocrypt/pexlsgio9nhbyzutfgewmac7qzd3dc1p.pdf %m47d972364247875d1f4f5b11c25f3c8f %ceurocrypt %@Antoine Joux,Louis Granboulan %*A practical attack against knapsack based hash functions %f/eurocrypt/cfmxul0pdo2njzi6dyayw1ireqttchlr.pdf %m73798f68f5dca11b525d17e5686e3492 %ceurocrypt %@Matthew Franklin,Moti Yung %*The blinding of weak signatures %f/eurocrypt/k5xlrdvkmeuupqycbevaojmijnt1lxon.pdf %mf1cc0b36610bcc726605f1e82f1fdc88 %ceurocrypt %@David Naccache,David M'RaÏhi,Serge Vaudenay,Dan Raphaeli %*Can D.S.A. be improved? — Complexity trade-offs with the digital signature standard — %f/eurocrypt/sxcpamidbtsr74apu15wwvjfveqkcj6e.pdf %m0001db7e862907c1265e3aceb17d3044 %ceurocrypt %@David Chaum %*Designated confirmer signatures %f/eurocrypt/1f7hfwanlqe3cjo0ryekygo9r4shdwtl.pdf %m6c4bf65aaa1474b48081bb242a835fcf %ceurocrypt %@Mihir Bellare,Phillip Rogaway %*Optimal asymmetric encryption %f/eurocrypt/a9nsjf8m5cu7wzvxpxry4lbemkhtonsj.pdf %md9649e4ef7362e4512c71227c58ad15b %ceurocrypt %@Glenn Orton %*A multiple-iterated trapdoor for dense compact knapsacks %f/eurocrypt/kvs5vacj7xwpwegu0pfyn2aeh69mh4tf.pdf %mbfff1a8fe4450bc56cf0af44e1aeebcc %ceurocrypt %@Florent Chabaud %*On the security of some cryptosystems based on error-correcting codes %f/eurocrypt/dig3vbfbnm4ixt1vojdnqaw7fr8yzmet.pdf %mf2ef4b5ba5841bccf0c546d88462e43a %ceurocrypt %@L. Chen,I. B. Damgård,T. P. Pedersen %*Parallel divertibility of proofs of knowledge %f/eurocrypt/bzapwikahr3hpgexftv8lku4q06dqrs9.pdf %me3a1df49e27979f034c05ce57971a4d5 %ceurocrypt %@Stefano D'Amiano,Giovanni Di Crescenzo %*Methodology for digital money based on general cryptographic tools %f/eurocrypt/fkk0i9bz7syg8mhhilyqrxnzwxgqjd2l.pdf %m8914230543a13ff343160d1805ebc46c %ceurocrypt %@L. Chen,T. P. Pedersen %*New group signature schemes %f/eurocrypt/jzztxiufcmy0mspvbwkdnnkeq7uo142i.pdf %md35e362e71ffeb8b8edd9c644fca7326 %ceurocrypt %@Kaisa Nyberg,Rainer A. Rueppel %*Message recovery for signature schemes based on the discrete logarithm problem %f/eurocrypt/i5hn4g1ks69pz8ttfelgqna3zqphwwbu.pdf %m2c9cdf3851673ddda3f38851706cf252 %ceurocrypt %@Chuan-Ming Li,Tzonelih Hwang,Narn-Yih Lee %*Threshold-multisignature schemes where suspected forgery implies traceability of adversarial shareholders %f/eurocrypt/xsf1apkfocai2gqndpjrmttjqoldvwwe.pdf %mcfb55aa0803112615ede2346582dd754 %ceurocrypt %@Willi Meier,Othmar Staffelbach %*The self-shrinking generator %f/eurocrypt/j5uqgo9h7zwifepse2idrt83fxlsnkw0.pdf %m92b3f4bc6312f2569e3ef78ab4788073 %ceurocrypt %@Mark Goresky,Andrew Klapper %*Feedback registers based on ramified extensions of the 2-adic numbers %f/eurocrypt/pahvkc3xnqpigelfj71iatu5bmxzoc9d.pdf %mb856815203c5a0f42a8dcd654f2ecafc %ceurocrypt %@Rainer Göttfert,Harald Niederreiter %*A general lower bound for the linear complexity of the product of shift-register sequences %f/eurocrypt/gfbomoydxunxjf9gscnrepqkkmpaly21.pdf %meffaa745d89cfdf18e5f439fcfb6a8aa %ceurocrypt %@Jovan Dj. Golić,Luke O'Connor %*Embedding and probabilistic correlation attacks on clock-controlled shift registers %f/eurocrypt/qcwu0clxmdirkzosn5adypvjg3ru1xys.pdf %md78edb9f8fc9bd7717362b6950431999 %ceurocrypt %@Richard Taylor %*Near optimal unconditionally secure authentication %f/eurocrypt/1bvqotrb27z3h0vjxmhdeg9escwy6nk8.pdf %m83a897de4755cc0d617ae175ab03a270 %ceurocrypt %@R. Safavi-Naini,L. Tombak %*Authentication codes in plaintext and chosen-content attacks %f/eurocrypt/hvsaz0wyzqhvjnlkimpa1co45pd8s7rn.pdf %m4b24f7cb47b58860c041cd22dc542d20 %ceurocrypt %@Christian Cachin,Ueli M. Maurer %*Linking information reconciliation and privacy amplification %f/eurocrypt/o4u7svap2khklgtt5foc96wqijuclbwa.pdf %m790758c2f3d3db771fa6d3ade12ba7f6 %ceurocrypt %@Mike Burmester,Yvo Desmedt %*A secure and efficient conference key distribution system %f/eurocrypt/bygz5ixmp10yc6oiafwsk2brlanusejq.pdf %m45e50e555e77883311171ce695fb0c20 %ceurocrypt %@Carlo Blundo,Antonella Cresti %*Space requirements for broadcast encryption %f/eurocrypt/3mb07inx5sbwotzyv19jncpgwd62ileg.pdf %m1be7d0100a11fdbba89a864100f3eabb %ceurocrypt %@Yuliang Zheng %*How to break and repair Leighton and Micali's key agreement protocol %f/eurocrypt/auojtfk5pleb3iuz8wvmkqa1sxr6wght.pdf %m691f8eb55b31ebfd5c97f96ff85d57a2 %ceurocrypt %@Tony Eng,Tatsuaki Okamoto %*Single-term divisible electronic coins %f/eurocrypt/5kymfh7bk9qbrmc2xflej4awtwujscpu.pdf %ma79f40ab3ca387a755c95eacf2e3ddde %ceurocrypt %@Paul Syverson,Catherine Meadows %*Formal requirements for key distribution protocols %f/eurocrypt/pjo02bz9zptexgsumjrhgoskcynd46tq.pdf %m7605996aeb2773600d48a5f9c43ffb55 %ceurocrypt %@Birgit Pfitzmann %*Breaking an efficient anonymous channel %f/eurocrypt/nyzcdwqkum73lrksdi8glqi02xtbupwp.pdf %m13310ca1d20796fd404ba5f117f7f2e2 %ceurocrypt %@Eli Biham %*On Matsui's linear cryptanalysis %f/eurocrypt/mrclj5u9l2emfftnwhyjd4vbqn30pv6k.pdf %m1f16a233a1b7ab3320ee9987d9d78793 %ceurocrypt %@Florent Chabaud,Serge Vaudenay %*Links between differential and linear cryptanalysis %f/eurocrypt/rm0zixw4nhkdey12j85mkgcvtdiqszpt.pdf %m550dd5e8cc4a485779256b14faa6fb49 %ceurocrypt %@Mitsuru Matsui %*On correlation between the order of S-boxes and the strength of DES %f/eurocrypt/fsw7dx0sxyt1cbqflymrga8avj2rwiph.pdf %m243cb0092415773a9cb0e82198c0a1da %ceurocrypt %@Jennifer Seberry,Xian-Mo Zhang,Yuliang Zheng %*Relationships among nonlinearity criteria %f/eurocrypt/l4asvg9yzkrz1btdqixbkyhfhcu6e2vw.pdf %m478912df4ad2a96bc0c061783cf91ac6 %ceurocrypt %@Peter de Rooij %*Efficient exponentiation using precomputation and vector addition chains %f/eurocrypt/3qhfr54udlpqguvtj7cynxkf801hblz2.pdf %m9b360e6ecf4db41e99960481dfd86b7d %ceurocrypt %@F. Damm,F. -P. Heider,G. Wambach %*MIMD-Factorisation on hypercubes %f/eurocrypt/ratnkfoqgxsluu3icjdfv4xqzgshc8hr.pdf %m30e09f14c8c68c2b3d16967483be9cf4 %ceurocrypt %@Lars R. Knudsen,Xuejia Lai %*New attacks on all double block length hash functions of hash rate 1, including the Parallel-DM %f/eurocrypt/cmqndtysk2tcbknhqjrgm4sbrae7pozw.pdf %m1504ba8300198582f00bd0c7c7cabedd %ceurocrypt %@Lars Ramkilde Knudsen %*New potentially ‘weak’ keys for DES amd LOK %f/eurocrypt/mgkcxaeswle8nol1ihaurtfjvophmnxd.pdf %ma18a1bcca3ef464b710a85e5993ee947 %ceurocrypt %@Markus Jakobsson %*Blackmailing using undeniable signatures %f/eurocrypt/yaurozlkaoxc763k8bniimpf0vh9fxys.pdf %m68bde74f93c1dbd2c688ca96a375775c %ceurocrypt %@Jan L. Camenisch,Jean-Marc Piveteau,Markus A. Stadler %*Blind signatures based on the discrete logarithm problem %f/eurocrypt/7a3ibn0fsf8pzn5tlg4aypx9zbdqhyli.pdf %mbbfc86a1faaa256363043d53aeaa5e76 %ceurocrypt %@C. Charnes,L. O'Connor,J. Pieprzyk,R. Safavi-Naini,Y. Zheng %*Comments on Soviet encryption algorithm %f/eurocrypt/h4tgiuez2clbfkmedkxwwoiy8rsuvb76.pdf %md73fc21ec96e7d2a3877708f1d254cd7 %ceurocrypt %@Kaisa Nyberg %*Linear approximation of block ciphers %f/eurocrypt/ywip52rmlyiabcsgdzqlv6tmpbznxoeg.pdf %m2ba599be221f030af12b71232d29f0dc %ceurocrypt %@Adi Shamir %*Memory efficient variants of public-key schemes for smart card applications %f/eurocrypt/5smgoixyyidbqk0gtpxj674jhd3vulka.pdf %m52034833c18de4b62f49c4738fc8b6b8 %ceurocrypt %@Renato Menicocci %*A systematic attack on clock controlled cascades %f/eurocrypt/n4tb0invy8civfqbkcp3rdrpszlmeuxf.pdf %mc2e524d0affddb239374513f53fe8fa5 %ceurocrypt %@Thomas Johansson,Ben Smeets %*On A2-codes including arbiter's attacks %f/eurocrypt/kfrlcam9vowruezlepn482p7gjqxyvug.pdf %mdac9e364f6d770fc3891a2552f8070f4 %ceurocrypt %@Eli Biham,Alex Biryukov %*An improvement of Davies' attack on DES %f/eurocrypt/zipg4ts3uzxoam7avw2n6rbsjnxykchg.pdf %m6a04e24807c43a755c6d6e4614202846 %ceurocrypt %@J. Hruby %*Q-deformed quantum cryptography %f/eurocrypt/fwbomycuk9ktlgz2oiehj4mg7aalb6f0.pdf %m8b23d57d39ffc16521b295c876f46f28 %ceurocrypt %@Thomas Johansson,Gregory Kabatianskii,Ben Smeets %*On the Relation Between A-Codes and Codes Correcting Independent Errors %f/eurocrypt/ekrlgsjyq1bxczmpnrwh7hzmnoxddyav.pdf %m7d01589af5b20e56b47545fa82e7f2bb %ceurocrypt %@R. Safavi-Naini,L. Tombak %*Optimal Authentication Systems %f/eurocrypt/rbtqkwelnjcqkdbrcjfws9oahao6lyvz.pdf %m19a840e8c5adfb5a73f2b5e4ee4db144 %ceurocrypt %@Brandon Dixon,Arjen K. Lenstra %*Factoring Integers Using SIMD Sieves %f/eurocrypt/ubhhcpe7tdllyxasvkxpri6swc4jangg.pdf %ma2e29a8d72f92188fbef2dcbae81a0c8 %ceurocrypt %@N. Demytko %*A New Elliptic Curve Based Analogue of RSA %f/eurocrypt/4j3hmrkgnucqxr5w1p2flsz9adam8o70.pdf %m21f0b7ec8b8036687ca0149fe8afd3a3 %ceurocrypt %@Simon Blackburn,Sean Murphy,Jacques Stern %*Weaknesses of a public-key cryptosystem based on factorizations of finite groups %f/eurocrypt/ip5y2xkjom8t7ce0jsluthdkzv34euyd.pdf %m8e444245f9521d7a60cf69759111acd4 %ceurocrypt %@Kaisa Nyberg %*Differentially uniform mappings for cryptography %f/eurocrypt/65osv3depuzrhtknrt7vpyqgqieg1klc.pdf %mb1a7c62c67d4ec94b3a074fab0829e0f %ceurocrypt %@T. Beth,C. Ding %*On Almost Perfect Nonlinear Permutations %f/eurocrypt/arsnp4zciqqtjxcie5luzagseyol1bwh.pdf %m1d561ed1fa5630c19b538a9f6f3868c4 %ceurocrypt %@Claude Carlet %*Two New Classes of Bent Functions %f/eurocrypt/7sk9lzvfqhlfexg01snypcubjmrd6mjc.pdf %m78fab5a586365dd4ec92b010ef7efb33 %ceurocrypt %@Thomas W. Cusick %*Boolean functions satisfying a higher order strict avalanche criterion %f/eurocrypt/pdkor36pzflqwutvejjzidka0ywlunvi.pdf %m7569f311810cd1801ff2c4cb9f5e9749 %ceurocrypt %@Marco Carpentieri,Alfredo De Santis,Ugo Vaccaro %*Size of Shares and Probability of Cheating in Threshold Schemes %f/eurocrypt/sqg4mpxfrbodwgszce8uyjm03a6hvtd5.pdf %m2317af4e3ceb6381240c823dcc4aa5c2 %ceurocrypt %@Kaoru Kurosawa,Koji Okada,Keiichi Sakano,Wakaha Ogata,Shigeo Tsujii %*Nonperfect Secret Sharing Schemes and Matroids %f/eurocrypt/gklf9xhkbypwzxccnuveldsj2og1ab4z.pdf %m0a83f22dfd3798f8b8e740786c4455ba %ceurocrypt %@Rainer Göttfert,Harald Niederreiter %*On the Linear Complexity of Products of Shift-Register Sequences %f/eurocrypt/owflxgtk4dmjn0ypit2cp8e9czdfhrrv.pdf %m1b7e9e054b3b1bf1a438562ee465b8cc %ceurocrypt %@Joan Daemen,René Govaerts,Joos Vandewalle %*Resynchronization Weaknesses in Synchronous Stream Ciphers %f/eurocrypt/duyqvpilljrxicg0v9hjopkez6egnzha.pdf %m65adeff1ace0783db5818e7ceabc2fdc %ceurocrypt %@Richard A. Games,Joseph J. Rushanan %*Blind Synchronization of m-Sequences with Even Span %f/eurocrypt/47ucrsoei9n53dsmjogaqjcevlbtfud1.pdf %m9ec9a345748df6d526e53d196fe40186 %ceurocrypt %@Jennifer Seberry,Xian-Mo Zhang,Yuliang Zheng %*On Constructions and Nonlinearity of Correlation Immune Functions %f/eurocrypt/o48gialf9wqrsptszhwug357oem6hyze.pdf %mc7d720158817881fee8c8775c54940aa %ceurocrypt %@Ivan Bjerre Damgård %*Practical and Provably Secure Release of a Secret and Exchange of Signatures %f/eurocrypt/wvptpbyaxtmrfjse6qozzhlk32ficiu5.pdf %md57b71f893918f5fa997fb3b992f138a %ceurocrypt %@Gustavus J. Simmons %*Subliminal Communication is Easy Using the DSA %f/eurocrypt/grf3lja8zqfoysqz6pki9jcgike5de17.pdf %mc1580441a53a5678d3d983ee16e6aba1 %ceurocrypt %@David Naccache %*Can O.S.S. be Repaired? - Proposal for a New Practical Signature Scheme - %f/eurocrypt/2srgnzftuabdonldxhk49vq6bpj8ymuz.pdf %m05aed34fb1e2e563eda28fef35744b93 %ceurocrypt %@Colin Boyd,Wenbo Mao %*On a Limitation of BAN Logic %f/eurocrypt/oetfgnerowiwt62kgcvyu3dlzaqushpm.pdf %m53689dd5a7f09fb2f0d1a047a7f4cf12 %ceurocrypt %@Choonsik Park,Kazutomo Itoh,Kaoru Kurosawa %*Efficient Anonymous Channel and All/Nothing Election Scheme %f/eurocrypt/cdig27vvynujmjhpotnpuboe58r0qxmw.pdf %m901cff1dc222a3f776d95e86962277e8 %ceurocrypt %@Josep Domingo-Ferrer %*Untransferable Rights in a Client-Independent Server Environment %f/eurocrypt/ig6b32uvnohsh8we5jmapdigyptlerlr.pdf %m6c3a6e631ed9fdc516a62494ea2a4bf5 %ceurocrypt %@Rafail Ostrovsky,Ramarathnam Venkatesan,Moti Yung %*Interactive Hashing Simplifies Zero-Knowledge Protocol Design %f/eurocrypt/ch9bn07cutvl8fmag6tknpkdp4ewdjez.pdf %m4bc02c6782026e1df6d66199b5f2174a %ceurocrypt %@Josh Benaloh,Michael de Mare %*One-Way Accumulators: A Decentralized Alternative to Digital Signatures %f/eurocrypt/ipqav4wgy0qfmg2sutake56lfdjdkbwr.pdf %m2e5e5d2bbdcd7b02073a96eaf1d46ffc %ceurocrypt %@Ivan B. Damgård,Lars R. Knudsen %*The breaking of the AR Hash Function %f/eurocrypt/jhflvcqaww3yynxdzzobukilcdu1be9n.pdf %mf25d6b577892262ecc060413ddf65c04 %ceurocrypt %@Bert den Boer,Antoon Bosselaers %*Collisions for the compression function of MD5 %f/eurocrypt/uhad1xjmoyl3lvcryb8zt4hkwtim9qn0.pdf %m6b5e45e5943bdf9e07da230edfed3d26 %ceurocrypt %@Jacques Patarin %*How to Find and Avoid Collisions for the Knapsack Hash Function %f/eurocrypt/zn34c9kfsw7pdy2zhwbuqjxsmilnti0v.pdf %mc077173c6433ba1a262dc2bc055efd44 %ceurocrypt %@Niels Ferguson %*Single Term Off-Line Coins %f/eurocrypt/sobwafxfwyuj20hkovr5vp7qmdyapkz3.pdf %m3b218b27ccdd6a5990b11b3bf5234ba1 %ceurocrypt %@R. J. F. Cramer,T. P. Pedersen %*Improved Privacy in Wallets with Observers %f/eurocrypt/l1nubsthqrjaieeuzdka6nhzkgyt8fvm.pdf %m2fecf9e9be9521e8529fc1b6b29ba6e8 %ceurocrypt %@Stefan Brands,David Chaum %*Distance-Bounding Protocols %f/eurocrypt/aied1kf65i3qnoxcwpf7t0hbxklv8j4c.pdf %m9f20c626db45ebbf890e8d4518f7996f %ceurocrypt %@Luke O’Connor %*On the Distribution of Characteristics in Bijective Mappings %f/eurocrypt/6g59cex4npvd3poviwu7tjo0lflsmjnf.pdf %m986120d76f273cd18d8af6ecc3ce0cfd %ceurocrypt %@Willi Meier %*On the Security of the IDEA Block Cipher %f/eurocrypt/lxlr8ft5tj2xkfgj63pcnwi4qhbs0s1y.pdf %mef977bb4d3abd232eb117d13ab5b3828 %ceurocrypt %@Mitsuru Matsui %*Linear Cryptanalysis Method for DES Cipher %f/eurocrypt/i3eo0ulfkyr8lmrzsgkjwb4qbogzdyqx.pdf %m7e15b515db9f7bcebe4e4cbf2204d84d %ceurocrypt %@Eli Biham %*New Types of Cryptanalytic Attacks Using Related Keys %f/eurocrypt/dzfrb1ntjpo0xpnckju43gu9wtxyoy8z.pdf %m947f8958d7d1de6bc51f155ecffc3e73 %ceurocrypt %@Gilles Brassard,Louis Salvail %*Secret-Key Reconciliation by Public Discussion %f/eurocrypt/usngzborjy3q4t2hiotfmrysizdeh58u.pdf %m4cf77a63301e7e3c72f89f57924cc240 %ceurocrypt %@Donald Beaver,Nicol So %*Global, Unpredictable Bit Generation Without Broadcast %f/eurocrypt/hpazy3o5bvj64feugm712xksrfrwg0qa.pdf %m44cf3ecd0bbd1709cd79d5f86c77776b %ceurocrypt %@Peter de Rooij %*On Schnorr’s Preprocessing for Digital Signature Schemes %f/eurocrypt/ajg7nyh2qq1yir0wbkicsm3xgf6dzhap.pdf %m8f6db72cf18d282296a6c3bc67c8f113 %ceurocrypt %@Mike Burmester %*Cryptanalysis of the Chang-Wu-Chen key distribution system %f/eurocrypt/jiqel792hgufgtzfbdpbrrtncawe3c8k.pdf %mc3a266a591a703a3e0978e79352188d9 %ceurocrypt %@Paul C. van Oorschot %*An Alternate Explanation of two BAN-logic “failures” %f/eurocrypt/1heavzfkupzhbg3ivu9rncwyldtsm7km.pdf %mfac683c489aef1d2867e24ad00ede3ab %ceurocrypt %@Gustavus J. Simmons %*The Consequences of Trust in Shared Secret Schemes %f/eurocrypt/g5yjhxlpyfasip9sd4dbe7zbnhkr8lik.pdf %m335b321589984910c23751dc9e8c02db %ceurocrypt %@G. Hornauer,W. Stephan,R. Wernsdorf %*Markov Ciphers and Alternating Groups %f/eurocrypt/b5mxy3nxgig4ff8h7cmkwrpssll1caro.pdf %mfd86fa531fb36c1ed16e23fa27260434 %ceurocrypt %@Choonsik Park,Kaoru Kurosawa,Tatsuaki Okamoto,Shigeo Tsujii %*On Key Distribution and Authentication in Mobile Radio Networks %f/eurocrypt/paukr9yfxvzhovqqfwi42ye6d3j7iagm.pdf %md7365fd80592065cb5110fcaa606b4ce %ceurocrypt %@C. Blundo,A. De Santis,D. R. Stinson,U. Vaccaro %*Graph Decompositions and Secret Sharing Schemes %f/eurocrypt/xnappcxy6ynv7o5eviwf4bmedh80jmt1.pdf %m1f3b5db9fc3d766b0517019c6aa8425a %ceurocrypt %@Yair Frankel,Yvo Desmedt %*Classification of Ideal Homomorphic Threshold Schemes over Finite Abelian Groups %f/eurocrypt/hbjas5um6wzol4tk3cd8ecrzuoeixnk1.pdf %m9d3dc777cf1cee19d1b9c1818cb4fdc4 %ceurocrypt %@T. Baritaud,H. Gilbert,M. Girault %*F.F.T. Hashing is not Collision-free %f/eurocrypt/3y6zkajib7leuvtsrdfuom8qm1hnaghp.pdf %m1728b4437d828523b21d47d6ed4b1768 %ceurocrypt %@C. P. Schnorr %*FFT-Hash II, Efficient Cryptographic Hashing %f/eurocrypt/4qktzj7ziglpyrxg09h13ennvbqm25st.pdf %mc802095985a8ca713ec5e70ce94faa00 %ceurocrypt %@Xucjia Lai,James L. Massey %*Hash Functions Based on Block Ciphers %f/eurocrypt/nw8rgm0xqum4s3frzb296ilhopny75ot.pdf %m7ee7dc7fd7f559ba4d0cbdbc6d52621d %ceurocrypt %@Thomas A. Berson %*Differential Cryptanalysis Mod 232 with Applications to MD5 %f/eurocrypt/gxeb9smknyqmo52wxntjzdr8jygu73al.pdf %mf517ec5d6fbbb53857618ae11c4df7cb %ceurocrypt %@Mitsuru Matsui,Atsuhiro Yamagishi %*A New Method for Known Plaintext Attack of FEAL Cipher %f/eurocrypt/ogfte134ijlhpyxipuqaznxfo8qhbv96.pdf %mc4015747a27372b8dec42e3f311e3798 %ceurocrypt %@Kaisa Nyberg %*On the construction of highly nonlinear permutations %f/eurocrypt/cvaznpwunuvrr87qixih5wmbtmbjod1f.pdf %m54ffc00abb538bdc9b57b537d0f3c9a9 %ceurocrypt %@Ralph Wernsdorf %*The One-Round Functions of the DES Generate the Alternating Group %f/eurocrypt/r92yx7xampyvzqcfcpg34qedngu1sias.pdf %m25a95a3721956c1db25e6127b46d0b4b %ceurocrypt %@Jovan Dj. Golić %*Correlation Via Linear Sequential Circuit Approximation of Combiners with Memory %f/eurocrypt/aldovh8aotume0ycqrz2wipz3wfulcbp.pdf %me76cefebdc76a8894bee3197292d1fa5 %ceurocrypt %@Miodrag J. Mihaljević,Jovan Dj. Golić %*Convergence of a Bayesian Iterative Error-Correction Procedure on a Noisy Shift Register Sequence %f/eurocrypt/uqestqc8pd5m30nesng7vfpvrmkubw1b.pdf %m32cbd9238f74a3843494f34ab44316f7 %ceurocrypt %@Luke O’Connor,Tim Snider %*Suffix trees and string complexity %f/eurocrypt/rjxy90n7wqepa4jkapvs3si2g5uhtyni.pdf %mb3e0d4d664df958295882f1ce7b512da %ceurocrypt %@Birgit Pfitzmann,Michael Waidner %*Attacks on Protocols for Server-Aided RSA Computation %f/eurocrypt/gsyud8jl0pjxniaqxneotd5tu94hm3mk.pdf %mc63525bcee2b1dda0287caefa9c28815 %ceurocrypt %@Greg Harper,Alfred Menezes,Scott Vanstone %*Public-Key Cryptosystems with Very Small Key Lengths %f/eurocrypt/kdeovmelfqxzxt02pmoncvhfqcztws9l.pdf %m7ef52a0c98cfa8ae02864ab800a083f8 %ceurocrypt %@Jörg Sauerbrey,Andreas Dietel %*Resource Requirements for the Application of Addition Chains in Modulo Exponentiation %f/eurocrypt/0lbz17n6wrlkunvka95yumobateqqxcw.pdf %m681ba290b63ba3c78b3c90427e472ceb %ceurocrypt %@B. Dixon,A. K. Lenstra %*Massively parallel elliptic curve factoring %f/eurocrypt/10orwiaernkvacjlos5tdmuiy3gwjbhe.pdf %m6ca40009d4e0b1ebec8a35133a3d9df6 %ceurocrypt % %*The Eurocrypt’92 Controversial Issue Trapdoor Primes and Moduli %f/eurocrypt/rbhbo09nyoajxd6qalqhzes8fv4gj1lw.pdf %md0ab12cb3cea5b7f2f42dc1644a4e4ae %ceurocrypt %@Ernest F. Brickell,Daniel M. Gordon,Kevin S. McCurley,David B. Wilson %*Fast Exponentiation with Precomputation %f/eurocrypt/4r1yqnc0ewcv3pvoudjq2mwusbpoy5kz.pdf %m70e7ce2c1a2ac25c06d4a64c56a625fb %ceurocrypt %@Michael J. Beller,Yacov Yacobi %*Batch Diffie-Hellman Key Agreement Systems and their Application to Portable Communications %f/eurocrypt/ukzumtqlaoehyvskcxpcyj70xg3smbni.pdf %m305fa7e1258052e6910bcb2dca7cbca2 %ceurocrypt %@Keiichi Iwamura,Tsutomu Matsumoto,Hideki Imai %*High-Speed Implementation Methods for RSA Scheme %f/eurocrypt/bfj4wpxjh6wiardl32hbomdixcse8z7n.pdf %ma1c06d90dc843a92b53a0f191a4c31d9 %ceurocrypt %@Ueli M. Maurer %*A Simplified and Generalized Treatment of Luby-Rackoff Pseudorandom Permutation Generators %f/eurocrypt/uaj09ysrilxcqh8do6rjzq57fegstyli.pdf %m385e5be49ea7283b78a4d90bdab803f7 %ceurocrypt %@Jacques Patarin %*How to Construct Pseudorandom and Super Pseudorandom Permutations from One Single Pseudorandom Function %f/eurocrypt/akghf25eempbntivjxbhcoqysl7cvklx.pdf %m6f3c4e3a425a610998329bfddc8dd7d5 %ceurocrypt %@Babak Sadeghiyan,Josef Pieprzyk %*A Construction for Super Pseudorandom Permutations from A Single Pseudorandom Function %f/eurocrypt/18gqzuofjjenmllgsievrzbw7vydmc03.pdf %m0354c00824704c80fde4a95fcfde3eb5 %ceurocrypt %@Donald Beaver %*How to Break a “Secure” Oblivious Transfer Protocol %f/eurocrypt/gdvtwml1u8k3bhhzyrixpcnn5cxgzaeb.pdf %mf28f871a8866adeefa303cff226ce0b1 %ceurocrypt %@Paul Barbaroux %*Uniform Results in Polynomial-Time Security %f/eurocrypt/naxw12lvjleznwbmr86btohtqidf3u9h.pdf %m11ffa22e2c5ac12ad1f8ad5149da9a95 %ceurocrypt %@Donald Beaver,Stuart Haber %*Cryptographic Protocols Provably Secure Against Dynamic Adversaries %f/eurocrypt/gjyn7fuvl4hrkq8xfpudkm1lwtcq6o3p.pdf %mfafb20195e0f85b84f2dfd612604552f %ceurocrypt %@Kazuo Ohta,Tatsuaki Okamoto,Atsushi Fujioka %*Secure Bit Commitment Function against Divertibility %f/eurocrypt/c8yfwyb4m3j76isdxo5uzaqhljoqzg9v.pdf %m00d023dfbe35af6fcc22aed1093fb3ac %ceurocrypt %@Ivan Damgård %*Non-Interactive Circuit Based Proofs and Non-Interactive Perfect Zero-knowledge with Preprocessing %f/eurocrypt/il7qhsvwxfdjci4uejdyftg85bhs0aou.pdf %mecc55896180f156ac50a8346b6aa7346 %ceurocrypt %@Ingrid Biehl,Johannes Buchmann,Bernd Meyer,Christian Thiel,Christoph Thiel %*Tools for Proving Zero Knowledge %f/eurocrypt/ogv9onsxy32icb4nqye1laivkhf8lu5m.pdf %m4cefc583f1e3011e3566830829124fde %ceurocrypt %@Eugène van Heyst,Torben Pryds Pedersen %*How to Make Efficient Fail-stop Signatures %f/eurocrypt/mk4ip0zmvuet8jrihbtu7xofkydd2qqn.pdf %m5e3668e4c6e0fb543216b85669288309 %ceurocrypt %@David Chaum,Torben Pryds Pedersen %*Transferred Cash Grows in Size %f/eurocrypt/pi0dxz1dwkj6mam5sk3w9bnuttsgocbi.pdf %m5e823264f7286e91e20b41d147c8bed5 %ceurocrypt %@H. Niederreiter,C. P. Schnorr %*Local Randomness in Candidate One-Way Functions %f/eurocrypt/hk2l9sqgdnedt0ui8mlzj4gqjm7xccar.pdf %m93d169439b28cbab4735418d6867004f %ceurocrypt %@Tatsuaki Okamoto,Kouichi Sakurai,Hiroki Shizuya %*How Intractable Is the Discrete Logarithm for a General Finite Group? %f/eurocrypt/2hirlay7pmlm0wpdgf8y1qzc9kbhwr5q.pdf %m7ffa6cd8a7c1358275cfa9826669c2f5 %ceurocrypt %@Ueli M. Maurer %*Factoring with an Oracle %f/eurocrypt/iqzlo4jku38jvd9vrhg0kxdcfqnps5lb.pdf %m8508c01bc35efb8e915a47ced8f2cca6 %ceurocrypt %@Rafi Heiman %*Secure Audio Teleconferencing: A Practical Solution %f/eurocrypt/spdojqxh6w7cfrofnb3apy2z9lga84xt.pdf %ma5bc97150506af5820d98a436ef2e8af %ceurocrypt %@Kenji Koyama %*Secure Conference Key Distribution Schemes for Conspiracy Attack %f/eurocrypt/xsbhj5tzlykah1krcvc7zv3qul829e0p.pdf %mde209ad38e011f0133a8c1fa15a54570 %ceurocrypt %@Rafi Heiman %*A Note on Discrete Logarithms with Special Structure %f/eurocrypt/tz4sh3bhnayva6cjevqprdximr87bwgy.pdf %m238c8918a80213d4010201e41b4b5aa2 %ceurocrypt %@Ueli M. Maurer,Yacov Yacobi %*A Remark on a Non-interactive Public-Key Distribution System %f/eurocrypt/4qcgldfpmewhnv6osgmrbiku9owlhety.pdf %m49a9c113c2ebb5d92a5f23e1e29a1c86 %ceurocrypt %@Lidong Chen,Ivan Damgård %*Security Bounds for Parallel Versions of Identification Protocols %f/eurocrypt/lpx87bvcxwugf5esi4c0waenhyrttvdh.pdf %m9fcfc567990ab3564373f1932b740005 %ceurocrypt %@Andrea Sgarro %*Information-Theoretic Bounds for Authentication Frauds %f/eurocrypt/rltewnuosw1mkd2skoxrlib93py5vqia.pdf %m0aab87396f7a7c5fc2ce639de1d78a06 %ceurocrypt %@Jovan Dj. Golić,Slobodan V. Petrović %*A Generalized Correlation Attack with a Probabilistic Constrained Edit Distance %f/eurocrypt/mptocci2eojf8genux7pqkvratf3whys.pdf %m4101c2370969f8487c7c5fd7be12fd67 %ceurocrypt %@Keiichi Iwamura,Tsutomu Matsumoto,Hideki Imai %*Systolic-Arrays for Modular Exponentiation Using Montgomery Method %f/eurocrypt/auqdm1cozktmngriofxe3srp26wv04lw.pdf %m7bc29081b5576250fba7682a571912f0 %ceurocrypt %@G. B. Agnew,R. C. Mullin,S. A. Vanstone %*On the Development of a Fast Elliptic Curve Cryptosystem %f/eurocrypt/pxiqs6jvfmynnec972gwhaz31k4cbkpu.pdf %m35abf58feb3ce85c4a9cb493cc108146 %ceurocrypt %@David Naccache %*A Montgomery-Suitable Fiat-Shamir-Like Authentication Scheme %f/eurocrypt/ixb1um0zgcvojwliednkwhfxhdoq86sb.pdf %me198fc18a275f8ad2fda7995854587f2 %ceurocrypt %@Eli Biham,Adi Shamir %*Differential Cryptanalysis of Feal and N-Hash %f/eurocrypt/izmga46sjnr2qejsdfidgt0lhu5vt1bb.pdf %m584f268d0dff43932301d2f40611d0e0 %ceurocrypt %@Xuejia Lai,James L. Massey,Sean Murphy %*Markov Ciphers and Differential Cryptanalysis %f/eurocrypt/2hue6iimjmwqkdguz4angrvo9qshx1t8.pdf %m7bbe8ae616f61df48f514f07875cd980 %ceurocrypt %@Paul Camion,Jacques Patarin %*The Knapsack Hash Function proposed at Crypto’89 can be broken %f/eurocrypt/mgfekp1chnlbdolfutby6taaqxxrzoqk.pdf %mc1c1066db0127b77fd25e7465dfc6700 %ceurocrypt %@M. J. Coster,B. A. LaMacchia,A. M. Odlyzko,C. P. Schnorr %*An Improved Low-Density Subset Sum Algorithm %f/eurocrypt/t9h6zdmgruisoakrjnpsboqaip7xxjy1.pdf %m7957c7d918ad8954c6d57a9f4089c1ac %ceurocrypt %@Valery I. Korzhik,Andrey I. Turkin %*Cryptanalysis of McEliece’s Public-Key Cryptosystem %f/eurocrypt/q6wedpqjgmncxvvo1nkkifitmasuybzo.pdf %m67f6c86114f7ea2b1697cb68a1027752 %ceurocrypt %@Peter de Rooij %*On the Security of the Schnorr Scheme using Preprocessing %f/eurocrypt/e5ncjdmwhkv7126zpurjxwk8qqigtiod.pdf %m2ac97f4f6b1ed7ec4064035bdb973332 %ceurocrypt %@Tatsuaki Okamoto,David Chaum,Kazuo Ohta %*Direct Zero Knowledge Proofs of Computational Power in Five Rounds %f/eurocrypt/ogmh6vvof5zkyz03ejw7pitwhtjrf82l.pdf %me8f33581def68c0e2ec13e34c259db0f %ceurocrypt %@Claude Crépeau,Miklós Sántha %*On the Reversibility of Oblivious Transfer %f/eurocrypt/vdjprfodri7j4kcq6itnwvb2oane9hku.pdf %m62656d1679ede20581c5528bd2f0d842 %ceurocrypt %@Sibylle Mund %*Ziv-Lempel Complexity for Periodic Sequences and its Cryptographic Application %f/eurocrypt/a1pmhcvokfyd97j3ntlsudhercrk4q8t.pdf %m32fed889f33b72cfb0efb8aadd16978f %ceurocrypt %@Toshiki Habutsu,Yoshifumi Nishio,Iwao Sasase,Shinsaku Mori %*A Secret Key Cryptosystem by Iterating a Chaotic Map %f/eurocrypt/ftowdovll0fzaaz7vkkjbeedriq6yn4m.pdf %m05a8f3125a351a5a6060d296248ba709 %ceurocrypt %@B. Preneel,René Govaerts,Joos Vandewalle %*Boolean Functions Satisfying Higher Order Propagation Criteria %f/eurocrypt/ycnzx1w3wtoj8qzmurfgjplv54msd2fu.pdf %m44b609752ef868bdd1f6549d1de260c1 %ceurocrypt %@Cees J. A. Jansen %*The Maximum Order Complexity of Sequence Ensembles %f/eurocrypt/xeoc7ali5es29vmtnoyfbqhain6ku1u0.pdf %m71615d1cbf9068f025a7af7d57ac0604 %ceurocrypt %@Jovan Dj. Golić %*The Number of Output Sequences of a Binary Sequence Generator %f/eurocrypt/r59w2kvowtumn4rppnihmdg8esqyxgu6.pdf %m684a31a2e5ac072bf91450f6c3931cd4 %ceurocrypt %@Zong-Duo Dai,Jun-Hui Yang %*Linear Complexity of Periodically Repeated Random Sequences %f/eurocrypt/f27k8zo6qx4uyfvidnckv0gradrg53ps.pdf %md0163ba28606596ed7d9b5d243a51445 %ceurocrypt %@Vladimir Chepyzhov,Ben Smeets %*On A Fast Correlation Attack on Certain Stream Ciphers %f/eurocrypt/eloimm2hft6ny0wjxzkgjga3dqqpkzv8.pdf %m63b195dac191417b877635ee7f681be5 %ceurocrypt %@Willi Meier,Othmar Staffelbach %*Analysis of Pseudo Random Sequences Generated by Cellular Automata %f/eurocrypt/gbpnue8wizbjgu57ldarweymi1sx4ctq.pdf %m4c40fda74ba5500a6b072fd24e82764c %ceurocrypt %@Yvo Desmedt,Moti Yung %*Weaknesses of Undeniable Signature Schemes %f/eurocrypt/l02doitcubsnnzpyhxd6vji5kauzxl9a.pdf %m3356b086cf125b47091f5757d9446001 %ceurocrypt %@Torben Pryds Pedersen %*Distributed Provers with Applications to Undeniable Signatures %f/eurocrypt/qrztuhf4uvdrzo9mgkl5cp27fxxtksmn.pdf %m37958d1bcb1fd0d02a1ab7bfe4c25b97 %ceurocrypt %@Atsushi Fujioka,Tatsuaki Okamoto,Kazuo Ohta %*Interactive Bi-Proof Systems and Undeniable Signature Schemes %f/eurocrypt/kzpj5nadgzqyelr3h4j16qibmpo0s9fm.pdf %m6f7b9d5bbe2bf1256502214379624fc6 %ceurocrypt %@David Chaum,Eugène van Heyst %*Group Signatures %f/eurocrypt/8dqpohkamzvsrprjglgcx3ww5stl9tk6.pdf %ma7e195816b21dc834f716b4644866aeb %ceurocrypt %@Colin Boyd %*Enhancing Secrecy by Data Compression: Theoretical and Practical Aspects %f/eurocrypt/4kg50jzyfa7tifn3tudpmomresqhnj8u.pdf %m0d5e4e15f4d48d6b39199fc009eeed1b %ceurocrypt %@C. P. Schnorr %*Factoring Integers and Computing Discrete Logarithms via Diophantine Approximation %f/eurocrypt/r6qahpoieyfe9x0zqsdbbvt8tyigzlma.pdf %mb842502fc3cc3034e96fcf89a3b586f6 %ceurocrypt %@Klaus Huber %*Some Considerations concerning the Selection of RSA Moduli %f/eurocrypt/vtn2qg4myflpqzxcoiar1dk7julxibkb.pdf %m0f442f9afa85c19debab30f8399ac045 %ceurocrypt %@Michael Portz %*On the Use of Interconnection Networks in Cryptography %f/eurocrypt/27gdnlv1rsrqhuiovwk0qfxxbgab95ie.pdf %mfde0250095dd4a4d12226bf28d8d0f3a %ceurocrypt %@T. Beth,F. Schaefer %*Non Supersingular Elliptic Curves for Public Key Cryptosystems %f/eurocrypt/was4y6vclryeb5eo7dhghfsozdlkmpgn.pdf %mc6f0f2930b507765104de14185f5582c %ceurocrypt %@François Morain %*Building Cyclic Elliptic Curves Modulo Large Primes %f/eurocrypt/fapd94jqvs75rug1m2zoponybc03nzke.pdf %made9b3a21ea25546857be83843017106 %ceurocrypt %@Haroka Shizuya,Toshiya Itoh,Kouichi Sakurai %*On the Complexity of Hyperelliptic Discrete Logarithm Problem %f/eurocrypt/cjmy1ulrwdtmosixzbqn6f0yjvhlpda8.pdf %m10ac0560dc1b99fcfb888e668f06fbc9 %ceurocrypt %@M. H. Dawson,S. E. Tavares %*An Expanded Set of S-box Design Criteria Based on Information Theory and its Relation to Differential-Like Attacks %f/eurocrypt/wei7nxnfy8kjwvdxhurs04zfia2pjzye.pdf %m36b179e5e9a43ffdb5b2ad878e67adc5 %ceurocrypt %@Luke O’Connor %*Enumerating Nondegenerate Permutations %f/eurocrypt/ijqylfthgkmxzkwojip0qcx1hz25l9df.pdf %mfb5057cfda18cb30937075289deb9524 %ceurocrypt %@Kaisa Nyberg %*Perfect nonlinear S-boxes %f/eurocrypt/k13x59irtvvu8eqyuckxhjldgebwzgmp.pdf %m88d581ebdade61dec3708bf44aa295d8 %ceurocrypt %@Rainer A. Rueppel %*A Formal Approach to Security Architectures %f/eurocrypt/vk4u2bjadpg8hp1f6eeadszxngixqqtc.pdf %me007c4960903ef59d0935aa1e414f6e4 %ceurocrypt %@Patrick Horster,Hans-Joachim Knobloch %*Discrete Logarithm Based Protocols %f/eurocrypt/lp2zwiicjjvd74mkgnhgkqzodplwm8u3.pdf %m1444b70f133f85120e66ae9da32b4c87 %ceurocrypt %@Tsutomu Matsumoto,Hideki Imai %*Human Identification Through Insecure Channel %f/eurocrypt/6sw8jmqocwcxgpo7y1tyux90gdllbadn.pdf %m6a673de4f282f6c67ff6581e82904064 %ceurocrypt %@B Goldburg,E Dawson,S Sridharan %*The Automated Cryptanalysis of Analog Speech Scramblers %f/eurocrypt/dhyzxtsvlv2ouc1gpjwmrkrea378kh09.pdf %m316b74f066fd497d879f0b0acd26d33b %ceurocrypt %@Babak Sadeghiyan,Josef Pieprzyk %*A Construction for One Way Hash Functions and Pseudorandom Bit Generators %f/eurocrypt/fggnzlpyz78bjyaqrco5sme394uhvjb2.pdf %m8912a9141d114f188c21d9855068845d %ceurocrypt %@Atsushi Fujioka,Tatsuaki Okamoto,Shoji Miyaguchi %*ESIGN: An Efficient Digital Signature Implementation for Smart Cards %f/eurocrypt/epom7ktyhionb5i3mrqjxx0rz96begnf.pdf %m9fa6ce6d58c762f0831206d45fba39c8 %ceurocrypt %@Ueli M. Maurer %*New Approaches to the Design of Self-Synchronizing Stream Ciphers %f/eurocrypt/dftbpsodxzjfu4en9kxwwjcneyl5vam2.pdf %mc792599639d3f1324e33d498900151c1 %ceurocrypt %@Josef Pieprzyk,Reihaneh Safavi-Naini %*Randomized Authentication Systems %f/eurocrypt/h3oy9xqiukdzajcxh5c1nk7lf8p2lrae.pdf %m78d61d2ee6b4660521df0c512ee31aef %ceurocrypt %@E. M. Gabidulin,A. V. Paramonov,O. V. Tretjakov %*Ideals over a Non-Commutative Ring and their Application in Cryptology %f/eurocrypt/05iutycsf1ayip9h7uhnz6ecgx3wkobs.pdf %m0069dbfd4484674308fa37cb5ff52454 %ceurocrypt %@Marc Girault %*Self-certified public keys %f/eurocrypt/4huxejufxnyhd2gtarq73cscpfjwsi9l.pdf %ma8c1e8118edf219660eabab9a85bfb51 %ceurocrypt %@Ueli M. Maurer,Yacov Yacobi %*Non-interactive Public-Key Cryptography %f/eurocrypt/ku73c0mrmpfagnlsisyeqltkvxuvj6fh.pdf %me0874b4126828f7ea69ec0c3da2167fa %ceurocrypt %@G. Zémor %*Hash Functions And Graphs With Large Girths %f/eurocrypt/zewy6rzyfak4msbficj8071lwjctrhhx.pdf %ma5900c8d84e31f0b14709987bbb1f32a %ceurocrypt %@Winfried B. Müller,Alan Oswald %*Dickson Pseudoprimes and Primality Testing %f/eurocrypt/pqkvcymapjmc3esxfiavwrdz6hnqn5ow.pdf %mbf7e9a670c0f046b15f9a9c0822035f9 %ceurocrypt %@J. K. Gibson %*Equivalent Goppa Codes and Trapdoors to McEliece’s Public Key Cryptosystem %f/eurocrypt/n2cxodu1re7l4wk0fvkiept6zbhdursp.pdf %m1155d474916d08e98992271e679aa4ac %ceurocrypt %@Torben Pryds Pedersen %*A Threshold Cryptosystem without a Trusted Party %f/eurocrypt/yub0ghscq6pykwtxefpkquaeiwn1jdsr.pdf %m2aeb1d2534005c727b61c92b27f70e13 %ceurocrypt %@Miodrag J. Mihaljević,Jovan Dj. Golić %*A Comparison of Cryptanalytic Principles Based on Iterative Error-Correction %f/eurocrypt/mzlpsa06jrdof42ymtiwdkp5ro3giv9f.pdf %m28a424a5eea1f15951049f5c91a2a3d3 %ceurocrypt %@Eli Biham %*Cryptanalysis of the Chaotic-Map Cryptosystem Suggested at EUROCRYPT’91 %f/eurocrypt/abcwiqls1rmy8vyojjxf35cma6h47k9g.pdf %m40b42cd725d26f08ab0b1fd6158be499 %ceurocrypt %@Shimshon Berkovits %*How To Broadcast A Secret %f/eurocrypt/przt0jllopc3gh6f2fs48dymqxhmynj1.pdf %m36be396d833bab8ac116d7253a7e3568 %ceurocrypt %@Josef Pieprzyk %*Probabilistic Analysis of Elementary Randomizers %f/eurocrypt/cr5rhakvybagzlxie9tgx32t6fzobqyp.pdf %mdc63b388f376eb1b5867027fa01314b3 %ceurocrypt %@B. Preneel,D. Chaum,W. Fumy,C. J. A. Jansen,P. Landrock,G. Roelofsen %*Race Integrity Primitives Evaluation (RIPE): A status report %f/eurocrypt/ypcypisfvbuglodgcf6tnwijtzhkmbah.pdf %m790276bf884306e7171c2a1d68413b47 %ceurocrypt %@Lennart Brynielsson %*The Information Leakage through a Randomly Generated Function %f/eurocrypt/8dqzj5hgn9cziwarkxyfmwmos0bgpt6u.pdf %m9672b8900d9a5569c20a59f25412c548 %ceurocrypt %@David Chaum %*Some Weaknesses of “Weaknesses of Undeniable Signatures” %f/eurocrypt/iex0y1b2cdftkadniz3hjpkymmg6lqot.pdf %m1de22f2e8431115f8d011f54b627607e %ceurocrypt %@Mike V. D. Burmester,Yvo Desmedt %*All Languages in NP Have Divertible Zero-Knowledge Proofs and Arguments Under Cryptographic Assumptions %f/eurocrypt/un82pgjasokkj1l3racxp5cmyshftbed.pdf %ma587021cbd0071ddcc70603a427719d0 %ceurocrypt %@George Davida,Yvo Desmedt,René Peralta %*On the Importance of Memory Resources in the Security of Key Exchange Protocols %f/eurocrypt/ypggc4lajzofqblvc1srm6dfvkxejak9.pdf %mec7e6397af60fc306aa67e06a8be393e %ceurocrypt %@S. Shinozaki,T. Itoh,A. Fujioka,S. Tsujii %*Provably Secure Key-Updating Schemes in Identity-Based Systems %f/eurocrypt/9onk1arbjeo6rkghasl2hg8uzizfecxc.pdf %m184857beeab09afcf6fd72f662540e54 %ceurocrypt %@Bert den Boer %*Oblivious transfer protecting secrecy %f/eurocrypt/795jy36sax1sjvwpfguiolreeitkhny8.pdf %m966af6ab0184d38c4092fd148a48e2ec %ceurocrypt %@Alfredo De Santis,Giuseppe Persiano %*Public-Randomness in Public-Key Cryptography %f/eurocrypt/wnewitrj3gez8o6rhluydbz1cjomix2g.pdf %mab82f41c12dbcb6887c07338c021b275 %ceurocrypt %@Ernest F. Brickell,Kevin S. McCurley %*An Interactive Identification Scheme Based on Discrete Logarithms and Factoring %f/eurocrypt/uzudlgh9i4dsiwfabbk8h51lkexpot3w.pdf %m9172dd37d5c1c44ba5740d033e9ce4ee %ceurocrypt %@Arjen K. Lenstra,Mark S. Manasse %*Factoring with two large primes %f/eurocrypt/zgcezlf2siukbbkqxhv6h4789wqdvsym.pdf %m2ffeb0859e61e14b1b67dbff01d878a5 %ceurocrypt %@Jan-Hendrik Evertse,Eugène van Heyst %*Which new RSA signatures can be computed from some given RSA signatures? %f/eurocrypt/4kalyirdghecuags758bq6wm2zcqhjox.pdf %ma914251110f417092cbab0442dadbc7f %ceurocrypt %@Renate Scheidler,Johannes A. Buchmann,Hugh C. Williams %*Implementation of a Key Exchange Protocol Using Real Quadratic Fields %f/eurocrypt/osrg13aebjwgzzfmsbt0nhqfdv92xxie.pdf %m32568f5f1af49cbecf51b7391c819032 %ceurocrypt %@François Morain %*Distributed Primality Proving and the Primality of (23539 + 1)/3 %f/eurocrypt/mowzltegsk5eygp370phbxianjfaui6f.pdf %m720adb25612b50717292091ead084206 %ceurocrypt %@Sheelagh Lloyd %*Properties of binary functions %f/eurocrypt/5ler7p2kfiewgi1nbzomd8rj06yhkuty.pdf %m1d3181dcfdc7871259dff59050a366e0 %ceurocrypt %@Josef Pieprzyk %*How to Construct Pseudorandom Permutations from Single Pseudorandom Functions %f/eurocrypt/d4aceifxkzs0jvktbr9ozfuvyxnjwmqd.pdf %m6e59920aacc223b5b857f8ec3937fee6 %ceurocrypt %@Kaisa Nyberg %*Constructions of bent functions and difference sets %f/eurocrypt/rsracu03h5zi7gekesxpmh98zglktjqm.pdf %mbe51f666c5fdba368c80622d2eeb6671 %ceurocrypt %@Bart Preneel,Werner Van Leekwijck,Luc Van Linden,René Govaerts,Joos Vandewalle %*Propagation Characteristics of Boolean Functions %f/eurocrypt/xvdt7bjlhgc9zn04nri6szdwr5wqp8qf.pdf %m1335ca4a208336484645a63cb416471e %ceurocrypt %@Harald Niederreiter %*The Linear Complexity Profile and the Jump Complexity of Keystream Sequences %f/eurocrypt/jy01swn792vojclixfhzsadgeuizfvut.pdf %mfc754a42908dccffbc54c96463e411df %ceurocrypt %@Zong-duo Dai,Thomas Beth,Dieter Gollmann %*Lower Bounds for the Linear Complexity of Sequences over Residue Rings %f/eurocrypt/mtcpmfpzqh0uxfkn4jubgve1k7avoe2a.pdf %mbf141b960b4c78cf28b39ea8555bd2be %ceurocrypt %@Cees J. A. Jansen %*On the Construction of Run Permuted Sequences %f/eurocrypt/lfm2wc1eijs70w4ehy9guza8us6yob3p.pdf %m9028c6f46e7caf34b04e33b2210b29bb %ceurocrypt %@Willi Meier,Othmar Staffelbach %*Correlation Properties of Combiners with Memory in Stream Ciphers (Extended Abstract) %f/eurocrypt/zq2g1qhwxmifgpcoruk87s9fsnxd43re.pdf %m57f92df745b60ee893adca3a0fae2609 %ceurocrypt %@Agnes Hui Chan,Mark Goresky,Andrew Klapper %*Correlation Functions of Geometric Sequences %f/eurocrypt/sc8zue1gzycxdkjqfwvmswmipnogbe5i.pdf %m9256482d0828bec5a1dd2ad3999a9902 %ceurocrypt %@Y. Yacobi %*Exponentiating Faster with Addition Chains %f/eurocrypt/4bnrctwmxdefrhxjllaboz3iq2kvsfug.pdf %m5c85fcfbb80b5227651e0418b333a1a2 %ceurocrypt %@Stephen R. Dussé,Burton S. Kaliski %*A Cryptographic Library for the Motorola DSP56000 %f/eurocrypt/x2ijtopdmtpsbgzo3vx7idfvm9g1w4rf.pdf %mb23f5aabf83c7a539a6fcee9f3cb5c54 %ceurocrypt %@Holger Orup,Erik Svendsen,Erik Andreasen %*VICTOR an efficient RSA hardware implementation %f/eurocrypt/iztms6nujkaomvei8vhhb41gywrjqbtl.pdf %m0208d77161838993872196f29e26efbe %ceurocrypt %@Charles H. Bennett,François Bessette,Gilles Brassard,Louis Salvail,John Smolin %*Experimental Quantum Cryptography %f/eurocrypt/amecwlh5xrowyan4i7hdgvpifjsr2bj8.pdf %m7e917ca07b62a472b10320697f664669 %ceurocrypt %@Ingemar Ingemarsson,Gustavus J. Simmons %*A Protocol to Set Up Shared Secret Schemes Without the Assistance of a Mutually Trusted Party %f/eurocrypt/qudynfzkrkbozm93pgw8qiyhtv6bc2mt.pdf %mdad01f70b26e003890a7f9cd302ef165 %ceurocrypt %@Andrea Sgarro %*Lower Bounds for Authentication Codes with Splitting %f/eurocrypt/wanclh2qsm9b8ut4x5qegk0fvipkrpe7.pdf %ma5fb6e57a87b45024af7bbdb0d82a40e %ceurocrypt %@Albrecht Beutelspacher,Ute Rosenbaum %*Essentially ℓ-fold secure authentication systems %f/eurocrypt/6eqqc9jmuf1pboznagadvsudnrpysi7r.pdf %m549714bf1b2183f0d7104232b8bce1ec %ceurocrypt %@Ben Smeets,Peter Vanroose,Zhe-xian Wan %*On the construction of authentication codes with secrecy and codes withstanding spoofing attacks of order L ≥ 2 %f/eurocrypt/rfxdqrltvukwyedmgnkbap2x97j6pgum.pdf %me419a4cf32d3a13911848ba208607e2c %ceurocrypt %@Jacques Stern,Philippe Toffin %*Cryptanalysis of a public-key cryptosystem based on approximations by rational numbers %f/eurocrypt/nnfxjye7zdhllamxsvt8rgh3o0udtfbw.pdf %m2c2542fc34fc8f915c62f224cd7dec8c %ceurocrypt %@Paul C. van Oorschot,Michael J. Wiener %*A Known-Plaintext Attack on Two-Key Triple Encryption %f/eurocrypt/qfo3dkoywe64nhwixspftctjeb9nzbdv.pdf %m41aa22ba8557e96229eeaeb6ce191d32 %ceurocrypt %@Shoji Miyaguchi,Kazuo Ohta,Masahiko Iwata %*Confirmation that Some Hash Functions Are Not Collision Free %f/eurocrypt/zbj5unpwsc18efdr9xy2ttvgdl3bkkfs.pdf %m2274d61c4c4f97fd0ca3ec7eed4e75ac %ceurocrypt %@Fritz Bauspieß,Hans-Joachim Knobloch,Peer Wichmann %*Inverting the Pseudo Exponentiation %f/eurocrypt/4zscjx5houdfkgl7dvyfmvnmleu30iaw.pdf %m0cbed22a3bf4eacfdd1e05bcec1e03de %ceurocrypt %@Tzonelih Hwang %*Cryptosystem for Group Oriented Cryptography %f/eurocrypt/glnqrz2ygxa8mql5odtcbx4thimjekra.pdf %m459a9bb19a6a711b8701eee4e58cd565 %ceurocrypt %@Ueli M. Maurer %*A Provably-Secure Strongly-Randomized Cipher %f/eurocrypt/jcbfe78bndkyulqcgdm3nalmzxs19zhx.pdf %m1033a6de1b471a4aaf39b9a1dcb8eff1 %ceurocrypt %@Kaoru Kurosawa,Yutaka Katayama,Wakaha Ogata,Shigeo Tsujii %*General public key residue cryptosystems and mental poker protocols %f/eurocrypt/8g95pianqjowurxz3dvc0lhqo6rtelfy.pdf %m0b6e17ce564ef77f15e61a959ab48ef0 %ceurocrypt %@Xuejia Lai,James L. Massey %*A Proposal for a New Block Encryption Standard %f/eurocrypt/gvmaux7ltcifmqofp9r6kkznw803zqoh.pdf %m793b6261571c2cca4a9338051a98c19f %ceurocrypt %@Valtteri Niemi %*A new trapdoor in knapsacks %f/eurocrypt/bga2tf5izcuqlch4k0rof9mevydznuhs.pdf %maad7324c910f242847abce95358724bc %ceurocrypt %@Alfredo De Santis,Moti Yung %*On the Design of Provably-Secure Cryptographic Hash Functions %f/eurocrypt/yaveurl84twvm0o691cphi23mupnakxn.pdf %m64e828bba55b86b797f310009068db02 %ceurocrypt %@H. Ong,C. P. Schnorr %*Fast Signature Generation with a Fiat Shamir — Like Scheme %f/eurocrypt/1ehmftkcqrr9zdepvoxsbdwmgzby5na0.pdf %m21a208646b9a1f4b7f029fa034da3e42 %ceurocrypt %@Gerrit Bleumer,Birgit Pfitzmann,Michael Waidner %*A Remark on a Signature Scheme Where Forgery can be Proved %f/eurocrypt/p9bevqcj4xsrgiuathxnyklcrbmfo7yp.pdf %m69fb96a804ee41427f51267d231e2099 %ceurocrypt %@Kazuo Ohta,Tatsuaki Okamoto,Kenji Koyama %*Membership Authentication for Hierarchical Multigroups Using the Extended Fiat-Shamir Scheme %f/eurocrypt/mhfwdppulvlq58woczcerq2ai0sgv1sh.pdf %m8073070f9b2a9af6d50564dce43885bc %ceurocrypt %@David Chaum %*Zero-Knowledge Undeniable Signatures (extended abstract) %f/eurocrypt/moyqtpdezf7xs8jbaxqhnucskycig6hv.pdf %m7690ca402b87f2424b770c79c6f06eef %ceurocrypt %@Louis Claude Guillou,Jean-Jacques Quisquater,Mike Walker,Peter Landrock,Caroline Shaer %*Precautions taken against various potential attacks %f/eurocrypt/z4biwqumdky8scs5aw6tlz2oudjaglht.pdf %m75b2b53dc945b272273f4ea0cc180319 %ceurocrypt %@Josep Domingo-Ferrer %*Software Run-Time Protection: A Cryptographic Issue %f/eurocrypt/x4x9s1ztcg3vmuhzc0byfsvwr2oluqqa.pdf %m52404b292d85b6cb1151e42ba6d335ca %ceurocrypt %@Marc Girault %*An identity-based identification scheme based on discrete logarithms modulo a composite number %f/eurocrypt/ulrjf1xiksdkqhv0ylafqb5wzovxm9mg.pdf %md5253c1252ff912d57b7f96053cb78b4 %ceurocrypt %@Jovan Dj. Golic,Miodrag J. Mihaljevic %*A Noisy Clock-Controlled Shift Register Cryptanalysis Concept Based on Sequence Comparison Approach %f/eurocrypt/wf4w6pkv0zotx7ri5uqcujjceilzx1sl.pdf %mae67bf3d930ac7c44cc31da6c038dd39 %ceurocrypt %@Burton S. Kaliski %*The MD4 Message Digest Algorithm %f/eurocrypt/u4x16nk8dyirirpqko7f3thmvyglzcxa.pdf %m055ded6ac1af546c647f3ef36ca6804b %ceurocrypt %@Mike Burmester %*A remark on the efficiency of identification schemes %f/eurocrypt/jhns6129lxywhotor4jtp0ecrugfapfm.pdf %m89e0bc3a159ef816483571ed1e7fbe04 %ceurocrypt %@Gisela Meister %*On an Implementation of the Mohan-Adiga Algorithm %f/eurocrypt/edzui2nwtxw1h6gvrmd39rbb0sluay5o.pdf %m736c3278ebe3d9c8eaf27e9e0cbefddf %ceurocrypt %@Whitfield Diffie %*The Adolescence of Public-Key Cryptography %f/eurocrypt/cymvqnj2pdnozycwth8kti9dgxb5rs1r.pdf %m8ab9689873cf66dbed569b0a0e72f218 %ceurocrypt %@Zvi Galil,Stuart Haber,Moti Yung %*A Secure Public-Key Authentication Scheme %f/eurocrypt/lpo7hdyboa45lufqkevicktt02ynnm9m.pdf %m3e84166f8d173cc8a84c61487bf2aa4a %ceurocrypt %@Gilles Brassard %*How to improve signature schemes %f/eurocrypt/n3i0mbuglsqblhtcxvpp7zwajyawxrf5.pdf %m5459f4bddc4cf46dff1fd90a3f49bcc1 %ceurocrypt %@W. J. Jaburek %*A Generalization of El Gamal’s Public Key Cryptosystem %f/eurocrypt/wdscih1mggwcnjf5kpazs3eoxukyvmph.pdf %m1914d4c067155795d8bd1db29a13cba7 %ceurocrypt %@Christoph G. Günther %*An Identity-Based Key-Exchange Protocol %f/eurocrypt/8tcovad3fx6gnna4owidlbuctrqvkmer.pdf %m05134d78fbd8216f83eefdf5344de864 %ceurocrypt %@Fritz Bauspieß,Hans-Joachim Knobloch %*How to Keep Authenticity Alive in a Computer Network %f/eurocrypt/gxdk7u8sfyevu0mljfrx3tvy4bawgtdn.pdf %m3c8e718114b693678aafbc63664e567c %ceurocrypt %@Hartmut Isselhorst %*The Use of Fractions in Public-Key Cryptosystems %f/eurocrypt/cvbazpb9emtfh5l8jrxf2n7kjtqqiwn4.pdf %m10a7e958eb5074665a85958374198528 %ceurocrypt %@Yair Frankel %*A Practical Protocol for Large Group Oriented Networks %f/eurocrypt/wunyrqcgpvoflznaxiv6wysz5miechta.pdf %m7bda03b08e29b242cd9603ddc5c8d48f %ceurocrypt %@Sheelagh Lloyd %*Counting Functions Satisfying a Higher Order Strict Avalanche Criterion %f/eurocrypt/vz04hmolajqs7wbxti826almer5cqsfo.pdf %mb5fba05b5175bb8e674e691ee296d6fe %ceurocrypt %@George Davida,Yvo Desmedt,René Peralta %*A Key Distribution System Based On Any One-Way Function %f/eurocrypt/vchisydp60dpt5t7xkv8nhm3mjjnfrai.pdf %m01785a21de7b66a3c121fb09d694e136 %ceurocrypt %@Josef P. Pieprzyk %*Non-linearity of Exponent Permutations %f/eurocrypt/hooblnwwazjfs5c4ltvfemraz8meb6qd.pdf %mfa91ac3e094577d7841569c651ab0436 %ceurocrypt %@Andrea Sgarro %*Informational Divergence Bounds for Authentication Codes %f/eurocrypt/bx6fgbmp3ta5zcvrzks7cgndpwhhylyw.pdf %mb69b6c771d070bee78f818bbc483945e %ceurocrypt %@Jean-Jacques Quisquater,Marc Girault %*2n-Bit Hash-Functions Using n-Bit Symmetric Block Cipher Algorithms %f/eurocrypt/z4cjip9seyhdqo8fbyvs2xwfq3hxjwna.pdf %m05d2d5c1451d4ffc91cd7c30a04e11e5 %ceurocrypt %@Stig F. Mjølsnes %*A Simple Technique for Diffusing Cryptoperiods %f/eurocrypt/4nwbgutk6dpqrxtsy3e9cip5z0qgvifm.pdf %mf7deecf1ecdc4d237034a5faa479a1d7 %ceurocrypt %@Mike V. D. Burmester,Fred Piper,Yvo Desmedt,Michael Walker %*A General Zero-Knowledge Scheme %f/eurocrypt/o0vfnha8ewkbo3kx7jdhz5iuqyjuprec.pdf %m136f7bb9a330b17294288af986f7276c %ceurocrypt %@Tatsuaki Okamoto,Kazuo Ohta %*Divertible Zero Knowledge Interactive Proofs and Commutative Random Self-Reducibility %f/eurocrypt/6cwz2eftrmrfsmnsyiituqgg3cnqj4aw.pdf %m44a2793e01adcd54aa00168c4a4ff05d %ceurocrypt %@Claude Crépeau %*Verifiable Disclosure of Secrets and Applications (Abstract) %f/eurocrypt/60ubq74fsy2tjnywrl1j5omfevwxb9vz.pdf %m93498b89db98121e51ea36e3cc927b1a %ceurocrypt %@Joan Boyar,Katalin Friedl,Carsten Lund %*Practical Zero-Knowledge Proofs: Giving Hints and Using Deficiencies %f/eurocrypt/fqxrdnpmicnsi2wzo3uwugl87jhv1e9y.pdf %me76d2eddb8f713b3628f3214f1d2a3bb %ceurocrypt %@Jacques Stern %*An alternative to the Fiat-Shamir protocol %f/eurocrypt/jqi265cmwxb3xdqinlt8kejfagw1fvto.pdf %m82c92429396529ca9973b19a5853534d %ceurocrypt %@Gilles Brassard,Claude Crepeau %*Sorting out zero-knowledge %f/eurocrypt/kt2ipruboejugaecqdh4yhl7vqdyj0ra.pdf %m9f4bae53b7304606de45fa941eb276c5 %ceurocrypt %@Gilles Brassard,Claude Crépeau,Moti Yung %*Everything in NP can be argued in perfect zero-knowledge in a bounded number of rounds %f/eurocrypt/svdqyax41fichbjk05c38y7meietumpz.pdf %m09fcac9df1f1648d7cb6587244784d3b %ceurocrypt %@Moti Yung %*Zero-Knowledge Proofs of Computational Power %f/eurocrypt/op3imt1hdigvjvqkhoexcsanwzyn5cr6.pdf %mde3c0a2431dc5f90f7712fb8b3b024b1 %ceurocrypt %@Bert den Boer %*More Efficient Match-Making and Satisfiability The Five Card Trick %f/eurocrypt/mhmri90jzhtsk6gcx4abzny1ldvvo2o8.pdf %mee4faac6e2a36894b98673411de15aa0 %ceurocrypt %@André Vandemeulebroecke,Etienne Vanzieleghem,Tony Denayer,Paul G. A. Jespers %*A Single Chip 1024 Bits RSA Processor %f/eurocrypt/evi0q4jvdzipwru7ukjq9ybwplfrn3ba.pdf %m2c73b84dfc74217a1749820e6aa178a0 %ceurocrypt %@Hedwig Cnudde %*Cryptel - The Practical Protection of an Existing Electronic Mail System %f/eurocrypt/nzfcytsxmmw2gjh0rxd7btg9wer1qk63.pdf %mdcc7be713c6e9e1fd5579db9aa241012 %ceurocrypt %@Jan Van Auseloos %*Technical Security: The Starting Point %f/eurocrypt/zwfddhik0iwvaxy7evhgqu9e6m1lmgz5.pdf %m79f338b6f999061490252747f1f78b4c %ceurocrypt %@Charles Siuda %*Security in Open Distributed Processing %f/eurocrypt/f2r9wxabej0ozwlxhmuksz4cdl65oqdy.pdf %m31f32b7ffd0f130b83693d5826c6309b %ceurocrypt %@J. Vandewalle,D. Chaum,W. Fumy,C. Jansen,P. Landrock,G. Roelofsen %*A European Call for Cryptographic Algorithms: Ripe; Race Integrity Primitives Evaluation %f/eurocrypt/kc2bvzt4ywaedn8v760fojog15rpmhle.pdf %md1d21e4ad763dd08f9609f6972bf2843 %ceurocrypt %@Mireille Antoine,Jean-François Brakeland,Marc Eloy,Yves Poullet %*Legal Requirements Facing New Signature Technology %f/eurocrypt/hxuhmnwtr7cma1uzvc25ye0bpdz9kqeg.pdf %m0ae0badc0fed4f5744929c12c452121a %ceurocrypt %@David Chaum %*Online Cash Checks %f/eurocrypt/qa1junx8xlkg2l7vgfpkz9i0tnjhoiob.pdf %mbbd6a362c07409d30f2ec8a092f21a7c %ceurocrypt %@David Chaum,Bert den Boer,Eugène van Heyst,Stig Mjølsnes,Adri Steenbeek %*Efficient Offline Electronic Checks %f/eurocrypt/djilrpwtjzqab6yet0ogzvo5dceufli1.pdf %m900e3ccd8a253afb2b87b9093430fdc5 %ceurocrypt %@Michael Waidner %*Unconditional Sender and Recipient Untraceability in Spite of Active Attacks %f/eurocrypt/rzb51vvzoi96gfsgmntkj2xhy8pqwdlu.pdf %m87d0bcc793f2737eeae07101d2457724 %ceurocrypt %@Jurjen Bos,Bert den Boer %*Detection of Disrupters in the DC Protocol %f/eurocrypt/zdrl4nda0gwnuzmytrsbkqqcx5olg2ev.pdf %me7863a8580f78c53cb0510c2f1865216 %ceurocrypt %@Philippe Flajolet,Andrew M. Odlyzko %*Random Mapping Statistics %f/eurocrypt/vypkmvtageel3shmc4wzpjh7d2xaq5du.pdf %m9ef6e167e21ae31b1430172c238bb176 %ceurocrypt %@Arjen K. Lenstra,Mark S. Manasse %*Factoring by electronic mail %f/eurocrypt/qjblngtbcaon2or1hh93wipdymuvk4sf.pdf %m8a9108d13621aea16d722094615cb567 %ceurocrypt %@Michael J. Wiener %*Cryptanalysis of Short RSA Secret Exponents %f/eurocrypt/ep8s9auldcvtaswjy6ronxfd0cblmjqe.pdf %m44309292b4f8e216bb8c0a1c69375485 %ceurocrypt %@Birgit Pfitzmann,Andreas Pfitzmann %*How to Break the Direct RSA-Implementation of Mixes %f/eurocrypt/duzcob4kvnsipgl0erzc5mafqkhyt9w6.pdf %m0e499b5d8f3e09c7113c8744a48b67ae %ceurocrypt %@Hakon N. Jendal,Yves J. B. Kuhn,James L. Massey %*An Information-Theoretic Treatment of Homophonic Substitution %f/eurocrypt/5t2kucpwosy9rmlrqmvnsxiikbzb6f4j.pdf %md30541ddb38476672e309ed8c325a121 %ceurocrypt %@Peer Wichmann %*Cryptanalysis of a Modified Rotor Machine %f/eurocrypt/ivxuz0yvshgoqyt5p1cktnwbilhfzlae.pdf %m21a54d8d08233ba6b47701d6e718554b %ceurocrypt %@Michael Bertilsson,Ernest F. Brickell,Ingemar Ingemarsson %*Cryptanalysis of Video Encryption Based on Space-Filling Curves %f/eurocrypt/aus4dke0rf9uxlkmq3q58wpynacmeiit.pdf %m0e17f9443430cad09afdf40289f57471 %ceurocrypt %@Yuliang Zheng,Tsutomu Matsumoto,Hideki Imai %*Impossibility and Optimality Results on Constructing Pseudorandom Permutations %f/eurocrypt/ftecm5knwde1ptrq9kzib6adapxuowv3.pdf %maa3cbf47c0c94b002b6e728106a1e2f5 %ceurocrypt %@Rainer A. Rueppel %*On the Security of Schnorr’s Pseudo Random Generator %f/eurocrypt/jvseqebczitg3rhfuyv7gldan8n96zdc.pdf %m724d91c0a357857f1f7f497d9e8e28a3 %ceurocrypt %@Jean-Jacques Quisquater,Jean-Paul Delescaille %*How easy is collision search? Application to DES %f/eurocrypt/uf9gskjxesboxzytnzrvh2ivpgcbf6ae.pdf %mabe21686d9fdac36ea88ba2d501ea250 %ceurocrypt %@Gustavus J. Simmons %*Prepositioned Shared Secret and/or Shared Control Schemes %f/eurocrypt/jpweemftwhrsofa0vcq51mznbq9ujpad.pdf %mb3f0c8dcf710447943039e21af652482 %ceurocrypt %@Ernest F. Brickell %*Some Ideal Secret Sharing Schemes %f/eurocrypt/4f9a8wjo165ttoxd3huuegdbspvqgiws.pdf %m26b8274f82e025ac3fc49cf63a40ccc7 %ceurocrypt %@M. De Soete,K. Vedder,M. Walker %*Cartesian Authentication Schemes %f/eurocrypt/ipjfdwlu1vnoxt97iknoreqsfelxyqzs.pdf %m73d37f66440341da34d64a83e68bb237 %ceurocrypt %@Albrecht Beutelspacher %*How to Say “No” %f/eurocrypt/t6yy384xg2zfkbihigcxkvespcjeq1fl.pdf %ma4b36f6d33752636a4eaa81396935b38 %ceurocrypt %@Philippe Godlewski,Chris Mitchell %*Key Minimal Authentication Systems for Unconditional Secrecy %f/eurocrypt/eol6yrgn74uatmtokhds0pkr1bjav5db.pdf %m1af90f9cefdd7b7318e78bfedd66ec65 %ceurocrypt %@Christoph G. Günther %*Parallel Generation of Recurring Sequences %f/eurocrypt/mjzn4h6lfzrouwctu7qy2t89bp5yf3vv.pdf %m12f34dbf536e57bbebaaf08efc8765b9 %ceurocrypt %@Harald Niederreiter %*Keystream Sequences with a Good Linear Complexity Profile for Every Starting Point %f/eurocrypt/0fzp2qcmextguq9juz8emsy6vw1bofdc.pdf %m7b599460e92cf7f7666f3fbf003d01d3 %ceurocrypt %@Thomas Beth,Zong-Duo Dai %*On the Complexity of Pseudo-Random Sequences - or: If You Can Describe a Sequence It Can’t be Random %f/eurocrypt/g40yj5tx6wa8eomizpjrso9qcrlqtz1n.pdf %m6e98cb366e3b463c105e25fc500dac0f %ceurocrypt %@Z. D. Dai,K. C. Zeng %*Feedforward Functions Defined by de Bruijn Sequences %f/eurocrypt/jzvfpc7vqeiyqdwxa4r3t8b1bk5mihd9.pdf %mc7019cec49661722e58388cf53aa279a %ceurocrypt %@Willi Meier,Othmar Staffelbach %*Nonlinearity Criteria for Cryptographic Functions %f/eurocrypt/wf4iutj0addswk5z91pporlfvxl2byeq.pdf %m5331eceef52af469352d089929b1212b %ceurocrypt %@A. H. Chan,M. Goresky,A. Klapper %*On the Linear Complexity of Feedback Registers %f/eurocrypt/xylp09vaypf5rohfwskzlb4nct3umatu.pdf %mfdd334b6abfae0cd5cf25aad1a5d4025 %ceurocrypt %@Muzhong Wang %*Linear Complexity Profiles and Continued Fractions %f/eurocrypt/hzjedyl5fmsy9wke0uocfmuwhrvcogi7.pdf %m3b8904b44438d8fae85dfbdb4381cbcd %ceurocrypt %@Réjane Forré %*A Fast Correlation Attack on Nonlinearly Feedforward Filtered Shift-Register Sequences %f/eurocrypt/qyej9nwtwgzc4skim1t7hb3kohmxs2ua.pdf %m7a8df623335a6215eb7f50d13bdd9188 %ceurocrypt %@Johannes A. Buchmann,Stephan Düllmann,Hugh C. Williams %*On the Complexity and Efficiency of a New Key Exchange System %f/eurocrypt/5s7coaxrbqhvjgayt4lebpqdcnigjfkm.pdf %mfef36b837f071dce88a076fb4ce665c4 %ceurocrypt %@Colin Boyd %*A New Multiple Key Cipher and an Improved Voting Scheme %f/eurocrypt/zbkhlujs8p9g3j6lhmysa7cqn5ct1mvi.pdf %m6ae2a9e2df6ec632bedca1a312d29e99 %ceurocrypt %@François Morain %*Atkin’s Test: News from the Front %f/eurocrypt/h46g1dz0yhkfovju9t2mmbtucibqrsle.pdf %m879db09ebed0ffa056051680a291a2d3 %ceurocrypt %@Ueli M. Maurer %*Fast Generation of Secure RSA-Moduli with Almost Maximal Diversity %f/eurocrypt/voqbz3irjje59nuadkktc0gxsrl6ltwg.pdf %m650b9e584cbed90d553c775b14923752 %ceurocrypt %@Yves Duhoux %*Deciphering Bronze Age Scripts of Crete The Case of Linear A %f/eurocrypt/jxcyialh2xepsjzfdy9i1rmf7vtb8nd6.pdf %m246af50098e563979b9271f285dccfe1 %ceurocrypt %@Wieb Bosma,Marc-Paul van der Hulst %*Faster Primality Testing %f/eurocrypt/qf9ibrm41e70ijslcqvpzpogydknhnba.pdf %mb08149807d04de6f8b2a42b9cb134278 %ceurocrypt %@Tzonelih Hwang,T. R. N. Rao %*Private-Key Algebraic-Code Cryptosystems with High Information Rates %f/eurocrypt/ennro6v5iu2by371rmjxqghpbewsctoj.pdf %m97cbf5f5f40d457a18887ff7d212e363 %ceurocrypt %@Jean-Jacques Quisquater,André Bouckaert %*Zero-knowledge procedures for confidential access to medical records %f/eurocrypt/pzkorjoi67ewq3thgxmjs2yqhmzclse4.pdf %m79782923999d330980bf42d7e668f4fa %ceurocrypt %@Josep Domingo i Ferrer,Llorenç Huguet i Rotger %*Full Secure Key Exchange and Authentication with no Previously Shared Secrets %f/eurocrypt/kqmydfn2s4g5u3aqvw9rmlejigiwfuyc.pdf %m91f503f578ef887b1903c3f28a2e7a9c %ceurocrypt %@Yves Roggeman %*Varying Feedback Shift Registers %f/eurocrypt/jbmnyvfq43s7da96pusrozdhx8lktoey.pdf %m932a464f9e2aead294ed652d0a71cc11 %ceurocrypt %@Dieter Gollmann,William G. Chambers %*A Cryptanalysis of Stepk,m-Cascades %f/eurocrypt/vw1vjbmzysamq5e8trctsca0kfhnxyd9.pdf %ma0beb9740b7ef07f55b15652715e5e48 %ceurocrypt %@C. P. Schnorr %*Efficient Identification and Signatures for Smart Cards %f/eurocrypt/r9uurvbqls8zbinjx3im0p2p7aavco5e.pdf %mec7845231be9256088a891fa7891f41e %ceurocrypt %@Michael Waidner,Birgit Pfitzmann %*The Dining Cryptographers in the Disco: Unconditional Sender and Recipient Untraceability with Computationally Secure Serviceability %f/eurocrypt/fa4oglnqvtkwmez7ciusrokdqsxc52j0.pdf %m7f087861bfebfbcf07bd608542a3a022 %ceurocrypt %@Glyn Carter %*Some Conditions on the Linear Complexity Profiles of Certain Binary Sequences %f/eurocrypt/znu2ofhemjg4wyol5uybxi16emrcrp0v.pdf %m890d98bb235991656286a577603eb119 %ceurocrypt %@Lawrence Brown,Jennifer Seberry %*On the Design of Permutation P in des Type Cryptosystems %f/eurocrypt/pmif13r0cbdehvo8xhlqzoy6wkggnaev.pdf %m7b5233442d048053757cbbf4102fc090 %ceurocrypt %@G. B. Agnew,R. C. Mullin,S. A. Vanstone %*A Fast Elliptic Curve Cryptosystem %f/eurocrypt/icauzd7sadmih1yfwge6xlbobcylt9e2.pdf %mffc348362ff1bad7e282c568455b1a56 %ceurocrypt %@Rainer A. Rueppel %*Key Agreements Based on Function Composition %f/eurocrypt/jfz6urf5nau8opvjm7g2y4wmhbgakxte.pdf %m4e3992a313298f067f57ae92f7b6f0a5 %ceurocrypt %@Kenji Koyama,Kazuo Ohta %*Security of Improved Identity-based Conference Key Distribution Systems %f/eurocrypt/sjr8ptcwdeebcz376g2boqqnomhyfp1k.pdf %m9c3ad434740a2e407df043d6e2f0dbb8 %ceurocrypt %@Yvo Desmedt %*Subliminal-free Authentication and Signature %f/eurocrypt/2vrstscduxchri4jn3tiq0q7y9zumekh.pdf %m911718870e4ab3f302cfccfa40428fa6 %ceurocrypt %@Gustavus J. Simmons,George B. Purdy %*Zero-Knowledge Proofs of Identity and Veracity of Transaction Receipts %f/eurocrypt/ocdjkndqf8ura2bgu1zwchvxk6xzyh7m.pdf %m22a8037b88e370b45b56ce58faef6e74 %ceurocrypt %@Ernest F. Brickell,Doug R. Stinson %*Authentication Codes with Multiple Arbiters %f/eurocrypt/ojuxm10qknh7suzitplwd2hxmc6vygy3.pdf %m56e8d64d659baee1e5948f7df08c280b %ceurocrypt %@Marijke De Soete %*Some Constructions for Authentication - Secrecy Codes %f/eurocrypt/apqebosi2dwxvhpmkhnzoyvgkfc8cxdm.pdf %md131474e9fb70c0e783d8955d46e6276 %ceurocrypt %@Thomas Beth %*Efficient Zero-Knowledge Identification Scheme for Smart Cards %f/eurocrypt/rhcnyaphuzwgaxooiimqr9xwlckdm40y.pdf %m29cac6b2ca1b4f90ebac41c297b17f23 %ceurocrypt %@Hans-Joachim Knobloch %*A Smart Card Implementation of the Fiat-Shamir Identification Scheme %f/eurocrypt/ohlynfk7jatfxltwh5ui3cvwqid2zkbm.pdf %m4baebf000d0d5c359c40f3b6aed0d40d %ceurocrypt %@Ph. Godlewski,P. Camion %*Manipulations and Errors, Detection and Localization %f/eurocrypt/xzn48je93dlcbiqvjivcfoesdpz2nm0w.pdf %m12d32c5c52a610d96d2e3c4d5a1a31f6 %ceurocrypt %@Svein J. Knapskog %*Privacy Protected Payments — Realization of a Protocol That Guarantees Payer Anonymity %f/eurocrypt/d9mjzq637sf5is0crecfbgdguwhlnbph.pdf %m6c932453ea0ba56b65db9af13342abca %ceurocrypt %@Louis C. Guillou,Jean-Jacques Quisquater %*A Practical Zero-Knowledge Protocol Fitted to Security Microprocessor Minimizing Both Transmission and Memory %f/eurocrypt/nvit7acrw34ol8pqgoepx9qizvdflght.pdf %m672d0bd14c6908c1a058d967a41b9acd %ceurocrypt %@Marc Girault,Robert Cohen,2)Mireille Campana %*A Generalized Birthday Attack %f/eurocrypt/x67t2du0dlgiegt3puvm9crqqnvfbywy.pdf %mab1f5df67e4ae91b97b4c974ad1b12ed %ceurocrypt %@G. Agnew,R. Mullin,S. Vanstone %*An Interactive Data Exchange Protocol Based on Discrete Exponentiation %f/eurocrypt/heodbbotg1jshaz3yxmykvf72zuqw5gs.pdf %mc37726c6c02423bf7f4f4edab074435b %ceurocrypt %@Jørgen Brandt,Ivan Bjerre Damgård,Peter Landrock %*Anonymous and Verifiable Registration in Databases %f/eurocrypt/wjluk3f8b40dumk7wcafoteet5gjdxiz.pdf %m3dec503588adccb7e3097c217d818427 %ceurocrypt %@David Chaum %*Elections with Unconditionally-Secret Ballots and Disruption Equivalent to Breaking RSA %f/eurocrypt/zwlyvpn9aatqkjhhpk1liwemxfo4jcbu.pdf %mec016b652cf1b22e818dd9523178a15c %ceurocrypt %@George I. Davida,Yvo G. Desmedt %*Passports and Visas Versus IDs %f/eurocrypt/7yxfwhq1i8afexuv59dzlewjnb0irtnr.pdf %m812d71860e91a70544dbbe57329a1762 %ceurocrypt %@Harald Niederreiter %*The Probabilistic Theory of Linear Complexity %f/eurocrypt/auxghmyancfzekjgcbrfvt5du691l80z.pdf %m9ecc0c139c64b5a75722c5b45701f384 %ceurocrypt %@Adina Di Porto,Piero Filipponi %*A Probabilistic Primality Test Based on the Properties of Certain Generalized Lucas Numbers %f/eurocrypt/v5zaxp6ntf9wucgxgrdlkn3siy7co4qb.pdf %mbedd45982ca29a761c22b928fcc501c5 %ceurocrypt %@C. P. Schnorr %*On the Construction of Random Number Generators and Random Function Generators %f/eurocrypt/46cebenciaz2ak3v7sl1idlwydmpz5qm.pdf %m2ec3c0bfc7dc4413c7a3ffdae15e4696 %ceurocrypt %@James A. Davis,Diane B. Holdridge %*Factorization of Large Integers on a Massively Parallel Computer %f/eurocrypt/pam1cuvsdeqlgctvi5jn48ibxzlrwexo.pdf %m0b5a36cca739f73e88ab5c587911cfeb %ceurocrypt %@Shin-ichi Kawamura,Kyoko Hirano %*A Fast Modular Arithmetic Algorithm Using a Residue Table %f/eurocrypt/sbox83tfsa2zikry7t1rol9z4gq0cbgi.pdf %mffaa234afa8f29aa74cc7bea46ce762b %ceurocrypt %@G. B. Agnew,R. C. Mullin,S. A. Vanstone %*Fast Exponentiation in GF(2n) %f/eurocrypt/fby8hyoi0ac2jr6xo1elmu57kxe3rlpv.pdf %mcb861fac4767691ddb127391405b124e %ceurocrypt %@Frank Hoornaert,Marc Decroos,Joos Vandewalle,René Govaerts %*Fast RSA-Hardware: Dream or Reality? %f/eurocrypt/g45tren0vnhvkshscjm93t2ijbcdimbu.pdf %m2afd80f240d69ca17b15dd66feb30a57 %ceurocrypt %@Raouf N. Gorgui-Naguib,Satnam S. Dlay %*Properties of the Euler Totient Function Modulo 24 and Some of Its Cryptographic Implications %f/eurocrypt/yugu5heo6zjsnzhcbqmirkxtvtgo9epc.pdf %m334732dd9e282c250ba07bed4082afbb %ceurocrypt %@P. J. Lee,E. F. Brickell %*An Observation on the Security of McEliece’s Public-Key Cryptosystem %f/eurocrypt/6e74k3ctcxjzmfhfaxpzwynbrudibjq1.pdf %ma89be436192174b5c0312c6f2c823dbc %ceurocrypt %@Brigitte Vallée,Marc Girault,Philippe Toffin %*How to Break Okamoto’s Cryptosystem by Reducing Lattice Bases %f/eurocrypt/6bzijgvkt5c4juqtusma8iyerclwbaen.pdf %m4068f6da4efd09f4367ff222d15c8e95 %ceurocrypt %@Bert den Boer %*Cryptanalysis of F.E.A.L. %f/eurocrypt/0qvsrzptc8fajepkuy9gdim4qarc6l5d.pdf %m3ad4095b1e36da9a81bd8280c8449af6 %ceurocrypt %@Willi Meier,Othmar Staffelbach %*Fast Correlation Attacks on Stream Ciphers %f/eurocrypt/v6ricqdyvktbkts8rdeqejhbzsaycl5f.pdf %mc0176082b36c70088dd30ea96f02c6e3 %ceurocrypt %@Shu Tezuka %*A New Class of Nonlinear Functions for Running-key Generators %f/eurocrypt/ocsogu92qfiwqmz7udkwxayscrfplaee.pdf %m8a2a073519c2ac2a7c8afb9839a793ef %ceurocrypt %@B. J. M. Smeets,W. G. Chambers %*Windmill Generators A generalization and an observation of how many there are %f/eurocrypt/qtrbvojz5xaxs6y3cupky1vozsdjwrf2.pdf %m85e255f73a01bfd852a0dd892528a167 %ceurocrypt %@William G Chambers,Dieter Gollmann %*Lock-in Effect in Cascades of Clock-Controlled Shift-Registers %f/eurocrypt/a0ztgquvhk1ma6bp4wejeig2nfdri8sc.pdf %mdb9eaa61c0445244d71aa63f0a1ebdfc %ceurocrypt %@Cunsheng Ding %*Proof of Massey’s Conjectured Algorithm %f/eurocrypt/bghuoptrxckf4yeljgmuqts7iddanba0.pdf %m3095fce310875302aa361d761e38102b %ceurocrypt %@Dongdai Lin,Mulan Liu %*Linear Recurring m-Arrays %f/eurocrypt/awxyw1friudquhs7ygltobtfpvpxskne.pdf %mc1360f63d7021d4504bec32f32979547 %ceurocrypt %@Eiji Okamoto %*Substantial Number of Cryptographic Keys and Its Application to Encryption Designs %f/eurocrypt/tzrq3e1sf80iibx5u2luheancj9phycj.pdf %m96f67906a91e3593b64eaa54489e91bd %ceurocrypt %@Andrea Sgarro %*A Measure of Semiequivocation %f/eurocrypt/jp9s3bt7yxquanxhdcevzgm4iliafkzs.pdf %m9e30a52f0decb59f46440c93abd5ebcd %ceurocrypt %@Marijke De Soete,Klaus Vedder %*Some New Classes of Geometric Threshold Schemes %f/eurocrypt/ezdjyrq9vvi7srw42tucmspg3f0glwyb.pdf %m2d47991a6c67308a736efca852880e80 %ceurocrypt %@Christoph G. Günther %*A Universal Algorithm for Homophonic Coding %f/eurocrypt/tqx236upieajztab0r9bvqwnsflo4hwm.pdf %mb5f13cbc3ea2a48f971ca27448ed0455 %ceurocrypt %@Tsutomu Matsumoto,Hideki Imai %*Public Quadratic Polynomial-Tuples for Efficient Signature-Verification and Message-Encryption %f/eurocrypt/mewlogqcram3oxszxdbpufiqpsvw6b5v.pdf %mcc345632670f39bd419bc720d91e487c %ceurocrypt %@Colin Boyd %*Some Applications of Multiple Key Ciphers %f/eurocrypt/wzk9exg0l5ivj3wdjiy4v2taqhykf7db.pdf %md317e96e2acf7b218589982d80db710c %ceurocrypt %@James L. Massey %*In Memoriam Tore Herlestam (1929–1986) %f/eurocrypt/57pubcok2pi3fejvgqhdxxmjcsvtz0o6.pdf %md2342e5604935077e778e2f34c36585e %ceurocrypt %@C. G. Günther %*Alternating Step Generators Controlled by De Bruijn Sequences %f/eurocrypt/rehvuccn3xlxeglm2zatzyjdq9d8k6i1.pdf %m06fe778c81b26be74fc52f93e7af3fa1 %ceurocrypt %@Thomas Siegenthaler,Réjane Forré,Amstein Walthert Kleiner %*Generation of Binary Sequences with Controllable Complexity and Ideal r-Tupel Distribution %f/eurocrypt/uludpx8yr5v3ipfqlktmcjzd1qi4bazo.pdf %m90ba7c13597a29566c6c7c19602821e3 %ceurocrypt %@Sibylle Mund,Dieter Gollmann,Thomas Beth %*Some Remarks on The Cross Correlation Analysis of Pseudo Random Generators %f/eurocrypt/lyipvysnukfdrj0kc9mlizzaow4pgren.pdf %m0b37cfdd624c7327706dec2da8bc82e2 %ceurocrypt %@Harald Niederreiter %*Sequences with Almost Perfect Linear Complexity Profile %f/eurocrypt/cnkrdbpkjp1zd0lfuvo7fwea2t6jn35s.pdf %m3b71dea569347e27c958bc4d0bb13db1 %ceurocrypt %@Rainer A. Rueppel %*When Shift Registers Clock Themselves %f/eurocrypt/itnba31fmmgv6yhcn2kxleoestjpowd9.pdf %maefbd76046bd7ba1415a1dc6e65639b4 %ceurocrypt %@Franz Pichler %*Finite State Machine Modelling of Cryptographic Systems in Loops %f/eurocrypt/onpygzjnlrmrc30z5t4uesxewypgmwuh.pdf %m260500926649b19fa361c367a6eaa3ae %ceurocrypt %@G. B. Agnew %*Random Sources for Cryptographic Systems %f/eurocrypt/b62exlzojpwkhme145fysz9cgdhunq3s.pdf %me0b6f132034364805dc783ebeeffb0df %ceurocrypt %@Andrew J. Clark %*Physical Protection of Cryptographic Devices %f/eurocrypt/2zfqyjnplkj8te6hm1ocusmcgwv3dxri.pdf %m1d60ef35030b95cb3169c6bf2b8f254b %ceurocrypt %@Holger Sedlak %*The RSA Cryptography Processor %f/eurocrypt/xgq1neb9sewhpi3cq7a2usz0h4vwyrvk.pdf %m550a0f3f15863c0efa931bcae720b11c %ceurocrypt %@F. Jorissen,J. Vandewalle,R. Govaerts %*Extension of Brickell’S Algorithm for Breaking High Density Knapsacks %f/eurocrypt/qt1kaalfrrw0dhpn6yfuei7bz4lidmbc.pdf %m316b4fd146f472248c474c9e2ce42d01 %ceurocrypt %@Ernest F. Brickell,Yacov Yacobi %*On Privacy Homomorphisms (Extended Abstract) %f/eurocrypt/jflbh5gvert76qip4ydxziw9xwktaqfr.pdf %m3df48b6448c4fb474591e4c7b80faeb1 %ceurocrypt %@David Chaum,Jan-Hendrik Evertse,Jeroen van de Graaf %*An Improved Protocol for Demonstrating Possession of Discrete Logarithms and Some Generalizations %f/eurocrypt/hp7ybaugixg18tolrj3pnzm2mwi5xbsl.pdf %md4a1ee427f83c48c0226e58a3e9cf5ea %ceurocrypt %@George I. Davida,Gilbert G. Walter %*A Public Key Analog Gyptosystem %f/eurocrypt/pztftxwqylxieg95knjrvamhapbnh63m.pdf %m1cb16620aeec2b0fc84c7976069a6299 %ceurocrypt %@Gustavus J. Simmons %*Message Authentication with Arbitration of Transmitter/Receiver Disputes %f/eurocrypt/uhdgjcgt4w3koymxihxrzmpbcfnto521.pdf %md627ed837a905636cee847a3c895a87a %ceurocrypt %@Albrecht Beutelspacher %*Perfect and Essentially Perfect Authentication Schemes %f/eurocrypt/ek3qzrmxcvhcteupjsd8l7w1mao46dhy.pdf %mecc168f22c14a2d6bd17fe16d5091c69 %ceurocrypt %@H J Beker,G. M Cole %*Message Authentication and Dynamic Passwords %f/eurocrypt/f2s9wepl1kf4q8agpvgew7acdiozhsn5.pdf %m91f030389f5047b2f0b4d96124e56588 %ceurocrypt %@I. Schaumüller-Bichl %*IC-Cards in High-Security Applications %f/eurocrypt/2rvfqk5le8bg1uchx40misy9zo3pnpcd.pdf %mc667aaac1334243c77a86342d004cab9 %ceurocrypt %@Ivan Bjerre Damgård %*Collision Free Hash Functions and Public Key Signature Schemes %f/eurocrypt/mjp0ua3cyfvirp5gozb19bdskcjftman.pdf %mab1832cc8eacb0a837ee8879b5d466ac %ceurocrypt %@Marc Girault %*Hash-Functions Using Modulo-N Operations %f/eurocrypt/gzrcj4ewvrokj8mdopziyhstf1seh0id.pdf %m907db58860877644924faa49d7833c01 %ceurocrypt %@David Chaum %*Blinding for Unanticipated Signatures %f/eurocrypt/bgten2unhivye7mk1psrqyfljgikxd53.pdf %mb1145b7883055da7799e910a06c8ff5d %ceurocrypt %@James L. Massey,Ueli Maurer,Muzhong Wang %*Non-Expanding, Key-Minimal, Robustly-Perfect, Linear and Bilinear Ciphers %f/eurocrypt/hvdnprcaq238nw0x1kejzmllbhguozar.pdf %m606c14b4801bdc69b30edc4a5a32b519 %ceurocrypt %@Jan-Hendrik Evertse %*Linear Structures in Blockciphers %f/eurocrypt/gmdslzxp4wktx5b6g1wscjozfy2rj07v.pdf %m0f1c0c37f315116f06c1bc27df7fe8ee %ceurocrypt %@Akihiro Shimizu,Shoji Miyaguchi %*Fast Data Encipherment Algorithm FEAL %f/eurocrypt/yog0caqsvfsth2mkdojzceiapl4x1j5w.pdf %m73b54fdf0b43b64a72eb38d7d640bcad %ceurocrypt %@Cees J. A. Jansen,Dick E. Boekee %*Modes of Blockcipher Algorithms and Their Protection Against Active Eavesdropping %f/eurocrypt/6ohcspyqo5alkzuxmefbwpqwyv1titk2.pdf %m0a5812ae2612ac194977bebaf9837200 %ceurocrypt %@Ingrid Verbauwhede,Frank Hoornaert,Joos Vandewalle,Hugo De Man %*Security Considerations in the Design and Implementation of a new DES chip %f/eurocrypt/bmeg3fpovkijwykdcanuyhuh1zwz4in6.pdf %m632b51c142b6f289d2517f2c5d6ff435 %ceurocrypt %@David P. Anderson,P. Venkat Rangan %*High-Performance Interface Architectures for Cryptographic Hardware %f/eurocrypt/yskoluzxfhj4jaxb0t3pedgpkfyq8umh.pdf %m0a12670668efa0c9ec6bf30a4b511fd0 %ceurocrypt %@Otto J. Horak %*The Contribution of E.B. Fleissner and A. Figl for Today’s Cryptography %f/eurocrypt/9gzupqr8rd6wfepsoeimxbhkyzivj3v0.pdf %m9565169d25c135745a08b0bb60486988 %ceurocrypt %@Ronald L. Rivest,Adi Shamir %*Efficient Factoring Based on Partial Information %f/eurocrypt/ugwitcsfcple2gh5edqnjvhuzz0fmmkx.pdf %m74bd553852d6f9d3e0d863aae004c9de %ceurocrypt %@Harald Niederreiter %*A Public-Key Cryptosystem Based on Shift Register Sequences %f/eurocrypt/6xgqfaewxljvgr4qp1thszimpcevw3zc.pdf %mc924dc9874ec2ebe25341c4de696ab16 %ceurocrypt %@Bernard Smeets %*A Comment on Niederreiter’s Public Key Cryptosystem %f/eurocrypt/i6sftjxhftnqde4gz1bqew7iaugsv2rl.pdf %m5dc62abe5aee9e5992ce201d8dd89043 %ceurocrypt %@J. Vandewalle,R. Govaerts,W. De Becker,M. Decroos %*Implementation Study of Public Key Cryptographic Protection in an Existing Electronic Mail and Document Handling System %f/eurocrypt/ablrxrvmeshz3x52d8cf7noguvpamg9w.pdf %mc6d72a1aae9f2aa4ca78d9d42d1c00f6 %ceurocrypt %@Winfried B. Müller,Rupert Nöbauer %*Cryptanalysis of the Dickson-Scheme %f/eurocrypt/z4kvpnquokmmgxwyju9vqs15bi2hczyw.pdf %m014d3b95663dbb4836d6148079d731e2 %ceurocrypt %@René Peralta %*Simultaneous Security of Bits in the Discrete Log %f/eurocrypt/bp81dg5i4xmjhodfyabzlu0npjqg36ve.pdf %me1d9c7f6d6a047fef8d78c8e228c2f10 %ceurocrypt %@Józef P. Pieprzyk %*On Public-Key Cryptosystems Built Using Polynomial Rings %f/eurocrypt/xrkovheahw2sk8vyr03nqgbco4azl1tu.pdf %m613f8902acb07fc7de7144e5d2e6ff10 %ceurocrypt %@Burton S. Kaliski,Ronald L. Rivest,Alan T. Sherman %*Is the Data Encryption Standard a Group? (Preliminary Abstract) %f/eurocrypt/9brcmduyiynmwcjpzuofd5sgp4k3z1vx.pdf %me95163fa5fc07374d7d07db3b71f9e05 %ceurocrypt %@Henk Meijer,Selim Akl %*Two New Secret Key Cryptosystems %f/eurocrypt/gkfgndyehrfuuxidn5ircab7vme2ljp3.pdf %m9811f4e5cc4425b2c46224dc5f77aa87 %ceurocrypt %@T. Siegenthaler %*Cryptanalysts Representation of Nonlinearly Filtered ML-Sequences %f/eurocrypt/gqblphajvxar746vmsktc5b9fcisri3k.pdf %mdace77b9ec6a11025b18baaf9a0ea335 %ceurocrypt %@Philippe Godlewski,Gérard D. Cohen %*Authorized Writing for “Write-Once” Memories %f/eurocrypt/z4nfcsqo63cjxrsedjrphklwz1bgdm2x.pdf %m13283a95936c47aa7e113f8a2001a9fe %ceurocrypt %@Tore Herlestam %*On Functions of Linear Shift Register Sequences %f/eurocrypt/ipftaz9chblmnnyqrzjkgbeslqv6maj0.pdf %m0a39d96b07bc94dc8e3fb04868fa4094 %ceurocrypt %@Dong-sheng Chen,Zong-duo Dai %*On Feedforward Transforms and p-Fold Periodic p-Arrays %f/eurocrypt/qyohwfk6wyuvqxr0t8jxbzf14nmdrh3i.pdf %m0ef6650b4e946ac647fafe9ff0f3cc1f %ceurocrypt %@Mu-Lan Liu,Zhe-xian Wan %*Generalized Multiplexed Sequences %f/eurocrypt/0vdfcxwhdztwsvqu3gleknjm8zghx4pb.pdf %m8a89b51b8549e7b60c113fa6fbf86b55 %ceurocrypt %@Bernard Smeets %*A Note on Sequences Generated by Clock Controlled Shift Registers %f/eurocrypt/rauv0ykaqbqej6d1us74hbg5xcmkrjmn.pdf %m9f2dfbbc373f4dc39ad4f9246b036bbf %ceurocrypt %@Neal R. Wagner,Paul S. Putter,Marianne R. Cain %*Using Algorithms as Keys in Stream Ciphers %f/eurocrypt/hpuzsxyhggwzxrioipn4fm5qcayeqdb6.pdf %mb6764b3bcb0f67045faeb4dceaf4453d %ceurocrypt %@Lennart Brynielsson %*On the Linear Complexity of Combined Shift Register Sequences %f/eurocrypt/imqbpflj0ozx79haybvjuhn5zf2xwlgc.pdf %mf037704b7c7947660a17dced562bb151 %ceurocrypt %@J. Bernasconi,C. G. Günther %*Analysis of a Nonlinear Feedforward Logic for Binary Sequence Generators %f/eurocrypt/u6lzduei8pldohq27bytngpa5zsqmhfc.pdf %ma5b8f8ebacbd776dfd4fc38645bed87c %ceurocrypt %@Rainer A. Rueppel %*Linear Complexity and Random Sequences %f/eurocrypt/ogykbkscxs2yjp0jna4rnhdqlxadcpi7.pdf %m76cdc0655b84adb18df6a81e8c2b9f10 %ceurocrypt %@Donald W Davies,Wyn L Price %*Engineering Secure Information Systems %f/eurocrypt/csnkz04ytiau3citjb6qphd9xfj2zyk7.pdf %m407e8069f5379927612b262ea051c073 %ceurocrypt %@Thomas Krivachy %*The Chipcard — An Identification Card with Cryptographic Protection %f/eurocrypt/jnm329iszbtgm8acwfou4xpqnshcxetz.pdf %m1f7031ef1fcff363a76873e5ecff9e0b %ceurocrypt %@U. Rimensberger %*Encryption Needs, Requirements and Solutions in Banking Networks %f/eurocrypt/51rbwsnvzupoyalv6fubghomtkcxy23t.pdf %mfadfbbf90e72108d2a787b38e12173d9 %ceurocrypt %@R. W. Jones,M. S. J. Baxter %*The Role of Encipherment Services in Distributed Systems %f/eurocrypt/shd8ycl0oamyekuqg3wevdw9vjbtzl6q.pdf %mc168cff23cd51f0bafe7874b48b6c51b %ceurocrypt %@G. B. Agnew %*Modeling of Encryption Techniques for Secrecy and Privacy in Multi-User Networks %f/eurocrypt/ce6zm7k9pkwclx45travgjayxrfn2mhd.pdf %ma6d4b926248f29ba6d9bfb31170dc969 %ceurocrypt %@Robert L. Bradey,Ian G. Graham %*Full Encryption in a Personal Computer System %f/eurocrypt/o2gba84m6qetbhpozjavwy3sxjn1dlsr.pdf %m531d886fa9b6a03adef3a478cf157b0c %ceurocrypt %@David Chaum %*Showing Credentials Without Identification %f/eurocrypt/osepjuctl8gvbx7r6ip5mkgwqlvd21j4.pdf %mb83cf4477f16bae5a442c5198cf08d56 %ceurocrypt %@Andreas Pfitzmann,Michael Waidner %*Networks Without User Observability — Design Options %f/eurocrypt/7uyk3ghndifvuoyobzcejsdtb1exlgp5.pdf %mf31343c9695ad8345b8dc387c0e3ebb6 %ceurocrypt %@Ronald V. Book,Friedrich Otto %*The Verifiability of Two-Party Protocols %f/eurocrypt/amwt14dfyocwbn5uepvgy7lethrjdoxl.pdf %me822c35b4de04bd5f1a28d0bad1e630a %ceurocrypt %@Gustavus J. Simmons %*The Practice of Authentication %f/eurocrypt/kmjbh2iqxlbyxundv8ofnrviq0zlpezs.pdf %m2e64b95cca32da3b546c466468a02319 %ceurocrypt %@M. Kowatsch,B. O. Eichinger,F. J. Seifert %*Message Protection by Spread Spectrum Modulation in a Packet Voice Radio Link %f/eurocrypt/k0ok2lvguypztycbqzafni5jblvtrchd.pdf %mf523b54a96924cfc2dc09d1b672fca2a %ceurocrypt %@G. Ruggiu %*Cryptology and Complexity Theories %f/eurocrypt/xui2ytfqrjk5lrsze9boznq7fvga1ims.pdf %m7f86cde496fac952c51442e11d9ba317 %ceurocrypt %@R. Lidl %*On Cryptosystems Based on Polynomials and Finite Fields %f/eurocrypt/xbvi1co8jfgt6atruxd7fl5dzgonjbky.pdf %m47551873ff96a0f02105af4470eef06a %ceurocrypt %@Józef P. Pieprzyk %*Algebraical Structures of Cryptographic Transformations %f/eurocrypt/r7pw3gsolxrf8shfm9emcivebaqxd65y.pdf %m4557a91a0080a87015499f339109ce35 %ceurocrypt %@S. Harari %*Non Linear Non Commutative Functions for Data Integrity %f/eurocrypt/t7oa538udxzg0lmhwfrqspvjlcxnbbym.pdf %mbd5abb71fcc73d62e924162f454466d6 %ceurocrypt %@L. H. Ozarow,A. D. Wyner %*Wire-Tap Channel II %f/eurocrypt/wou6mtaqx7fynosurxcm5jgs1iv28ncp.pdf %mfdb0d9337401c21ff85f68b0a31d7141 %ceurocrypt %@Andrea Sgarro %*Equivocations for Homophonic Ciphers %f/eurocrypt/mhlbo71omad4zc6ehzuxaxb8dfyqnfrk.pdf %ma4d433748fe4e6d70097d723d9630445 %ceurocrypt %@Marc Davio,Yvo Desmedt,Jean-Jacques Quisquater %*Propagation Characteristics of the DES %f/eurocrypt/pbqfq1g5dh0wibnk34ylmgci6r98wzuy.pdf %m47201fccbb34c134f6a8f0bf0d50f7b6 %ceurocrypt %@James L. Massey,Rainer A. Rueppel %*Linear Ciphers and Random Sequence Generators with Multiple Clocks %f/eurocrypt/e58nqlldns24katmu3yvcoz0iqtwmfvx.pdf %mbc2a731a9820820ead69dfe0459169e8 %ceurocrypt %@T. Beth,F. C. Piper %*The Stop-and-Go-Generator %f/eurocrypt/xjs8macpuhfvxkmeb7dkzitoheir49zj.pdf %m134b1e7695d2ee42d7d89bcb5e163ed7 %ceurocrypt %@Dieter Gollmann %*Pseudo Random Properties of Cascade Connections of Clock Controlled Shift Registers %f/eurocrypt/ntkwbdv15z7ul8t3pjxvqgrkoox9f46a.pdf %m7e65c508f08a41b152fdd27387c2842c %ceurocrypt %@Rainer Vogel %*On the linear complexity of cascaded sequences %f/eurocrypt/dwake12w7qmrmtsrhcptcgbffxzvnzu0.pdf %m67daeabad91c69beb6cb0cfb886e4f9f %ceurocrypt %@C. P. Schnorr,W. Alexi %*RSA-bits are 0.5 + ε secure %f/eurocrypt/rmenu02mg7kb6tosylhovu3jbz5yxqes.pdf %mb1fb7c7f54fed42653508b532341dde9 %ceurocrypt %@Oded Goldreich %*On the Number of Close-and-Equal Pairs of Bits in a String (with Implications on the Security of RSA’s L.S.B) (Extended Abstract) %f/eurocrypt/kz6wtz1mlds4bghpb3altnonsueqjfcx.pdf %m36bc15282ef446ae99e51869363f36b8 %ceurocrypt %@P. Delsarte,Y. Desmedt,A. Odlyzko,P. Piret %*Fast Cryptanalysis of the Matsumoto-Imai Public Key Scheme %f/eurocrypt/fiy3lwprypdzg10fa5mzucenavj498xu.pdf %ma74c2960509656fa90c9342cfacf04f3 %ceurocrypt %@R. M. F. Goodman,A. J. McAuley %*A New Trapdoor Knapsack Public Key Cryptosystem %f/eurocrypt/304cwc8g9tdm7umltpwiyaerbr1xbvzy.pdf %m7f3bfa4afe050bce43eb1a4146216cfd %ceurocrypt %@Ronald L. Rivest %*RSA Chips (Past/Present/Future) (Extended abstract) %f/eurocrypt/ow0lvke7fmgbwz28hja6b1ixgjftutpr.pdf %m1a6a6f41a6fe782b32f1dc0408e8b396 %ceurocrypt %@James A. Davis,Diane B. Holdridge,Gustavus J. Simmons %*Status Report on Factoring (At the Sandia National Laboratories) %f/eurocrypt/a8ypxzjs2vdj9pflceahu6qmwrzt1nnl.pdf %m487b9aabc944b2d684fa17c97c0f9d8e %ceurocrypt %@John Gordon %*Strong Primes are Easy to Find %f/eurocrypt/cqleimrbd2m4qnjpzxvaewb8hk03z1uy.pdf %med32d33a2f61b9e76851bf93b1ddb603 %ceurocrypt %@R. W. Jones %*User Functions for the Generation and Distribution of Encipherment Keys %f/eurocrypt/riptu52vfltq7vxasjnasbhyolczqemx.pdf %m124e70b91c8a8bb68ae8521bb4560c4b %ceurocrypt %@Rolf Blom %*An Optimal Class of Symmetric Key Generation Systems %f/eurocrypt/rtwi67xdd3fslibknqzhaqr1ycczyh4n.pdf %m3bb43c1d848741287d59c16391923e36 %ceurocrypt %@B. J. M. Smeets %*On the Use of the Binary Multiplying Channel in a Private Communication System %f/eurocrypt/wdo8o6d0bclfr2mhzq4acem3eip5nxvy.pdf %m6ad5c547d616dc02bb77c7697552db81 %ceurocrypt %@Gordon B. Agnew %*Secrecy and Privacy in a Local Area Network Environment %f/eurocrypt/l25764yfxrwjsogiqa1uetcpuhe0madr.pdf %m5cf836a020f0745009770c243d551948 %ceurocrypt %@Gustavus J. Simmons %*The Subliminal Channel and Digital Signatures %f/eurocrypt/zxetvw0iqqolm8rg6pcnend9rvhywg4b.pdf %me944d40a2b5a1458363888f68c41daf6 %ceurocrypt %@Richard Berger,René Peralta,Tom Tedrick %*A Provably Secure Oblivious Transfer Protocol %f/eurocrypt/wx8tuvvpgyhrw9xz7meocatkqaikqmdr.pdf %m339a68ceaa4e52e99c5a3d01ab821900 %ceurocrypt %@Oded Goldreich %*On Concurrent Identification Protocols (Extended Abstract) %f/eurocrypt/er06fcqivmnykxau4wjngqcrd2ewjbvf.pdf %m764f5038a3e8ca9378ba33a0b9700848 %ceurocrypt %@A. Ecker %*Time-Division Multiplexing Scramblers: Selecting Permutations and Testing the System %f/eurocrypt/vsb4ydepi5w7xewsrauztpbd1kcxgzuh.pdf %m88d3ca419e760440a4f9ae94e06bf219 %ceurocrypt %@A. Bouckaert %*Security of Transportable Computerized Files %f/eurocrypt/bxge1sw5nyf9kltpqxpeoziragjldhk0.pdf %m7036ce31511a38b3fe390c0be721ca38 %ceurocrypt %@S. C. Serpell,C. B. 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Wenisch', 'affiliation': 'Univ. of Michigan, Ann Arbor, MI, USA'} %*Memory persistency %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6853222 %f/isca/i6vc3sunlmayqy7ea2hxgsbze45kf8kl.pdf %m993b4458dd434976050766e902634548 %cisca %@[{'name': 'Morteza Hoseinzadeh', 'affiliation': 'Dept. of Comput. Eng., Sharif Univ. of Technol., Tehran, Iran'}, {'name': 'Mohammad Arjomand', 'affiliation': 'Dept. of Comput. Eng., Sharif Univ. of Technol., Tehran, Iran'}, {'name': 'Hamid Sarbazi-Azad', 'affiliation': 'Dept. of Comput. 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Kandemir', 'affiliation': 'Dept. of CSE, Pennsylvania State Univ., University Park, PA, USA'} %*HIOS: A host interface I/O scheduler for Solid State Disks %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6853216 %f/isca/fb6gqhia47zjiquwo9m83xur1svklja2.pdf %m1f3be20e87e6952b3d35a4540f63b8cb %cisca %@[{'name': 'David Lo'}, {'name': ' Liqun Cheng'}, {'name': 'Rama Govindaraju'}, {'name': 'Luiz Andre Barroso'}, {'name': 'Christos Kozyrakis'} %*Towards energy proportionality for large-scale latency-critical workloads %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6853237 %f/isca/5g6rdhakufwtvivjoodb9msieq1kexhp.pdf %mdf6eeea681325d379fc53c5b3d59f3b8 %cisca %@[{'name': ' Yanpei Liu', 'affiliation': 'Univ. of Wisconsin, Madison, WI, USA'}, {'name': 'Stark C. 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'Department of Computer Science, State University of New York at Binghamton, USA'}, {'name': 'Dmitry Ponomarev', 'affiliation': 'Department of Computer Science, State University of New York at Binghamton, USA'} %*Branch regulation: Low-overhead protection from code reuse attacks %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6237009 %f/isca/mfdfrldoub4zzaqrs9vje6gpikqmwxy0.pdf %m110e58b65263a6e92fc2f14aa496cccb %cisca %@[{'name': 'John Demme', 'affiliation': 'Computer Architecture Security and Technology Lab, Department of Computer Science, Columbia University, NY, 10027, USA'}, {'name': 'Robert Martin', 'affiliation': 'Computer Architecture Security and Technology Lab, Department of Computer Science, Columbia University, NY, 10027, USA'}, {'name': 'Adam Waksman', 'affiliation': 'Computer Architecture Security and Technology Lab, Department of Computer Science, Columbia University, NY, 10027, USA'}, {'name': 'Simha Sethumadhavan', 'affiliation': 'Computer Architecture Security and Technology Lab, Department of Computer Science, Columbia University, NY, 10027, USA'} %*Side-channel vulnerability factor: A metric for measuring information leakage %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6237010 %f/isca/ft2ptgs3aqqv8ud5clmjbzyejywipo90.pdf %m596f02873f68f3a864e3bb63e465b57b %cisca %@[{'name': 'Robert Martin', 'affiliation': '4Computer Architecture and Security Technologies Lab, Department of Computer Science, Columbia University, New York, USA'}, {'name': 'John Demme', 'affiliation': '4Computer Architecture and Security Technologies Lab, Department of Computer Science, Columbia University, New York, USA'}, {'name': 'Simha Sethumadhavan', 'affiliation': '4Computer Architecture and Security Technologies Lab, Department of Computer Science, Columbia University, New York, USA'} %*TimeWarp: Rethinking timekeeping and performance monitoring mechanisms to mitigate side-channel attacks %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6237011 %f/isca/ngirndyavjpk6zsjcl32mpur9e5mbdxu.pdf %ma7024e8273fe3bf823667ec4ecc64b4c %cisca %@[{'name': 'Jonathan Valamehr', 'affiliation': 'UC Santa Barbara, USA'}, {'name': 'Melissa Chase', 'affiliation': 'Microsoft Research, USA'}, {'name': 'Seny Kamara', 'affiliation': 'Microsoft Research, USA'}, {'name': 'Andrew Putnam', 'affiliation': 'Microsoft Research, USA'}, {'name': 'Dan Shumow', 'affiliation': 'Microsoft Research, USA'}, {'name': 'Vinod Vaikuntanathan', 'affiliation': 'University of Toronto, Canada'}, {'name': 'Timothy Sherwood', 'affiliation': 'UC Santa Barbara, USA'} %*Inspection resistant memory: Architectural support for security from physical examination %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6237012 %f/isca/onlzgfi3cwryx57uzt0vj9syxqmwunbe.pdf %m8b29fe48bafa7b2b8f8328cf38f906f4 %cisca %@[{'name': 'Yi Xu', 'affiliation': 'Department of Electrical and Computer Engineering, University of Pittsburgh, USA'}, {'name': 'Jun Yang', 'affiliation': 'Department of Electrical and Computer Engineering, University of Pittsburgh, USA'}, {'name': 'Rami Melhem', 'affiliation': 'Department of Computer Science, University of Pittsburgh, USA'} %*Tolerating process variations in nanophotonic on-chip networks %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6237013 %f/isca/nodzbaozkv7ah2typw0eryisjf9sntpi.pdf %mf70d3284944ecaa4f55ef1989b26948f %cisca %@[{'name': 'Pranay Koka', 'affiliation': 'Oracle Labs, USA'}, {'name': 'Michael O. McCracken', 'affiliation': 'Oracle Labs, USA'}, {'name': 'Herb Schwetman', 'affiliation': 'Oracle Labs, USA'}, {'name': 'Chia-Hsin Owen Chen', 'affiliation': 'MIT CSAIL, USA'}, {'name': 'Xuezhe Zheng', 'affiliation': 'Oracle Labs, USA'}, {'name': 'Ron Ho', 'affiliation': 'Oracle Labs, USA'}, {'name': 'Kannan Raj', 'affiliation': 'Oracle Labs, USA'}, {'name': 'Ashok V. Krishnamoorthy', 'affiliation': 'Oracle Labs, USA'} %*A micro-architectural analysis of switched photonic multi-chip interconnects %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6237014 %f/isca/a4ehzkbgsdy0fpxmc3zeoh8jnqi6wv9u.pdf %m64b1355eaa180eecdbda838791540565 %cisca %@[{'name': 'Aaron Carpenter', 'affiliation': 'Binghamton University, USA'}, {'name': 'Jianyun Hu', 'affiliation': 'Dept. of Electrical and Computer Engineering, University of Rochester, USA'}, {'name': 'Ovunc Kocabas', 'affiliation': 'Dept. of Electrical and Computer Engineering, University of Rochester, USA'}, {'name': 'Michael Huang', 'affiliation': 'Dept. of Electrical and Computer Engineering, University of Rochester, USA'}, {'name': 'Hui Wu', 'affiliation': 'Dept. of Electrical and Computer Engineering, University of Rochester, USA'} %*Enhancing effective throughput for transmission line-based bus %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6237015 %f/isca/7rplsdfycn3q8iebuxj2mqukn1vwc9pt.pdf %m16824e0be34b23faad9009e98408f56b %cisca %@[{'name': 'Michihiro Koibuchi', 'affiliation': 'National Institute of Informatics / SOKENDAI, 2-1-2, Hitotsubashi, Chiyoda-ku, Tokyo, JAPAN 101-8430'}, {'name': 'Hiroki Matsutani', 'affiliation': 'Keio University, 3-14-1, Hiyoshi, Kohoku-ku, Yokohama, JAPAN 223-8522'}, {'name': 'Hideharu Amano', 'affiliation': 'Keio University, 3-14-1, Hiyoshi, Kohoku-ku, Yokohama, JAPAN 223-8522'}, {'name': 'D. Frank Hsu', 'affiliation': 'Fordham University, 113 West 60th Street, New York, 10023, USA'}, {'name': 'Henri Casanova', 'affiliation': "University of Hawai'i at Manoa, 1680 East-West Road, Honolulu, 96822, USA"} %*A case for random shortcut topologies for HPC interconnects %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6237016 %f/isca/3hgia7d8sau1vcizbkuv69tnle2pp5kj.pdf %m84b535f3ba427aa392419feacd08e49f %cisca %@[{'name': 'Santosh Nagarakatte', 'affiliation': 'Computer and Information Science, University of Pennsylvania, USA'}, {'name': 'Milo M. K. Martin', 'affiliation': 'Computer and Information Science, University of Pennsylvania, USA'}, {'name': 'Steve Zdancewic', 'affiliation': 'Computer and Information Science, University of Pennsylvania, USA'} %*Watchdog: Hardware for safe and secure manual memory management and full memory safety %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6237017 %f/isca/roadlgtlx4bjkif8teifschcuoz05qna.pdf %med53946f313087a5b2d1b4e4c99a14a6 %cisca %@[{'name': 'Joseph Devietti', 'affiliation': 'University of Washington, USA'}, {'name': 'Benjamin P. Wood', 'affiliation': 'University of Washington, USA'}, {'name': 'Karin Strauss', 'affiliation': 'University of Washington, USA'}, {'name': 'Luis Ceze', 'affiliation': 'University of Washington, USA'}, {'name': 'Dan Grossman', 'affiliation': 'University of Washington, USA'}, {'name': 'Shaz Qadeer', 'affiliation': 'Microsoft Research, USA'} %*RADISH: Always-on sound and complete race detection in software and hardware %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6237018 %f/isca/cl8bg9upyps2fynq5xo3tnb4isqriaaw.pdf %ma5de6daf13cb934364a81f5275c6578a %cisca %@[{'name': 'Kenzo Van Craeynest', 'affiliation': 'Ghent University, Belgium'}, {'name': 'Aamer Jaleel', 'affiliation': 'Intel Corporation, VSSAD, Hudson, MA, USA'}, {'name': 'Lieven Eeckhout', 'affiliation': 'Ghent University, Belgium'}, {'name': 'Paolo Narvaez', 'affiliation': 'Intel Corporation, VSSAD, Hudson, MA, USA'}, {'name': 'Joel Emer', 'affiliation': 'Intel Corporation, VSSAD, Hudson, MA, USA'} %*Scheduling heterogeneous multi-cores through performance impact estimation (PIE) %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6237019 %f/isca/cybrinon7wkqgut5aahxeb1ip03dguj9.pdf %m084c90d5d8d9a01738b6dcb173c97648 %cisca %@[{'name': 'Ting Cao', 'affiliation': 'Australian National University, Australia'}, {'name': 'Stephen M Blackburn', 'affiliation': 'Australian National University, Australia'}, {'name': 'Tiejun Gao', 'affiliation': 'Australian National University, Australia'}, {'name': 'Kathryn S McKinley', 'affiliation': 'Microsoft Research, USA'} %*The Yin and Yang of power and performance for asymmetric hardware and managed software %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6237020 %f/isca/hijeqrbpjoqnmoxz1wglcm5749fuhtar.pdf %m984b11bd10d3319e6a5b5fc46a45341f %cisca %@[{'name': 'Evgeni Krimer', 'affiliation': 'Electrical and Computer Engineering Department, The University of Texas at Austin, USA'}, {'name': 'Patrick Chiang', 'affiliation': 'School of Electrical Engineering and Computer Science, Oregon State University, USA'}, {'name': 'Mattan Erez', 'affiliation': 'Electrical and Computer Engineering Department, The University of Texas at Austin, USA'} %*Lane decoupling for improving the timing-error resiliency of wide-SIMD architectures %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6237021 %f/isca/sozpv3ltfgrkrlibidoy1whcj8xfmxnn.pdf %mfbdc14f4694f5e435d21b5976ef1f308 %cisca %@[{'name': 'Timothy N. Miller', 'affiliation': 'Department of Computer Science and Engineering, The Ohio State University, USA'}, {'name': 'Renji Thomas', 'affiliation': 'Department of Computer Science and Engineering, The Ohio State University, USA'}, {'name': 'Xiang Pan', 'affiliation': 'Department of Computer Science and Engineering, The Ohio State University, USA'}, {'name': 'Radu Teodorescu', 'affiliation': 'Department of Computer Science and Engineering, The Ohio State University, USA'} %*VRSync: Characterizing and eliminating synchronization-induced voltage emergencies in many-core processors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6237022 %f/isca/nomws1andkeixhfbqkpt7cm0g29eaypq.pdf %me841800be211f92126ab0197ee93c8a3 %cisca %@[{'name': 'Ioannis Doudalis', 'affiliation': 'Intel Corporation, USA'}, {'name': 'Milos Prvulovic', 'affiliation': 'Georgia Institute of Technology, USA'} %*Euripus: A flexible unified hardware memory checkpointing accelerator for bidirectional-debugging and reliability %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6237023 %f/isca/dr1pzooslmgw27quxugmnswvbfxpaeyj.pdf %m577fb2fe64b1b8542944835ada01d115 %cisca %@[{'name': 'Arun Arvind Nair', 'affiliation': 'The University of Texas at Austin, USA'}, {'name': 'Stijn Eyerman', 'affiliation': 'Ghent University, Belgium'}, {'name': 'Lieven Eeckhout', 'affiliation': 'Ghent University, Belgium'}, {'name': 'Lizy Kurian John', 'affiliation': 'The University of Texas at Austin, USA'} %*A first-order mechanistic model for architectural vulnerability factor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6237024 %f/isca/mcd2elpy9tvboh1cwqxukkgg6o3am0fr.pdf %m8c09b5a961c6be9eca5addc48f3f3504 %cisca %@[{'name': 'Aniruddha N. Udipi', 'affiliation': 'University of Utah, USA'}, {'name': 'Naveen Muralimanohar', 'affiliation': 'HP Labs, USA'}, {'name': 'Rajeev Balsubramonian', 'affiliation': 'University of Utah, USA'}, {'name': 'Al Davis', 'affiliation': 'University of Utah, USA'}, {'name': 'Norman P. Jouppi', 'affiliation': 'HP Labs, USA'} %*LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6237025 %f/isca/0pzhrvlqbsfmgx1kxzaan3ugmtpwbyeo.pdf %m544d0a3b1b920784f4ff641ef2f844c3 %cisca %@[{'name': 'Arkaprava Basu', 'affiliation': 'University of Wisconsin-Madison, USA'}, {'name': 'Mark D. Hill', 'affiliation': 'University of Wisconsin-Madison, USA'}, {'name': 'Michael M. Swift', 'affiliation': 'University of Wisconsin-Madison, USA'} %*Reducing memory reference energy with opportunistic virtual caching %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6237026 %f/isca/a6wxp1fdvw23an9omelunhclf7mkzgsd.pdf %m2df3b7eb62c825247049d08303418a54 %cisca %@[{'name': 'Zhe Wang', 'affiliation': 'The University of Texas at San Antonio, USA'}, {'name': 'Samira M. Khan', 'affiliation': 'The University of Texas at San Antonio, USA'}, {'name': 'Daniel A. Jimé,nez', 'affiliation': 'The University of Texas at San Antonio, USA'} %*Improving writeback efficiency with decoupled last-write prediction %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6237027 %f/isca/wiym8xnwutatspf7d1ohgszfqjo2zxnd.pdf %m0491b22af895dd685fa6ac52398090cd %cisca %@[{'name': 'Jaewoong Sim', 'affiliation': 'Georgia Institute of Technology, USA'}, {'name': 'Jaekyu Lee', 'affiliation': 'Georgia Institute of Technology, USA'}, {'name': 'Moinuddin K. Qureshi', 'affiliation': 'Georgia Institute of Technology, USA'}, {'name': 'Hyesoon Kim', 'affiliation': 'Georgia Institute of Technology, USA'} %*FLEXclusion: Balancing cache capacity and on-chip bandwidth via Flexible Exclusion %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6237028 %f/isca/vjh3zd5culkwjtdotqo80pr1sze47y6r.pdf %m08602da479f5abc56d66a22475f63ae9 %cisca %@[{'name': 'Gaurang Upasani', 'affiliation': "Dept. d'Arquitectura de Computadors, Universitat Politè,cnica de Catalunya, Barcelona, Spain"}, {'name': 'Xavier Vera', 'affiliation': 'Intel Barcelona Research Center, Intel Labs, Barcelona, Spain'}, {'name': 'Antonio Gonzá,lez', 'affiliation': "Dept. d'Arquitectura de Computadors, Universitat Politè,cnica de Catalunya, Barcelona, Spain"} %*Setting an error detection infrastructure with low cost acoustic wave detectors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6237029 %f/isca/4knhjzd8dxp9rcaqtapj0y3mxmi7grck.pdf %mbca31de5e2e16cbf3c1e8f1f8cdb8124 %cisca %@[{'name': 'Andrea Pellegrini', 'affiliation': 'Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, USA'}, {'name': 'Joseph L. Greathouse', 'affiliation': 'Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, USA'}, {'name': 'Valeria Bertacco', 'affiliation': 'Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, USA'} %*Viper: Virtual pipelines for enhanced reliability %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6237030 %f/isca/fstqm2c43rnhcsvbzljva8im6ewopget.pdf %mdbd340f03f42b5c68cfeb53bb2d72e09 %cisca %@[{'name': 'Olivier Temam', 'affiliation': 'INRIA Saclay, France'} %*A defect-tolerant accelerator for emerging high-performance applications %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6237031 %f/isca/cl3qkkre6unalab0wzen52ydj8h7gvxq.pdf %m0099cfa3c712fb31496aefb8f3a806c4 %cisca %@[{'name': 'Yoongu Kim', 'affiliation': 'Carnegie Mellon University, USA'}, {'name': 'Vivek Seshadri', 'affiliation': 'Carnegie Mellon University, USA'}, {'name': 'Donghyuk Lee', 'affiliation': 'Carnegie Mellon University, USA'}, {'name': 'Jamie Liu', 'affiliation': 'Carnegie Mellon University, USA'}, {'name': 'Onur Mutlu', 'affiliation': 'Carnegie Mellon University, USA'} %*A case for exploiting subarray-level parallelism (SALP) in DRAM %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6237032 %f/isca/q8kczdw5jxhcrtv2gm3fuj7hosw6dgir.pdf %m25b2e32f446384028d1e836d9419999a %cisca %@[{'name': 'Moinuddin K. Qureshi', 'affiliation': 'Georgia Institute of Technology, USA'}, {'name': 'Michele M. Franceschini', 'affiliation': 'IBM T. J. Watson Research Center, NY, USAs'}, {'name': 'Ashish Jagmohan', 'affiliation': 'IBM T. J. Watson Research Center, NY, USAs'}, {'name': 'Luis A. Lastras', 'affiliation': 'IBM T. J. Watson Research Center, NY, USAs'} %*PreSET: Improving performance of phase change memories by exploiting asymmetry in write times %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6237033 %f/isca/g3qwav8ccn7ig4ryidudfqxvkhf1l2on.pdf %m23065d1df09163c9c100656558d7fd22 %cisca %@[{'name': 'Elliott Cooper-Balis', 'affiliation': 'University of Maryland, USA'}, {'name': 'Paul Rosenfeld', 'affiliation': 'University of Maryland, USA'}, {'name': 'Bruce Jacob', 'affiliation': 'University of Maryland, USA'} %*Buffer-on-board memory systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6237034 %f/isca/ykc7vgr0esl4gpwwbbjzxiafqhtjs5nn.pdf %mc8505585b43d77a62178148d78dc866a %cisca %@[{'name': 'Myoungsoo Jung', 'affiliation': 'Department of Computer Science and Engineering, The Pennsylvania State University, USA'}, {'name': 'Ellis H. Wilson', 'affiliation': 'Department of Computer Science and Engineering, The Pennsylvania State University, USA'}, {'name': 'Mahmut Kandemir', 'affiliation': 'Department of Computer Science and Engineering, The Pennsylvania State University, USA'} %*Physically addressed queueing (PAQ): Improving parallelism in solid state disks %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6237035 %f/isca/1ipcqzceg93ol0wmtjenr74pywflduhd.pdf %me44d9c36d0406129f28e2e9d2414bd23 %cisca %@[{'name': 'Rachata Ausavarungnirun', 'affiliation': 'Carnegie Mellon University, USA'}, {'name': 'Kevin Kai-Wei Chang', 'affiliation': 'Carnegie Mellon University, USA'}, {'name': 'Lavanya Subramanian', 'affiliation': 'Carnegie Mellon University, USA'}, {'name': 'Gabriel H. Loh', 'affiliation': 'Advanced Micro Devices, Inc., USA'}, {'name': 'Onur Mutlu', 'affiliation': 'Carnegie Mellon University, USA'} %*Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6237036 %f/isca/s0ztvizjengixbfwsxturmwhlchkmab2.pdf %mefabd95249445d30a29d9f80de055c2e %cisca %@[{'name': 'R Manikantan', 'affiliation': 'Department of Computer Science and Automation, Indian Institute of Science, Bangalore, India'}, {'name': 'Kaushik Rajan', 'affiliation': 'Microsoft Research India, Bangalore, India'}, {'name': 'R Govindarajan', 'affiliation': 'Department of Computer Science and Automation, Indian Institute of Science, Bangalore, India'} %*Probabilistic Shared Cache Management (PriSM) %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6237037 %f/isca/n5x1temz7b3cfzvimak9nt2ogcuesrdq.pdf %mcad39977b3b227949f1b1e8c260d4879 %cisca %@[{'name': 'Nadathur Satish', 'affiliation': 'Parallel Computing Lab, Intel Corporation, USA'}, {'name': 'Changkyu Kim', 'affiliation': 'Parallel Computing Lab, Intel Corporation, USA'}, {'name': 'Jatin Chhugani', 'affiliation': 'Parallel Computing Lab, Intel Corporation, USA'}, {'name': 'Hideki Saito', 'affiliation': 'Intel Compiler Lab, Intel Corporation, USA'}, {'name': 'Rakesh Krishnaiyer', 'affiliation': 'Intel Compiler Lab, Intel Corporation, USA'}, {'name': 'Mikhail Smelyanskiy', 'affiliation': 'Parallel Computing Lab, Intel Corporation, USA'}, {'name': 'Milind Girkar', 'affiliation': 'Intel Compiler Lab, Intel Corporation, USA'}, {'name': 'Pradeep Dubey', 'affiliation': 'Parallel Computing Lab, Intel Corporation, USA'} %*Can traditional programming bridge the Ninja performance gap for parallel computing applications? %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6237038 %f/isca/ru5haivp6dtfpo0bxlcwlkqgsv3styak.pdf %m146a0dc857878a48b6ceb82c863d6832 %cisca %@[{'name': 'Melanie Kambadur', 'affiliation': 'Columbia University, New York, USA'}, {'name': 'Kui Tang', 'affiliation': 'Columbia University, New York, USA'}, {'name': 'Martha A. Kim', 'affiliation': 'Columbia University, New York, USA'} %*Harmony: Collection and analysis of parallel block vectors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6237039 %f/isca/3mgxsvjy8cfokhnxyacz6qwgeplfnr0r.pdf %m5844de7842ba4290a99a997a894ea5a7 %cisca %@[{'name': 'David Wentzlaff', 'affiliation': 'Princeton University, USA'}, {'name': 'Christopher J. Jackson', 'affiliation': 'Tilera Corp., USA'}, {'name': 'Patrick Griffin', 'affiliation': 'Google Inc., USA'}, {'name': 'Anant Agarwal', 'affiliation': 'Tilera Corp., USA'} %*Configurable fine-grain protection for multicore processor virtualization %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6237040 %f/isca/6ccojf39zixjrhbw5lhna1s8vdfpvdtx.pdf %m2df9a0048181005b068cb5a4a9ad772e %cisca %@[{'name': 'Jeongseob Ahn', 'affiliation': 'Computer Science Department, KAIST, Korea'}, {'name': 'Seongwook Jin', 'affiliation': 'Computer Science Department, KAIST, Korea'}, {'name': 'Jaehyuk Huh', 'affiliation': 'Computer Science Department, KAIST, Korea'} %*Revisiting hardware-assisted page walks for virtualized systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6237041 %f/isca/cw8wmnkzhpfysi0gbgor1dtixjpqzekl.pdf %mcd3806bedcb3096ce2625363f53d4f1d %cisca %@[{'name': 'Vasileios Kontorinis', 'affiliation': 'Department of Computer Science and Engineering, UC San Diego, USA'}, {'name': 'Liuyi Eric Zhang', 'affiliation': 'Department of Computer Science and Engineering, UC San Diego, USA'}, {'name': 'Baris Aksanli', 'affiliation': 'Department of Computer Science and Engineering, UC San Diego, USA'}, {'name': 'Jack Sampson', 'affiliation': 'Department of Computer Science and Engineering, UC San Diego, USA'}, {'name': 'Houman Homayoun', 'affiliation': 'Department of Computer Science and Engineering, UC San Diego, USA'}, {'name': 'Eddie Pettis', 'affiliation': 'Google Inc., USA'}, {'name': 'Dean M. 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Vijaykumar', 'affiliation': 'Sch. of Electr. & Comput. Eng., Purdue Univ., USA'} %*Rescue: a microarchitecture for testability and defect tolerance %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1431554 %f/isca/hnfbmjpodruxhu5g27sej4lvpky0iwrv.pdf %m00f142118c23df926b1284d0a9e23f22 %cisca %@[{'name': 'M.A. Gomaa', 'affiliation': 'Sch. of Electr. & Comput. Eng., Purdue Univ., USA'}, {'name': 'T.N. Vijaykumar', 'affiliation': 'Sch. of Electr. & Comput. Eng., Purdue Univ., USA'} %*Opportunistic transient-fault detection %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1431555 %f/isca/slo1er6bamplgffkg4hzs9jq80ro5zij.pdf %mf3939c1fcfc43b058797f51beb5536c4 %cisca %@[{'name': 'S. Balensiefer', 'affiliation': 'Dept. of Comput. Sci. & Eng., Univ. of Washington, WA, USA'}, {'name': 'L. Kregor-Stickles', 'affiliation': 'Dept. of Comput. Sci. & Eng., Univ. of Washington, WA, USA'}, {'name': 'M. Oskin', 'affiliation': 'Dept. of Comput. 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Eng., Wisconsin Univ., Madison, WI, USA'} %*Improving multiprocessor performance with coarse-grain coherence tracking %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1431561 %f/isca/oa5ysmxhlw7nicfuteb3vm6ke1sq0pwj.pdf %mc9349878e804968657cc7111dad966e5 %cisca %@[{'name': 'S. Hines', 'affiliation': 'Comput. Sci. Dept., Florida State Univ., Tallahassee, FL, USA'}, {'name': 'J. Green', 'affiliation': 'Comput. Sci. Dept., Florida State Univ., Tallahassee, FL, USA'}, {'name': 'G. Tyson', 'affiliation': 'Comput. Sci. Dept., Florida State Univ., Tallahassee, FL, USA'}, {'name': 'D. Whalley', 'affiliation': 'Comput. Sci. Dept., Florida State Univ., Tallahassee, FL, USA'} %*Improving program efficiency by packing instructions into registers %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1431562 %f/isca/lfaegriw2jikspukdy3ps48qqb9hjuxg.pdf %m0ebf975d87ab415bb7764b418013f2c7 %cisca %@[{'name': 'N. Clark', 'affiliation': 'Adv. Comput. Archit. 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Sci. & Eng., California Univ., San Diego, CA, USA'} %*BugNet: continuously recording program execution for deterministic replay debugging %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1431564 %f/isca/ezfrocuknqpwl1sp9mqz6yv2aojbx0ue.pdf %m06cfdffd32b0dba602401b442c844030 %cisca %@[{'name': 'M. Annavaram', 'affiliation': 'Microarchitecture Res. Lab., Intel Corp., Santa Clara, CA, USA'}, {'name': 'E. Grochowski', 'affiliation': 'Microarchitecture Res. Lab., Intel Corp., Santa Clara, CA, USA'}, {'name': 'J. Shen', 'affiliation': 'Microarchitecture Res. Lab., Intel Corp., Santa Clara, CA, USA'} %*Mitigating Amdahl's law through EPI throttling %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1431565 %f/isca/wanzuwoymdxgjvz0pqctvru9n64g25fk.pdf %m36e900f31f75b27ecdd99bd3ff7aabdb %cisca %@[{'name': 'E. Talpes', 'affiliation': 'Dept. of Comput. & Electr. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA'}, {'name': 'D. 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Eng., Univ. of Texas at Austin, TX, USA'} %*Techniques for efficient processing in runahead execution engines %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1431571 %f/isca/wrntpqv6fzmiqyb7oehc1mox3vyhugpg.pdf %me1ee5d1f5876b99405157bb4333fd511 %cisca %@[{'name': 'D.A. Jimenez', 'affiliation': 'Dept. of Comput. Sci., Rutgers Univ., USA'} %*Piecewise linear branch prediction %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1431572 %f/isca/pyljf3nl7nss9d8k0pithqbtw6qdifco.pdf %m5ef6fc6568af82576cedbbfd1249d0ba %cisca %@[{'name': 'A. Seznec', 'affiliation': 'IRISA/INRIA/HIPEAC, Rennes, France'} %*Analysis of the O-GEometric history length branch predictor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1431573 %f/isca/rjkb5ihsvmtidef9x468yq0af31rjyww.pdf %m30f22512310e9d9b0e64854d9223d5ff %cisca %@[{'name': 'R. Kumar', 'affiliation': 'Dept. of Comput. Sci. & Eng., California Univ., San Diego, CA, USA'}, {'name': 'V. Zyuban', 'affiliation': 'Dept. of Comput. Sci. & Eng., California Univ., San Diego, CA, USA'}, {'name': 'D.M. Tullsen', 'affiliation': 'Dept. of Comput. Sci. & Eng., California Univ., San Diego, CA, USA'} %*Interconnections in multi-core architectures: understanding mechanisms, overheads and scaling %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1431574 %f/isca/sj45wnajkgibpc18olqkgtbwudvmh0or.pdf %m5eb54680f1faba50fb869e5720782d61 %cisca %@[{'name': 'J. Kim', 'affiliation': 'Comput. Syst. Lab., Stanford Univ., CA, USA'}, {'name': 'W.J. Dally', 'affiliation': 'Comput. Syst. Lab., Stanford Univ., CA, USA'}, {'name': 'B. Towles'}, {'name': 'A.K. Gupta'} %*Microarchitecture of a high radix router %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1431575 %f/isca/ftfgitwvmjbohlasnu6spxohz4aeq0kn.pdf %m6f045f8f4d29d9dc7394682ec64edb51 %cisca %@[{'name': ' Daeho Seo', 'affiliation': 'Sch. of Electr. & Comput. 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Lai'} %*Scalable load and store processing in latency tolerant processors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1431577 %f/isca/lde5f1nsv3myod9w2x0jupanirlshmvk.pdf %md5e2be2b0862a3ff56e1777c9e26ea04 %cisca %@[{'name': 'A. Roth', 'affiliation': 'Dept. of Comput. & Inf. Sci., Pennsylvania Univ., Philadelphia, PA, USA'} %*Store vulnerability window (SVW): re-execution filtering for enhanced load optimization %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1431578 %f/isca/ua1qnecw7gxla0wlgijqyp35hvfu4hbp.pdf %m604fbf420a1e2c6795f7c5a71b60b405 %cisca %@[{'name': 'E.F. Torres', 'affiliation': 'HiPEAC NoE, Zaragoza Univ., Spain'}, {'name': 'P. Ibanez', 'affiliation': 'HiPEAC NoE, Zaragoza Univ., Spain'}, {'name': 'V. Vinals', 'affiliation': 'HiPEAC NoE, Zaragoza Univ., Spain'}, {'name': 'J.M. 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J %*Computer Modules: An architecture for large digital modules %uhttp://dl.acm.org/ft_gateway.cfm?id=803988&type=pdf %f/isca/rxtp8dpknjqfqhzby35xav6esl41iemk.pdf %mfdbd8a4c09bb0c5be8b15ee349dd3700 %cisca %@Zaks, Rodna %*A microprogrammed architecture for front end processing %uhttp://dl.acm.org/ft_gateway.cfm?id=803989&type=pdf %f/isca/kgrgxm4zzc0hiclu25ee1pwuh8iabfvt.pdf %mb698b5c74f6652ecb9168c7617bc6c03 %cisca %@Vranesic, Z. G., Hamacher, V. C., Leung, Y. Y %*Design of a fully variable-length structured minicomputer %uhttp://dl.acm.org/ft_gateway.cfm?id=803990&type=pdf %f/isca/vwf9covngsghxe4juet1mzbjiyki3td7.pdf %ma481c943721e54aea190a9a791233041 %cisca %@Marvel, Orin E %*Happe Honeywell Associative Parallel Processing Ensemble %uhttp://dl.acm.org/ft_gateway.cfm?id=803991&type=pdf %f/isca/pw9xj5agkyv08tpsm3xechzkmaiquu1o.pdf %m3bf9b0b51705e696664a8240b1ad5164 %cisca %@Schaffner, Mario R %*A computer architecture and its programming language %uhttp://dl.acm.org/ft_gateway.cfm?id=803992&type=pdf %f/isca/mwv1nhkiqgsun8clvrpudef9moob4fjr.pdf %m3c731fbdafb14a24b00641368e24b805 %cisca %@Stephen M. Kofsky,Daniel R. Johnson,John A. Stratton,Wen-mei W. Hwu,Sanjay J. Patel,Steven S. Lumetta %*Implementing a GPU Programming Model on a Non-GPU Accelerator Architecture %f/isca/8zm5iuvywqt1iah47kd6sroxcbyjstln.pdf %m4f14ad14e6f29752ee9b5588fa913f9e %cisca %@[{'name': 'Lieven Eeckhout', 'affiliation': 'Ghent University', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/7866793/7866812/7866812-photo-1-small.gif', 'p': ['Lieven Eeckhout is a professor in the Department of Electronics and Information Systems at Ghent University. Contact him at lieven.eeckhout@ugent.be.']}} %*Looking Forward to Upcoming Themes %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7866812 %f/micro/3easflxlmdg45yxp8mjc6hqzvgtirn0s.pdf %m53fec0126e5d820d584ac61a35a80f98 %cmicro %@[{'name': 'Pradip Bose', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ['Pradip Bose is a distinguished research staff member and manager of the Reliability- and Power-Aware Microarchitectures group at the IBM T.J. Watson Research Center. Contact him at pbose@us.ibm.com.']}}, {'name': 'Alper Buyuktosunoglu', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ['Alper Buyuktosunoglu is a research staff member at the IBM T.J. Watson Research Center. Contact him at alperb@us.ibm.com.']}} %*Architectural Support for Cognitive Processing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7866814 %f/micro/qeif5okjg9wxhbpdov4mjpsruzblefgn.pdf %m586f6cb33f922ed10f03c6d76627ab54 %cmicro %@[{'name': 'James E. Smith', 'bio': {'p': ['James E. Smith is an emeritus professor in the Department of Electrical and Computer Engineering at the University of Wisconsin-Madison. He is currently working on his own, studying new computing paradigms. His previous research interests included high-performance, energy-efficient, and fault-tolerant computer processors and systems. Smith received a PhD in computer science from the University of Illinois. Contact him at jes@ece.wisc.edu.']}} %*Research Agenda: Spacetime Computation and the Neocortex %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7866805 %f/micro/sh6vpylwo3ed4hetsyp7n2mzfkgmb1jw.pdf %m7ed44b0278ffd3271df0df87797f5dd0 %cmicro %@[{'name': 'Yuhao Zhu', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ['Yuhao Zhu is a PhD candidate in the Department of Electrical and Computer Engineering at the University of Texas at Austin. Contact him at yzhu@utexas.edu.']}}, {'name': 'Vijay Janapa Reddi', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ['Vijay Janapa Reddi is an assistant professor in the Department of Electrical and Computer Engineering at the University of Texas at Austin. Contact him at vj@ece.utexas.edu.']}}, {'name': 'Robert Adolf', 'affiliation': 'Harvard University', 'bio': {'p': ['Robert Adolf is a PhD candidate in the School of Engineering and Applied Sciences at Harvard University. Contact him at rdadolf@seas.harvard.edu.']}}, {'name': 'Saketh Rama', 'affiliation': 'Harvard University', 'bio': {'p': ['Saketh Rama is a PhD student in the School of Engineering and Applied Sciences at Harvard University. Contact him at rama@seas.harvard.edu.']}}, {'name': 'Brandon Reagen', 'affiliation': 'Harvard University', 'bio': {'p': ['Brandon Reagen is a PhD candidate in the School of Engineering and Applied Sciences at Harvard University. Contact him at reagen@fas.harvard.edu.']}}, {'name': 'Gu-Yeon Wei', 'affiliation': 'Harvard University', 'bio': {'p': ['Gu-Yeon Wei is the Wei Gordon McKay Professor of Electrical Engineering and Computer Science at Harvard University. Contact him at guyeon@eecs.harvard.edu.']}}, {'name': 'David Brooks', 'affiliation': 'Harvard University', 'bio': {'p': ['David Brook is the Haley Family Professor of Computer Science at Harvard University. He is an editorial board member of IEEE Micro. Contact him at dbrooks@eecs.harvard.edu.']}} %*Cognitive Computing Safety: The New Horizon for Reliability / The Design and Evolution of Deep Learning Workloads %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7866796 %f/micro/xifhlwtmujypcgakwnbk7l0ts3zhevya.pdf %m2aa534380e9399d2b98748b7aa1372aa %cmicro %@[{'name': 'Reza Yazdani', 'affiliation': 'Universitat Politecnica de Catalunya', 'bio': {'p': ['Reza Yazdani is a PhD student at the Universitat Politècnica de Catalunya. His research interests include the design of highperformance and low-power accelerators for cognitive computing architectures, fault-tolerant design, embedded systems, and VLSI design. Yazdani received an MS in computer architecture from the University of Tehran. Contact him at ryazdani@ac.upc.edu.']}}, {'name': 'Albert Segura', 'affiliation': 'Universitat Politecnica de Catalunya', 'bio': {'p': ['Albert Segura is a PhD student at the Universitat Politècnica de Catalunya. His research interests include cognitive computing on GPU architectures. Segura received an MS in computer architecture from UPC. Contact him at asegura@ac.upc.edu.']}}, {'name': 'Jose-Maria Arnau', 'affiliation': 'Universitat Politecnica de Catalunya', 'bio': {'p': ['José-María Arnau is a postdoctoral researcher at the Universitat Politècnica de Catalunya. His research interests include low-power architectures for cognitive computing. Arnau received a PhD in computer architecture from UPC. Contact him at jarnau@ac.upc.edu.']}}, {'name': 'Antonio Gonzalez', 'affiliation': 'Universitat Politecnica de Catalunya', 'bio': {'p': ['Antonio Gonzalez is a full professor in the Computer Architecture Department at the Universitat Politècnica de Catalunya. His research interests include computer architecture, compilers, and parallel processing. González received a PhD in computer engineering from UPC. He is an IEEE Fellow. Contact him at antonio@ac.upc.edu.']}} %*Low-Power Automatic Speech Recognition Through a Mobile GPU and a Viterbi Accelerator %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7898353 %f/micro/zzcbgvpiudjtvns3f1nrld64hore2my0.pdf %md8ebc4df0197166171570acd2dd4bd33 %cmicro %@[{'name': 'Masab Ahmad', 'affiliation': 'University of Connecticut', 'bio': {'p': ['Masab Ahmad is a PhD student in the Electrical and Computer Engineering Department at the University of Connecticut. His research interests include parallel computing, architectures, and workload characterization. Ahmad received an MS in electrical and computer engineering from the University of Connecticut. He is a member of IEEE. Contact him at masab.ahmad@uconn.edu.']}}, {'name': 'Christopher J. Michael', 'affiliation': 'Naval Research Laboratory', 'bio': {'p': ['Christopher J. Michael is a computer engineer at the Naval Research Laboratory. His research interests include heterogeneous computing, special-purpose computer architecture, spatiotemporal data modeling, and large-volume streaming data processing. Michael received a PhD in electrical engineering from Louisiana State University. He is a member of IEEE and ACM. Contact him at chris.michael@nrlssc.navy.mil.']}}, {'name': 'Omer Khan', 'affiliation': 'University of Connecticut', 'bio': {'p': ['Omer Khan is an assistant professor in the Department of Electrical and Computer Engineering at the University of Connecticut. His research interests include hardware-software mechanisms for scalability, concurrency, locality, resiliency, security, and programmability of future massive-scale parallel computing models, architectures, and platforms. Khan received a PhD in electrical and computer engineering from the University of Massachusetts Amherst. He is a member of IEEE and ACM. Contact him at khan@uconn.edu.']}} %*Efficient Situational Scheduling of Graph Workloads on Single-Chip Multicores and GPUs %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7866797 %f/micro/bk8r2fzgajpesy13ycpwvihravdhqosz.pdf %m4b5ee0d1e751190e4d3f438d50486dd6 %cmicro %@[{'name': 'Muhammet Mustafa Ozdal', 'affiliation': 'Bilkent University', 'bio': {'p': ['Muhammet Mustafa Ozdal is an assistant professor in the Department of Computer Engineering at Bilkent University. His research interests include high-performance computing, heterogeneous architectures, and hardware accelerators. Mustafa Ozdal received a PhD in computer science from the University of Illinois at Urbana-Champaign. Contact him at mustafa.ozdal@cs.bilkent.edu.tr.']}}, {'name': 'Serif Yesil', 'affiliation': 'University of Illinois at Urbana-Champaign', 'bio': {'p': ['Serif Yesil is a PhD student in the Computer Science Department at the University of Illinois at Urbana-Champaign. His research interests include computer architecture, heterogeneous architectures, and parallel computing. Yesil received an MS in computer engineering from Bilkent University. Contact him at syesil2@illinois.edu.']}}, {'name': 'Taemin Kim', 'affiliation': 'Intel', 'bio': {'p': ['Taemin Kim is a research scientist in Strategic CAD Labs at Intel. His research interests include accelerator architecture synthesis from high-level specifications. Kim received a PhD in computer engineering from North Carolina State University. He is a member of IEEE and ACM. Contact him at taemin.kim@intel.com.']}}, {'name': 'Andrey Ayupov', 'affiliation': 'Intel', 'bio': {'p': ['Andrey Ayupov is a research scientist in Strategic CAD Labs at Intel. His research interests include hardware agile design, high-level synthesis, and accelerator design. Ayupov received a PhD in computer engineering from the Moscow Institute of Physics and Technology. Contact him at andrey.ayupov@intel.com.']}}, {'name': 'John Greth', 'affiliation': 'Intel', 'bio': {'p': ['John Greth is a logic designer in the Data Center Group at Intel. His research interests include quantitative economics, macroeconomics, and organizational development. Greth received an MS in computer and electrical engineering from Carnegie Mellon University. Contact him at john.greth@intel.com.']}}, {'name': 'Steven Burns', 'affiliation': 'Intel', 'bio': {'p': ['Steven Burns is a senior principal engineer in Strategic CAD Labs at Intel. His interests include large-scale optimization, effective utilization of advanced process technologies, and software-centric flows for designing accelerator hardware. Burns received a PhD in computer science from Caltech. Contact him at steven.m.burns@intel.com.']}}, {'name': 'Ozcan Ozturk', 'affiliation': 'Bilkent University', 'bio': {'p': ['Ozcan Ozturk is an associate professor in the Department of Computer Engineering at Bilkent University. His research interests include accelerators, many-core architectures, parallel computing, and computer architecture. Ozturk received a PhD in computer science and engineering from Pennsylvania State University. Contact him at ozturk@cs.bilkent.edu.tr.']}} %*Graph Analytics Accelerators for Cognitive Systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7866810 %f/micro/rx1aewm92sols8jbynnyd4v3b0vehwk6.pdf %mfef67bccccecf215d48b6c78e319b035 %cmicro %@[{'name': 'Mateja Putic', 'affiliation': 'University of Virginia', 'bio': {'p': ['Mateja Putic is a PhD candidate in the High-Performance Low-Power (HPLP) Lab at the University of Virginia. Putic received an MS in electric engineering from the University of Virginia. He is a member of Eta Kappa Nu. Contact him at mp3t@virginia.edu.']}}, {'name': 'A.J. Varshneya', 'affiliation': 'University of Virginia', 'bio': {'p': ['A.J. Varshneya is an undergraduate research assistant in the HPLP Lab at the University of Virginia. He is a Rodman Scholar and recipient of the James S. Miller Award at the University of Virginia. Contact him at ajv4dg@virginia.edu.']}}, {'name': 'Mircea R. Stan', 'affiliation': 'University of Virginia', 'bio': {'p': ['Mircea R. Stan is a professor in the Charles L. Brown Department of Electrical and Computer Engineering at the University of Virginia, where he leads the HPLP Lab. He also is a co-director of the Center for Automata Processing. Stan received a PhD in electrical and computer engineering from the University of Massachusetts at Amherst. Stan is a Fellow of the IEEE and a member of ACM, and of Eta Kappa Nu, Phi Kappa Phi, and Sigma Xi. Contact him at mircea@virginia.edu.']}} %*Hierarchical Temporal Memory on the Automata Processor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7866798 %f/micro/yjhkvqx94tx1frfmdbicylnoazr5esht.pdf %m5a13e7367f4105abfcc04b03f7b8b4b5 %cmicro %@[{'name': 'Babak Falsafi', 'affiliation': 'EPFL', 'bio': {'p': ['Babak Falsafi is a professor in the Department of Computer and Communication Sciences at EPFL and the founding director of the EcoCloud research center. His research interests include datacenters, emerging technologies, and evaluation methodologies for servers. Falsafi received a PhD in computer science from the University of Wisconsin-Madison. Contact him at babak.falsafi@epfl.ch.']}}, {'name': 'Bill Dally', 'affiliation': 'Stanford University', 'bio': {'p': ['Bill Dally is the Willard R. and Inez Kerr Bell Professor of Computer Science and Electrical Engineering at Stanford University. He is also a chief scientist and senior vice president of research at Nvidia. Dally received a PhD in computer science from Caltech. He has received the ACM Maurice Wilkes Award, the IEEE Seymour Cray Award, and the ACM Eckert-Mauchly Award. He is a member of the National Academy of Engineering and a Fellow of IEEE, ACM, and the American Academy of Arts and Sciences. Contact him at dally@stanford.edu.']}}, {'name': 'Desh Singh', 'affiliation': 'Amazon', 'bio': {'p': ['Desh Singh is a senior manager of software development at Amazon in Toronto. Singh received a PhD in computer engineering from the University of Toronto.']}}, {'name': 'Derek Chiou', 'affiliation': 'Microsoft', 'bio': {'p': ['Derek Chiou is a partner hardware group engineering manager at Microsoft and a research scientist at the University of Texas at Austin. His research interests include accelerating datacenter applications and infrastructure, rapid system design, and fast, accurate simulation. Chiou received a PhD in electrical engineering and computer science from the Massachusetts Institute of Technology. Contact him at derek@ece.utexas.edu.']}}, {'name': 'Joshua J. Yi', 'affiliation': 'Dechert', 'bio': {'p': ['Joshua J. Yi is a patent litigation associate at Dechert. His research interests include highperformance computer architecture and performance methodology. Yi received a PhD in electrical engineering from the University of Minnesota, Minneapolis, and a JD from the University of Texas at Austin. Contact him at joshua.yi@dechert.com.']}}, {'name': 'Resit Sendag', 'affiliation': 'University of Rhode Island', 'bio': {'p': ['Resit Sendag is a professor of electrical and computer engineering at the University of Rhode Island. His research interests include microarchitecture, memory systems, and simulation techniques. Sendag received a PhD in electrical engineering from the University of Minnesota, Minneapolis. Contact him at sendag@ele.uri.edu.']}} %*FPGAs versus GPUs in Data centers %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7866802 %f/micro/uhk7aeomcvtjpnr9gs3i8nzm4yhaqdiz.pdf %m09968bb2c363b84cea292476df937a42 %cmicro %@[{'name': 'Richard Mateosian', 'bio': {'p': ['Richard Mateosian is a freelance technical writer in the San Francisco Bay Area. Contact him at xrmxrm@gmail.com.']}} %*Resistance Is Futile %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7866806 %f/micro/ojsm4auee2zik3dy5gwr80xo6kujhblq.pdf %m4275c571853d0d8460fc378265e5ae0d %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'Harvard Business School', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/7866793/7866808/7866808-photo-1-small.gif', 'p': ['Shane Greenstein is a professor at the Harvard Business School. Contact him at sgreenstein@hbs.edu.']}} %*Technology Policy and the Trump Administration %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7866808 %f/micro/ogbyuawvqsorenjeaz4urnhdjg6p5f8v.pdf %m6399c973394f37a165554fd7911dddc7 %cmicro %@[{'name': 'Lieven Eeckhout', 'affiliation': 'Ghent University', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/7924209/7924283/7924283-photo-1-small.gif', 'p': ['Lieven Eeckhout is a professor in the Department of Electronics and Information Systems at Ghent University. Contact him at lieven.eeckhout@ugent.be.']}} %*Hot Chips: Industry and Academia Cutting-Edge Microprocessors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7924283 %f/micro/1fzt9q6osyggixiusa02djq7ccjwk5xv.pdf %mb743a15047ed36d1c07f45491935019a %cmicro %@[{'name': 'Bryan Chin', 'affiliation': 'OnRamp BioInformatics'}, {'name': 'Subhasish Mitra', 'affiliation': 'Stanford University'} %*Hot Chips 28 %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7924245 %f/micro/lrnztnqekqzgejxoy5hkcvmsi3carw2j.pdf %m750b885bdaaf44246653a34e31c804b4 %cmicro %@[{'name': 'Denis Foley', 'affiliation': 'Nvidia'}, {'name': 'John Danskin', 'affiliation': 'Nvidia'} %*Ultra-Performance Pascal GPU and NVLink Interconnect %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7924274 %f/micro/sbkfhljgsdprocwofmvqrl0k5bxt6xa2.pdf %m07abe23025029dd33d71805cdc9a2bca %cmicro %@[{'name': 'Kaiyuan Guo', 'affiliation': 'Tsinghua University and DeePhi'}, {'name': 'Song Han', 'affiliation': 'Stanford University and DeePhi'}, {'name': 'Song Yao', 'affiliation': 'DeePhi'}, {'name': 'Yu Wang', 'affiliation': 'Tsinghua University and DeePhi'}, {'name': 'Yuan Xie', 'affiliation': 'University of California, Santa Barbara'}, {'name': 'Huazhong Yang', 'affiliation': 'Tsinghua University'} %*Software-Hardware Codesign for Efficient Neural Network Acceleration %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7924276 %f/micro/al6cy5dmjs08lrmfu9powkbihrgzvqst.pdf %m77a7494e46de8baf4da6f7d7b4dee610 %cmicro %@[{'name': 'Nigel Stephens', 'affiliation': 'ARM'}, {'name': 'Stuart Biles', 'affiliation': 'ARM'}, {'name': 'Matthias Boettcher', 'affiliation': 'ARM'}, {'name': 'Jacob Eapen', 'affiliation': 'ARM'}, {'name': 'Mbou Eyole', 'affiliation': 'ARM'}, {'name': 'Giacomo Gabrielli', 'affiliation': 'ARM'}, {'name': 'Matt Horsnell', 'affiliation': 'ARM'}, {'name': 'Grigorios Magklis', 'affiliation': 'ARM'}, {'name': 'Alejandro Martinez', 'affiliation': 'ARM'}, {'name': 'Nathanael Premillieu', 'affiliation': 'ARM'}, {'name': 'Alastair Reid', 'affiliation': 'ARM'}, {'name': 'Alejandro Rico', 'affiliation': 'ARM'}, {'name': 'Paul Walker', 'affiliation': 'ARM'} %*The ARM Scalable Vector Extension %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7924233 %f/micro/2s3d0rvzmyqomkptujai8ewrlb9pkfjy.pdf %m1cd2e53f2a9da3d8d9a4c0c06ecf5d06 %cmicro %@[{'name': 'Satish Kumar Sadasivam', 'affiliation': 'IBM'}, {'name': 'Brian W. Thompto', 'affiliation': 'IBM'}, {'name': 'Ron Kalla', 'affiliation': 'IBM'}, {'name': 'William J. Starke', 'affiliation': 'IBM'} %*IBM Power9 Processor Architecture %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7924241 %f/micro/wuoixcvfvcjbk6sa3nkd5mpdzmsba4th.pdf %m25770fdc6ff654f6bddd2eb19bdc4fa6 %cmicro %@[{'name': 'Jack Doweck', 'affiliation': 'Intel'}, {'name': 'Wen-Fu Kao', 'affiliation': 'Intel'}, {'name': 'Allen Kuan-yu Lu', 'affiliation': 'Intel'}, {'name': 'Julius Mandelblat', 'affiliation': 'Intel'}, {'name': 'Anirudha Rahatekar', 'affiliation': 'Intel'}, {'name': 'Lihu Rappoport', 'affiliation': 'Intel'}, {'name': 'Efraim Rotem', 'affiliation': 'Intel'}, {'name': 'Ahmad Yasin', 'affiliation': 'Intel'}, {'name': 'Adi Yoaz', 'affiliation': 'Intel'} %*Inside 6th-Generation Intel Core: New Microarchitecture Code-Named Skylake %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7924286 %f/micro/ctgdc4vx0lepbw2jva3onb7zqk9mnazg.pdf %mf4383e731df068aca9fda7c7cda350dc %cmicro %@[{'name': 'Brent Bohnenstiehl', 'affiliation': 'University of California, Davis'}, {'name': 'Aaron Stillmaker', 'affiliation': 'University of California, Davis'}, {'name': 'Jon Pimentel', 'affiliation': 'University of California, Davis'}, {'name': 'Timothy Andreas', 'affiliation': 'University of California, Davis'}, {'name': 'Bin Liu', 'affiliation': 'University of California, Davis'}, {'name': 'Anh Tran', 'affiliation': 'University of California, Davis'}, {'name': 'Emmanuel Adeagbo', 'affiliation': 'University of California, Davis'}, {'name': 'Bevan Baas', 'affiliation': 'University of California, Davis'} %*KiloCore: A Fine-Grained 1,000-Processor Array for Task-Parallel Applications %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7924211 %f/micro/ywsimeiebkfhzdbpvadxyqc73sjphmul.pdf %m32d304a2664da6405a245e441feae9e0 %cmicro %@[{'name': 'Michael McKeown', 'affiliation': 'Princeton University'}, {'name': 'Yaosheng Fu', 'affiliation': 'Princeton University'}, {'name': 'Tri Nguyen', 'affiliation': 'Princeton University'}, {'name': 'Yanqi Zhou', 'affiliation': 'Princeton University'}, {'name': 'Jonathan Balkind', 'affiliation': 'Princeton University'}, {'name': 'Alexey Lavrov', 'affiliation': 'Princeton University'}, {'name': 'Mohammad Shahrad', 'affiliation': 'Princeton University'}, {'name': 'Samuel Payne', 'affiliation': 'Princeton University'}, {'name': 'David Wentzlaff', 'affiliation': 'Princeton University'} %*Piton: A Manycore Processor for Multitenant Clouds %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7924281 %f/micro/793squo8uncadbhbzjxsfvtlfjdy5z12.pdf %me8eda12e1370d2d6c3ce1553df727e63 %cmicro %@[{'name': 'Richard H. Stern', 'affiliation': 'George Washington University Law School'} %*FTC and Apple Sue Qualcomm for Cell Phone Standardization Skullduggery: Part 1 %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7924238 %f/micro/kdmbjsv6exlucv4wnijh0yoeq5szflqr.pdf %m45fda250bfed092bb410aa23b4cde644 %cmicro %@[{'name': 'Stavros Volos', 'affiliation': 'Microsoft Research'}, {'name': 'Djordje Jevdjic', 'affiliation': 'University of Washington'}, {'name': 'Babak Falsafi', 'affiliation': 'EPFL'}, {'name': 'Boris Grot', 'affiliation': 'University of Edinburgh'} %*Fat Caches for Scale-Out Servers %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7924260 %f/micro/rqkutyfmpynazqedcnghjtiswmbe7il9.pdf %m2e792e773881626c13e56cf649e5c5e0 %cmicro %@[{'name': 'Margaret Martonosi', 'affiliation': 'Princeton University'} %*2016 Maurice Wilkes Award Given to Timothy Sherwood %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7924282 %f/micro/crdzv7lbqisndyeznjh4tuphxm03va9p.pdf %m3f786874320f33ae978b2e2aaf1ef8cc %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'Harvard Business School', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/7924209/7924287/7924287-photo-1-small.gif', 'p': ['Shane Greenstein is a professor at the Harvard Business School. Contact him at sgreenstein@hbs.edu.']}} %*The Value of Free in GDP %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7924287 %f/micro/rfhzwzjhmlxavepnygyogxbj7u1mt0ew.pdf %ma17bc711e0d5e21d9ffec00d10f66e8a %cmicro %@[{'name': 'Lieven Eeckhout', 'affiliation': 'Ghent University', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/7948654/7948685/7948685-photo-1-small.gif', 'p': ['Lieven Eeckhout is a professor in the Department of Electronics and Information Systems at Ghent University. Contact him at lieven.eeckhout@ugent.be.']}} %*Thoughts on the Top Picks Selections %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7948685 %f/micro/fgdzyajp0c8tic3knerjmbzrwkoeladp.pdf %m650c68d9785f92ddbfdd9302b7783f83 %cmicro %@[{'name': 'Aamer Jaleel', 'affiliation': 'Nvidia', 'bio': {'p': ['Aamer Jaleel is a principal research scientist at Nvidia. Contact him at ajaleel@nvidia.com.']}}, {'name': 'Moinuddin Qureshi', 'affiliation': 'Georgia Tech', 'bio': {'p': ['Moinuddin Qureshi is an associate professor in the School of Electrical and Computer Engineering at Georgia Tech. Contact him at moin@ece.gatech.edu.']}} %*Top Picks from the 2016 Computer Architecture Conferences %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7948670 %f/micro/dgxzbnkfjpgh3ljshyqoe5m6norbt81q.pdf %m65ded22a6854b29179976138fe5cade6 %cmicro %@[{'name': 'Yu-Hsin Chen', 'affiliation': 'Massachusetts Institute of Technology', 'bio': {'p': ['Yu-Hsin Chen is a PhD student in the Department of Electrical Engineering and Computer Science at the Massachusetts Institute of Technology. His research interests include energy-efficient multimedia systems, deep learning architectures, and computer vision. Chen received an MS in electrical engineering and computer science from the Massachusetts Institute of Technology. He is a student member of IEEE. Contact him at yhchen@mit.edu.']}}, {'name': 'Joel Emer', 'affiliation': 'Nvidia and Massachusetts Institute of Technology', 'bio': {'p': ['Joel Emer is a senior distinguished research scientist at Nvidia and a professor of electrical engineering and computer science at the Massachusetts Institute of Technology. His research interests include spatial and parallel architectures, performance modeling, reliability analysis, and memory hierarchies. Emer received a PhD in electrical engineering from the University of Illinois. He is a Fellow of IEEE. Contact him at jsemer@mit.edu.']}}, {'name': 'Vivienne Sze', 'affiliation': 'Massachusetts Institute of Technology', 'bio': {'p': ['Vivienne Sze is an assistant professor in the Department of Electrical Engineering and Computer Science at the Massachusetts Institute of Technology. Her research interests include energy-aware signal processing algorithms and low-power architecture and system design for multimedia applications, such as machine learning, computer vision, and video coding. Sze received a PhD in electrical engineering from the Massachusetts Institute of Technology. She is a senior member of IEEE. Contact her at sze@mit.edu.']}} %*Using Dataflow to Optimize Energy Efficiency of Deep Neural Network Accelerators %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7948671 %f/micro/rl2ft5ecqemxsziawlj9itovzh8pfgdr.pdf %m77e81fa3bad85a66d9fd146e62b97c38 %cmicro %@[{'name': 'Mahdi Nazm Bojnordi', 'affiliation': 'University of Utah', 'bio': {'p': ['Mahdi Nazm Bojnordi is an assistant professor in the School of Computing at the University of Utah. His research focuses on computer architecture, with an emphasis on energy-efficient computing. Nazm Bojnordi received a PhD in electrical engineering from the University of Rochester. Contact him at bojnordi@cs.utah.edu.']}}, {'name': 'Engin Ipek', 'affiliation': 'University of Rochester', 'bio': {'p': ['Engin Ipek is an associate professor in the Department of Electrical and Computer Engineering and the Department of Computer Science at the University of Rochester. His research interests include energy-efficient architectures, high-performance memory systems, and the application of emerging technologies to computer systems. Ipek received a PhD in electrical and computer engineering from Cornell University. He has received the 2014 IEEE Computer Society TCCA Young Computer Architect Award, two IEEE Micro Top Picks awards, and an NSF CAREER award. Contact him at ipek@ece.rochester.edu.']}} %*The Memristive Boltzmann Machines %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7948667 %f/micro/junxoosw0vipmmsfly8tlignavdp4zqc.pdf %mc919113c8f660d3c68c272ce861975a1 %cmicro %@[{'name': 'Yipeng Huang', 'affiliation': 'Columbia University', 'bio': {'p': ['Yipeng Huang is a PhD candidate in the Computer Architecture and Security Technologies Lab at Columbia University. His research interests include applications of analog computing and benchmarking of robotic systems. Huang has an MPhil in computer science from Columbia University. He is a member of the IEEE Computer Society and ACM SIGARCH. Contact him at yipeng@cs.columbia.edu.']}}, {'name': 'Ning Guo', 'affiliation': 'Columbia University', 'bio': {'p': ['Ning Guo is a hardware engineer at Cognescent. His research interests include continuous-time analog/hybrid computing and energy-efficient approximate computing. Guo received a PhD in electrical engineering from Columbia University, where he performed the work for this article. Contact him at ng2364@columbia.edu.']}}, {'name': 'Mingoo Seok', 'affiliation': 'Columbia University', 'bio': {'p': ['Mingoo Seok is an assistant professor in the Department of Electrical Engineering at Columbia University. His research interests include low-power, adaptive, and cognitive VLSI systems design. Seok received a PhD in electrical engineering from the Univer-sity of Michigan, Ann Arbor. He has received an NSF CAREER award and is a member of IEEE. Contact him at mgseok@ee.columbia.edu.']}}, {'name': 'Yannis Tsividis', 'affiliation': 'Columbia University', 'bio': {'p': ['Yannis Tsividis is the Edwin Howard Armstrong Professor of Electrical Engineering at Columbia University. His research interests include analog and hybrid analog/digital integrated circuit design for computation and signal processing. Tsividis received a PhD in electrical engineering from the University of California, Berkeley. He is a Life Fellow of IEEE. Contact him at tsividis@ee.columbia.edu.']}}, {'name': 'Simha Sethumadhavan', 'affiliation': 'Columbia University', 'bio': {'p': ['Simha Sethumadhavan is an associate professor in the Department of Computer Science at Columbia University. His research interests include computer architecture and computer security. Sethumadhavan received a PhD in computer science from the University of Texas at Austin. He has received an Alfred P. Sloan fellowship and an NSF CAREER award. Contact him at simha@cs.columbia.edu.']}} %*Analog Computing in a Modern Context: A Linear Algebra Accelerator Case Study %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7948662 %f/micro/ocmqjgyzl9ombbiehkk5urs08dexjna6.pdf %mb84bc3a68bfbe9c571d563a16f8cf30f %cmicro %@[{'name': 'Tony Nowatzki', 'affiliation': 'University of California, Los Angeles', 'bio': {'p': ['Tony Nowatzki is an assistant professor in the Department of Computer Science at the University of California, Los Angeles. His research interests include architecture and compiler codesign and mathematical modeling. Nowatzki received a PhD in computer science from the University of Wisconsin-Madison. He is a member of IEEE. Contact him at tjn@cs.ucla.edu.']}}, {'name': 'Vinay Gangadhar', 'affiliation': 'University of Wisconsin-Madison', 'bio': {'p': ['Vinay Gangadhar is a PhD student in the Department of Electrical and Computer Engineering at the University of Wiscon-sin-Madison. His research interests include hardware/software codesign of programmable accelerators, microarchitecture, and GPU computing. Gangadhar received an MS in electrical and computer engineering from the University of Wisconsin-Madison. He is a student member of IEEE. Contact him at vinay@cs.wisc.edu.']}}, {'name': 'Karthikeyan Sankaralingam', 'affiliation': 'University of Wisconsin-Madison', 'bio': {'p': ['Karthikeyan Sankaralingam is an associate professor in the Department of Computer Sciences and the Department of Electrical and Computer Engineering at the University of Wisconsin—Madison, where he also leads the Vertical Research Group. His research interests include microarchitecture, architecture, and very large-scale integration. Sankaralingam received a PhD in computer science from the University of Texas at Austin. He is a senior member of IEEE. Contact him at karu@cs.wisc.edu.']}}, {'name': 'Greg Wright', 'affiliation': 'Qualcomm Research', 'bio': {'p': ['Greg Wright is the director of engineering at Qualcomm Research. His research interests include processor architecture, virtual machines, compilers, parallel algorithms, and memory models. Wright received a PhD in computer science from the University of Manchester. Contact him at gwright@qti.qualcomm.com.']}} %*Domain Specialization Is Generally Unnecessary for Accelerators %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7948663 %f/micro/hoqakgsbolyabgvfetrzjd5nhxjy2k7w.pdf %m4684e74b3600be2c952a81d0a2f5168b %cmicro %@[{'name': 'Adrian M. Caulfield', 'affiliation': 'Microsoft', 'bio': {'p': ['Adrian M. Caulfield is a principal research hardware development engineer at Microsoft Research. His research interests include computer architecture and reconfigurable computing. Caulfield received a PhD in computer engineering from the University of California, San Diego. Contact him at acaulfie@microsoft.com.']}}, {'name': 'Eric S. Chung', 'affiliation': 'Microsoft', 'bio': {'p': ['Eric S. Chung is a researcher at Microsoft Research NExT, where he leads an effort to accelerate large-scale machine learning using FPGAs. Chung received a PhD in electrical and computer engineering from Carnegie Mellon University. Contact him at erchung@microsoft.com.']}}, {'name': 'Andrew Putnam', 'affiliation': 'Microsoft', 'bio': {'p': ['Andrew Putnam is a principal research hardware development engineer at Microsoft Research NExT. His research interests include reconfigurable computing, future datacenter design, and computer architecture. Putnam received a PhD in computer science and engineering from the University of Washington. Contact him at anputnam@microsoft.com.']}}, {'name': 'Hari Angepat', 'affiliation': 'Microsoft', 'bio': {'p': ['Hari Angepat is a senior software engineer at Microsoft and a PhD candidate at the University of Texas at Austin. His research interests include novel FPGA accelerator architectures, hardware/software codesign techniques, and approaches for flexible hardware design. Angepat received an MS in computer engineering from the University of Texas at Austin. Contact him at haangepa@microsoft.com.']}}, {'name': 'Daniel Firestone', 'affiliation': 'Microsoft', 'bio': {'p': ['Daniel Firestone is the tech lead and manager for the Azure Networking Host SDN team at Microsoft. His team builds the Azure virtual switch and SmartNIC. Contact him at fstone@microsoft.com.']}}, {'name': 'Jeremy Fowers', 'affiliation': 'Microsoft', 'bio': {'p': ['Jeremy Fowers is a senior research hardware design engineer in the Catapult team at Microsoft Research NeXT. He specializes in the design and implementation of FPGA accelerators across a variety of application domains, and is currently focused on machine learning. Fowers received a PhD in electrical engineering from the University of Florida. Contact him at jfowers@microsoft.com.']}}, {'name': 'Michael Haselman', 'affiliation': 'Microsoft', 'bio': {'p': ['Michael Haselman is a senior software engineer at Microsoft ASG (Bing). His research interests include FPGAs, computer architecture, and distributed computing. Haselman received a PhD in electrical engineering from the University of Washington. Contact him at mikehase@microsoft.com.']}}, {'name': 'Stephen Heil', 'affiliation': 'Microsoft', 'bio': {'p': ['Stephen Heil is a principal program manager at Microsoft Research. His research interests include field-programmable gate arrays, application accelerators, and rack-scale system design. Heil received a BS in electrical engineering technology and computer science from the College of New Jersey (formerly Trenton State College). Contact him at stephen.heil@microsoft.com.']}}, {'name': 'Matt Humphrey', 'affiliation': 'Microsoft', 'bio': {'p': ['Matt Humphrey is a principal engineer at Microsoft, where he works on Azure. His research interests include analog and digital electronics and the architecture of high-scale distributed software systems. Humphrey received an MS in electrical engineering from the Georgia Institute of Technology. Contact him at mhumphr@microsoft.com.']}}, {'name': 'Puneet Kaur', 'affiliation': 'Microsoft', 'bio': {'p': ['Puneet Kaur is a principal software engineer at Microsoft. Her research interests include distributed systems and scalability. Kaur received a MTech in computer science from the Indian Institute of Technology, Kanpur. Contact her at punekaur@microsoft.com.']}}, {'name': 'Joo-Young Kim', 'affiliation': 'Microsoft', 'bio': {'p': ['Joo-Young Kim is a senior research hardware development engineer at Microsoft Research. His research interests include high-performance, energy-efficient computer architectures for various datacenter workloads, such as data compression, video trans-coding, and machine learning. Kim received a PhD in electrical engineering from Korea Advanced institute of Science and Technology (KAIST). Contact him at jooyoung@microsoft.com.']}}, {'name': 'Daniel Lo', 'affiliation': 'Microsoft', 'bio': {'p': ['Daniel Lo is a research hardware development engineer at Microsoft Research. His research interests include designing highperformance accelerators on FPGAs. Lo received a PhD in electrical and computer engineering from Cornell University. Contact him at dlo@microsoft.com.']}}, {'name': 'Todd Massengill', 'affiliation': 'Microsoft', 'bio': {'p': ['Todd Massengill is a senior hardware design engineer at Microsoft Research. His research interests include hardware acceleration of artificial intelligence applications, biologically inspired computing, and tools to improve hardware engineering design, collaboration, and efficiency. Massengill received an MS in electrical engineering from the University of Washington. Contact him at toddma@microsoft.com.']}}, {'name': 'Kalin Ovtcharov', 'affiliation': 'Microsoft', 'bio': {'p': ['Kalin Ovtcharov is a research hardware development engineer at Microsoft Research NeXT. His research interests include accelerating computationally intensive tasks on FPGAs in areas such as machine learning, image processing, and video compression. Ovtcharov received a BS in computer engineering from McMaster University. Contact him at kaovt@microsoft.com.']}}, {'name': 'Michael Papamichael', 'affiliation': 'Microsoft', 'bio': {'p': ["Michael Papamichael is a researcher at Microsoft Research, where he's working on the Catapult project. His research interests include hardware acceleration, reconfigurable computing, on-chip interconnects, and methodologies to facilitate hardware specialization. Papamichael received a PhD in computer science from Carnegie Mellon University. Contact him at papamix@microsoft.com."]}}, {'name': 'Lisa Woods', 'affiliation': 'Microsoft', 'bio': {'p': ['Lisa Woods is a principal program manager for the Catapult project at Microsoft Research, where she focuses on driving strategic alignment between the Catapult team and its many internal and external partners as well as scalability and execution for the project. Woods received an MS in computer science. Contact her at lisa.woods@microsoft.com.']}}, {'name': 'Sitaram Lanka', 'affiliation': 'Microsoft', 'bio': {'p': ['Sitaram Lanka is a partner group engineering manager in Search Platform at Microsoft Bing. His research interests include web and enterprise search, large-scale distributed systems, machine learning, and reconfigurable hardware in datacenters. Lanka received a PhD in computer science from the University of Pennsylvania. Contact him at slanka@microsoft.com.']}}, {'name': 'Derek Chiou', 'affiliation': 'Microsoft', 'bio': {'p': ['Derek Chiou is a partner hardware group engineering manager at Microsoft and a research scientist at the University of Texas at Austin. His research interests include accelerating datacenter applications and infrastructure, rapid system design, and fast, accurate simulation. Chiou received a PhD in electrical engineering and computer science from the Massachusetts Institute of Technology. Contact him at dechiou@microsoft.com.']}}, {'name': 'Doug Burger', 'affiliation': 'Microsoft', 'bio': {'p': ['Doug Burger is a distinguished engineer at Microsoft, where he leads a Disruptive Systems team at Microsoft Research NExT and cofounded Project Catapult. Burger received a PhD in computer science from the University of Wisconsin. He is an IEEE and ACM Fellow. Contact him at dburger@microsoft.com.']}} %*Configurable Clouds %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7948672 %f/micro/0ruahceqxomwmdxf5zvogr2c6ifytngi.pdf %m370de85910034108a3ba92c18470fd26 %cmicro %@[{'name': 'Moein Khazraee', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Moein Khazraee is a PhD candidate in the Department of Computer Science and Engineering at the University of California, San Diego. His research interests include ASIC Clouds, NRE, and specialization. Khazraee received an MS in computer science from the University of California, San Diego. Contact him at mkhazraee@ucsd.edu.']}}, {'name': 'Luis Vega Gutierrez', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Luis Vega Gutierrez is a staff research associate in the Department of Computer Science and Engineering at the University of California, San Diego. His research interests include ASIC Clouds, low-cost ASIC design, and systems. Vega received an MSc in electrical and computer engineering from the University of Kaiserslautern, Germany. Contact him at lvgutierrez@ucsd.edu.']}}, {'name': 'Ikuo Magaki', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Ikuo Magaki is an engineer at Apple. He performed the work for this article as a Toshiba visiting scholar in the Department of Computer Science and Engineering at the University of California, San Diego. His research interests include ASIC design and ASIC Clouds. Magaki received an MSc in computer science from Keio University, Japan. Contact him at ikuo.magaki@icloud.com.']}}, {'name': 'Michael Bedford Taylor', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Michael Bedford Taylor advises his PhD students at various well-known west coast universities. He performed the work for this article while at the University of California, San Diego. His research interests include tiled multicore architecture, dark silicon, HLS accelerators for mobile, Bitcoin mining hardware, and ASIC Clouds. Taylor received a PhD in electrical engineering and computer science from the Massachusetts Institute of Technology. Contact him at profmbt@uw.edu.']}} %*Specializing a Planet's Computation: ASIC Clouds %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7948657 %f/micro/gxrtqwjnixk2sqwmcgrvedbbfeokl81n.pdf %mf052cec72fc27b78af276d1b3e44c79a %cmicro %@[{'name': 'Mingyu Gao', 'affiliation': 'Stanford University', 'bio': {'p': ['Mingyu Gao is a PhD student in the Department of Electrical Engineering at Stanford University. His research interests include energy-efficient computing and memory systems, specifically on practical and efficient near-data processing for data-intensive analytics applications, high-density and low-power reconfigurable architectures for datacenter services, and scalable accelerators for large-scale neural networks. Gao received an MS in electrical engineering from Stanford University. He is a student member of IEEE. Contact him at mgao12@stanford.edu.']}}, {'name': 'Christina Delimitrou', 'affiliation': 'Cornell University', 'bio': {'p': ['Christina Delimitrou is an assistant professor in the Departments of Electrical and Computer Engineering and Computer Science at Cornell University, where she works on computer architecture and distributed systems. Her research interests include resource-efficient datacenters, scheduling and resource management with quality-of-service guarantees, disaggregated cloud architectures, and cloud security. Delimitrou received a PhD in electrical engineering from Stanford University. She is a member of IEEE and ACM. Contact her at delimitrou@cornell.edu.']}}, {'name': 'Dimin Niu', 'affiliation': 'Samsung Semiconductor', 'bio': {'p': ['Dimin Niu is a senior memory architect in the Memory Solutions Lab in the US R&D center at Samsung Semiconductor. His research interests include computer architecture, emerging nonvolatile memory technologies, and processing near-/in-memory architecture. Niu received a PhD in computer science and engineering from Pennsylvania State University. Contact him at dimin.niu@ssi.samsung.com.']}}, {'name': 'Krishna T. Malladi', 'affiliation': 'Samsung Semiconductor', 'bio': {'p': ['Krishna T. Malladi is a staff architect in the Memory Solutions Lab in the US R&D center at Samsung Semiconductor. His research interests include next-generation memory and storage systems for datacenter platforms. Malladi received a PhD in electrical engineering from Stanford University. Contact him at k.tej@ssi.samsung.com.']}}, {'name': 'Hongzhong Zheng', 'affiliation': 'Samsung Semiconductor', 'bio': {'p': ['Hongzhong Zheng is a senior manager in the Memory Solutions Lab in the US R&D center at Samsung Semiconductor. His research interests include novel memory system architecture with DRAM and emerging memory technologies, processing in-memory architecture for machine learning applications, computer architecture and system performance modeling, and energy-efficient computing system designs. Zheng received a PhD in electrical and computer engineering from the University of Illinois at Chicago. He is a member of IEEE and ACM. Contact him at hz.zheng@ssi.samsung.com.']}}, {'name': 'Bob Brennan', 'affiliation': 'Samsung Semiconductor', 'bio': {'p': ['Bob Brennan is the senior vice president of the Memory Solutions Lab in the US R&D center at Samsung Semiconductor. He has led numerous research projects on memory system architecture, SoC architecture, CPU validation, and low-power system design. Brennan received an MS in electrical engineering from the University of Virginia. Contact him at bob.brennan@ssi.samsung.com.']}}, {'name': 'Christos Kozyrakis', 'affiliation': 'Stanford University', 'bio': {'p': ['Christos Kozyrakis is an associate professor in the Departments of Electrical Engineering and Computer Science at Stanford University, where he investigates hardware architectures, system software, and programming models for systems ranging from cell phones to warehouse-scale datacenters. His research interests include resource-efficient cloud computing, energy-efficient computing and memory systems for emerging workloads, and scalable operating systems. Kozyrakis has a PhD in computer science from the University of California, Berkeley. He is a fellow of IEEE and ACM. Contact him at kozyraki@stanford.edu.']}} %*DRAF: A Low-Power DRAM-Based Reconfigurable Acceleration Fabric %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7948664 %f/micro/sevzjaytedfxcpmc93akblxthnu65b0z.pdf %m410a95b42166a0966b8d250c8eec5025 %cmicro %@[{'name': 'Jayneel Gandhi', 'affiliation': 'University of Wisconsin-Madison', 'bio': {'p': ['Jayneel Gandhi is a research scientist at VMware Research. His research interests include computer architecture, operating systems, memory system design, virtual memory, and virtualization. Gandhi has a PhD in computer sciences from the University of Wisconsin-Madison, where he completed the work for this article. He is a member of ACM. Contact him at gandhij@vmware.com.']}}, {'name': 'Mark D. Hill', 'affiliation': 'University of Wisconsin-Madison', 'bio': {'p': ['Mark D. Hill is the John P. Morgridge Professor, Gene M. Amdahl Professor of Computer Sciences, and Computer Sciences Department Chair at the University of W is-consin-Madison, where he also has a courtesy appointment in the Department of Electrical and Computer Engineering. His research interests include parallel computer system design, memory system design, and computer simulation. Hill has a PhD in computer science from the University of California, Berkeley. He is a fellow of IEEE and ACM. He serves as vice chair of the Computer Community Consortium. Contact him at markhill@cs.wisc.edu.']}}, {'name': 'Michael M. Swift', 'affiliation': 'University of Wisconsin-Madison', 'bio': {'p': ['Michael M. Swift is an associate professor in the Computer Sciences Department at the University of Wisconsin—Madison. His research interests include operating system reliability, the interaction of architecture and operating systems, and device driver architecture. Swift has a PhD in computer science from the University of Washington. He is a member of ACM. Contact him at swift@cs.wisc.edu.']}} %*Agile Paging for Efficient Memory Virtualization %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7948666 %f/micro/gwxspyl9ctv30omsfq76irzdkhjuaqwy.pdf %m6f3eac32190e8bf04d3e4ffb34b2b061 %cmicro %@[{'name': 'Daniel Lustig', 'affiliation': 'Princeton University', 'bio': {'p': ['Daniel Lustig is a research scientist at Nvidia. His research interests include computer architecture and memory consistency models. Lustig received a PhD in electrical engineering from Princeton University, where he performed the work for this article. He is a member of IEEE and ACM. Contact him at dlustig@nvidia.com.']}}, {'name': 'Geet Sethi', 'affiliation': 'Rutgers University', 'bio': {'p': ['Geet Sethi is a PhD student in the Department of Computer Science at Stanford University. His research interests include serverless computing, machine learning, and computer architecture. Sethi received a BS in computer science and mathematics from Rutgers University, where he performed the work for this article. He is a student member of IEEE and ACM. Contact him at geet@cs.stanford.edu.']}}, {'name': 'Abhishek Bhattacharjee', 'affiliation': 'Rutgers University', 'bio': {'p': ['Abhishek Bhattacharjee is an associate professor in the Department of Computer Science at Rutgers University. His research interests span the hardware-software interface. Bhattacharjee received a PhD in electrical engineering from Princeton University. He is a member of IEEE and ACM. Contact him at abhib@cs.rutgers.edu.']}}, {'name': 'Margaret Martonosi', 'affiliation': 'Princeton University', 'bio': {'p': ["Margaret Martonosi is the Hugh Trumbull Adams'35 Professor of Computer Science at Princeton University. Her research interests include computer architecture and mobile computing, with an emphasis on power-efficient heterogeneous systems. Martonosi has a PhD in electrical engineering from Stanford University. She is a Fellow of IEEE and ACM. Contact her at mrm@princeton.edu."]}} %*Transistency Models: Memory Ordering at the Hardware-OS Interface %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7948679 %f/micro/iy09p8zdvpi6yf5znwala7xqtgkljgb4.pdf %m9292a5ba786c96a405d12fe14f664e9d %cmicro %@[{'name': 'James Bornholt', 'affiliation': 'University of Washington', 'bio': {'p': ['James Bornholt is a PhD student in the Paul G. Allen School of Computer Science and Engineering at the University of Washington. His research interests include programming languages and formal methods, focusing on program synthesis. Bornholt received an MS in computer science from the University of Washington. Contact him at bornholt@cs.washington.edu.']}}, {'name': 'Randolph Lopez', 'affiliation': 'University of Washington', 'bio': {'p': ['Randolph Lopez is a graduate student in bioengineering at the University of Washington. His research interests include the intersection of synthetic biology, DNA nanotechnology, and molecular diagnostics. Lopez received a BS in bioengineering from the University of California, San Diego. Contact him at rmlb@uw.edu.']}}, {'name': 'Douglas M. Carmean', 'affiliation': 'Microsoft', 'bio': {'p': ['Douglas M. Carmean is a partner architect at Microsoft. His research interests include new architectures on future device technology. Carmean received a BS in electrical and electronics engineering from Oregon State University. Contact him at dcarmean@microsoft.com.']}}, {'name': 'Luis Ceze', 'affiliation': 'University of Washington', 'bio': {'p': ['Luis Ceze is the Torode Family Associate Professor in the Paul G. Allen School of Computer Science and Engineering at the University of Washington. His research interests include the intersection between computer architecture, programming languages, and biology. Ceze received a PhD in computer science from the University of Illinois at Urbana—Champaign. Contact him at luisceze@cs.washington.edu.']}}, {'name': 'Georg Seelig', 'affiliation': 'University of Washington', 'bio': {'p': ['Georg Seelig is an associate professor in the Department of Electrical Engineering and the Paul G. Allen School of Computer Science and Engineering at the University of Washington. His research interests include understanding how biological organisms process information using complex biochemical networks and how such networks can be engineered to program cellular behavior. Seelig received a PhD in physics from the University of Geneva. Contact him at gseelig@uw.edu.']}}, {'name': 'Karin Strauss', 'affiliation': 'Microsoft Research', 'bio': {'p': ['Karin Strauss is a senior researcher at Microsoft Research and an affiliate faculty at the University of Washington. Her research interests include studying the application of biological mechanisms and other emerging technologies to storage and computation, and building systems that are efficient and reliable with them. Strauss received a PhD in computer science from the University of Illinois at Urbana—Champaign. Contact her at kstrauss@microsoft.com.']}} %*Toward a DNA-Based Archival Storage System %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7948677 %f/micro/gnwj0pv4m7r6huteypiuos1xyikdlltf.pdf %m8013ac57b4d032b8c5cdaefd1c813a63 %cmicro %@[{'name': 'Yazhou Zu', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ['Yazhou Zu is aPhD student in the Department of Electrical and Computer Engineering at the University of Texas at Austin. His research interests include resilient and energy-efficient processor design and management. Zu received a BS in microelectronics from Shanghai Jiao Tong University of China. Contact him at yazhou.zu@utexas.edu.']}}, {'name': 'Wei Huang', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ['Wei Huang is a staff researcher at Advanced Micro Devices Research, where he works on energy-efficient processors and systems. Huang received a PhD in electrical and computer engineering from the University of Virginia. He is a member of IEEE. Contact him at wein.huang@amd.com.']}}, {'name': 'Indrani Paul', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ['Indrani Paul is a principal member of the technical staff at Advanced Micro Devices, where she leads the Advanced Power Management group, which focuses on innovating future power and thermal management approaches, system-level power modeling, and APIs. Paul received a PhD in electrical and computer engineering from the Georgia Institute of Technology. Contact her at indrani.paul@amd.com.']}}, {'name': 'Vijay Janapa Reddi', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ['Vijay Janapa Reddi is an assistant professor in the Department of Electrical and Computer Engineering at the University of Texas at Austin. His research interests span the definition of computer architecture, including software design and optimization, to enhance mobile quality of experience and improve the energy efficiency of high-performance computing systems. Janapa Reddi received a PhD in computer science from Harvard University. Contact him at vj@ece.utexas.edu.']}} %*Ti-States: Power Management in Active Timing Margin Processors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7948655 %f/micro/tjr94c0yv1xxpifhcl5osbznbevf3esw.pdf %maee08879e69e855028139a9cd4ea28c3 %cmicro %@[{'name': 'Alexei Colin', 'affiliation': 'Carnegie Mellon University', 'bio': {'p': ['Alexei Colin is a graduate student in the Department of Electrical and Computer Engineering at Carnegie Mellon University. His research interests include reliability, programmability, and efficiency of software on energy-harvesting devices. Colin received an MSc in electrical and computer engineering from Carnegie Mellon University. He is a student member of ACM. Contact him at acolin@andrew.cmu.edu.']}}, {'name': 'Graham Harvey', 'affiliation': 'Disney Research Pittsburgh', 'bio': {'p': ['Graham Harvey is an associate show electronic engineer at Walt Disney Imagineering. His research interests include real-world applications of wireless technologies to enhance guest experiences in themed environments. Harvey received a BS in electrical and computer engineering from Carnegie Mellon University. He completed the work for this article while interning at Disney Research Pittsburgh. Contact him at graham.n.harvey@disney.com.']}}, {'name': 'Alanson P. Sample', 'affiliation': 'Disney Research Pittsburgh', 'bio': {'p': ['Alanson P. Sample is an associate lab director and principal research scientist at Disney Research Pittsburgh, where he leads the Wireless Systems group. His research interests include enabling new guest experiences and sensing and computing devices byapplying novel approaches to electromagnetics, RF and analog circuits, and embedded systems. Sample received a PhD in electrical engineering from the University of Washington. He is a member of IEEE and ACM. Contact him at alanson.sample@disneyresearch.com.']}}, {'name': 'Brandon Lucia', 'affiliation': 'Carnegie Mellon University', 'bio': {'p': ['Brandon Lucia is an assistant professor in the Department of Electrical and Computer Engineering at Carnegie Mellon University. His research interests include the boundaries between computer architecture, compilers, system software, and programming languages, applied to emerging, intermittently powered systems and efficient parallel systems. Lucia received a PhD in computer science and engineering from the University of Washington. He is a member of IEEE and ACM. Contact him at blucia@ece.cmu.edu or http://brandonlucia.com.']}} %*An Energy-Aware Debugger for Intermittently Powered Systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7948658 %f/micro/kdbae8yy2vr57xtsrw0z6qfkdatoojgf.pdf %m19e7a5978ba47cf52905d56d778db1a9 %cmicro %@[{'name': 'Uri Weiser', 'affiliation': 'Technion-Israel Institute of Technology', 'bio': {'p': ['Uri Weiser is an emeritus professor in the Electrical Engineering Department at the Technion-Israel Institute of Technology (IIT). Contact him at uri.weiser@ee.technion.ac.il.']}} %*Insights from the 2016 Eckert-Mauchly Award Recipient %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7948660 %f/micro/qmr3vp7yp0u5qoxggxjt8lehmenznsjd.pdf %ma938d1674530bd6e4dfac34c794d4400 %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'Harvard Business School', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/7948654/7948676/7948676-photo-1-small.gif', 'p': ['Shane Greenstein is a professor at the Harvard Business School. Contact him at sgreenstein@hbs.edu.']}} %*Two Sides to Scale %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7948676 %f/micro/ouxwn1a5pudsfzlcgkegnakwy32y4qer.pdf %m32803c7b4411c6672acaea0b515f7417 %cmicro %@[{'name': 'Lieven Eeckhout', 'affiliation': 'Ghent University', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/7419153/7419154/7419154-photo-1-small.gif', 'p': ['Lieven Eeckhout is a professor in the Department of Electronics and Information Systems at Ghent University. Contact him at lieven.eeckhout@ugent.be.']}} %*Looking Forward to the 2016 Theme Issues %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7419154 %f/micro/srkoy8zquiekzjpm429fbndmtvaewcar.pdf %mec2eb2248b0420a942604898fc35cb93 %cmicro %@[{'name': 'Rajeev Balasubramonian', 'affiliation': 'University of Utah', 'bio': {'p': ['Rajeev Balasubramonian is a professor at the University of Utah. Contact him at rajeev@cs.utah.edu.']}}, {'name': 'Boris Grot', 'affiliation': 'University of Edinburgh', 'bio': {'p': ['Boris Grot is an assistant professor in the School of Informatics at the University of Edinburgh. Contact him at boris.grot@ed.ac.uk.']}} %*Near-Data Processing [Guest editors' introduction] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7419155 %f/micro/zdpxvmvrlgyzn4ksqub1omoxrk0hefb8.pdf %m0977f28ab2863a9d86400201522da608 %cmicro %@[{'name': 'Babak Falsafi', 'affiliation': 'EPFL', 'bio': {'p': ['Babak Falsafi is the founding director of the EcoCloud research center and a professor in the School of Computer and Communication Sciences at EPFL. Contact him at babak.falsafi@epfl.ch.']}}, {'name': 'Mircea Stan', 'affiliation': 'University of Virginia', 'bio': {'p': ['Mircea Stan is a professor in the Electrical and Computer Engineering Department at the University of Virginia. Contact him at mircea@virginia.edu.']}}, {'name': 'Kevin Skadron', 'affiliation': 'University of Virginia', 'bio': {'p': ['Kevin Skadron is the Harry Douglas Forsyth Professor and Department Chair for Computer Science at the University of Virginia. Contact him at skadron@virginia.edu.']}}, {'name': 'Nuwan Jayasena', 'affiliation': 'AMD Research', 'bio': {'p': ['Nuwan Jayasena is a principal member of technical staff at AMD Research. Contact him at nuwan.jayasena@amd.com.']}}, {'name': 'Yunji Chen', 'affiliation': 'State Key Lab of Computer Architecture, Chinese Academy of Sciences', 'bio': {'p': ['Yunji Chen is a full professor in the Institute of Computing Technology at the State Key Lab of Computer Architecture, Chinese Academy of Sciences. Contact him at cyj@ict.ac.cn.']}}, {'name': 'Jinhua Tao', 'affiliation': 'University of Chinese Academy of Sciences', 'bio': {'p': ['Jinhua Tao is a PhD candidate at the University of Chinese Academy of Sciences. Contact him at taojinhua@ict.ac.cn.']}}, {'name': 'Ravi Nair', 'affiliation': 'IBM Thomas J.Watson Research Center', 'bio': {'p': ['Ravi Nair is a distinguished research staff member at the IBM Thomas. J. Watson Research Center. Contact him at nair@us.ibm.com.']}}, {'name': 'Jaime Moreno', 'affiliation': 'IBM Thomas J.Watson Research Center', 'bio': {'p': ['Jaime Moreno is the Worldwide Technology and Operations Manager, Computing as a Service, at the IBM Thomas J. Watson Research Center. Contact him at jhmoreno@us.ibm.com.']}}, {'name': 'Naveen Muralimanohar', 'affiliation': 'Hewlett Packard Labs', 'bio': {'p': ['Naveen Muralimanohar is a principal research scientist at Hewlett Packard Labs. Contact him at naveen.muralimanohar@hpe.com.']}}, {'name': 'Karthikeyan Sankaralingam', 'affiliation': 'University of Wisconsin-Madison', 'bio': {'p': ['Karthikeyan Sankaralingam is an associate professor at the University of Wiscon-sin-Madison. Contact him at karu@cs.wisc.edu.']}}, {'name': 'Cristian Estan', 'affiliation': 'Google', 'bio': {'p': ['Cristian Estan is a software engineer in search infrastructure at Google. Contact him at estan@google.com.']}} %*Near-Memory Data Services %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7419157 %f/micro/rz1lqursbdtmacj08ipmvsxgntqzewdi.pdf %m027c148bfe284d1301180d6e968cfaf5 %cmicro %@[{'name': 'Berkin Akin', 'affiliation': 'Intel Labs', 'bio': {'p': ['Berkin Akin is a research scientist at Intel Labs. His research interests include computer architecture, memory systems, high-performance and energy-efficient computing, near-data processing, algorithm/architecture codesign, and reconfigurable computing. Akin received his PhD in electrical and computer engineering from Carnegie Mellon University. Contact him at berkin.akin@intel.com.']}}, {'name': 'Franz Franchetti', 'affiliation': 'Carnegie Mellon University', 'bio': {'p': ['Franz Franchetti is an associate research professor in the Department of Electrical and Computer Engineering at Carnegie Mellon University. His research focuses on automatic performance tuning and program generation for emerging parallel platforms and algorithm/hardware cosynthesis. Franchetti received his Dr techn (PhD) in computational mathematics from the Vienna University of Technology. Contact him at franzf@ece.cmu.edu.']}}, {'name': 'James C. Hoe', 'affiliation': 'Carnegie Mellon University', 'bio': {'p': ['James C. Hoe is a professor in the Department of Electrical and Computer Engineering at Carnegie Mellon University. His research interests include computer architecture and high-level hardware description and synthesis. Hoe received his PhD in electrical engineering and computer science from the Massachusetts Institute of Technology. He is a fellow of IEEE. Contact him at jhoe@ece.cmu.edu.']}} %*HAMLeT Architecture for Parallel Data Reorganization in Memory %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7325181 %f/micro/njixqpvoedhyxnewhjtswga340ftz5k2.pdf %ma5360b4f66519aabc25b04b35364f9fc %cmicro %@[{'name': 'Hadi Asghari-Moghaddam', 'affiliation': 'University of Illinois at Urbana-Champaign', 'bio': {'p': ['Hadi Asghari-Moghaddam is a PhD student in the Department of Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign. His research interests include near-data computing and energy-efficient computer architecture. Asghari-Moghad-dam received his MS in electrical and computer engineering from the University of Wiscon-sin-Madison. Contact him at asghari2@illinois.edu.']}}, {'name': 'Amin Farmahini-Farahani', 'affiliation': 'University of Wisconsin-Madison', 'bio': {'p': ['Amin Farmahini-Farahani is an engineer at Advanced Micro Devices, where he works on research projects on processing in memory. His research interests include memory systems, energy-efficient processing, and reconfigurable computing. Farmahini-Farahani received his PhD in electrical and computer engineering from the University of Wisconsin-Madison, where he completed the work for this article. Contact him at afarmahi@amd.com.']}}, {'name': 'Katherine Morrow', 'affiliation': 'University of Wisconsin-Madison', 'bio': {'p': ['Katherine Morrow is an associate professor in the Department of Electrical and Computer Engineering at the University of Wis-consin-Madison. Her research interests include reconfigurable computing and the use of technology to improve student learning in undergraduate computer engineering courses. Morrow received her PhD in electrical and computer engineering from Northwestern University. She is a member of IEEE and the ACM. Contact her at klmorrow@wisc.edu.']}}, {'name': 'Jung Ho Ahn', 'affiliation': 'Seoul National University', 'bio': {'p': ['Jung Ho Ahn is an associate professor in the Graduate School of Convergence Science and Technology at Seoul National University, where he leads the Scalable Computer Architecture Laboratory. His research interests include bridging the gap between the performance demand of emerging applications and the performance potential of modern and future massively parallel systems. Ahn received his PhD in electrical engineering from Stanford University. He is a senior member of IEEE. Contact him at gajh@snu.ac.kr.']}}, {'name': 'Nam Sung Kim', 'affiliation': 'University of Illinois at Urbana-Champaign', 'bio': {'p': ['Nam Sung Kim is an associate professor in the Department of Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign. His research focuses on devices, circuits, and architectures for energy-efficient computing. Kim received his PhD in computer science and engineering from the University of Michigan. He is an IEEE Fellow. Contact him at nskim@illinois.edu.']}} %*Near-DRAM Acceleration with Single-ISA Heterogeneous Processing in Standard Memory Modules %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7419158 %f/micro/d3w2lnciqa6jgsm97wbpkjxzifdtfoyc.pdf %m9c2eee14f1fc94acf75839774e4812f8 %cmicro %@[{'name': 'Ioannis Sourdis', 'affiliation': 'Chalmers University of Technology', 'bio': {'p': ['Ioannis Sourdis is an associate professor in the Department of Computer Science and Engineering at Chalmers University of Technology, Sweden. His research interests include the architecture and design of computer and networking systems, reconfigurable computing, interconnection networks, and fault-tolerant computing. Sourdis received his PhD in computer engineering from the Delft University of Technology. He is a member of IEEE and the ACM. Contact him at sourdis@chalmers.se.']}}, {'name': 'Danish Anis Khan', 'affiliation': 'Chalmers University of Technology', 'bio': {'p': ['Danish Anis Khan is a manager of embedded systems at the Space and Upper Atmosphere Research Commission in Pakistan. His research interests include fault-tolerant systems, reconfigurable computing, and digital signal processing. Khan received his MSc in embedded electronics system design from Chalmers University of Technology, where he completed the work for this article. Contact him at danishak@gmail.com.']}}, {'name': 'Alirad Malek', 'affiliation': 'Chalmers University of Technology', 'bio': {'p': ['Alirad Malek is a PhD student in the Computer Science and Engineering Department at Chalmers University of Technology, Sweden. His research interests include fault-tolerant system design, interconnection networks, multicore architectures, and reconfigurable computing. Malek received his MSc in system-on-chip from Lund University of Technology. Contact him at aliradm@chalmers.se.']}}, {'name': 'Stavros Tzilis', 'affiliation': 'Chalmers University of Technology', 'bio': {'p': ['Stavros Tzilis is a PhD student in the Computer Science and Engineering Department at Chalmers University of Technology, Sweden. His research interests include fault tolerance, graceful degradation, and runtime management for performance, energy efficiency, and lifetime extension. Tzilis received his MSc in computer engineering from the Delft University of Technology. Contact him at tzilis@chalmers.se.']}}, {'name': 'Georgios Smaragdos', 'affiliation': 'Erasmus Medical Center', 'bio': {'p': ['Georgios Smaragdos is a PhD student in the Neuroscience Department at the Erasmus Medical Center, the Netherlands. His research interests include reconfigurable computing, fault-tolerant computing, and high-performance computational neuroscience. Smaragdos received his MSc in computer engineering from the Delft University of Technology. Contact him at g.smaragdos@erasmusmc.nl.']}}, {'name': 'Christos Strydis', 'affiliation': 'Erasmus Medical Center', 'bio': {'p': ['Christos Strydis is an assistant professor in the Neuroscience Department at the Erasmus Medical Center, the Netherlands. His research interests include high-performance computational neuroscience and biomedical microelectronic implants. Strydis received his PhD in computer engineering from the Delft University of Technology. He is a member of IEEE. Contact him at c.strydis@erasmusmc.nl.']}} %*Resilient Chip Multiprocessors with Mixed-Grained Reconfigurability %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7006345 %f/micro/euk2gx0cnt1rdj93zryhvxmas7pof4pg.pdf %m8e230f130e7ffe677703bf2c1b6dd9a0 %cmicro %@[{'name': 'Amoghavarsha Suresh', 'affiliation': 'University of Minnesota', 'bio': {'p': ['Amoghavarsha Suresh works as a performance modeler in the Performance Measurement and Characterization Laboratory in the San Diego Supercomputing Center. His research interests include developing tools for workload characterization and modeling power and performance of high-performance computing workloads. Suresh received an MS in electrical and computer engineering from the University of Minnesota, where he completed the work for this article. Contact him at sure043@umn.edu.']}}, {'name': 'John Sartori', 'affiliation': 'University of Minnesota', 'bio': {'p': ['John Sartori is an assistant professor in the Electrical and Computer Engineering Department at the University of Minnesota. His research interests include energy-efficient, stochastic, robust, and scalable computing. Sartori received a PhD in electrical and computer engineering from the University of Illinois at Urbana-Champaign. Contact him at jsartori@umn.edu.']}} %*Automated Algorithmic Error Resilience Based on Outlier Detection %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7006347 %f/micro/vjpnvflrsckeox2s6wb3kiohngmqcp89.pdf %m16f4f8b12ef48ec8c47153115f5ee77d %cmicro %@[{'name': 'Onur Mutlu', 'affiliation': 'CarnegieMellon University', 'bio': {'p': ['Onur Mutlu is the Strecker Early Career Professor at Carnegie Mellon University. Contact him at omutlu@gmail.com.']}}, {'name': 'Rich Belgard', 'bio': {'p': ['Rich Belgard is an independent consultant for computer manufacturers, software companies, and investor groups and an expert and consultant to law firms. Contact him at belgard@gmail.com.']}}, {'name': 'Nick Tredennick', 'affiliation': 'Jonetix', 'bio': {'p': ['Nick Tredennick is a VP and engineer at Jonetix. He is a life fellow of IEEE. Contact him at bozo@computer.org.']}}, {'name': 'Michael Schlansker', 'affiliation': 'HP Labs', 'bio': {'p': ['Michael Schlansker is a Distinguished Technologist at the Hewlett Packard Enterprise Labs. Contact him at mike_schlansker@hpe.com.']}} %*The 2014 MICRO Test of Time Award Winners: From 1978 to 1992 %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7419159 %f/micro/rwvznmfg5xwdln7hlyhuae0ojjkfkttq.pdf %m70e98e2fc81d6f8c8a6b12613f48b0eb %cmicro %@[{'name': 'Lieven Eeckhout', 'affiliation': 'Ghent University', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/7453073/7453077/7453077-photo-1-small.gif', 'p': ['Lieven Eeckhout is a professor in the Department of Electronics and Information Systems at Ghent University. Contact him at lieven.eeckhout@ugent.be.']}} %*Hot Chips: The Annual Feast of Riches %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7453077 %f/micro/bjzie6a3hxpyalgrt501ibg4sd7hqf9z.pdf %m973c20524209d1cd09f7905c8cedb8fe %cmicro %@[{'name': 'Rajeevan Amirtharajah', 'affiliation': 'University of California, Davis', 'bio': {'p': ['Rajeevan Amirtharajah is a professor in the Electrical and Computer Engineering Department at the University of California, Davis. Contact him at ramirtha@ucdavis.edu.']}}, {'name': 'Behnam Robatmili', 'affiliation': 'AxStream', 'bio': {'p': ['Behnam Robatmili is the CTO and cofounder of AxStream. Contact him at behnam@axstream.io.']}} %*Hot Chips 27 %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7453085 %f/micro/8ngvbmooca4egxap75ukbz9fq1shlj3i.pdf %m0a4cd7bd3d1408f83f8c062022938b3f %cmicro %@[{'name': 'Yunsup Lee', 'affiliation': 'University of California, Berkeley', 'bio': {'p': ['Yunsup Lee is a PhD candidate in the Department of Electrical Engineering and Computer Sciences at the University of California, Berkeley. He received an MS in computer science from the University of California, Berkeley. Contact him at yunsup@eecs.berkeley.edu.']}}, {'name': 'Andrew Waterman', 'affiliation': 'University of California, Berkeley', 'bio': {'p': ['Andrew Waterman is a PhD candidate in the Department of Electrical Engineering and Computer Sciences at the University of California, Berkeley. He received an MS in computer science from the University of California, Berkeley. Contact him at waterman@eecs.berkeley.edu.']}}, {'name': 'Henry Cook', 'affiliation': 'University of California, Berkeley', 'bio': {'p': ['Henry Cook is a PhD candidate in the Department of Electrical Engineering and Computer Sciences at the University of California, Berkeley. He received an MS in computer science from the University of California, Berkeley. Contact him at hcook@eecs.berkeley.edu.']}}, {'name': 'Brian Zimmer', 'affiliation': 'University of California, Berkeley', 'bio': {'p': ['Brian Zimmer is a research scientist in the Circuits Research Group at Nvidia. He received a PhD in electrical engineering and computer science from the University of California, Berkeley, where he performed the research for this article. Contact him at brianzimmer@gmail.com.']}}, {'name': 'Ben Keller', 'affiliation': 'University of California, Berkeley', 'bio': {'p': ['Ben Keller is a PhD student in the Department of Electrical Engineering and Computer Sciences at the University of California, Berkeley. He received an MS in electrical engineering from the University of California, Berkeley. Contact him at bkeller@eecs.berkeley.edu.']}}, {'name': 'Alberto Puggelli', 'affiliation': 'University of California, Berkeley', 'bio': {'p': ['Alberto Puggelli is the director of technology at Lion Semiconductor. He received a PhD in electrical engineering from the University of California, Berkeley, where he performed the research for this article. Contact him at alberto.puggelli@gmail.com.']}}, {'name': 'Jaehwa Kwak', 'affiliation': 'University of California, Berkeley', 'bio': {'p': ['Jaehwa Kwak is a PhD candidate in the Department of Electrical Engineering and Computer Science at the University of California, Berkeley. He received an MS in electrical engineering and computer sciences from Seoul National University. Contact him at jhkwak@eecs.berkeley.edu.']}}, {'name': 'Ruzica Jevtic', 'affiliation': 'University of California, Berkeley', 'bio': {'p': ['Ružica Jevtić is an assistant professor at the Universidad de Antonio de Nebrija in Madrid. She received a PhD in electrical engineering from Technical University of Madrid and was a postdoctoral fellow at the University of California, Berkeley, where she performed the research for this article. Contact her at rjevtic21@gmail.com.']}}, {'name': 'Stevo Bailey', 'affiliation': 'University of California, Berkeley', 'bio': {'p': ['Stevo Bailey is a PhD student in the Department of Electrical Engineering and Computer Science at the University of California, Berkeley. He received an MS from the University of California, Berkeley. Contact him at stevo.bailey@eecs.berkeley.edu.']}}, {'name': 'Milovan Blagojevic', 'affiliation': 'University of California, Berkeley', 'bio': {'p': ["Milovan Blagojević is a PhD student in a CIFRE program at the Berkeley Wireless Research Center, STMicroelectronics, and Institut Supérieur d'Electronique de Paris. He received an MSc in electrical engineering from the University of Belgrade, Serbia. Contact him at milovan.blagojevic@st.com."]}}, {'name': 'Pi-Feng Chiu', 'affiliation': 'University of California, Berkeley', 'bio': {'p': ['Pi-Feng Chiu is a PhD student in the Department of Electrical Engineering and Computer Sciences at the University of California, Berkeley. She received an MS in electrical engineering from the National Tsing Hua University. Contact her at pfchiu@eecs.berkeley.edu.']}}, {'name': 'Rimas Avizienis', 'affiliation': 'University of California, Berkeley', 'bio': {'p': ['Rimas Aviženis is a PhD candidate in the Department of Electrical Engineering and Computer Sciences at the University of California, Berkeley. He received an MS in computer science from the University of California, Berkeley. Contact him at rimas@eecs.berkeley.edu.']}}, {'name': 'Brian Richards', 'affiliation': 'University of California, Berkeley', 'bio': {'p': ['Brian Richards is a research staff engineer at the University of California, Berkeley, and a founding member of the Berkeley Wireless Research Center. He received an MS in electrical engineering and computer science from the University of California, Berkeley. Contact him at richards@eecs.berkeley.edu.']}}, {'name': 'Jonathan Bachrach', 'affiliation': 'University of California, Berkeley', 'bio': {'p': ['Jonathan Bachrach is an adjunct assistant professor in the Department of Electrical Engineering and Computer Sciences at the University of California, Berkeley. He received a PhD in computer science from the University of Massachusetts, Amherst. Contact him at jrb@pobox.com.']}}, {'name': 'David Patterson', 'affiliation': 'University of California, Berkeley', 'bio': {'p': ['David Patterson is the Pardee Professor of Computer Science at the University of California, Berkeley. He received a PhD in computer science from the University of California, Los Angeles. Contact him at pattrsn@eecs.berkeley.edu.']}}, {'name': 'Elad Alon', 'affiliation': 'University of California, Berkeley', 'bio': {'p': ['Elad Alon is an associate professor in the Department of Electrical Engineering and Computer Sciences at the University of California, Berkeley, and a codirector of the Berkeley Wireless Research Center. He received a PhD in electrical engineering from Stanford University. Contact him at elad@eecs.berkeley.edu.']}}, {'name': 'Bora Nikolic', 'affiliation': 'University of California, Berkeley', 'bio': {'p': ['Borivoje Nikolić is the National Semiconductor Distinguished Professor of Engineering at the University of California, Berkeley. He received a PhD in electrical and computer engineering from the University of California, Davis. Contact him at bora@eecs.berkeley.edu.']}}, {'name': 'Krste Asanovic', 'affiliation': 'University of California, Berkeley', 'bio': {'p': ['Krste Asanović is a professor in the Department of Electrical Engineering and Computer Sciences at the University of California, Berkeley. He received a PhD in computer science from the University of California, Berkeley. Contact him at krste@berkeley.edu.']}} %*An Agile Approach to Building RISC-V Microprocessors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7436635 %f/micro/vowxyrql8wuvg6tp7mshhpeuizze05kf.pdf %m6a2c5e30cc00521af13079dba789007d %cmicro %@[{'name': 'Guhan Krishnan', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ['Guhan Krishnan is a Fellow and the lead chip architect for APU client products at Advanced Micro Devices. His research interests include low-power computer architecture and memory system design. Krishnan received an MS in electrical engineering from the State University of New York, Buffalo. Contact him at guhan.krishnan@amd.com.']}}, {'name': 'Dan Bouvier', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ['Dan Bouvier is a senior Fellow and chief portfolio architect for client products at Advanced Micro Devices, where he leads the SoC definition of all notebook and desktop APUs. His research interests include SoC architecture, memory and I/O systems, and microprocessor microarchitecture. Bouvier received a BS in electrical engineering from Arizona State University. Contact him at dan.bouvier@amd.com.']}}, {'name': 'Samuel Naffziger', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ['Samuel Naffziger is a corporate Fellow responsible for low-power technology development at Advanced Micro Devices. His research interests include processor circuits, architecture, and power management. Naffziger received an MS in electrical engineering from Stanford University. He is a fellow of IEEE. Contact him at samuel.naffziger@amd.com.']}} %*Energy-Efficient Graphics and Multimedia in 28-nm Carrizo Accelerated Processing Unit %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7453078 %f/micro/usfu2qrd4irzpnaowtczsp0hckinxvm5.pdf %m59265cb38957c633173435d961ada4c7 %cmicro %@[{'name': 'Avinash Sodani', 'affiliation': 'Intel', 'bio': {'p': ['Avinash Sodani is a senior principal engineer at Intel and the chief architect of the Knights Landing processor. His research interests include computer architecture, highperformance computing, parallel programming, and applications. Sodani received a PhD in computer science from the University of Wisconsin-Madison. Contact him at avinash.sodani@intel.com.']}}, {'name': 'Roger Gramunt', 'affiliation': 'Intel', 'bio': {'p': ['Roger Gramunt is a senior computer architect at Intel and one of the primary architects of the Knights Landing core. His research interests include core architecture, graphics architecture, binary translation, and vector instruction sets. Gramunt received an MS in computer engineering from the Universitat Politecnica de Catalunya. Contact him at roger.gramunt@intel.com.']}}, {'name': 'Jesus Corbal', 'affiliation': 'Intel', 'bio': {'p': ['Jesus Corbal is a principal engineer at Intel and one of the primary architects of the Knights Landing vector processing unit. His research interests include vector microarchitectures and instruction-set architecture SIMD extensions. Corbal received a PhD in computer engineering from the Universitat Politecnica de Catalunya. Contact him at jesus.corbal@intel.com.']}}, {'name': 'Ho-Seop Kim', 'affiliation': 'Intel', 'bio': {'p': ['Ho-Seop Kim is a senior staff computer architect at Intel. His research interests include core architecture, caching and virtualization, performance monitoring, and dynamic binary translation. Kim received a PhD in electrical and computer engineering from the University of Wisconsin-Madison. Contact him at ho-seop.kim@intel.com.']}}, {'name': 'Krishna Vinod', 'affiliation': 'Intel', 'bio': {'p': ['Krishna Vinod is a senior computer architect at Intel and the architect of the Knights Landing L2 cache and core-to-mesh interconnect. His research interests include caching, coherency, and multicore messaging. Vinod received an MS in electrical engineering from Case Western Reserve University. Contact him at krishna.n.vinod@intel.com.']}}, {'name': 'Sundaram Chinthamani', 'affiliation': 'Intel', 'bio': {'p': ['Sundaram Chinthamani is a senior performance architect at Intel and the performance lead of the Knights Landing processor. His research interests include highperformance computing, computer performance modeling using simulation, and queuing networks. Chinthamani received a PhD in computer engineering from the University of Saskatchewan. Contact him at sundaram.chinthamani@intel.com.']}}, {'name': 'Steven Hutsell', 'affiliation': 'Intel', 'bio': {'p': ['Steven Hutsell is a staff microprocessor architect at Intel and one of the primary memory architects for the Knights Landing processor. His research interests include CPU and graphics architecture, memory and caching systems, multichip interconnects, and quantum computing. Hutsell received a PhD in electrical and computer engineering from Portland State University. Contact him at steven.r.hutsell@intel.com.']}}, {'name': 'Rajat Agarwal', 'affiliation': 'Intel', 'bio': {'p': ['Rajat Agarwal is a principal engineer at Intel. His research focuses on high-memory-bandwidth solutions for high-performance computing products. Agarwal received a BTech in electronics and communications engineering from the National Institute of Technology, India. Contact him at rajat.agarwal@intel.com.']}}, {'name': 'Yen-Chen Liu', 'affiliation': 'Intel', 'bio': {'p': ['Yen-Chen Liu is a senior server architect at Intel. His research interests include on-chip/off-chip interconnect fabric, multisocket cache coherency, and chip multiprocessor multicore processor designs. Liu received an MS in electrical and computer engineering from the University of Wisconsin-Madison. Contact him at yen-cheng.liu@intel.com.']}} %*Knights Landing: Second-Generation Intel Xeon Phi Product %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7453080 %f/micro/t3irfyo8lfrkujxeux9bj7bomcm6eqg0.pdf %mf022a6ba48c33b09bb5bd8d7e1b94867 %cmicro %@[{'name': 'Sagheer Ahmad', 'affiliation': 'Xilinx', 'bio': {'p': ['Sagheer Ahmad is a director of architecture responsible for the system-on-chip (SoC) and processor system architecture at Xilinx. His research interests include SoC architecture, processor systems, on-chip interconnects, and system safety. Ahmad received an MS in electrical engineering from the University of Southern California. Contact him at sagheer@xilinx.com.']}}, {'name': 'Vamsi Boppana', 'affiliation': 'Xilinx', 'bio': {'p': ['Vamsi Boppana is a vice president responsible for processing, systems, software, and applications engineering at Xilinx. He is also the site director and CTO for Xilinx India. Boppana received a PhD in electrical engineering from the University of Illinois at Urbana—Champaign. Contact him at vamsib@xilinx.com.']}}, {'name': 'Ilya Ganusov', 'affiliation': 'Xilinx', 'bio': {'p': ['Ilya Ganusov is a principal engineer at Xilinx. His research interests include microarchitecture and electronic design automation for field-programmable gate array (FPGA) and SoC architectures. Ganusov received a PhD in electrical and computer engineering from Cornell University. He is a member of IEEE and ACM. Contact him at ilya.ganusov@xilinx.com.']}}, {'name': 'Vinod Kathail', 'affiliation': 'Xilinx', 'bio': {'p': ['Vinod Kathail is a distinguished engineer at Xilinx, where he is responsible for all embedded SW development tools, including the SDSoC environment. His research interests include parallel architectures, heterogeneous programming environments, high-level synthesis, and embedded vision systems. Kathail received an ScD in computer science from the Massachusetts Institute of Technology. He is a member of IEEE and ACM. Contact him at vinodk@xilinx.com.']}}, {'name': 'Vidya Rajagopalan', 'affiliation': 'Xilinx', 'bio': {'p': ['Vidya Rajagopalan completed the work for this article while serving as a corporate vice president of processing, systems, software, and applications engineering at Xilinx. Rajagopalan received an MS in electrical engineering from the University of Maryland College Park. Contact her at vidya.rajagopalan@xilinx.com.']}}, {'name': 'Ralph Wittig', 'affiliation': 'Xilinx', 'bio': {'p': ['Ralph Wittig is a distinguished engineer and director of computing platforms at Xilinx. His research interests include computer architecture, multicore processor systems, hybrid computing platforms, and heterogeneous platform programming models. Wittig received an MASc in computer engineering from the University of Toronto. Contact him at wittig@xilinx.com.']}} %*A 16-nm Multiprocessing System-on-Chip Field-Programmable Gate Array Platform %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7453086 %f/micro/njlqkfbyz194ptmubadpsowvn3axzylt.pdf %m3a2a259279d69855c52a74994d2efcbf %cmicro %@[{'name': 'Rajeevan Amirtharajah', 'affiliation': 'University of California, Davis', 'bio': {'p': ['Rajeevan Amirtharajah is a professor in the Electrical and Computer Engineering Department at the University of California, Davis. He has a PhD in electrical engineering from the Massachusetts Institute of Technology. Contact him at ramirtha@ucdavis.edu.']}}, {'name': 'Behnam Robatmili', 'affiliation': 'AxStream', 'bio': {'p': ['Behnam Robatmili is the CTO and cofounder of AxStream. He has a PhD in computer sciences from the University of Texas at Austin. Contact him at behnam@axstream.io.']}} %*Hot Chips 27 Highlights %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7453075 %f/micro/xzi73eomarzsbkmxj2cuhtg8svcbo1iv.pdf %mdcdf28d46982d4589ce7bbf28d32d099 %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'Harvard Business School', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/7453073/7453092/7453092-photo-1-small.gif', 'p': ['Shane Greenstein is a professor at the Harvard Business School. Contact him at sgreenstein@hbs.edu.']}} %*What Does a Skunk Works Do? %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7453092 %f/micro/o2us6pfkuirhcawrqj7xg5whjfzokbg8.pdf %m4da54657fcc52ca2db966383c0462a42 %cmicro %@[{'name': 'Lieven Eeckhout', 'affiliation': 'Ghent University', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/7484939/7484954/7484954-photo-1-small.gif', 'p': ['Lieven Eeckhout is a professor in the Department of Electronics and Information Systems at Ghent University. Contact him at lieven.eeckhout@ugent.be.']}} %*Top Picks and Welcoming New Editorial Board Members %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7484954 %f/micro/jv6fr8jibowcecvtgsw7axoy0nl4hdpm.pdf %m8bed0a645a06f1a5c279184e43b629e0 %cmicro %@[{'name': 'Milo Martin', 'affiliation': 'Google', 'bio': {'p': ['Milo Martin is a staff software engineer at Google. Contact him at milom@google.com.']}}, {'name': 'Daniel Sorin', 'affiliation': 'Duke University', 'bio': {'p': ['Daniel Sorin is the W.H. Gardner Jr. Professor of Electrical and Computer Engineering at Duke University. Contact him at sorin@ee.duke.edu.']}} %*Top Picks from the 2015 Computer Architecture Conferences %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7484948 %f/micro/mefyxdqi492uzpjsumol7kjnvrrtvelh.pdf %m517269730517cbc911b1e25e06139512 %cmicro %@[{'name': 'André, Seznec', 'affiliation': 'INRIA', 'bio': {'p': ['André Seznec is a senior research director at INRIA. His research interests include speculative execution, pipeline design, and memory hierarchy and systems. Seznec received a PhD in computer sciences from the University of Rennes. He is an IEEE Fellow. Contact him at andre.seznec@inria.fr.']}}, {'name': 'Joshua San Miguel', 'affiliation': 'University of Toronto', 'bio': {'p': ['Joshua San Miguel is a PhD candidate in the Edward S. Rogers Sr. Department of Electrical and Computer Engineering at the University of Toronto. His research interests include branch prediction, approximate computing, and networks on chip. San Miguel received a BASc in engineering science from the University of Toronto. Contact him at joshua.sanmiguel@utoronto.ca.']}}, {'name': 'Jorge Albericio', 'affiliation': 'University of Toronto', 'bio': {'p': ['Jorge Albericio is a postdoctoral fellow in the Edward S. Rogers Sr. Department of Electrical and Computer Engineering at the University of Toronto. His research interests include branch prediction, architectures for machine intelligence algorithms, memory hierarchy, and approximate computing. Albericio received a PhD in systems engineering and computing from the University of Zaragoza. Contact him at jorge@ece.utoronto.ca.']}} %*Practical Multidimensional Branch Prediction %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7478425 %f/micro/lu0d9prh7tfqav3ymxcbpmwossndceok.pdf %m9d9b20b620e1d9edd4eee9926f49ffe6 %cmicro %@[{'name': 'Tony Nowatzki', 'affiliation': 'University of Wisconsin--Madison', 'bio': {'p': ['Tony Nowatzki is a PhD student in the Department of Computer Sciences at the University of Wisconsin—Madison. He received an MS in computer science from the University of Wisconsin—Madison. He is a student member of IEEE. Contact him at tjn@cs.wisc.edu.']}}, {'name': 'Vinay Gangadhar', 'affiliation': 'University of Wisconsin--Madison', 'bio': {'p': ['Vinay Gangadhar is a PhD student in the Department of Electrical and Computer Engineering at the University of Wisconsin—Madison. He received an MS in electrical and computer engineering from the University of Wisconsin—Madison. He is a student member of IEEE. Contact him at vinay@cs.wisc.edu.']}}, {'name': 'Karthikeyan Sankaralingam', 'affiliation': 'University of Wisconsin--Madison', 'bio': {'p': ['Karthikeyan Sankaralingam is an associate professor in the Department of Computer Sciences and the Department of Electrical and Computer Engineering at the University of Wisconsin—Madison. He received a PhD in computer science from the University of Texas at Austin. He is a senior member of IEEE. Contact him at karu@cs.wisc.edu.']}} %*A Heterogeneous Von Neumann/Explicit Dataflow Processor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7478423 %f/micro/kjx4nxt1e7r2gcfy0hqaoa95kusphb6q.pdf %m1bdcf3798bcd40c4734922bf7e2248a4 %cmicro %@[{'name': 'Chen-Han Ho', 'affiliation': 'University of Wisconsin--Madison', 'bio': {'p': ['Chen-Han Ho is a design engineer at Qualcomm. His research interests include microprocessor architecture and circuit design. Ho received a PhD in computer science from the University of Wisconsin—Madison where he completed the work for this article. Contact him at ho9@wisc.edu.']}}, {'name': 'Sung Jin Kim', 'affiliation': 'University of Wisconsin--Madison', 'bio': {'p': ['Sung Jin Kim is a PhD student in the Department of Computer Science at the University of Wisconsin—Madison. His research interests include microprocessor architecture and circuit design. Kim received a PhD in computer engineering from the University of Wisconsin—Madison. Contact him at sung@cs.wisc.edu.']}}, {'name': 'Karthikeyan Sankaralingam', 'affiliation': 'University of Wisconsin--Madison', 'bio': {'p': ['Karthikeyan Sankaralingam is an associate professor in the Department of Computer Sciences and the Department of Electrical and Computer Engineering at the University of Wisconsin—Madison where he also leads the Vertical Research Group. His research interests include microarchitecture, architecture, and very large-scale integration. Sankaralingam received a PhD in computer science from the University of Texas at Austin. He is a senior member of IEEE. Contact him at karu@cs.wisc.edu.']}} %*Accelerating the Accelerator Memory Interface with Access-Execute and Dataflow %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7478424 %f/micro/lgysmfxyezn4n0kw38jxmst2z7apheqd.pdf %m8b275169b787b5c74cf8e003421b7ab0 %cmicro %@[{'name': 'Johann Hauswald', 'affiliation': 'University of Michigan', 'bio': {'p': ['Johann Hauswald is a PhD candidate in the Computer Science and Engineering Department at the University of Michigan. He received an MS in computer science and engineering from the University of Michigan. Contact him at jahausw@umich.edu.']}}, {'name': 'Michael A. Laurenzano', 'affiliation': 'University of Michigan', 'bio': {'p': ['Michael A. Laurenzano is a PhD candidate in the Computer Science and Engineering Department at the University of Michigan. He received an MS in computer science and engineering from the University of California, San Diego. Contact him at mlaurenz@umich.edu.']}}, {'name': 'Yunqi Zhang', 'affiliation': 'University of Michigan', 'bio': {'p': ['Yunqi Zhang is a PhD candidate in the Computer Science and Engineering Department at the University of Michigan. He received an MS in computer science and engineering from the University of California, San Diego. Contact him at yunqi@umich.edu.']}}, {'name': 'Cheng Li', 'affiliation': 'University of Michigan', 'bio': {'p': ['Cheng Li is a PhD student in the Computer Science and Engineering Department at the University of Illinois, Urbana-Champaign. She received an MS in computer science and engineering from the University of Michigan, where she completed the work for this article. Contact her at elfchris@umich.edu.']}}, {'name': 'Austin Rovinski', 'affiliation': 'University of Michigan', 'bio': {'p': ['Austin Rovinski is an undergraduate student in electrical engineering at the University of Michigan. Contact him at rovinski@umich.edu.']}}, {'name': 'Arjun Khurana', 'affiliation': 'University of Michigan', 'bio': {'p': ["Arjun Khurana is a master's student in the Computer Science and Engineering Department at the University of Michigan. He received a BSE in electrical engineering from the University of Michigan. Contact him at khuranaa@umich.edu."]}}, {'name': 'Ronald G. Dreslinski', 'affiliation': 'University of Michigan', 'bio': {'p': ['Ronald G. Dreslinski is an assistant professor in the Computer Science and Engineering Department at the University of Michigan. He received a PhD in computer science and engineering from the University of Michigan. Contact him at rdreslin@umich.edu.']}}, {'name': 'Trevor Mudge', 'affiliation': 'University of Michigan', 'bio': {'p': ['Trevor Mudge is the Bredt Family Professor of Computer Science and Engineering at the University of Michigan, Ann Arbor. He received a PhD in computer science from the University of Illinois, Urbana-Champaign. Contact him at tnm@umich.edu.']}}, {'name': 'Vinicius Petrucci', 'affiliation': 'Federal University of Bahia', 'bio': {'p': ['Vinicius Petrucci is an assistant professor in the Department of Computer Science at the Federal University of Bahia, Brazil. He received a PhD in computer science from the Fluminense Federal University, Brazil. Contact him at petrucci@dcc.ufba.br.']}}, {'name': 'Lingjia Tang', 'affiliation': 'University of Michigan', 'bio': {'p': ['Lingjia Tang is an assistant professor in the Computer Science and Engineering Department at the University of Michigan. She received a PhD in computer science from the University of Virginia. Contact her at lingjia@umich.edu.']}}, {'name': 'Jason Mars', 'affiliation': 'University of Michigan', 'bio': {'p': ['Jason Mars is an assistant professor in the Computer Science and Engineering Department at the University of Michigan. He received a PhD in computer science from the University of Virginia. Contact him at profmars@umich.edu.']}} %*Sirius Implications for Future Warehouse-Scale Computers %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7478443 %f/micro/sgyag4qm7fsc3j0vf9kkbxownhwvajzx.pdf %mcb5a1eb1d6a29c4272a3d9250bcaf0cb %cmicro %@[{'name': 'Svilen Kanev', 'affiliation': 'Google', 'bio': {'p': ['Svilen Kanev is a PhD candidate at Harvard University and a tenured intern at Google, where he performed the research for this article. His research interests include performance analysis and modeling, datacenter hardware, and anything spanning the hardware-software boundary. Kanev received an MSc in computer science from Harvard University. Contact him at skanev@eecs.harvard.edu.']}}, {'name': 'Juan Pablo Darago', 'affiliation': 'Google', 'bio': {'p': ['Juan Pablo Darago is a software engineer at Google Switzerland, where he works on infrastructure for Google Shopping. His research interests include optimization, highperformance computing, and computer architecture. Darago has an MSc in computer science from the University of Buenos Aires. Contact him at jpdarago@google.com.']}}, {'name': 'Kim Hazelwood', 'affiliation': 'Google', 'bio': {'p': ['Kim Hazelwood is a senior engineering manager in the Infrastructure Division at Facebook. Her research interests include data-center-scale performance analysis. Hazelwood received a PhD in computer science from Harvard University. She performed the research for this article while she was a software engineer at Google. Contact her at kimhazelwood@fb.com.']}}, {'name': 'Parthasarathy Ranganathan', 'affiliation': 'Google', 'bio': {'p': ['Parthasarathy Ranganathan is a principal engineer at Google, where he is designing their next-generation systems. His research interests include systems architecture and management, power management, and energy efficiency for servers and datacenters. Ranganathan received a PhD in computer engineering from Rice University. He is a Fellow of IEEE and ACM. Contact him at parthas@google.com.']}}, {'name': 'Tipp Moseley', 'affiliation': 'Google', 'bio': {'p': ['Tipp Moseley is a staff engineer at Google, where he works on datacenter-scale performance analysis. His research interests include compilers, operating systems, performance analysis, runtime systems, fault tolerance, and optimized lock-free data structures. Moseley received a PhD in computer science from the University of Colorado at Boulder. Contact him at tipp@google.com.']}}, {'name': 'Gu-Yeon Wei', 'affiliation': 'Harvard University', 'bio': {'p': ['Gu-Yeon Wei is a Gordon McKay Professor of Electrical Engineering and Computer Science at Harvard University. His research interests include mixed-signal integrated circuits, computer architecture, and runtime software, looking for cross-layer opportunities to develop energy-efficient systems. Wei received a PhD in electrical engineering from Stanford University. Contact him at guyeon@eecs.harvard.edu.']}}, {'name': 'David Brooks', 'affiliation': 'Harvard University', 'bio': {'p': ['David Brooks is the Haley Family Professor of Computer Science at Harvard University. His research interests include architectural and software approaches to address power, thermal, and reliability issues for embedded and high-performance computing systems. Brooks received a PhD in electrical engineering from Princeton University. Contact him at dbrooks@eecs.harvard.edu.']}} %*Profiling a Warehouse-Scale Computer %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7478434 %f/micro/sviyyg4wfdj6ui839baltzwuposcmhxk.pdf %m5dcca49e5c90a8abc5477d1da233f078 %cmicro %@[{'name': 'Pat Pannuto', 'affiliation': 'University of Michigan', 'bio': {'p': ['Pat Pannuto is a PhD candidate in the Computer Science and Engineering Department at the University of Michigan. His research interests include systems design for microscale systems and technologies for high-fidelity indoor localization. Pannuto received a BSE in computer engineering from the University of Michigan. He also received the National Defense Science & Engineering Graduate Fellowship, the National Science Foundation Graduate Research Fellowship Program Fellowship, and the Qualcomm Innovation Fellowship. Contact him at ppannuto@umich.edu.']}}, {'name': 'Yoonmyung Lee', 'affiliation': 'Sungkyunkwan University', 'bio': {'p': ['Yoonmyung Lee is an assistant professor in the Department of Semiconductor Systems Engineering at Sungkyunkwan University. His research interests include energy-efficient integrated circuits design for low-power, highperformance VLSI systems and millimeter-scale wireless sensor systems. Lee received a PhD in electrical engineering from the University of Michigan. He also received a Samsung Scholarship and Intel PhD Fellowship. Contact him at yoonmyung@skku.edu.']}}, {'name': 'Ye-Sheng Kuo', 'affiliation': 'University of Michigan', 'bio': {'p': ['Ye-Sheng Kuo is a research fellow in the Computer Science and Engineering Department at the University of Michigan. His research interests include embedded systems, sensor networks, and visible light communication. Kuo received a PhD in electrical engineering from the University of Michigan. Contact him at samkuo@umich.edu.']}}, {'name': 'ZhiYoong Foo', 'affiliation': 'University of Michigan', 'bio': {'p': ['ZhiYoong Foo is the chief executive officer of CubeWorks, a start-up spun out of the University of Michigan. His research interests include low-cost and low-power VLSI circuit systems integration. Foo received a PhD in electrical engineering from the University of Michigan, where he completed the work for this article. Contact him at zhiyoong@umich.edu.']}}, {'name': 'Benjamin Kempke', 'affiliation': 'University of Michigan', 'bio': {'p': ['Benjamin Kempke is a PhD candidate in the Electrical Engineering and Computer Science and Engineering Departments at the University of Michigan. His research interests include the design of low-power and high-accuracy indoor RF localization technologies. Kempke received an MSE in computer science and engineering from the University of Michigan. Contact him at bpkempke@umich.edu.']}}, {'name': 'Gyouho Kim', 'affiliation': 'University of Michigan', 'bio': {'p': ['Gyouho Kim is a research fellow in the Electrical Engineering Department at the University of Michigan. His research interests include ultra-low-power VLSI design for energy-constrained systems and novel sensing platforms. Kim received a PhD in electrical engineering from the University of Michigan. Contact him at gyouho@umich.edu.']}}, {'name': 'Ronald G. Dreslinski', 'affiliation': 'University of Michigan', 'bio': {'p': ["Ronald G. Dreslinski is an assistant professor in the Computer Science and Engineering Department at the University of Michigan. His research interests include near-threshold computing (NTC), architectural simulator development, and high-radix on-chip interconnects. Dreslinski received a PhD in computer science and engineering from the University of Michigan. He is the winner of the ISSCC 2011 student design contest and is the recipient of the Young Computer Architect Award from the IEEE Computer Society's Technical Committee on Computer Architecture. Contact him at rdreslin@umich.edu."]}}, {'name': 'David Blaauw', 'affiliation': 'University of Michigan', 'bio': {'p': ['David Blaauw is a professor in the Electrical and Computer Engineering Department at the University of Michigan. His research interests include VLSI design, ultra-low power, and high-performance design. Blaauw received a PhD in computer science from the University of Illinois, Urbana-Champaign. He is an IEEE Fellow. Contact him at blaauw@umich.edu.']}}, {'name': 'Prabal Dutta', 'affiliation': 'University of Michigan', 'bio': {'p': ['Prabal Dutta is an associate professor in the Electrical Engineering and Computer Science Department at the University of Michigan. His research interests include design, deployment, and scaling of wireless, embedded, networked, and sensory systems for applications in health, energy, and the environment. Dutta received a PhD in computer science from the University of California, Berkeley. He is the recipient of an Alfred P. Sloan Research Fellowship, an NSF CAREER Award, a Popular Science Brilliant Ten Award, and an Intel Early Career Award. Contact him at prabal@eecs.umich.edu.']}} %*MBus: A System Integration Bus for the Modular Microscale Computing Class %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7484947 %f/micro/p3wuelcearmpvhokw1rqn5t9kqsflhjd.pdf %ma494154b61f0f7a6bd5469ea7c7db915 %cmicro %@[{'name': 'Kaisheng Ma', 'affiliation': 'Pennsylvania State University', 'bio': {'p': ['Kaisheng Ma is a PhD student in the Department of Computer Science and Engineering at Pennsylvania State University. His research interests include energy-harvesting architectures, machine learning, and neuromorphic computing. Ma received an ME in microelectronics from Peking University. Contact him at kxm505@cse.psu.edu.']}}, {'name': 'Xueqing Li', 'affiliation': 'Pennsylvania State University', 'bio': {'p': ['Xueqing Li is a postdoctoral researcher in the Department of Computer Science and Engineering at Pennsylvania State University. His research interests include high-performance data converters, wireless transceivers, self-powered nonvolatile systems, and circuits and systems using emerging devices. Li received a PhD in electronics engineering from Tsinghua University. He is a member of IEEE. Contact him at lixueq@cse.psu.edu.']}}, {'name': 'Karthik Swaminathan', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ['Karthik Swaminathan is a researcher at the Reliability and Power-Aware Microarchitecture Group at the IBM T.J. Watson Research Center. His research interests include power-efficient and resilient systems, approximate computing, and cognitive architectures. Swaminathan received a PhD in computer science and engineering from Pennsylvania State University. Contact him at kvswamin@us.ibm.com.']}}, {'name': 'Yang Zheng', 'affiliation': 'Pennsylvania State University', 'bio': {'p': ['Yang Zheng is a software engineer at Google. His research interests include computer architecture design and nonvolatile memory. Zheng received an MS in computer science and engineering from Pennsylvania State University, where he completed the work for this article. Contact him at yxz184@cse.psu.edu.']}}, {'name': 'Shuangchen Li', 'affiliation': 'University of California, Santa Barbara', 'bio': {'p': ['Shuangchen Li is a PhD student in the Department of Electrical and Computer Engineering at the University of California, Santa Barbara. His research interests include computer architecture, especially emerging nonvolatile memory. Li received an MS in electronic engineering from Tsinghua University. Contact him at shuangchenli@ece.ucsb.edu.']}}, {'name': 'Yongpan Liu', 'affiliation': 'Tsinghua University', 'bio': {'p': ['Yongpan Liu is an associate professor in the Department of Electronic Engineering at Tsinghua University. His research interests include nonvolatile computation, low-power VLSI design, emerging circuits and systems, and design automation. Liu received a PhD in electronics engineering from Tsinghua University. He is a member of IEEE, ACM, and the Institute of Electronics, Information, and Communication Engineers. Contact him at ypliu@tsinghua.edu.cn.']}}, {'name': 'Yuan Xie', 'affiliation': 'University of California, Santa Barbara', 'bio': {'p': ['Yuan Xie is a professor in the Department of Electrical and Computer Engineering at the University of California, Santa Barbara. His research interests include computer architecture, electronic design automation, and VLSI design. Xie received a PhD in electrical engineering from Princeton University. He is a Fellow of IEEE. Contact him at yuanxie@ece.ucsb.edu.']}}, {'name': 'John Jack Sampson', 'affiliation': 'Pennsylvania State University', 'bio': {'p': ['John (Jack) Sampson is an assistant professor in the Department of Computer Science and Engineering at Pennsylvania State University. His research interests include energy-efficient computing, architectural adaptations to exploit emerging technologies, and mitigating the impact of dark silicon. Sampson received a PhD in computer engineering from the University of California, San Diego. He is a member of IEEE. Contact him at sampson@cse.psu.edu.']}}, {'name': 'Vijaykrishnan Narayanan', 'affiliation': 'Pennsylvania State University', 'bio': {'p': ['Vijaykrishnan Narayanan is a distinguished professor of computer science and engineering and electrical engineering at Pennsylvania State University. His research focuses on energy-efficient computing. Narayanan received a PhD in computer science from the University of South Florida. He is a Fellow of IEEE and ACM. Contact him at vijay@cse.psu.edu.']}} %*Nonvolatile Processor Architectures: Efficient, Reliable Progress with Unstable Power %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7478428 %f/micro/b7cfvdshqwxj3tlncq2boaehfg9zyiut.pdf %m678f71aa307e2eec7f79d2ee55610179 %cmicro %@[{'name': 'Ajaykumar Kannan', 'affiliation': 'University of Toronto', 'bio': {'p': ['Ajaykumar Kannan is an advanced design engineer in the Intel Programmable Solutions Group. His research interests include silicon-interposer-based networks on chip. Kannan received an MASc in computer engineering from the University of Toronto, where he completed the work for this article. Contact him at kannan.ajay@gmail.com.']}}, {'name': 'Natalie Enright Jerger', 'affiliation': 'University of Toronto', 'bio': {'p': ['Natalie Enright Jerger is an associate professor in the Department of Electrical and Computer Engineering at the University of Toronto. Her research interests include multi-and many-core architectures, on-chip networks, cache coherence protocols, memory systems, and approximate computing. Enright Jerger received a PhD in computer architecture from the University of Wisconsin-Madison. She is the recipient of an Alfred P. Sloan Research Fellowship, the Borg Early Career Award, the 2014 Ontario Professional Engineers Young Engineer Medal, and the 2012 Ontario Ministry of Research and Innovation Early Researcher Award. She served as program co-chair of the 7th Network-on-Chip Symposium (NOCS) and as program chair of the 20th International Symposium on High-Performance Computer Architecture (HPCA). Contact her at enright@eecg.toronto.edu.']}}, {'name': 'Gabriel H. Loh', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ["Gabriel H. Loh is a Fellow at Advanced Micro Devices. His research interests include computer architecture, processor microarchitecture, emerging technologies, and 3D die stacking. Loh received a PhD in computer science from Yale University. He's a senior member of IEEE and an ACM distinguished scientist. Contact him at gabriel.loh@amd.com."]}} %*Exploiting Interposer Technologies to Disintegrate and Reintegrate Multicore Processors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7484949 %f/micro/d0o1s72hjhwysluiktybnfjcia4f38rc.pdf %mc33ecd1c582fb4d3fda7d0bc09d8cab6 %cmicro %@[{'name': 'Sheng Li', 'affiliation': 'Intel Labs', 'bio': {'p': ["Sheng Li is a staff research scientist and a technical lead on enterprise big data at Intel's Parallel Computing Lab. He received a PhD in electrical engineering from the University of Notre Dame. Contact him at sheng.r.li@intel.com."]}}, {'name': 'Hyeontaek Lim', 'affiliation': 'Carnegie Mellon University', 'bio': {'p': ['Hyeontaek Lim is a postdoctoral researcher in the Computer Science Department at Carnegie Mellon University. He received a PhD in computer science from Carnegie Mellon University. Contact him at hl@cs.cmu.edu.']}}, {'name': 'Victor W. Lee', 'affiliation': 'Intel Labs', 'bio': {'p': ["Victor W. Lee is a principal engineer and research scientist at Intel's Parallel Computing Lab. He received an MS in electrical engineering and computer science from the Massachusetts Institute of Technology. Contact him at victor.w.lee@intel.com."]}}, {'name': 'Jung Ho Ahn', 'affiliation': 'Seoul National University', 'bio': {'p': ['Jung Ho Ahn is an associate professor in the Graduate School of Convergence Science and Technology at Seoul National University. He received a PhD in electrical engineering from Stanford University. Contact him at gajh@snu.ac.kr.']}}, {'name': 'Anuj Kalia', 'affiliation': 'Carnegie Mellon University', 'bio': {'p': ['Anuj Kalia is a PhD student in computer science at Carnegie Mellon University. He received a BS in computer science and engineering from the Indian Institute of Technology, Delhi. Contact him at akalia@cs.cmu.edu.']}}, {'name': 'Michael Kaminsky', 'affiliation': 'Intel Labs', 'bio': {'p': ['Michael Kaminsky is a senior research scientist at Intel Labs and Intel Science and Technology Center for Cloud Computing, and an adjunct faculty member of the Computer Science Department at Carnegie Mellon University. He received a PhD in computer science from the Massachusetts Institute of Technology. Contact him at michael.e.kaminsky@intel.com.']}}, {'name': 'David G. Andersen', 'affiliation': 'Carnegie Mellon University', 'bio': {'p': ['David G. Andersen is an associate professor in the Computer Science Department at Carnegie Mellon University. He received a PhD in computer science from the Massachusetts Institute of Technology. Contact him at dga@cs.cmu.edu.']}}, {'name': 'Seongil O', 'affiliation': 'Seoul National University', 'bio': {'p': ['Seongil O is a senior engineer at Samsung Electronics. He received a PhD in intelligent convergence systems from Seoul National University, where he completed the work for this article. Contact him at swdfish@snu.ac.kr.']}}, {'name': 'Sukhan Lee', 'affiliation': 'Seoul National University', 'bio': {'p': ['Sukhan Lee is a PhD student in the Department of Transdisciplinary Studies at Seoul National University. He received an MS in electrical and electronic engineering from Yonsei University. Contact him at infy1026@snu.ac.kr.']}}, {'name': 'Pradeep Dubey', 'affiliation': 'Intel Labs', 'bio': {'p': ["Pradeep Dubey is an Intel Fellow and the director of Intel's Parallel Computing Lab. He received a PhD in electrical engineering from Purdue University. Contact him at pradeep.dubey@intel.com."]}} %*Achieving One Billion Key-Value Requests per Second on a Single Server %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7436652 %f/micro/rvugzjp2cmioazrmcblgfh53xwtn769o.pdf %mafd001f88aa2c91885a2214708145d2b %cmicro %@[{'name': 'Mark C. Jeffrey', 'affiliation': 'Massachusetts Institute of Technology', 'bio': {'p': ['Mark C. Jeffrey is a PhD student in the Department of Electrical Engineering and Computer Science at the Massachusetts Institute of Technology. His research interests include parallel architectures, programming models, and speculative execution. Jeffrey received an MASc in electrical and computer engineering from the University of Toronto. He is a student member of IEEE. Contact him at mcj@csail.mit.edu.']}}, {'name': 'Suvinay Subramanian', 'affiliation': 'Massachusetts Institute of Technology', 'bio': {'p': ['Suvinay Subramanian is a PhD student in the Department of Electrical Engineering and Computer Science at the Massachusetts Institute of Technology. His research interests include parallel architectures and scalable multicore systems. Subramanian received an SM in electrical engineering and computer science from the Massachusetts Institute of Technology. He is a student member of IEEE. Contact him at suvinay@csail.mit.edu.']}}, {'name': 'Cong Yan', 'affiliation': 'University of Washington', 'bio': {'p': ['Cong Yan is a PhD student in the Department of Computer Science and Engineering at the University of Washington. Her research interests include concurrency control protocols, program-analysis-assisted databases, and scalable multicore systems. Yan received an SM in electrical engineering and computer science from the Massachusetts Institute of Technology. She is a student member of IEEE. Contact her at congy@cs.washington.edu.']}}, {'name': 'Joel Emer', 'affiliation': 'Nvidia', 'bio': {'p': ['Joel Emer is a senior distinguished research scientist at Nvidia. He is also a professor of electrical engineering and computer science at the Massachusetts Institute of Technology. His research interests include spatial and parallel architectures, performance modeling, reliability analysis, and memory hierarchies. Emer received a PhD in electrical engineering from the University of Illinois. He is a Fellow of IEEE. Contact him at emer@csail.mit.edu.']}}, {'name': 'Daniel Sanchez', 'affiliation': 'Massachusetts Institute of Technology', 'bio': {'p': ['Daniel Sanchez is an assistant professor in the Department of Electrical Engineering and Computer Science at the Massachusetts Institute of Technology. His research interests include scalable memory hierarchies, architectural support for parallelization, and architectures with quality-of-service guarantees. Sanchez received a PhD in electrical engineering from Stanford University. He is a member of IEEE. Contact him at sanchez@csail.mit.edu.']}} %*Unlocking Ordered Parallelism with the Swarm Architecture %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7436649 %f/micro/skiedbyjn0v49lnfwobcggpkx6r2w1do.pdf %mbf9c2904ba3de67582514f4c065aa298 %cmicro %@[{'name': 'Jayneel Gandhi', 'affiliation': 'University of Wisconsin--Madison', 'bio': {'p': ['Jayneel Gandhi is a PhD student in the Computer Sciences Department at University of Wisconsin-Madison. He received an MS in computer engineering from North Carolina State University and an MS in computer sciences from the University of Wisconsin-Madison. He is a student member of the ACM. Contact him at jayneel@cs.wisc.edu.']}}, {'name': 'Vasileios Karakostas', 'affiliation': 'Barcelona Supercomputing Center', 'bio': {'p': ['Vasileios Karakostas is a PhD student in the Computer Architecture Department at Universitat Politecnica de Catalunya and a researcher in the Computer Architecture for Parallel Paradigms group at Barcelona Supercomputing Center. He received an MS in computer architecture, networks, and systems from the Universitat Politecnica de Catalunya. He is a student member of ACM and IEEE. Contact him at vasilis.karakostas@bsc.es.']}}, {'name': 'Furkan Ayar', 'affiliation': 'Barcelona Supercomputing Center', 'bio': {'p': ['Furkan Ayar is an MS student in the Computer Engineering Department at Yildiz Technical University. He received a BS in computer engineering from Dumlupinar University. He performed the work for this article while an intern at the Barcelona Supercomputing Center. Contact him at frkn.ayar@gmail.com.']}}, {'name': 'Adriá,n Cristal', 'affiliation': 'Barcelona Supercomputing Center', 'bio': {'p': ['Adrian Cristal is a scientific researcher at the Spanish National Research Council (CISC-IIIA) and a comanager of the Computer Architecture for Parallel Paradigms research group at the Barcelona Supercomputing Center. He received a PhD in computer science from the Polytechnic University of Catalonia. Contact him at adrian.cristal@bsc.es.']}}, {'name': 'Mark D. Hill', 'affiliation': 'University of Wisconsin--Madison', 'bio': {'p': ['Mark D. Hill is the John P. Morgridge Professor, the Gene M. Amdahl Professor of Computer Sciences, and the Computer Sciences Department Chair at the University of Wisconsin-Madison, where he also has a courtesy appointment in the Department of Electrical and Computer Engineering. He received a PhD in computer science from the University of California, Berkeley. He is a Fellow of IEEE and ACM. Contact him at markhill@cs.wisc.edu.']}}, {'name': 'Kathryn S. McKinley', 'affiliation': 'Microsoft', 'bio': {'p': ['Kathryn S. McKinley is a principal researcher at Microsoft. She received a PhD in computer science from Rice University. She is a Fellow of IEEE and ACM. Contact her at mckinley@microsoft.com.']}}, {'name': 'Mario Nemirovsky', 'affiliation': 'ICREA', 'bio': {'p': ['Mario Nemirovsky is a Catalan Institution for Research and Advanced Studies (ICREA) Senior Research Professor at the Barcelona Supercomputing Center. He received a PhD in electrical and computer engineering from the University of California, Santa Barbara. Contact him at mario.nemirovsky@bsc.es.']}}, {'name': 'Michael M. Swift', 'affiliation': 'University of Wisconsin--Madison', 'bio': {'p': ['Michael M. Swift is an associate professor in the Computer Sciences Department at the University of Wisconsin-Madison. He received a PhD in computer science from the University of Washington. He is a member of ACM. Contact him at swift@cs.wisc.edu.']}}, {'name': 'Osman S. Ü,nsal', 'affiliation': 'Barcelona Supercomputing Center', 'bio': {'p': ['Osman S. Unsal is a comanager of the Computer Architecture for Parallel Paradigms research group at the Barcelona Supercomputing Center. He received a PhD in electrical and computer engineering from the University of Massachusetts, Amherst. He is a member of IEEE and ACM. Contact him at osman.unsal@bsc.es.']}} %*Range Translations for Fast Virtual Memory %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7436661 %f/micro/u9njoedxkch07svnkp5yr1zlwzt6j2gs.pdf %m0605efabb156850ff7c00efbbd647d9e %cmicro %@[{'name': 'Per Stenströ,m', 'affiliation': 'Chalmers University of Technology', 'bio': {'p': ['Per Stenström is a professor in the Department of Computer Science and Engineering at Chalmers University of Technology. Contact him at per.stenstrom@chalmers.se.']}} %*2015 Maurice Wilkes Award Given to Christos Kozyrakis %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7484941 %f/micro/lehto849awgcoqxg2htzabvnjckf1sf5.pdf %mfc1f9c87339123b232a9de66c5bd662b %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'Harvard Business School', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/7484939/7484952/7484952-photo-1-small.gif', 'p': ['Shane Greenstein is a professor at the Harvard Business School. Contact him at sgreenstein@hbs.edu.']}} %*Economic Growth from Technical Advance %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7484952 %f/micro/cruykpqexbqws302agtio4ozwnrudfvi.pdf %mfe6ae72484c1151ccb32396a287835b2 %cmicro %@[{'name': 'Lieven Eeckhout', 'affiliation': 'Ghent University', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/7542453/7542462/7542462-photo-1-small.gif', 'p': ['Lieven Eeckhout is a professor in the Department of Electronics and Information Systems at Ghent University. Contact him at lieven.eeckhout@ugent.be.']}} %*Hot Interconnects and Debates on Computer Architecture Research Directions %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7542462 %f/micro/vbqgqfj32b16wlpopxrufh8cyzja9gl4.pdf %m2ced6f8e05ac1dcf1277229148a0cef8 %cmicro %@[{'name': 'Ryan E. Grant', 'affiliation': 'Sandia National Laboratories', 'bio': {'p': ['Ryan E. Grant is a senior member of technical staff in the Center for Computational Research at Sandia National Laboratories. Contact him at regrant@sandia.gov.']}}, {'name': 'Ada Gavrilovska', 'affiliation': 'Georgia Tech', 'bio': {'p': ['Ada Gavrilovska is a senior research scientist in the College of Computing at Georgia Tech. Contact her at ada@cc.gatech.edu.']}} %*Hot Interconnects 23 %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7542467 %f/micro/iqvyapk0pqgnlf8swcujyzoj7nmtxtrm.pdf %md4561e9964dbb014e6cbe3f5ec9898e9 %cmicro %@[{'name': 'Salvatore Di Girolamo', 'affiliation': 'ETH Zü,rich', 'bio': {'p': ["Salvatore Di Girolamo is a PhD student at ETH Zürich. His research interests include high-performance networking and communication offload for next-generation networks and RMA programming. Di Girolamo received an MSc in computer science and networking from the University of Pisa and Scuola Superiore Sant'Anna, Italy. Contact him at digirols@inf.ethz.ch."]}}, {'name': 'Pierre Jolivet', 'affiliation': 'CNRS', 'bio': {'p': ['Pierre Jolivet is a scientist at CNRS in the Toulouse Institute of Computer Science Research. His research interests include numerical linear algebra, computational physics, and high-performance scientific computing. Jolivet received a PhD in applied mathematics from the Université de Grenoble. Contact him at pierre.jolivet@enseeiht.fr.']}}, {'name': 'Keith D. Underwood', 'affiliation': 'Intel', 'bio': {'p': ['Keith D. Underwood leads a product architecture team for next-generation host fabric interfaces in the Omni-PathArchitecture group at Intel. His research interests include hardware/software co-design to support HPC networking, enhanced collective operation architectures, and alternative computing architectures. Underwood received a PhD in computer engineering from Clemson University. Contact him at keith.d.underwood@intel.com.']}}, {'name': 'Torsten Hoefler', 'affiliation': 'ETH Zü,rich', 'bio': {'p': ['Torsten Hoefler is an assistant professor in the Department of Computer Science at ETH Zürich. His research interests include performance-centric software development, scalable networks, parallel programming techniques, and performance modeling. Hoefler received a PhD in computer science from Indiana University. Contact him at htor@infethz.ch.']}} %*Exploiting Offload-Enabled Network Interfaces %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7542472 %f/micro/of0hm6ie2huanzexgd5tixrrcyqwfblv.pdf %m9218e221876c00dfc7e2fabc2f170bd9 %cmicro %@[{'name': 'John W. Lockwood', 'affiliation': 'Algo-Logic Systems', 'bio': {'p': ['John W. Lockwood is the CEO of Algo-Logic Systems. His research interests include design of low-latency networking systems, reconfigurable logic, and high-performance computing. Lockwood received a PhD in electrical and computer engineering from the University of Illinois, Urbana—Champaign. He is a member of IEEE, ACM, and Tau Beta Pi. Contact him at jwlockwd@algo-logic.com.']}}, {'name': 'Madhu Monga', 'affiliation': 'Algo-Logic Systems', 'bio': {'p': ['Madhu Monga is a technical staff member at Algo-Logic Systems. Her research interests include designing high-performance FPGA-based solutions for datacenters. Monga received an MS in computer engineering from Iowa State University. Contact her at madhu@algo-logic.com.']}} %*Implementing Ultra-Low-Latency Datacenter Services with Programmable Logic %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7542471 %f/micro/lxmigbnywuekmbdfjtqir6o7vyejfs2z.pdf %m6fa5594bda2c58344de4f46368c4a6a6 %cmicro %@[{'name': 'Amitabha Banerjee', 'affiliation': 'VMware', 'bio': {'p': ['Amitabha Banerjee is a staff engineer at VMware. His research interests include performance issues in computer systems. Banerjee received a PhD in computer science from the University of California, Davis. Contact him at banerjeea@vmware.com.']}}, {'name': 'Rishi Mehta', 'affiliation': 'VMware', 'bio': {'p': ['Rishi Mehta is a staff engineer at VMware. His research interests include networking performance in computer systems. Mehta received an MS in computer science from North Carolina State University. Contact him at rmehta@vmware.com.']}}, {'name': 'Zach Shen', 'affiliation': 'VMware', 'bio': {'p': ['Zach Shen is a senior member of technical staff at VMware. His research interests include improving the networking performance of interconnected computer systems. Shen received a PhD in electrical engineering from the University of Cambridge. Contact him at zshen@vmware.com.']}} %*Supporting NUMA-Aware I/O in Virtual Machines %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7542469 %f/micro/8eakkjibhqytue2mwarvhyg9nosfjgcw.pdf %md98fa063f18ea9b2d245e1dbe028c383 %cmicro %@[{'name': 'Mark S. Birrittella', 'affiliation': 'Intel', 'bio': {'p': ['Mark S. Birrittella is the architect for the Omni-Path Architecture link transfer layer at Intel. His research interests include computer network architectures and protocols, highperformance clock distribution, and efficient clock domain crossing techniques. Birrittella received an MS in electrical engineering from the University of Florida. Contact him at mark.s.birrittella@intel.com.']}}, {'name': 'Mark Debbage', 'affiliation': 'Intel', 'bio': {'p': ['Mark Debbage is a principal engineer in the Enterprise and HPC Platform Group at Intel, where he is the lead architect of the host fabric interface for the 100 Series of OPA products. Debbage received a PhD in electronics and computer science from the University of Southampton. Contact him at mark.debbage@intel.com.']}}, {'name': 'Ram Huggahalli', 'affiliation': 'Intel', 'bio': {'p': ['Ram Huggahalli leads the fabric performance modeling team in the Intel OPA group. He is a principal engineer specializing in network architecture and simulation methodologies. Huggahalli received an MS in electrical engineering and an MS in engineering management from the University of Missouri. Contact him at ram.huggahalli@intel.com.']}}, {'name': 'James Kunz', 'affiliation': 'Intel', 'bio': {'p': ['James Kunz is the lead architect for the switch for the 100 Series of OPA products. His research interests include highperformance switch architectures, HPC fabric diagnostic strategies and tools, and switch performance tradeoffs. Kunz received a BS in electrical engineering from the University of Minnesota. Contact him at james.kunz@intel.com.']}}, {'name': 'Tom Lovett', 'affiliation': 'Intel', 'bio': {'p': ['Tom Lovett is part of the Intel OPA group and manages the Core Architecture team. His research interests include high-performance interconnects, congestion management, and time synchronization. Lovett received an MS in electrical engineering from the University of Illinois. Contact him at thomas.d.lovett@intel.com.']}}, {'name': 'Todd Rimmer', 'affiliation': 'Intel', 'bio': {'p': ['Todd Rimmer is a principal engineer and the lead software architect for the Intel Omni-Path Fabric. His research interests include high-performance computing, remote direct memory access, high-performance I/O, and InfiniBand. Rimmer received a BS in computer science from Drexel University. Contact him at todd.rimmer@intel.com.']}}, {'name': 'Keith D. Underwood', 'affiliation': 'Intel', 'bio': {'p': ['Keith D. Underwood leads a product architecture team for next-generation host fabric interfaces in the Intel Omni-Path Architecture group. His research interests include hardware/software co-design to support HPC networking, enhanced collective operation architectures, and alternative computing architectures. Underwood received a PhD in computer engineering from Clemson University. Contact him at keith.d.underwood@intel.com.']}}, {'name': 'Robert C. Zak', 'affiliation': 'Intel', 'bio': {'p': ['Robert C. Zak leads an architecture and technology pathfinding effort in the Intel Omni-Path Architecture group. His research interests include hardware/software interfaces, dynamic congestion control and quality of service, and improving power efficiency. Zak received an MS in computer science from the Massachusetts Institute of Technology. Contact him at robert.c.zak@intel.com.']}} %*Enabling Scalable High-Performance Systems with the Intel Omni-Path Architecture %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7542460 %f/micro/guh3vtm8flgrhfxvdikn2ljbxpy0seca.pdf %md8d646746d8f3a0bbd10b6828b2eb892 %cmicro %@[{'name': 'Trevor Mudge', 'affiliation': 'University of Michigan'}, {'name': 'Frederic T. Chong', 'affiliation': 'University of Chicago'}, {'name': 'Igor L. Markov', 'affiliation': 'University of Michigan'}, {'name': 'Resit Sendag', 'affiliation': 'University of Rhode Island'}, {'name': 'Joshua J. Yi', 'affiliation': 'Dechert'}, {'name': 'Derek Chiou', 'affiliation': 'University of Texas at Austin'} %*Impact of Future Technologies on Architecture %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7542468 %f/micro/bkpgu1xnc9zwpc5dsvnhjeixq3mogvq8.pdf %m9fb950e64d56e0f96a62703aa94744b3 %cmicro %@[{'name': 'Mark D. Hill', 'affiliation': 'University of Wisconsin-Madison'}, {'name': 'Dave Christie', 'affiliation': 'Advanced Micro Devices'}, {'name': 'David Patterson', 'affiliation': 'University of California, Berkeley'}, {'name': 'Joshua J. Yi', 'affiliation': 'Dechert'}, {'name': 'Derek Chiou', 'affiliation': 'University of Texas at Austin'}, {'name': 'Resit Sendag', 'affiliation': 'University of Rhode Island'} %*Proprietary versus Open Instruction Sets %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7542457 %f/micro/exglqq4k6zmuhskrcp8beftwbv9nwra0.pdf %mec6cc38ca7b4b16c4405569122ce3e2d %cmicro %@[{'name': 'Onur Mutlu', 'affiliation': 'ETH Zurich', 'bio': {'p': ['Onur Mutlu is a full professor of computer science at ETH Zurich and a faculty member at Carnegie Mellon University. Contact him at onur.mutlu@inf.ethz.ch.']}}, {'name': 'Rich Belgard', 'bio': {'p': ['Rich Belgard is an independent consultant for computer manufacturers, software companies, and investor groups and an expert and consultant to law firms. Contact him at belgard@gmail.com.']}}, {'name': 'Thomas R. Gross', 'affiliation': 'ETH Zurich'}, {'name': 'Norman R. Jouppi', 'affiliation': 'Google'}, {'name': 'John L. Hennessy', 'affiliation': 'Stanford University'}, {'name': 'Steven Przybylski', 'affiliation': 'Verdande Group'}, {'name': 'Chris Rowen', 'affiliation': 'Cadence Design Systems'}, {'name': 'Yale N. Patt', 'affiliation': 'University of Texas at Austin'}, {'name': 'Wen-Mei W. Hwu', 'affiliation': 'University of Illinois at Urbana-Champaign'}, {'name': 'Stephen W. Melvin'}, {'name': 'Michael C. Shebanow', 'affiliation': 'Samsung'}, {'name': 'Tse-Yu Yeh', 'affiliation': 'Apple'}, {'name': 'Andy Wolfe', 'affiliation': 'Santa Clara University'} %*Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7542473 %f/micro/zab0sioh7z2yuhunrtivlgqyj8efktk4.pdf %m2dc1453b9e5fc4a7e02358b83a9f0393 %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'Harvard Business School', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/7542453/7542459/7542459-photo-1-small.gif', 'p': ['Shane Greenstein is a professor at the Harvard Business School. Contact him at sgreenstein@hbs.edu.']}} %*Ten Open Questions for Techno-Optimists %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7542459 %f/micro/nusfpt1aabpxl4tzf803ujkh6oigq7oe.pdf %m69fe03b8f8196f3166737c7bacc2dead %cmicro %@[{'name': 'Lieven Eeckhout', 'affiliation': 'Ghent University', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/7723773/7723787/7723787-photo-1-small.gif', 'p': ['Lieven Eeckhout is a professor in the Department of Electronics and Information Systems at Ghent University. Contact him at lieven.eeckhout@ugent.be.']}} %*Security and Our Reader Survey %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7723787 %f/micro/hucll5xaoy1sb2kgrqiemstgpwo0zyba.pdf %m0966c3f59341745a539c0873c2b5c512 %cmicro %@[{'name': 'Mohit Tiwari', 'affiliation': 'University of Texas at Austin'}, {'name': 'Todd Austin', 'affiliation': 'University of Michigan'} %*On Architectural Support for Systems Security %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7723802 %f/micro/zvcfa0bbiuoyh3gz2egillsf6ohnndre.pdf %m21e5f4c3e5f5b44b7af2a75a636faecc %cmicro %@[{'name': 'Fangfei Liu', 'affiliation': 'Princeton University'}, {'name': 'Hao Wu', 'affiliation': 'Princeton University'}, {'name': 'Kenneth Mai', 'affiliation': 'Carnegie Mellon University'}, {'name': 'Ruby B. Lee', 'affiliation': 'Princeton University'} %*Newcache: Secure Cache Architecture Thwarting Cache Side-Channel Attacks %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7723806 %f/micro/cr2xfpz3eyxjdtvi7ad1agwqzm8rl5uj.pdf %m7e67480726c9b54b5da8e903fffdc927 %cmicro %@[{'name': 'Guru Venkataramani', 'affiliation': 'George Washington University'}, {'name': 'Jie Chen', 'affiliation': 'George Washington University'}, {'name': 'Milos Doroslovacki', 'affiliation': 'George Washington University'} %*Detecting Hardware Covert Timing Channels %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7723790 %f/micro/bownz2ab9e1vutf7y8ax0pifspvdkrxg.pdf %mcd6bcb52ac888d4ff22086b5aea67246 %cmicro %@[{'name': 'Tianwei Zhang', 'affiliation': 'Princeton University'}, {'name': 'Ruby B. Lee', 'affiliation': 'Princeton University'} %*Monitoring and Attestation of Virtual Machine Security Health in Cloud Computing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7723793 %f/micro/hlkrt87xts6bqn2ofmqunw4gucxv3spl.pdf %mf70c69a1fa22bbdb9d80226b63e5d63c %cmicro %@[{'name': 'Robert N.M. Watson', 'affiliation': 'University of Cambridge', 'bio': {'p': ['Robert N.M. Watson is a university senior lecturer at the University of Cambridge Computer Laboratory. He received a PhD in computer science from the University of Cambridge. Contact him at robert.watson@cl.cam.ac.uk.']}}, {'name': 'Robert M. Norton', 'affiliation': 'University of Cambridge', 'bio': {'p': ['Robert M. Norton is a research associate at the University of Cambridge Computer Laboratory. He received a PhD from the University of Cambridge. Contact him at robert.norton@cl.cam.ac.uk.']}}, {'name': 'Jonathan Woodruff', 'affiliation': 'University of Cambridge', 'bio': {'p': ['Jonathan Woodruff is a research associate at the University of Cambridge Computer Laboratory. He received a PhD from the University of Cambridge. Contact him at jonathan.woodruff@cl.cam.ac.uk.']}}, {'name': 'Simon W. Moore', 'affiliation': 'University of Cambridge', 'bio': {'p': ['Simon W. Moore is a professor of computer engineering at the University of Cambridge Computer Laboratory. He received a PhD in computer science from the University of Cambridge. Contact him at simon.moore@cl.cam.ac.uk.']}}, {'name': 'Peter G. Neumann', 'affiliation': 'SRI International', 'bio': {'p': ['Peter G. Neumann is a senior principal scientist in the Computer Science Laboratory at SRI International. He received a PhD in applied math from Harvard University. Contact him at neumann@csl.sri.com.']}}, {'name': 'Jonathan Anderson', 'affiliation': 'Memorial University', 'bio': {'p': ['Jonathan Anderson is an assistant professor in the Electrical and Computer Engineering Department at Memorial University. He received a PhD from the University of Cambridge. Contact him at jonathan.anderson@mun.ca.']}}, {'name': 'David Chisnall', 'affiliation': 'University of Cambridge', 'bio': {'p': ['David Chisnall is a senior research associate at the University of Cambridge Computer Laboratory. He received a PhD in computer science from Swansea University. Contact him at david.chisnall@cl.cam.ac.uk.']}}, {'name': 'Brooks Davis', 'affiliation': 'SRI International', 'bio': {'p': ['Brooks Davis is a senior software engineer at SRI International. He received a BS in computer science from Harvey Mudd College. Contact him at brooks@csl.sri.com.']}}, {'name': 'Ben Laurie', 'affiliation': 'Google', 'bio': {'p': ['Ben Laurie is head of security and transparency at Google DeepMind. Contact him at benl@google.com.']}}, {'name': 'Michael Roe', 'affiliation': 'University of Cambridge', 'bio': {'p': ['Michael Roe is a senior research associate at the University of Cambridge. He received a PhD in computer science from the University of Cambridge. Contact him at michael.roe@cl.cam.ac.uk.']}}, {'name': 'Nirav H. Dave', 'affiliation': 'Google', 'bio': {'p': ['Nirav H. Dave is an engineer at Google. He received a PhD in electrical engineering and computer science from the Massachusetts Institute of Technology. Contact him at niravhdave@gmail.com.']}}, {'name': 'Khilan Gudka', 'affiliation': 'University of Cambridge', 'bio': {'p': ['Khilan Gudka is a research associate in the Security group at the University of Cambridge Computer Laboratory. He received a PhD from Imperial College London. Contact him at khilan.gudka@cl.cam.ac.uk.']}}, {'name': 'Alexandre Joannou', 'affiliation': 'University of Cambridge', 'bio': {'p': ["Alexandre Joannou is a PhD student at the University of Cambridge Computer Laboratory. He received an MEng in embedded systems at Ecole Centrale d'Electronique and an MS in computer architecture from UPMC Sorbonne University. Contact him at alexandre.joannou@cl.cam.ac.uk."]}}, {'name': 'A. Theodore Markettos', 'affiliation': 'University of Cambridge', 'bio': {'p': ['A. Theodore Markettos is a senior research associate at the University of Cambridge Computer Laboratory. He received a PhD in computer science from the University of Cambridge. Contact him at theo.markettos@cl.cam.ac.uk.']}}, {'name': 'Ed Maste', 'affiliation': 'University of Cambridge', 'bio': {'p': ['Ed Maste is a consultant to the University of Cambridge and SRI International. He received a BASc in computer engineering from the University of Waterloo. Contact him at emaste@FreeBSD.org.']}}, {'name': 'Steven J. Murdoch', 'affiliation': 'University College London', 'bio': {'p': ['Steven J. Murdoch is a Royal Society University Research Fellow in the Information Security Research Group of University College London. He received a PhD in computer science from the University of Cambridge. Contact him at s.murdoch@ucl.ac.uk.']}}, {'name': 'Colin Rothwell', 'affiliation': 'University of Cambridge', 'bio': {'p': ['Colin Rothwell is a PhD student at the University of Cambridge. He received a BA in computer science from the University of Cambridge. Contact him at colin.rothwell@cl.cam.ac.uk.']}}, {'name': 'Stacey D. Son', 'affiliation': 'University of Cambridge', 'bio': {'p': ['Stacey D. Son is a consultant to the University of Cambridge and SRI International. He received a BS in electrical engineering from Brigham Young University. Contact him at sson@me.com.']}}, {'name': 'Munraj Vadera', 'affiliation': 'University of Cambridge', 'bio': {'p': ['Munraj Vadera is a software developer in the finance industry. He completed the work for this article as a research assistant at the University of Cambridge Computer Laboratory. He received a BA in computer science from the University of Cambridge. Contact him at munraj.vadera@gmail.com.']}} %*Fast Protection-Domain Crossing in the CHERI Capability-System Architecture %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7723791 %f/micro/ljwengpr09tkm4dva1uisckiyfhyxbo2.pdf %maebffa0497ecbbf8ced6d40180a0e179 %cmicro %@[{'name': 'Chandra K.H. Suresh', 'affiliation': 'New York University'}, {'name': 'Bodhisatwa Mazumdar', 'affiliation': 'NYU Abu Dhabi'}, {'name': 'Sk Subidh Ali', 'affiliation': 'Indian Institute of Technology, Tirupati'}, {'name': 'Ozgur Sinanoglu', 'affiliation': 'NYU Abu Dhabi'} %*A Comparative Security Analysis of Current and Emerging Technologies %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7723782 %f/micro/psrioj9vijgmx3nrxul8dla4vwetqszp.pdf %m636e25a13884fe702083e9bfa6ee0f00 %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'Harvard Business School'} %*No Rosetta Stone for Market Vitality %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7723792 %f/micro/rh89xcvaehamjimwsgeuncuo4ynf3f0p.pdf %m34a31de0a32e0a3e31ad493124628a98 %cmicro %@[{'name': 'Lieven Eeckhout', 'affiliation': 'Ghent University', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/7765184/7765236/7765236-photo-1-small.gif', 'p': ['Lieven Eeckhout is a professor in the Department of Electronics and Information Systems at Ghent University. Contact him at lieven.eeckhout@ugent.be.']}} %*The Internet of Things Revolution %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7765236 %f/micro/3luswr209c8pznc6bvlghawdmtqodpmj.pdf %m9b691a5d86f2e74599f3782c8b9036dc %cmicro %@[{'name': 'Vijay Janapa Reddi', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ['Vijay Janapa Reddi is an assistant professor in the Department of Electrical and Computer Engineering at the University of Texas at Austin. Contact him at vj@ece.utexas.edu.']}}, {'name': 'Hyesoon Kim', 'affiliation': 'Georgia Institute of Technology', 'bio': {'p': ['Hyesoon Kim is an associate professor in the School of Computer Science at the Georgia Institute of Technology. Contact her at hyesoon@cc.gatech.edu.']}} %*On the Internet of Things %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7765237 %f/micro/wokaryriflwdzhct9fxq3hj7ngpmv6tu.pdf %mbc9a493781326623552e92dba4aa177b %cmicro %@[{'name': 'Andreas Engel', 'affiliation': 'Technische Universitä,t Darmstadt', 'bio': {'p': ['Andreas Engel is a postdoctoral researcher at Technische Universität Darmstadt. His research interests include microcontroller-and FPGA-based wireless sensor networks, energy-management concepts for long-term WSN operation, and coarse-grained reconfigurable array-based hardware accelerators. Engel received a PhD in engineering from Technische Universität Darmstadt. Contact him at engel@esa.cs.tu-darmstadt.de.']}}, {'name': 'Andreas Koch', 'affiliation': 'Technische Universitä,t Darmstadt', 'bio': {'p': ['Andreas Koch is a full professor and the head of the Embedded Systems and Applications group in the Computer Science Department at Technische Universität Darmstadt. His research interests include application-specific computer architectures and their design and programming tools. Koch received a PhD in engineering from Technische Universität Braunschweig. Contact him at koch@esa.cs.tu-darmstadt.de.']}} %*Heterogeneous Wireless Sensor Nodes that Target the Internet of Things %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7765192 %f/micro/kvoyqbk6jfyug79mw0dsuac41qlrdivl.pdf %m1e78dc3903728032c3db97b7ee9c110d %cmicro %@[{'name': 'Bongjun Kim', 'affiliation': 'Pohang University of Science and Technology', 'bio': {'p': ['Bongjun Kim is a PhD student in the Department of Computer Science and Engineering at Pohang University of Science and Technology (POSTECH). His research focuses on compiler optimization for the Internet of Things and security. Kim received a BS in computer science and engineering from POSTECH. Contact him atbong90@postech.ac.kr.']}}, {'name': 'Seonyeong Heo', 'affiliation': 'Pohang University of Science and Technology', 'bio': {'p': ['Seonyeong Heo is a PhD student in the Department of Computer Science and Engineering at Pohang University of Science and Technology (POSTECH). Her research interests include compiler optimization for dynamic software updating and the Internet of Things. Heo received a BS in computer science and engineering from POSTECH. Contact her at heosy@postech.ac.kr.']}}, {'name': 'Gyeongmin Lee', 'affiliation': 'Pohang University of Science and Technology', 'bio': {'p': ['Gyeongmin Lee is a PhD student in the Department of Creative IT Engineering at Pohang University of Science and Technology (POSTECH). His research focuses on the programmability of IoT applications. Lee received a BS in computer science and engineering from POSTECH. Contact him at paina@postech.ac.kr.']}}, {'name': 'Soyeon Park', 'affiliation': 'Pohang University of Science and Technology', 'bio': {'p': ['Soyeon Park is an undergraduate student in the Department of Computer Science and Engineering at Pohang University of Science and Technology (POSTECH). Her research interests include computer systems and security. Contact her at thdusdl1219@postech.ac.kr.']}}, {'name': 'Hanjun Kim', 'affiliation': 'Pohang University of Science and Technology', 'bio': {'p': ['Hanjun Kim is an assistant professor in the Departments of Creative IT Engineering and Computer Science and Engineering at Pohang University of Science and Technology (POSTECH). His research interests include computer architecture and compiler optimization for distributed and emerging systems. Kim has a PhD in computer science from Princeton University. Contact him at hanjun@postech.ac.kr.']}}, {'name': 'Jong Kim', 'affiliation': 'Pohang University of Science and Technology', 'bio': {'p': ['Jong Kim is a professor in the Department of Computer Science and Engineering at Pohang University of Science and Technology (POSTECH). He is also a director of POSTECH Information Research Laboratories. His research interests include system and network security, mobile embedded software, dependable computing, and parallel and distributed computing. Kim received a PhD in computer engineering from Pennsylvania State University. Contact him at jkim@postech.ac.kr.']}} %*Heterogeneous Distributed Shared Memory for Lightweight Internet of Things Devices %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7765242 %f/micro/vhwodjca8sz1ydi05keq27sp6lfuiwle.pdf %m26034c0f156c2315e7a6cae6841ebe09 %cmicro %@[{'name': 'Moreno Ambrosin', 'affiliation': 'University of Padua', 'bio': {'p': ['Moreno Ambrosin is a PhD student in computer science at the University of Padua. His research interests include distributed systems security. Ambrosin received an MSc in computer science from the University of Padua. He is a student member of IEEE. Contact him at ambrosin@math.unipd.it.']}}, {'name': 'Arman Anzanpour', 'affiliation': 'University of Turku', 'bio': {'p': ["Arman Anzanpour is a PhD student in the IoT for Health group at the University of Turku. His research interests include the Internet of Things and smart health monitoring frameworks. Anzanpour received a master's degree in biomedical engineering from Amirkabir University of Technology. He is a student member of IEEE. Contact him at armanz@utu.fi."]}}, {'name': 'Mauro Conti', 'affiliation': 'University of Padua', 'bio': {'p': ['Mauro Conti is an associate professor in the Department of Mathematics at the University of Padua. His research interests include security and privacy. Conti received a PhD in computer science from Sapienza University of Rome. His awards include a Marie Curie Fellowship and a fellowship by the German DAAD. He is an associate editor of IEEE Communications Surveys & Tutorials and IEEE Transactions on Information Forensics and Security. He is a senior member of IEEE. Contact him at conti@math.unipd.it.']}}, {'name': 'Tooska Dargahi', 'affiliation': 'CNIT (Consorzio Nazionale Interuniversitario per le Telecomunicazioni)', 'bio': {'p': ['Tooska Dargahi is a postdoctoral researcher at CNIT (Consorzio Nazionale Interuniversitario per le Telecomunicazioni) and the University of Rome Tor Vergata. Her research interests include security and privacy. Dargahi received a PhD in computer engineering from Islamic Azad University, Science and Research Branch. She is a professional member of ACM. Contact her at tooska.dargahi@cnit.it.']}}, {'name': 'Sanaz Rahimi Moosavi', 'affiliation': 'University of Turku', 'bio': {'p': ['Sanaz Rahimi Moosavi is a PhD student in the Department of Information Technology at the University of Turku. Her research interests include security and privacy, healthcare technology, the Internet of Things, and lightweight cryptography. Rahimi Moosavi received an MSc (Tech.) in IT networked systems security from the University of Turku. She is a student member of IEEE. Contact her at saramo@utu.fi.']}}, {'name': 'Amir M. Rahmani', 'affiliation': 'University of Turku', 'bio': {'p': ['Amir M. Rahmani is the Marie Curie Global Fellow at the University of California, Irvine, and TU Wien, Austria. He is also an adjunct professor (docent) in embedded parallel and distributed computing at the University of Turku. His research interests include self-aware parallel and distributed computing, healthcare Internet of Things, and embedded systems. Rahmani received a PhD in ICT from the University of Turku. He is a member of IEEE. Contact him at amirr1@uci.edu.']}}, {'name': 'Pasi Liljeberg', 'affiliation': 'University of Turku', 'bio': {'p': ['Pasi Liljeberg is an adjunct professor of embedded computing architectures at the University of Turku. His research interests include the Internet of Things, healthcare technology, embedded systems, and multicore processor architectures. Liljeberg received a PhD in communication systems from the University of Turku. He is a member of IEEE. Contact him at pasi.liljeberg@utu.fi.']}} %*On the Feasibility of Attribute-Based Encryption on Internet of Things Devices %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7765239 %f/micro/ljhtf8uy4iazx196swbkleqgn0wfkhpo.pdf %m13830356b9c056f51828e92aa51f9c68 %cmicro %@[{'name': 'Damian Roca', 'affiliation': 'Barcelona Supercomputing Center'}, {'name': 'Daniel Nemirovsky', 'affiliation': 'Barcelona Supercomputing Center'}, {'name': 'Mario Nemirovsky', 'affiliation': 'ICREA at Barcelona Supercomputing Center'}, {'name': 'Rodolfo Milito', 'affiliation': 'Cisco Systems'}, {'name': 'Mateo Valero', 'affiliation': 'Barcelona Supercomputing Center and Universitat Politè,cnica de Catalunya'} %*Emergent Behaviors in the Internet of Things: The Ultimate Ultra-Large-Scale System %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7765233 %f/micro/12bgzznw8cohiabvg75f6sjelxkrdktr.pdf %ma2b337f252eeae48f0c25dfa2ade78d5 %cmicro %@[{'name': 'Ravi Iyer', 'affiliation': 'Intel', 'bio': {'p': ['Ravi Iyer is a senior principal engineer, CTO, and director in New Business Initiatives at Intel. He is an IEEE Fellow. Contact him at ravishankar.iyer@intel.com.']}}, {'name': 'Emre Ozer', 'affiliation': 'ARM', 'bio': {'p': ['Emre Ozer is a principal research engineer at ARM Research in Cambridge. Contact him at emre.ozer@arm.com.']}} %*Visual IoT: Architectural Challenges and Opportunities; Toward a Self-Learning and Energy-Neutral IoT %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7765234 %f/micro/emx7pyhgqmcvvwtyzunzlpa9fibqi1kf.pdf %me7d61761a7cfdde5ffd99eaf61f49914 %cmicro %@[{'name': 'Nikolaos Chrysos', 'affiliation': 'IBM Research Zurich'}, {'name': 'Fredy Neeser', 'affiliation': 'IBM Research Zurich'}, {'name': 'Rolf Clauberg', 'affiliation': 'IBM Research Zurich'}, {'name': 'Daniel Crisan', 'affiliation': 'IBM Research Zurich'}, {'name': 'Kenneth M. Valk', 'affiliation': 'IBM Systems &,amp, Technology Group'}, {'name': 'Claude Basso', 'affiliation': 'IBM Research'}, {'name': 'Cyriel Minkenberg', 'affiliation': 'IBM Research Zurich'}, {'name': 'Mitch Gusat', 'affiliation': 'IBM Research Zurich'} %*Unbiased Quantized Congestion Notification for Scalable Server Fabrics %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7325171 %f/micro/mphqfoctwj7y342ea5zsnckgxjrdu8ab.pdf %mecc90d35c7dc1d6380751601e6626f26 %cmicro %@[{'name': 'David H. Albonesi', 'affiliation': 'Cornell University'} %*2015 International Symposium on Computer Architecture Influential Paper Award %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7765241 %f/micro/hb9wzoajr06legmv18rudtse2htxflkf.pdf %m504653bfc8ee690c87126e9ae1ff3ba4 %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'Harvard Business School', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/7765184/7765191/7765191-photo-1-small.gif', 'p': ['Shane Greenstein is a professor at the Harvard Business School. Contact him at sgreenstein@hbs.edu.']}} %*Congestion on the Last Mile %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7765191 %f/micro/xwhvi3rsmyj0amog2i9qzb4nvrbq8cwy.pdf %mf36e0631d5bd6fa56510d79a89100d9a %cmicro %@[{'name': 'Lieven Eeckhout', 'affiliation': 'Ghent University', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/7057031/7057601/7057601-photo-1-small.gif', 'p': ['Lieven Eeckhout is a professor in the Department of Electronics and Information Systems at Ghent University. Contact him at lieven.eeckhout@ugent.be.']}} %*Building on 35 Years toward a Vibrant Future %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7057601 %f/micro/yt8ljsnrhou9eojybvpqx6hn0ewad7m4.pdf %mac73d7ea07cea3becd9ac048e5be1e8e %cmicro %@[{'name': 'Calin Cascaval', 'affiliation': 'Qualcomm Research Silicon Valley', 'bio': {'p': ['Calin Cascaval is a senior director at Qualcomm Research Silicon Valley, where he is leading projects in parallel and heterogeneous computing, including the MARE runtime system and programming model for heterogeneous computing, parallel libraries and applications, such as the Zoomm parallel browser, and compiler technologies, such as the MCJS JavaScript engine. Cascaval has a PhD in computer science from the University of Illinois at Urbana-Champaign. He is a member of IEEE and the ACM. Contact him at cascaval@acm.org.']}} %*Special Issue on Mobile Systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7057575 %f/micro/jugc5hhpsokdfxd8z6t0lsfazeqkx2nr.pdf %m85d7600776f8353c07472a6810e951c3 %cmicro %@[{'name': 'Mircea Horea Ionica', 'affiliation': 'Trinity College Dublin', 'bio': {'p': ['Mircea Horea Ionică is a PhD student in the School of Computer Sciences and Statistics at Trinity College Dublin. His research interests include multicore computing and embedded systems. Ionică has a BSc in systems engineering and computer sciences from Universitatea Politehnica in Timi§oara. He is a member of Lero, the Irish Software Engineering Research Centre. Contact him at ionicam@tcd.ie.']}}, {'name': 'David Gregg', 'affiliation': 'Trinity College Dublin', 'bio': {'p': ['David Gregg is a senior lecturer in the School of Computer Sciences and Statistics at Trinity College Dublin. His research interests include compilers, software development tools, and program optimization with a focus on multicore architectures. Gregg has a DTech in computer science from the Technische Universität in Vienna. He is a member of Lero. Contact him at dgregg@tcd.ie.']}} %*The Movidius Myriad Architecture's Potential for Scientific Computing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7006377 %f/micro/myk7frjctvonllfkupn6oawshqemzpi2.pdf %m08fdbbe211d31552f83279a8c9600e60 %cmicro %@[{'name': 'Hyojong Kim', 'affiliation': 'Georgia Institute of Technology', 'bio': {'p': ['Hyojong Kim is a PhD student in the School of Computer Science at the Georgia Institute of Technology. His research focuses on memory systems for near-data processing. Kim has a BS in electrical and computer engineering from Seoul National University. Contact him at hyojong.kim@gatech.edu.']}}, {'name': 'Hongyeol Lim', 'affiliation': 'Sejong University', 'bio': {'p': ['Hongyeol Lim is a PhD student in the Department of Computer Science and Engineering at Sejong University. His research interests include high-performance computer architecture and memory hierarchy design with 3D-stacked memory in embedded systems. Lim has a BS in computer engineering from Sejong University. He is a member of IEEE and the ACM. Contact him at hylim@sju.ac.kr.']}}, {'name': 'Dilan Manatunga', 'affiliation': 'Georgia Institute of Technology', 'bio': {'p': ['Dilan Manatunga is a PhD student in the School of Computer Science at the Georgia Institute of Technology. His research focuses on optimizations for mobile operating systems and architectures. Manatunga has a BS in computer science from the Georgia Institute of Technology. Contact him at dmanatunga@gatech.edu.']}}, {'name': 'Hyesoon Kim', 'affiliation': 'Georgia Institute of Technology', 'bio': {'p': ['Hyesoon Kim is an associate professor in the School of Computer Science at the Georgia Institute of Technology. Her research interests include high-performance, energy-efficient heterogeneous architectures, interaction between programmers, compilers, and microarchitectures, and developing tools to help parallel programming. Kim has a PhD in computer engineering from the University of Texas at Austin. She is a member of IEEE and the ACM. Contact her at hyesoon@cc.gatech.edu.']}}, {'name': 'Gi-Ho Park', 'affiliation': 'Sejong University', 'bio': {'p': ['Gi-Ho Park is an associate professor in the Department of Computer Science and Engineering at Sejong University. His research interests include advanced computer architectures, memory system design, system-on-chip (SoC) design, and embedded system design. Park has a PhD in computer science from Yonsei University. He is a member of IEEE and a professional member of the ACM. Contact him at ghpark@sejong.ac.kr.']}} %*Accelerating Application Start-up with Nonvolatile Memory in Android Systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7006346 %f/micro/hm7jwnfuzwt3aggock8fyvauolm9tzhb.pdf %mdcbb254e28787a9ffc461fdf36fa38b8 %cmicro %@[{'name': 'Yuhao Zhu', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ['Yuhao Zhu is a PhD student in the Department of Electrical and Computer Engineering at the University of Texas at Austin. His research focuses on improving the energy efficiency of mobile Web computing holistically, spanning processor architecture, runtime systems, and language extensions. Zhu has a BS in computer science and engineering from Beihang University. Contact him at yzhu@utexas.edu.']}}, {'name': 'Matthew Halpern', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ['Matthew Halpern is a PhD student in the Department of Electrical and Computer Engineering at the University of Texas at Austin. His research interests include runtime systems and computer architecture for mobile computing. Halpern has a BS in electrical and computer engineering from the University of Texas at Austin. Contact him at matthalp@utexas.edu.']}}, {'name': 'Vijay Janapa Reddi', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ['Vijay Janapa Reddi is an assistant professor in the Department of Electrical and Computer Engineering at the University of Texas at Austin. His research interests include processor architecture and system software design and implementation for addressing performance, power, thermal, energy, and reliability issues for mobile and highperformance computing. Janapa Reddi has a PhD in computer science from Harvard University. Contact him at vj@ece.utexas.edu.']}} %*The Role of the CPU in Energy-Efficient Mobile Web Browsing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7006342 %f/micro/6khsubds3lxt029nqrybaifpv7zmhkcj.pdf %mb2efb800fdcefc53f2b0d2098bf38a5b %cmicro %@[{'name': 'YaoZu Dong', 'affiliation': 'Shanghai Jiao Tong University', 'bio': {'p': ["YaoZu Dong is a PhD candidate in the Department of Computer Science and Engineering at Shanghai Jiao Tong University and a software architect in the Intel Open Source Technology Center. His research interest focuses on architecture and systems, including virtualization, operating systems, and distributed and parallel computing. Dong has a master's degree in electronic engineering from Shanghai Jiao Tong University. Contact him at dongyaozu@gmail.com."]}}, {'name': 'JunJie Mao', 'affiliation': 'Tsinghua University', 'bio': {'p': ['JunJie Mao is a PhD candidate in the Department of Computer Science and Technology at Tsinghua University. His research interests include virtualization architecture, static bug detection in operating systems, and dynamic failure diagnosis in large-scale software systems. Mao has a BS in computer science and technology from Tsinghua University. Contact him at eternal.n08@gmail.com.']}}, {'name': 'HaiBing Guan', 'affiliation': 'Shanghai Jiao Tong University', 'bio': {'p': ['HaiBing Guan is a professor in the Department of Computer Science and Engineering at Shanghai Jiao Tong University. His research interests include computer architecture, compiling, virtualization, and hard-ware-software codesign. Guan has a PhD in computer science from Tongji University. He is a member of IEEE and the ACM. Contact him at hbguan@sjtu.edu.cn.']}}, {'name': 'Jian Li', 'affiliation': 'Shanghai Jiao Tong University', 'bio': {'p': ['Jian Li is an associate professor in the School of Software at Shanghai Jiao Tong University. His research interests include embedded systems and virtualization, real-time scheduling theory, network protocol design, and quality of service. Li has a PhD in computer science from the Institut National Polytechnique de Lorraine. He is a member of IEEE and the ACM. Contact him at li-jian@sjtu.edu.cn.']}}, {'name': 'Yu Chen', 'affiliation': 'Tsinghua University', 'bio': {'p': ['Yu Chen is an associate professor in the Department of Computer Science and Technology at Tsinghua University. His research focuses on operating systems, including virtualization, optimization for multicore architecture, system security, and distributed and parallel computing. Chen has a PhD in computer science from the National University of Defense Technology. Contact him at yuchen@mail.tsinghua.edu.cn.']}} %*A Virtualization Solution for BYOD With Dynamic Platform Context Switching %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7006388 %f/micro/nirgfm7a4cvhxiey0j3btcpwlzsawrqp.pdf %m1dd575af398ff16051c2ac7d2ebb801f %cmicro %@[{'name': 'Chenxiong Qian', 'affiliation': 'Hong Kong Polytechnic University', 'bio': {'p': ['Chenxiong Qian is a research assistant in the Department of Computing at the Hong Kong Polytechnic University. His research focuses on security and privacy with an emphasis on mobile security. Qian has a BEng in software engineering from Nanjing University. Contact him at cscqian@comp.polyu.edu.hk.']}}, {'name': 'Xiapu Luo', 'affiliation': 'Hong Kong Polytechnic University', 'bio': {'p': ['Xiapu Luo is a research assistant professor in the Department of Computing and an associate researcher at the Shenzhen Research Institute at the Hong Kong Polytechnic University. His research focuses on smartphone security, network security and privacy, and Internet measurement. Luo has a PhD in computer science from the Hong Kong Polytechnic University. He is the corresponding author, contact him at csxluo@comp.polyu.edu.hk.']}}, {'name': 'Yu Le', 'affiliation': 'Hong Kong Polytechnic University', 'bio': {'p': ['Yu Le is a research assistant in the Department of Computing at the Hong Kong Polytechnic University. His research focuses on security and privacy with an emphasis on mobile security. Le has a BEng in information security from Nanjing University of Posts and Telecommunications. Contact him at cslyu@comp.polyu.edu.hk.']}}, {'name': 'Guofei Gu', 'affiliation': 'Texas A&,amp,M University', 'bio': {'p': ['Guofei Gu is an associate professor in the Department of Computer Science and Engineering at Texas A&M University. His research interests include network and system security, social Web security, and cloud and software-defined networking (SDN/ OpenFlow) security. Gu has a PhD in computer science from the Georgia Institute of Technology. Contact him at guofei@cse.tamu.edu.']}} %*VulHunter: Toward Discovering Vulnerabilities in Android Applications %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7057600 %f/micro/d4ywjofqrktsbrpndtihq3gomph9w0sc.pdf %m9e4cbc1418c8ed37e9686326019d7f9f %cmicro %@[{'name': 'Richard Mateosian', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/7057031/7057572/7057572-photo-1-small.gif', 'p': ['Richard Mateosian is a freelance technical writer in the San Francisco Bay Area. Contact him at xrmxrm@gmail.com.']}} %*The Future of Work %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7057572 %f/micro/xwsnugrhzoljcnqyv2e1qyfjviz8gtsu.pdf %mfcc99b19644780983afd83a7a00a69c2 %cmicro %@[{'name': 'Richard H. Stern', 'affiliation': 'Kellogg Huber Hansen Todd Evans &,amp, Figel', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/7057031/7057599/7057599-photo-1-small.gif', 'p': ['Richard H. Stern is an attorney at Kellogg Huber Hansen Todd Evans & Figel and a law professor at George Washington University Law School. He has been writing Micro Law columns for IEEE Micro for the past three decades. Contact him at rstern@khhte.com or rstern@law.gwu.edu.']}} %*Federal Circuit Speaks Out on Determining RAND Royalties for Standards %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7057599 %f/micro/jokwclg6mrta9bsvz01kfyjqrxt3ixcp.pdf %m2b708931f7ecfd95ace3e8cc66b935ac %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'Northwestern University', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/7057031/7057581/7057581-photo-1-small.gif', 'p': ['Shane Greenstein is the Kellogg Chair in Information Technology at the Kellogg School of Management, Northwestern University. Contact him at greenstein@kellogg.northwestern.edu.']}} %*Networking standards and russell's revisionism (review of, "Open standards and the digital age: history, ideology, and networks, russel, a.; 2014)[book review] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7057581 %f/micro/j3jmglb8srav5e0zqkgsfz7frtlh1vi6.pdf %me142173ad76ebc34ccb4c01b786fccb7 %cmicro %@[{'name': 'Lieven Eeckhout', 'affiliation': 'Ghent University'} %*Hot Chips in an Increasingly Diverse Microprocessor Landscape %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7091771 %f/micro/jiht8wvxr42ceky95c0bykdqe36jrzpz.pdf %mcb3c6cbf059705bc34cda1b002cf5866 %cmicro %@[{'name': 'Samuel Naffziger', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ["Samuel Naffziger is a corporate fellow at Advanced Micro Devices, where he is responsible for low-power technology development for AMD's products. His interests include processor design and power management. Naffziger has an MS in electrical engineering from Stanford University. He is an IEEE Fellow."]}}, {'name': 'Guri Sohi', 'affiliation': 'University of Wisconsin-Madison', 'bio': {'p': ['Guri Sohi is the John P. Morgridge Professor and the E. David Cronon Professor of Computer Sciences at the University of Wisconsin—Madison. His interests include instruction-level processors, decentralized microarchitectures, speculative multithreading, and multicore microprocessors. Sohi has a PhD in electrical and computer engineering from the University of Illinois. He is a fellow of IEEE and the ACM.']}} %*Hot Chips 26 %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7091777 %f/micro/rlahffzjce6mtpain9ou3oqhr50bggt2.pdf %m3927502f51bbc208d1c0245fbabcc591 %cmicro %@[{'name': 'Toshio Yoshida', 'affiliation': 'Fujitsu', 'bio': {'p': ['Toshio Yoshida is a director of the LSI Development Division in the Next Generation Technical Computing Unit at Fujitsu. His research interests include microprocessor architecture. Yoshida has an MS in physics from the University of Tokyo.']}}, {'name': 'Mikio Hondou', 'affiliation': 'Fujitsu', 'bio': {'p': ['Mikio Hondou is a manager in the Next Generation Technical Computing Unit at Fujitsu. His research focuses on performance and architecture for microprocessors. Hondou has an MS in physics from Keio University.']}}, {'name': 'Takekazu Tabata', 'affiliation': 'Fujitsu', 'bio': {'p': ['Takekazu Tabata is an engineer in the Processor Development Division in the Enterprise Server Business Unit at Fujitsu. His research interests include microprocessor architecture. Tabata has an ME in information engineering from the Hiroshima City University.']}}, {'name': 'Ryuji Kan', 'affiliation': 'Fujitsu', 'bio': {'p': ["Ryuji Kan is a manager in the Enterprise Server Business Unit at Fujitsu, where he's working on both the architecture and circuit design of processors. His research focuses on integrating hardware and software. Kan has an ME in communications and computer engineering from Kyoto University."]}}, {'name': 'Naohiro Kiyota', 'affiliation': 'Fujitsu', 'bio': {'p': ['Naohiro Kiyota is a manager in the Enterprise Server Business Unit at Fujitsu. His research interests focus on cache architecture for processors. Kiyota has a BE in electronic engineering from Kyoto University.']}}, {'name': 'Hiroyuki Kojima', 'affiliation': 'Fujitsu', 'bio': {'p': ['Hiroyuki Kojima is a manager in the Enterprise Server Business Unit at Fujitsu. His research focuses on cache architecture for processors. Kojima has an ME in control engineering from the Tokyo Institute of Technology.']}}, {'name': 'Koji Hosoe', 'affiliation': 'Fujitsu', 'bio': {'p': ['Koji Hosoe is a manager of the System Development Division in the Next Generation Technical Computing Unit at Fujitsu. His research interests include memory and interconnect architecture for HPC systems. Hosoe has an ME in electrical engineering from Nagoya University.']}}, {'name': 'Hiroshi Okano', 'affiliation': 'Fujitsu Laboratories', 'bio': {'p': ['Hiroshi Okano is a research manager in the Server Technologies Laboratory at Fujitsu Laboratories. His research interests focus on high-performance techniques for microprocessors under power constraints. Okano has an ME in electrical engineering from Hiroshima University.']}} %*Sparc64 XIfx: Fujitsu's Next-Generation Processor for High-Performance Computing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7021857 %f/micro/clepov7s6gkx2awmujirzd0crdeytawj.pdf %m96f578ee32c668bc026942e58758d213 %cmicro %@[{'name': 'Irma Esmer Papazian', 'affiliation': 'Intel', 'bio': {'p': ['Irma Esmer Papazian is a principal engineer at Intel. She was the performance lead for the Ivy Bridge server. Her research interests include server architecture development, performance analysis and modeling techniques, pre-and post-silicon performance validation, and workload projections. Esmer Papazian has an MS in computer engineering from University of Wisconsin-Madison. Contact her at irma.esmer@intel.com.']}}, {'name': 'Sailesh Kottapalli', 'affiliation': 'Intel', 'bio': {'p': ['Sailesh Kottapalli is an Intel Fellow. He was the lead architect for Ivy Bridge Server. His research interests include uncore architecture, multisocket scalability, and server features. Kottapalli has an MS in computer engineering from Virginia Polytechnic Institute and State University. Contact him at sailesh.kottapalli@intel.com.']}}, {'name': 'Jeff Baxter', 'affiliation': 'Intel', 'bio': {'p': ['Jeff Baxter is a senior principal engineer at Intel. He leads the performance evaluation team. His research interests include architecture performance techniques and evaluation methodologies. Baxter has a PhD in electrical engineering from the University of Illinois. Contact him at jeff.baxter@intel.com.']}}, {'name': 'Jeff Chamberlain', 'affiliation': 'Intel', 'bio': {'p': ['Jeff Chamberlain is a cache and coherent fabric architect, focusing on high-end server products at Intel. He was lead architect for the Ivy Bridge server on-chip interconnect and LLC. Chamberlain has an MA in mathematics from the University of California, Los Angeles. Contact him at jeffrey.d.chamberlain@intel.com.']}}, {'name': 'Geetha Vedaraman', 'affiliation': 'Intel', 'bio': {'p': ['Geetha Vedaraman is a server coherence agent architect at Intel, where she was the lead home agent architect on the Ivy Bridge server, and also works on coherence protocol specifications. Vedaraman has an MS in computer science from the University of Wisconsin—Madison. Contact her at geetha.vedaraman@intel.com.']}}, {'name': 'Brian Morris', 'affiliation': 'Intel', 'bio': {'p': ['Brian Morris is a memory controller architect at Intel. His work focuses on improving the performance and reliability of the memory subsystem. Morris has an MS in electrical engineering from Purdue University. Contact him at brian.s.morris@intel.com.']}} %*Ivy Bridge Server: A Converged Design %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7091791 %f/micro/tg3qfwkbfh4zdulmp0yaxzcurq7onbe1.pdf %m9c955bfa92a863f88a8f8907213def5b %cmicro %@[{'name': 'Bradley Burres', 'affiliation': 'Intel', 'bio': {'p': ['Bradley Burres is a senior principal engineer working on datacenter solutions at Intel, where he drove the Atom-server concept and was the Avoton lead architect. Burres has an MS in electrical engineering from the Worcester Polytechnic Institute.']}}, {'name': 'Johan van de Groenendaal', 'affiliation': 'Intel', 'bio': {'p': ['Johan van de Groenendaal is a principal engineer working on innovative solutions for the datacenter at Intel. van de Groenendaal has a PhD in electronics from the University of Cape Town.']}}, {'name': 'Praveen Mosur', 'affiliation': 'Intel', 'bio': {'p': ['Praveen Mosur is a principal engineer working on network security and compression hardware accelerators at Intel. Mosur has an MS in electrical and computer engineering from Auburn University.']}}, {'name': 'Jonathan Robinson', 'affiliation': 'Intel', 'bio': {'p': ["Jonathan Robinson is an integration architect at Intel, where he's working to define global architectures, flows, and methodologies for SoC products. Robinson has an MS in electrical engineering from Mississippi State University."]}}, {'name': 'Ian Steiner', 'affiliation': 'Intel', 'bio': {'p': ['Ian Steiner is a server power management architect at Intel, specializing in power efficiency and power/performance optimizations. Steiner has an MS in electrical engineering from the University of Illinois.']}}, {'name': 'Yi-Feng Liu', 'affiliation': 'Intel', 'bio': {'p': ["Yi-Feng Liu is a silicon architect at Intel, where he's working on power management architecture. Liu has an MS in electrical and computer engineering from the University of Wisconsin—Madison."]}}, {'name': 'Sin S. Tan', 'affiliation': 'Intel', 'bio': {'p': ['Belliappa Kuttanna is an Intel Fellow in the Platform Engineering Group at Intel. He is the chief architect for the Intel Atom and Quark CPUs. Kuttanna has an MS in electrical engineering from Texas A&M University.']}}, {'name': 'Erik McShane', 'affiliation': 'Intel', 'bio': {'p': ['Sridhar Lakshmanamurthy is a senior principal engineer at Intel. He leads the IOSF and on-die coherent fabrics architecture for Atom SoCs. Lakshmanamurthy has an MS in computer engineering from Rice University.']}}, {'name': 'Belliappa Kuttanna', 'affiliation': 'Intel', 'bio': {'p': ['Sin S. Tan is an architect leading reset and the system management bus across market segments at Intel. Tan has an MS in electrical engineering from the University of Toledo.']}}, {'name': 'Sridhar Lakshmanamurthy', 'affiliation': 'Intel', 'bio': {'p': ['Erik McShane is a silicon architect leading the next-generation microserver PCH at Intel. McShane has a PhD in electrical engineering from the University of Illinois.']}} %*Intel Atom C2000 Processor Family: Power-Efficient Datacenter Processing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7045418 %f/micro/azmuawxwlhxdcf6qr8gvkit9yhbeirlp.pdf %m55b7263e16a9822ed7dbe857dd0de556 %cmicro %@[{'name': 'Kathirgamar Aingaran', 'affiliation': 'Oracle', 'bio': {'p': ['Kathirgamar Aingaran is a director of hardware development at Oracle. His interests are in joint hardware-software development. Aingaran has an MS in electrical engineering from Stanford University. He is a senior member of IEEE. Contact him at aings.aingaran@oracle.com.']}}, {'name': 'Sumti Jairath', 'affiliation': 'Oracle', 'bio': {'p': ['Sumti Jairath is a senior hardware architect at Oracle. His research interests include hardware-software interaction, software-spe-cific hardware design, and coherence scaling. Jairath has a BTech in electronics and communication engineering from the National Institute of Technology, Kurukshetra, India. Contact him at sumti.jairath@oracle.com.']}}, {'name': 'Georgios Konstadinidis', 'affiliation': 'Oracle', 'bio': {'p': ['Georgios Konstadinidis is a senior hardware architect at Oracle, where he is involved in process technology, physical design meth-odology, and power management. Konstadi-nidis has a PhD in microelectronics from the Technical University of Berlin. Contact him at georgios.konstadinidis@oracle.com.']}}, {'name': 'Serena Leung', 'affiliation': 'Oracle', 'bio': {'p': ['Serena Leung is a senior principal hardware engineer at Oracle. Her interests are multiprocessor cache and coherency design. Leung has an MS in electrical engineering and computer science from the University of California, Berkeley. Contact her at serena.leung@oracle.com.']}}, {'name': 'Paul Loewenstein', 'affiliation': 'Oracle', 'bio': {'p': ['Paul Loewenstein is a senior principal hardware engineer at Oracle. His research interests include multiprocessor cache coherence proto-cols, formal memory models, deadlock and livelock avoidance, and error detection and correction. Loewenstein has a PhD in computer science from the University of Cam-bridge. Contact him at paul.loewenstein @oracle.com.']}}, {'name': 'Curtis McAllister', 'affiliation': 'Oracle', 'bio': {'p': ['Curtis McAllister is a senior director of hardware engineering at Oracle. His research interests include multiprocessor coherence, parallel processing, and timing optimization. McAllister has a BS in computer engineering from Iowa State University. Contact him at curtis.mcallister@oracle.com.']}}, {'name': 'Stephen Phillips', 'affiliation': 'Oracle', 'bio': {'p': ['Stephen Phillips is a senior director of the Sparc Architecture Group at Oracle. His research interests include high-performance microprocessors, cache coherence, and hardware acceleration. Phillips has an MS in electrical engineering from Rutgers University. Contact him at stephen. phillips@oracle.com.']}}, {'name': 'Zoran Radovic', 'affiliation': 'Oracle', 'bio': {'p': ['Zoran Radovic is a senior principal engineer in the microelectronics division of Oracle. His research interests include architectural support for programming languages and operating systems, distributed computing, and software reliability. Radovic has a PhD in computer science from Uppsala University. Contact him at zoran.radovic@oracle.com.']}}, {'name': 'Ram Sivaramakrishnan', 'affiliation': 'Oracle', 'bio': {'p': ['Ram Sivaramakrishnan is a director of hardware at Oracle. His research interests include low-power cache design for high-throughput multithreaded architectures and low-overhead multiprocessor coherency pro-tocols. Sivaramakrishnan has an MS in electrical engineering from the University of Nevada, Las Vegas. Contact him at ram.sivaramakrishnan@oracle.com.']}}, {'name': 'David Smentek', 'affiliation': 'Oracle', 'bio': {'p': ['David Smentek is a senior hardware architect at Oracle. His research interests include computer architecture, computer arith-metic, performance modeling, and on-chip networks for multicore architectures. Smen-tek has an MS in electrical engineering from Stanford University. Contact him at david.smentek@oracle.com.']}}, {'name': 'Thomas Wicki', 'affiliation': 'Oracle', 'bio': {'p': ["Thomas Wicki is a senior principal hardware engineer in Oracle's Microelectronics Architecture group. His research interests include scalable system architectures and interconnect designs. Wicki has a PhD in electrical engineering from the Swiss Federal Institute of Technology, Zurich. Contact him at thomas.wicki@oracle.com."]}} %*M7: Oracle's Next-Generation Sparc Processor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7091786 %f/micro/fep9ntdnu4ioxzy2h5jhl6ckug1ivgow.pdf %m6ac096d2adf70e34f7cba02bce7732d5 %cmicro %@[{'name': 'Darrell Boggs', 'affiliation': 'Nvidia', 'bio': {'p': ['Darrell Boggs is a senior distinguished engineer and senior director of CPU architecture at Nvidia. His interests include computer architectures and low-power designs. Boggs has an MS in electrical engineering from Brigham Young University. Contact him at dboggs@nvidia.com.']}}, {'name': 'Gary Brown', 'affiliation': 'Nvidia', 'bio': {'p': ['Gary Brown is the vice president of CPU engineering at Nvidia. His interests include efficient micro architectures and CPU-GPU synergy. Brown has an MS in electrical engineering from Brigham Young University. Contact him at garyb@nvidia.com.']}}, {'name': 'Nathan Tuck', 'affiliation': 'Nvidia', 'bio': {'p': ['Nathan Tuck is a principal engineer and software manager at Nvidia. His interests include software optimization techniques and CPU architectures. Tuck has a BS in computer science from Harvey Mudd Col-lege. Contact him at ntuck@nvidia.com.']}}, {'name': 'K S Venkatraman', 'affiliation': 'Nvidia', 'bio': {'p': ['K S Venkatraman is a principal engineer and senior architecture manager at Nvidia. His interests include architecture, hardware design, verification, performance, and competitive analysis. Venkatraman has an MS in electrical and computer engineering from Villanova University. Contact him at ksv@nvidia.com.']}} %*Denver: Nvidia's First 64-bit ARM Processor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7045419 %f/micro/wceuwaurr143mvf6xzobmdvehgloqj9s.pdf %m061c123d102f51ee18ec9a3022bc2901 %cmicro %@[{'name': 'Brendan Barry', 'bio': {'p': ['Brendan Barry is vice president of engineering at Movidius, where he leads development of hardware and design tools and contributes to the Myriad and SHAWE microarchitecture and physical design. His research interests include hardware computer-vision accel-eration, processor, and SoC architecture. Barry has a BEng in electronic engineering from Dublin City University. Contact him at brendan.barry@movidius.com.']}}, {'name': 'Cormac Brick', 'bio': {'p': ['Cormac Brick is vice president of software engineering at Movidius, where he works on integrating Movidius Myriad technology to enable new computer vision and imaging products. His research interests include computer vision, sensor fusion, and artificial intelligence. Brick has a BEng in electronic engineering from University College Cork. Contact him at cormac.brick@movidius.com.']}}, {'name': 'Fergal Connor', 'bio': {'p': ['Fergal Connor is a staff engineer at Movi-dius, where he is working on the next generation of the SHAVE processor. His research interests include power-efficient processor architectures and multicore processor design. Connor has an MEng in electronic engineering from Dublin City University. Contact him at fergal.connor@movidius.com.']}}, {'name': 'David Donohoe', 'bio': {'p': ['David Donohoe is an embedded software architect at Movidius, where he leads the research, development, and software specification activities around high-throughput pixel-processing pipelines, targeting embedded and mobile applications. Donohoe has a BEng in electronic engineering from Dublin City University. Contact him at david.donohoe @movidius.com.']}}, {'name': 'David Moloney', 'bio': {'p': ['David Moloney is the chief technology officer of Movidius. His research interests include processor architecture, computer vision algorithms and hardware acceleration and systems, hardware and multiprocessor design for DSP communications, highperformance computing, and multimedia applications. Moloney has a PhD in mechanical engineering on high-performance computer architecture from Trinity College Dublin. Contact him at david.moloney@ movidius.com.']}}, {'name': 'Richard Richmond', 'bio': {'p': ['Richard Richmond is a staff engineer at Movidius. His research interests include low-power hardware acceleration of computationally intensive image signal processing and computer vision algorithms. Richmond has an MEng in electronic engineering from Edinburgh University. Contact him at richard.richmond@movidius.com.']}}, {'name': "Martin O'Riordan", 'bio': {'p': ["Martin O'Riordan is the chief compiler architect at Movidius, where he leads the SHAVE processor compiler development based on LLVM infrastructure and also worked on the SHAVE instruction set architecture and Myriad microarchi tecture. Q'Riordan has a BSc in computer science from Trinity College Dublin. Contact him at martin.oriordan@movidius.com."]}}, {'name': 'Vasile Toma', 'bio': {'p': ['Vasile Toma is a design engineer at Movi-dius. His research interests include chip-card security, SoC and processor architecture, DSp, and computer vision. Toma has a BEng electronic engineering from the Poli-tehnica University of Timisoara, Romania. Contact him at vasile.toma@movidius.com.']}} %*Always-on Vision Processing Unit for Mobile Applications %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7024073 %f/micro/2uvcn0bqkrjfact7mqozehiygpumyo6s.pdf %mb8fecb915216ba6481f1ed1a997e564b %cmicro %@[{'name': 'Javed Barkatullah', 'affiliation': 'CoinTerra', 'bio': {'p': ['Javed Barkatullah is the founder and principal of Barkatech Consulting. He was the contract senior director of ASIC engineering for CoinTerra, where he completed the design and implementation of two generations of bitcoin mining processors. His research interests include design and implementation of energy-efficient special-pur-pose processors. Barkatullah has a PhD in electrical and computer engineering from the University of Iowa. Contact him at javed@barkatech.com.']}}, {'name': 'Timo Hanke', 'affiliation': 'CoinTerra', 'bio': {'p': ['Timo Hanke is a mathematician, cryptogra-pher, and cryptocurrency expert. He is the CTO at CoinTerra. His research interests include developing novel cryptography-based payment protocols and identity layers for Bitcoin. Hanke has a PhD in mathematics from the University of Potsdam, Ger-many. Contact him at timo@cointerra.com.']}} %*Goldstrike 1: CoinTerra's First-Generation Cryptocurrency Mining Processor for Bitcoin %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7045415 %f/micro/yf2ueto4zfdbz6jrcxnmcqqgdpl5ugis.pdf %m0873df324798bd6359c8f97d435f5e62 %cmicro %@[{'name': 'Richard H. Stern', 'affiliation': 'Kellogg Huber Hansen Todd Evans &,amp, Figel', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/7091755/7091764/7091764-photo-1-small.gif', 'p': ['Richard H. Stern is an attorney at Kellogg Huber Hansen Todd Evans & Figel and a law professor at George Washington University Law School. He has been writing Micro Law columns for IEEE Micro for the past three decades. Contact him at rstern@khhte.com or rstern@law.gwu.edu.']}} %*Justice Department Agrees IEEE's New RAND Policy Isn't Price Fixing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7091764 %f/micro/yidtkkj4azpjvwdag5xhlfqxfobec7r2.pdf %m67c94de6d65e148a36f47ea127fbf6b3 %cmicro %@[{'name': 'Onur Mutlu', 'affiliation': 'Carnegie Mellon University'}, {'name': 'Rich Belgard'} %*Introducing the MICRO Test of Time Awards: Concept, Process, 2014 Winners, and the Future %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7091778 %f/micro/md5zbcdyfxpjvqjpfu2haktervzbgo8u.pdf %mb2f35a95c023afbc88faa497f2bcb3cf %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'Northwestern University', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/7091755/7091756/7091756-photo-1-small.gif', 'p': ['Shane Greenstein is the Kellogg Chair in Information Technology at the Kellogg School of Management, Northwestern University.']}} %*Behind the Buzz of Behavioral Data %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7091756 %f/micro/oeuaskbkfr3ge5ywlzmgn1ixfltdrjcb.pdf %m256c8b20c930ac17122e0aac1c7a9c1a %cmicro %@[{'name': 'Lieven Eeckhout', 'affiliation': 'Ghent University', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/7129787/7130465/7130465-photo-1-small.gif', 'p': ['Lieven Eeckhout is a professor in the Department of Electronics and Information Systems at Ghent University. Contact him at lieven.eeckhout@ugent.be.']}} %*The State of the Computer Architecture Field and Its Top Picks %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7130465 %f/micro/ajdwpbugmtoiyeuo9keswl3hn75ncqvs.pdf %m598b940a4189edfa73575fd924ebfef0 %cmicro %@[{'name': 'Luis Ceze', 'affiliation': 'University of Washington', 'bio': {'p': ['Luis Ceze is the Torode Family Associate Professor in the Department of Computer Science and Engineering at the U niversi ty of Washington. Contact him at luisceze@cs. washington.edu.']}}, {'name': 'Karin Strauss', 'affiliation': 'Microsoft Research', 'bio': {'p': ['Karin Strauss is a researcher at Microsoft Research and affiliate faculty in the Department of Computer Science and Engineering at the University of Washington. Contact her at kstrauss@microsoft.com.']}} %*The 2014 Top Picks in Computer Architecture %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7130470 %f/micro/wtppx4lskoid0r7ynfshdegt8waug3zv.pdf %m6b68583a884f8aeb556624f08be08f01 %cmicro %@[{'name': 'Andrew Putnam', 'affiliation': 'Microsoft Research NExT', 'bio': {'p': ['Andrew Putnam is a principal research hardware development engineer in Microsoft Research NExT. His research interests include reconfigurable computing, future datacenter design, and computer architecture. Putnam has a PhD in computer science and engineering from the University of Washington. Contact him at anputnam@microsoft.com.']}}, {'name': 'Adrian M. Caulfield', 'affiliation': 'Microsoft Research NExT', 'bio': {'p': ['Adrian M. Caulfield is a senior research hardware development engineer in Microsoft Research NExT. His research interests include computer architecture and reconfigurable computing. Caulfield has a PhD in computer engineering from the University of California, San Diego. Contact him at acaulfie@microsoft.com.']}}, {'name': 'Eric S. Chung', 'affiliation': 'Microsoft Research NExT', 'bio': {'p': ['Eric S. Chung is a researcher in Microsoft Research NExT. His research focuses on the intersection of computer architecture and reconfigurable computing with FPGAs. Chung has a PhD in electrical and computer engineering from Carnegie Mellon University. Contact him at erchung@microsoft.com.']}}, {'name': 'Derek Chiou', 'affiliation': 'Bing', 'bio': {'p': ['Derek Chiou is a principal architect at Bing and an associate professor (on leave) at the University of Texas at Austin. His research interests include FPGA-based acceleration, high-level descriptions of hardware, and highperformance computer simulation techniques. Chiou has a PhD in electrical engineering and computer science from the Massachusetts Institute of Technology. Contact him at dechiou@microsoft.com.']}}, {'name': 'Kypros Constantinides', 'affiliation': 'Amazon Web Services', 'bio': {'p': ['Kypros Constantinides is a senior hardware development engineer at Amazon Web Services. His research interests include scalable server platform architectures for datacenters and heterogeneous compute architectures. Constantinides has a PhD in computer science and engineering from the University of Michigan. He performed the research for this article while at Microsoft Research. Contact him at kypros@amazon.com.']}}, {'name': 'John Demme', 'affiliation': 'Columbia University', 'bio': {'p': ['John Demme is an associate research scientist at Columbia University. His research interests include programming paradigms for spatial computing and data-intensive computing. Demme has a PhD in computer science from Columbia University. Contact him at jdd@cs.columbia.edu.']}}, {'name': 'Hadi Esmaeilzadeh', 'affiliation': 'the Georgia Institute of Technology', 'bio': {'p': ['Hadi Esmaeilzadeh is the Allchin Family Early Career Professor of Computer Science at the Georgia Institute of Technology. He founded and directs the Alternative Computing Technologies Lab. His research interests include developing new technologies and cross-stack solutions to build next-generation computer systems for emerging applications. Esmaeilzadeh has a PhD in computer science from the University of Washington. Contact him at hadi@cc.gatech.edu.']}}, {'name': 'Jeremy Fowers', 'affiliation': 'Microsoft Research', 'bio': {'p': ['Jeremy Fowers is a research engineer in the Catapult team at Microsoft Research. His research focuses on creating FPGA accelerators and frameworks to better use custom FPGA logic and hard intellectual-property blocks. Fowers has a PhD in electrical engineering from the University of Florida. Contact him at jfowers@microsoft.com.']}}, {'name': 'Gopi Prashanth Gopal', 'affiliation': 'Amazon', 'bio': {'p': ['Gopi Prashanth Gopal is a senior engineering manager at Amazon. His research interests include computer vision, virtual reality, and machine learning. Prashanth Gopal has an MS in computational engineering from Mississippi State University. He performed the research for this article while at Bing. Contact him at gopiprashanth@gmail.com.']}}, {'name': 'Jan Gray', 'bio': {'p': ['Jan Gray is a consultant, computer architect, and software architect. His research focuses on the design of FPGA-optimized soft processor arrays and computation accelerators. Gray has a BMath in computer science and electrical engineering from the University of Waterloo, Canada. Contact him at jsgray@acm.org.']}}, {'name': 'Michael Haselman', 'affiliation': 'Microsoft Applied Sciences Group (Bing)', 'bio': {'p': ['Michael Haselman is a software engineer at Microsoft Applied Sciences Group (Bing). His research interests include FPGAs and computation accelerators. Haselman has a PhD in electrical engineering from the University of Washington. Contact him at mikehase@microsoft.com.']}}, {'name': 'Scott Hauck', 'affiliation': 'University of Washington', 'bio': {'p': ['Scott Hauck is a professor in the Department of Electrical Engineering at the University of Washington and a consultant with Microsoft on the Catapult project. His research focuses on FPGAs and reconfigurable computing. Hauck has a PhD in computer science and engineering from the University of Washington. Contact him at hauck@uw.edu.']}}, {'name': 'Stephen Heil', 'affiliation': 'Microsoft Research', 'bio': {'p': ['Stephen Heil is a principal program manager at Microsoft Research. His research focuses on the development of custom programmable hardware accelerators for use in Microsoft datacenters. Heil has a BS in electrical engineering technology and computer science from the College of New Jersey (formerly Trenton State College). Contact him at stephen.heil@microsoft.com.']}}, {'name': 'Amir Hormati', 'affiliation': 'Google', 'bio': {'p': ['Amir Hormati is a senior software engineer at Google. His research focuses on large-scale data analysis and storage platforms. Hormati has a PhD in computer science and engineering from the University of Michigan. He performed the research for this article while at Microsoft Research. Contact him at hormati@gmail.com.']}}, {'name': 'Joo-Young Kim', 'affiliation': 'Microsoft Research', 'bio': {'p': ['Joo-Young Kim is a senior research hardware development engineer at Microsoft Research. His research focuses on high-performance accelerator design for datacenter workloads. Kim has a PhD in electrical engineering from the Korea Advanced Institute of Science and Technology. Contact him at jooyoung@microsoft.com.']}}, {'name': 'Sitaram Lanka', 'affiliation': 'Bing', 'bio': {'p': ['Sitaram Lanka is a group engineering manager for Search Platform at Bing. His research interests include distributed systems, large-scale systems, and fault tolerance. Lanka has a PhD in computer science from the University of Pennsylvania. Contact him at slanka@microsoft.com.']}}, {'name': 'James Larus', 'affiliation': 'É,cole Polytechnique Fé,dé,rale de Lausanne', 'bio': {'p': ['James Larus is a professor and the dean of the School of Computer and Communication Sciences at Ecole Polytechnique Fédérale de Lausanne. His research interests include programming languages, compilers, and computer architecture. Larus has a PhD in computer science from the University of California, Berkeley. He is an ACM Fellow. Contact him at james.larus@epf1.ch.']}}, {'name': 'Eric Peterson', 'affiliation': 'Microsoft Research', 'bio': {'p': ['Eric Peterson is a principal mechanical architect at Microsoft Research. His research interests include new datacenter energy systems and system integration. Peterson has a BS in mechanical engineering from Texas A&M University. Contact him at eric.peterson@microsoft.com.']}}, {'name': 'Simon Pope', 'affiliation': 'Microsoft', 'bio': {'p': ["Simon Pope is a program manager for Microsoft. His research focuses on the nexus of computing and psychology. Pope has a master's in cognitive science from the University of New South Wales. Contact him at simon.pope@microsoft.com."]}}, {'name': 'Aaron Smith', 'affiliation': 'Microsoft Research', 'bio': {'p': ['Aaron Smith is a principal research software development engineer at Microsoft Research. His research focuses on the development of advanced optimizing compilers and microprocessors. Smith has a PhD in computer science from the University of Texas at Austin. Contact him at aaron.smith@microsoft.com.']}}, {'name': 'Jason Thong', 'affiliation': 'Microsoft Research', 'bio': {'p': ['Jason Thong is a hardware design engineer with Microsoft Research. His research interests include hardware acceleration, heterogeneous computing, and computer-aided design. Thong has a PhD in computer engineering from McMaster University. Contact him at a-jathon@microsoft.com.']}}, {'name': 'Phillip Yi Xiao', 'affiliation': 'Bing', 'bio': {'p': ["Phillip Yi Xiao is a senior software engineer at Bing. His research focuses on distributed computing architecture and machine learning. Xiao has a master's in computer science and engineering from JiaoTong University. Contact him at phxiao@microsoft.com."]}}, {'name': 'Doug Burger', 'affiliation': 'Microsoft Research NExT', 'bio': {'p': ['Doug Burger directed the Hardware, Devices, and Experiences Group at Microsoft Research NExT. His research interests include cloud architecture, efficient silicon architectures, and machine-learned personal services. Burger has a PhD in computer science from the University of Wisconsin-Madison. He is an IEEE and ACM Fellow. Contact him at dburger@microsoft.com.']}} %*A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7106407 %f/micro/pgiyrqx8nb3kuhl2lopuwmazaj5hvxjo.pdf %m6065822a3f869d4934080d330a40c377 %cmicro %@[{'name': 'Tianshi Chen', 'affiliation': 'State Key Laboratory of Computer Architecture', 'bio': {'p': ['Tianshi Chen is an associate professor at the State Key Laboratory of Computer Architecture at the Chinese Academy of Sci-ences. His research interests include computer architecture, parallel processing, and computational intelligence. Chen has a PhD in computer science from University of Science and Technology of China. Contact him at chentianshi@ict.ac.cn.']}}, {'name': 'Zidong Du', 'affiliation': 'State Key Laboratory of Computer Architecture', 'bio': {'p': ['Zidong Du is a PhD student at the State Key Laboratory of Computer Architecture at the Chinese Academy of Sciences. His research interests include parallel processing, computer architecture, and machine learning. Du has a BSc in electronic engineering from Tsinghua University. Contact him at duzidong@ict.ac.cn.']}}, {'name': 'Ninghui Sun', 'affiliation': 'State Key Laboratory of Computer Architecture', 'bio': {'p': ['Ninghui Sun is a professor at the State Key Laboratory of Computer Architecture at the Chinese Academy of Sciences. His research interests include supercomputing, computer architecture, and programming language. Sun has a PhD in computer science from the Institute of Computing Technology at the Chinese Academy of Sciences. Contact him at snh@ict.ac.cn.']}}, {'name': 'Jia Wang', 'affiliation': 'State Key Laboratory of Computer Architecture', 'bio': {'p': ['Jia Wang is an engineer at the China Merchants Bank. His research interests include parallel processing, computer architecture, and machine learning. Wang has an MSc in computer science from the State Key Laboratory of Computer Architecture at the Chinese Academy of Sciences, where he performed the work for this article. Contact him at brownwj@l63.com.']}}, {'name': 'Chengyong Wu', 'affiliation': 'State Key Laboratory of Computer Architecture', 'bio': {'p': ['Chengyong Wu is a professor at the State Key Laboratory of Computer Architecture at the Chinese Academy of Sciences. His research interests include programming language and compiler and computer architecture. Wu has a PhD in computer science from the Institute of Computing Technology at the Chinese Academy of Sciences. Contact him at cwu@ict.ac.cn.']}}, {'name': 'Yunji Chen', 'affiliation': 'State Key Laboratory of Computer Architecture', 'bio': {'p': ['Yunji Chen is a professor at the State Key Laboratory of Computer Architecture at the Chinese Academy of Sciences. His research interests include parallel processing, computer architecture, and machine learning. Chen has a PhD in computer science from the Institute of Computing Technology at the Chinese Academy of Sciences. Contact him at cyj@ict.ac.cn.']}}, {'name': 'Olivier Temam', 'affiliation': 'INRIA'} %*A High-Throughput Neural Network Accelerator %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7106400 %f/micro/imsqael2o7fvrw1hfz0gtxzvxm693kru.pdf %m526b28e6394a91494a6e6693dab9b2ea %cmicro %@[{'name': 'Lisa Wu', 'affiliation': 'Intel Labs', 'bio': {'p': ['Lisa Wu is a research scientist at Intel Labs. Her research interests include computer architecture, accelerators, energy-efficient computing on high-performance computing, and emerging applications related to big data, machine learning, and computational biology. Wu has a PhD in computer science from Columbia University. She is a member of the ACM SIGARCH. Contact her at lisa.wu @intel.com.']}}, {'name': 'Andrea Lottarini', 'affiliation': 'Columbia University', 'bio': {'p': ["Andrea Lottarini is a PhD student in the Department of Computer Science at Columbia University. His research interests include computer architecture and heterogeneous computing. Lottarini has an MS in computer science from Università di Pisa and Scuola Superiore Sant'Anna. Contact him at flottarini@cs.columbia.edu."]}}, {'name': 'Timothy K. Paine', 'affiliation': 'Columbia University', 'bio': {'p': ["Timothy K. Paine is a master's student in the Department of Computer Science at Columbia University. His research interests include hardware accelerators for machine learning and data processing. Paine has a BS in computer science from Columbia University. Contact him at tkp2108@columbia.edu."]}}, {'name': 'Martha A. Kim', 'affiliation': 'Columbia University', 'bio': {'p': ['Martha A. Kim is an assistant professor in the Computer Science Department at Columbia University. Her research interests include computer architecture, parallel hardware and software systems, and energy-efficient computation on big data. Kim has a PhD in computer science from the University of Washington. She is a member of IEEE and the ACM. Contact her at martha@cs.columbia.edu.']}}, {'name': 'Kenneth A. Ross', 'affiliation': 'Columbia University', 'bio': {'p': ['Kenneth A. Ross is a professor in the Computer Science Department at Columbia University. His research focuses on database management systems, particularly their performance on modern multicore machines, GPUs, and other accelerator platforms. Ross has a PhD in computer science from Stanford University. He is a member of the ACM. Contact him at karg@cs.columbia.edu.']}} %*The Q100 Database Processing Unit %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7106397 %f/micro/t4jqfy2gcpw91l3hukrvyxtinbekoewz.pdf %mee3b239b4663e470fda729432a449bc6 %cmicro %@[{'name': 'Advait Madhavan', 'affiliation': 'University of California, Santa Barbara', 'bio': {'p': ['Advait Madhavan is a PhD candidate in the Electrical and Computer Engineering Department at the University of California, Santa Barbara. His research focuses on novel methods for information processing, including conceptualization of high-level architectures, analog and digital circuit implementation, and modeling the physics of architectural topologies. Madhavan has an MS in electrical engineering from the University of California, Santa Barbara. He is a member of IEEE. Contact him at advait @ece.ucsb.edu.']}}, {'name': 'Timothy Sherwood', 'affiliation': 'University of California, Santa Barbara', 'bio': {'p': ['Timothy Sherwood is a professor in the Department of Computer Science at the University of California, Santa Barbara. His research focuses on the development of processors exploiting novel technologies, designed for provable properties, and/or implementing hardware-aware algorithms. Sherwood has a PhD in computer science from the University of California, San Diego. He is a senior member of IEEE and an ACM Distinguished Scientist. Contact him at sherwood@cs.ucsb.edu.']}}, {'name': 'Dmitri Strukov', 'affiliation': 'University of California, Santa Barbara', 'bio': {'p': ['Dmitri Strukov is an assistant professor in the Electrical and Computer Engineering Department at the University of California, Santa Barbara. His research focuses on physical implementation of computation, including device physics, circuit design, and high-level architecture, with an emphasis on emerging device technologies. Strukov has a PhD in electrical engineering from Stony Brook University. He is a member of IEEE, the ACM, and the MRS. Contact him at strukov@ece.ucsb.edu.']}} %*Race Logic: Abusing Hardware Race Conditions to Perform Useful Computation %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7106377 %f/micro/n1duypivehwolrjogrqezkz0dxaxci2b.pdf %m7b27d95fb1de66e9c56fdfc4bd60137b %cmicro %@[{'name': 'Yakun Sophia Shao', 'affiliation': 'Harvard Univ., Cambridge, MA, USA', 'bio': {'p': ['Yakun Sophia Shao is a PhD candidate in computer science at Harvard University. Her research focuses on computer architecture, particularly on modeling and design for specialized architectures. Shao has an MS in computer science from Harvard University. Contact her at shao@eecs.harvard.edu.']}}, {'name': 'Brandon Reagen', 'affiliation': 'Harvard Univ., Cambridge, MA, USA', 'bio': {'p': ['Brandon Reagen is a PhD student in computer science at Harvard University. His research interests include methods for low-power, high-performance design leveraging specialized hardware, accelerator-centric sys-tems, and computer architecture/VLSI codesign. Reagen has an MS in computer science from Harvard University. Contact him at reagen@fas.harvard.edu.']}}, {'name': ' Gu-Yeon Wei', 'affiliation': 'Harvard Univ., Cambridge, MA, USA', 'bio': {'p': ['Gu-Yeon Wei is a Gordon McKay Professor of Electrical Engineering and Computer Science at Harvard University. His research interests include mixed-signal integrated cir-cuits, computer architecture, and runtime software, looking for cross-layer opportunities to develop energy-efficient systems. Wei has a PhD in electrical engineering from Stanford University. Contact him at guyeon@eecs.harvard.edu.']}}, {'name': 'David Brooks', 'affiliation': 'Harvard Univ., Cambridge, MA, USA', 'bio': {'p': ['David Brooks is the Haley Family Professor of Computer Science at Harvard University. His research interests include architectural and software approaches to address power, thermal, and reliability issues for embedded and high-performance computing systems. Brooks has a PhD in electrical engineering from Princeton University. Contact him at dbrooks@eecs.harvard.edu.']}} %*The Aladdin Approach to Accelerator Design and Modeling %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7106399 %f/micro/9ttn7dxyajzm1r4kvojiuiskwlepxq8c.pdf %m23cd2880459dd869088d9bcff46d8a41 %cmicro %@[{'name': 'Daniel Lustig', 'affiliation': 'Princeton University', 'bio': {'p': ['Daniel Lustig is a PhD candidate in the Department of Electrical Engineering at Princeton University. His research focuses on the design and verification of memory systems for heterogeneous computing platforms. Lustig has an MA in electrical engineering from Princeton University. He is a student member of IEEE and the ACM. Contact him at dlustig@princeton.edu.']}}, {'name': 'Michael Pellauer', 'affiliation': 'Intel', 'bio': {'p': ['Michael Pellauer is a senior research scientist at Nvidia. His research focuses on computer architecture, with emphasis on nonstandard accelerator architectures using spatial programming. Pellauer has a PhD in computer science from the Massachusetts Institute of Technology. He performed the research for this article while at Intel. Contact him atmpellauer@nvidia.com.']}}, {'name': 'Margaret Martonosi', 'affiliation': 'Princeton University', 'bio': {'p': ["Margaret Martonosi is the Hugh Trumbull Adams '35 Professor of Computer Science at Princeton University. Her research focuses on computer architecture and mobile computing, with emphasis on power-efficient systems. Martonosi has a PhD in electrical engineering from Stanford University. She is a fellow of IEEE and the ACM. Contact her at mrm@princeton.edu."]}} %*Verifying Correct Microarchitectural Enforcement of Memory Consistency Models %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7106405 %f/micro/uujmczvb394rnpljaydhqktk0e5qpo7m.pdf %mf79cbf114f6c9b7c21165e2a5e43bb4a %cmicro %@[{'name': 'Meng Zhang', 'affiliation': 'Duke University', 'bio': {'p': ["Meng Zhang is a software engineer at Oracle, where she's working on storage performance. Her research interests include memory system design and verification. Zhang has a PhD in computer architecture from Duke University, where she completed the work for this article. Contact her at zhangmeng916@gmail.com."]}}, {'name': 'Jesse D. Bingham', 'affiliation': 'Intel', 'bio': {'p': ['Jesse D. Bingham is a formal verification engineer at Intel, where he has applied, developed, supported, and researched formal hardware verification techniques. His research interests include arithmetic formal verification, protocol verification, theorem proving, and computer architecture. Bingham has a PhD in computer science from the University of British Columbia. Contact him at jesse.d.bingham@intel.com.']}}, {'name': 'John Erickson', 'affiliation': 'Intel', 'bio': {'p': ['John Erickson is a formal verification engineer at Intel, where he applies formal validation to many-integrated-core processor designs. His research interests include formal verification, hardware verification, and automated theorem proving. Erickson has a PhD in computer science, with a focus on automated theorem proving, from the University of Texas at Austin. Contact him at john.erickson @intel.com.']}}, {'name': 'Daniel J. Sorin', 'affiliation': 'Duke University', 'bio': {'p': ['Daniel J. Sorin is the W.H. Gardner Jr. Associate Professor of Electrical and Computer Engineering at Duke University. His research interests include computer architecture, reliability, and verification. Sorin has a PhD in electrical and computer engineering from the University of Wisconsin-Madison. Contact him at sorin@ee.duke.edu.']}} %*PVCoherence: Designing Flat Coherence Protocols for Scalable Verification %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7106379 %f/micro/0ordp3zlbzgyulnyxpc5sui7k9m8tdwa.pdf %md4e80586ba8658eb674d73aac6fa00f9 %cmicro %@[{'name': 'Seyed Majid Zahedi', 'affiliation': 'Duke University', 'bio': {'p': ['Seyed Majid Zahedi is a PhD student in the Department of Computer Science at Duke University. His research focuses on microeconomics and game theory for hardware resource allocation and management. Zahedi has an MS in electrical and computer engineering from the University of Tehran. He is a member of IEEE. Contact him at zahedi@cs.duke.edu.']}}, {'name': 'Benjamin C. Lee', 'affiliation': 'Duke University', 'bio': {'p': ['Benjamin C. Lee is an assistant professor in the Department of Electrical and Computer Engineering at Duke University. His research interests include energy-efficient design, emerging technologies, statistical methods, and algorithmic economics for computer architecture. Lee has a PhD in computer science from Harvard University. He is a member of IEEE and the ACM. Contact him at benjamin.c.lee@duke.edu.']}} %*Sharing Incentives and Fair Division for Multiprocessors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7106408 %f/micro/cao5esntzhdvspfxq8quneagp4m9yk7b.pdf %m954ade7ae88a9b0ce04d74f4d033729a %cmicro %@[{'name': 'Bharath Pichai', 'affiliation': 'Rutgers University', 'bio': {'p': ['Bharath Pichai is a software development engineer at Amazon, where he works on the Amazon Web Services infrastructure. His research interests include compilers, programming languages, architecture, and data-bases. Pichai has an MS in computer science from Rutgers University, where he completed the research for this article. Contact him at bsp57@cs.rutgers.edu.']}}, {'name': 'Lisa Hsu', 'affiliation': 'Qualcomm Research', 'bio': {'p': ['Lisa Hsu is a staff engineer in the R&D wing of Qualcomm. Her research interests include architecture, memory system design, and performance modeling. Hsu has a PhD in computer science from the University of Michigan, Ann Arbor. Contact her at hsul@qti.qualcomm.com.']}}, {'name': 'Abhishek Bhattacharjee', 'affiliation': 'Rutgers University', 'bio': {'p': ['Abhishek Bhattacharjee is an assistant professor in the Department of Computer Science at Rutgers University. His research interests include the intersection of architecture and operating systems, memory systems architecture, and virtualization. Bhattacharjee has a PhD in electrical engineering from Princeton University. Contact him at abhib@cs.rutgers.edu.']}} %*Address Translation for Throughput-Oriented Accelerators %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7106386 %f/micro/hiuwsyx157my6b9zklfckiedljq4rjmp.pdf %m87219df4f187ee31049e48bb272c7070 %cmicro %@[{'name': 'Arthur Perais', 'bio': {'p': ["Arthur Perais is a PhD candidate with the Amdahl's Law is Forever research group at INRIA Rennes. His research interests include core micro architecture and increasing sequential performance. Perais has an MS in computer science from the Universite of Rennes. He is a student member of IEEE. Contact him at arthur. perais@inria.fr."]}}, {'name': 'Andre Seznec', 'bio': {'p': ["André Seznec is a research director at INRIA Rennes, where he leads the Amdahl's Law is Forever research group. His research focuses on microprocessor architecture, including caches, branch predictors, and all forms of speculative execution. Seznec has a PhD in computer science from the Universite of Rennes. He is an IEEE Fellow. Contact him at andre.seznec@inria.fr."]}} %*EOLE: Toward a Practical Implementation of Value Prediction %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7130475 %f/micro/tkdxapzsbi9unl6ahgjijwh2wm851vqz.pdf %mf000021d3e6481c26976a773adb63571 %cmicro %@[{'name': 'Steven Pelley', 'affiliation': 'University of Michigan', 'bio': {'p': ['Steven Pelleyis a software developer at Snowflake Computing. His research interests include new database designs and memory interfaces for NVRAM. Pelley has a PhD in computer science and engineering from the University of Michigan, where he performed the work for this article. Contact him at spelley@umich.edu.']}}, {'name': 'Peter M. Chen', 'affiliation': 'University of Michigan', 'bio': {'p': ['Peter M. Chenis an Arthur F. Thurnau Professor in the Department of Electrical Engineering and Computer Science at the University of Michigan. His research interests include operating systems, computer security, and fault-tolerant computing. Chen has a PhD in computer science from the University of California at Berkeley. He is a fellow of IEEE and the ACM. Contact him at pmchen@umich.edu.']}}, {'name': 'Thomas F. Wenisch', 'affiliation': 'University of Michigan', 'bio': {'p': ['Thomas F. Wenischis an associate professor in the Department of Electrical Engineering and Computer Science at the University of Michigan. His research interests include multiprocessor and multicore systems, multicore programmability, smartphone architecture, datacenter architecture, and performance evaluation methodology. Wenisch has a PhD in electrical and computer engineering from Carnegie Mellon University. He is a member of IEEE and the ACM. Contact him at twenisch@umich.edu.']}} %*Memory Persistency: Semantics for Byte-Addressable Nonvolatile Memory Technologies %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7106393 %f/micro/0t5qxtd2sg86kzzldsvvhrr9mae4ekal.pdf %m4725d82e2745fd00e84f038f62067b47 %cmicro %@[{'name': 'James Bornholt', 'affiliation': 'University of Washington', 'bio': {'p': ['James Bornholt is a PhD student in the Department of Computer Science and Engineering at the University of Washington. His research focuses on how programming lan-guages, computer systems, and hardware architectures evolve and cooperate to address the competing demands of performance, energy efficiency, and accuracy. Bornholt has a BPhil in computer science from the Australian National University. Contact him at bornholt@cs.washington.edu.']}}, {'name': 'Todd Mytkowicz', 'affiliation': 'Microsoft Research', 'bio': {'p': ['Todd Mytkowicz is a researcher at Microsoft Research. His research focuses on creating abstractions that help programmers easily express complex problems and yet are sufficiently constrained to deliver efficient and powerful implementations. Mytkowicz has a PhD in computer science from the University of Colorado at Boulder. Contact him at toddm@microsoft.com.']}}, {'name': 'Kathryn S. McKinley', 'affiliation': 'Microsoft Research', 'bio': {'p': ['Kathryn S. McKinley is a principal researcher at Microsoft Research. Her research focuses on creating systems (programming languages, compilers, runtimes, and architectures) that make programming easy and the resulting programs efficient. McKinley has a PhD in computer science from Rice University. She is a fellow of IEEE and the ACM. Contact her at mckinley@microsoft.com.']}} %*Uncertain&lt;T&gt;: Abstractions for Uncertain Hardware and Software %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7106409 %f/micro/mxl2v87wkn5svybotwdrcjlrif6qza3u.pdf %m9474b852f98331c08145bd69cd93127f %cmicro %@[{'name': 'Trevor Mudge', 'affiliation': 'University of Michigan'} %*Thoughts on Winning the 2014 Eckert-Mauchly Award %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7130458 %f/micro/vv2tyscyibha1kgrmdxremz68tznau40.pdf %mddea3302e5810f50c7267f001c4e3597 %cmicro %@[{'name': 'Richard Mateosian', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/7129787/7130464/7130464-photo-1-small.gif', 'p': ['Richard Mateosian is a freelance technical writer in the San Francisco Bay Area. Contact him at xrmxrm@gmail.com.']}} %*Writing Well %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7130464 %f/micro/53sgzwjcgqlfikzqs9uepu41xkanhvb0.pdf %m3700945acf4add2464f8fe326823fa4d %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'Northwestern University', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/7129787/7130463/7130463-photo-1-small.gif', 'p': ['Shane Greenstein is the Kellogg Chair in Information Technology at the Kellogg School of Management, Northwestern University. Contact him at greenstein@ kellogg.northwestern.edu.']}} %*Twenty Years of the Commercial Internet, Part 1 %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7130463 %f/micro/bpeqav7dhztymbjuetncgm34fgrjs6rx.pdf %m7fc71170a1a7dc36b6ab9064bffd73fd %cmicro %@[{'name': 'Lieven Eeckhout', 'affiliation': 'Ghent University', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/7182235/7182240/7182240-photo-1-small.gif', 'p': ['Lieven Eeckhout is a professor in the Department of Electronics and Information Systems at Ghent University. Contact him at lieven.eeckhout@ugent.be.']}} %*Heterogeneity in Response to the Power Wall %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7182240 %f/micro/2wlzoiahbytujpszq37ob6fmctw5femg.pdf %m74ec3845f42d580cc3f51417ef572e00 %cmicro %@[{'name': 'Ravi Iyer', 'affiliation': 'Intel', 'bio': {'p': ['Ravi Iyer is a senior principal engineer, CTO, and director in New Business Initiatives at Intel. His interests include systems on chip and chip multiprocessors, including novel cores, accelerators, innovative cache and memory hierarchies, quality of service, heterogeneous architectures, algorithms and workloads, and performance and power analysis. Iyer has a PhD in computer science from Texas A&M University. He is an IEEE Fellow. Contact him at ravishankar.iyer@intel.com.']}}, {'name': 'Dean Tullsen', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Dean Tullsen is a professor in the Computer Science and Engineering Department at the University of California, San Diego. His research focuses on parallel architectures, including multithreading, multicores, and datacenters. Tullsen has a PhD from the University of Washington. He is a fellow of IEEE and the ACM. Contact him at tullsen@cs.ucsd.edu.']}} %*Heterogeneous Computing [Guest editors' introduction] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7182244 %f/micro/35r8b21mhlev0ixnt6agwszycqget7ul.pdf %md554ebc3a433e96ebbeb8c943fddcdf1 %cmicro %@[{'name': 'Johannes Langguth', 'affiliation': 'Simula Research Laboratory', 'bio': {'p': ['Johannes Langguth is a postdoctoral fellow at Simula Research Laboratory. His research interests include computer architecture, parallel algorithms, combinatorial optimization, and high-performance scientific computing on multicore CPUs and GPUs. Langguth has a PhD in computer science from the University of Bergen. Contact him at langguth@simula.no.']}}, {'name': 'Mohammed Sourouri', 'affiliation': 'Simula Research Laboratory', 'bio': {'p': ['Mohammed Sourouri is a PhD student at Simula Research Laboratory. He is also a member of the Scientific Computation Group at the University of California, San Diego. His research focuses on parallel computing and domain-specific source-to-source translators. Sourouri has an MSc in computer science from the University of Oslo. Contact him at mohamso@simula.no.']}}, {'name': 'Glenn Terje Lines', 'affiliation': 'Simula Research Laboratory', 'bio': {'p': ['Glenn Terje Lines is a senior research scientist at Simula Research Laboratory. His research interests include numerical methods for partial differential equations and computer simulation of cardiac electro-physiology. Lines has a PhD in computer science from the University of Oslo. Contact him at glennli@simula.no.']}}, {'name': 'Scott B. Baden', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Scott B. Baden is professor in the Department of Computer Science and Engineering at the University of California, San Diego. His research focuses on domain-specific translation, performance programming, and adaptive and irregular applications. Baden has a PhD in computer science from the University of California, Berkeley. He is a senior member of IEEE, a member of SIAM, and a senior fellow at the San Diego Supercomputer Center. Contact him at baden@eng.ucsd.edu.']}}, {'name': 'Xing Cai', 'affiliation': 'Simula Research Laboratory', 'bio': {'p': ['Xing Cai is the head of the HPC group at Simula Research Laboratory and a professor of computer science at the University of Oslo. His research interests include parallel programming and high-performance scientific computing on multicore CPUs and GPUs, numerical methods for solving partial differential equations (PDEs) and generic PDE software. Cai has a PhD in scientific computing from the University of Oslo. Contact him at xingca@simula.no.']}} %*Scalable Heterogeneous CPU-GPU Computations for Unstructured Tetrahedral Meshes %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7155461 %f/micro/6v5rpvjfeoihu8q2bsaoexiztbz0munw.pdf %m256255aae8cacdbb96890a9263b9bbb4 %cmicro %@[{'name': 'Guoyang Chen', 'affiliation': 'North Carolina State University', 'bio': {'p': ['Guoyang Chen is a PhD student in the Department of Computer Science at North Carolina State University. His research interests include heterogeneous computing, com-pilers, and parallel computing. Chen has a BS in computer science from the University of Science and Technology of China. Contact him at gchenll@ncsu.edu.']}}, {'name': 'Bo Wu', 'affiliation': 'Colorado School of Mines', 'bio': {'p': ['Bo Wu is an assistant professor in the Department of Electrical Engineering and Computer Science at the Colorado School of Mines. His research interests include high-performance computing, heterogeneous computing, program analysis and optimizations, and compilers. Wu has a PhD in computer science from the College of William and Mary. Contact him at bwu @mines.edu.']}}, {'name': 'Dong Li', 'affiliation': 'University of California, Merced', 'bio': {'p': ['Dong Li is an assistant professor in the Department of Electrical Engineering and Computer Science at the University of California, Merced. His research interests include high-performance computing, performance modeling, programming models, architecture, and runtime. Li has a PhD in computer science from Virginia Tech. Contact him at dli35@ucmerced.edu.']}}, {'name': 'Xipeng Shen', 'affiliation': 'North Carolina State University', 'bio': {'p': ['Xipeng Shen is an associate professor in the Department of Computer Science at North Carolina State University. He is also an adjunct associate professor at the College of William and Mary and an IBM Canada CAS Research Faculty Fellow. His research interests include compilers, program analysis and optimizations, heterogeneous computing, high-performance computing, and machine learning. Shen has a PhD in computer science from the University of Rochester. Contact him at xshen5@ncsu.edu.']}} %*Enabling Portable Optimizations of Data Placement on GPU %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7106396 %f/micro/i49nwbe1sckgytls57hmp6naeafthyjp.pdf %m873eca84528b0e761c8c0086bb24ebc6 %cmicro %@[{'name': 'Michael J. Schulte', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ["Michael J. Schulte is a senior fellow at Advanced Micro Devices, where he's the principal investigator on AMD's FastForward 2 Node Architecture Project. His research interests include power-efficient processor design, heterogeneous processor architectures, and high-performance com-=puting. Schulte has a PhD in electrical engineering from the University of Texas at Austin. Contact him at michael.schulte@amd.com."]}}, {'name': 'Mike Ignatowski', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ["Mike Ignatowski is a fellow at Advanced Micro Devices, where he's the principal investigator for AMD's FastForward 2 Memory Technology Project. His research interests include emerging memory technology and architectures. Ignatowski has an MS in computer engineering from the University of Michigan. Contact him at"]}}, {'name': 'Gabriel H. Loh', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ["Gabriel H. Loh is a fellow at Advanced Micro Devices. His research interests include computer architecture, processor microarchitecture, emerging technologies, and 3D die stacking. Loh has a PhD in computer science from Yale University. He's a senior member of IEEE and an ACM distinguished scientist. Contact him at"]}}, {'name': 'Bradford M. Beckmann', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ['Bradford M. Beckmann is a senior member of the technical staff at Advanced Micro Devices, where he directs research in the areas of heterogeneous (CPU+GPU) archi-tectures, cache coherence protocols, memory constancy models, on-chip networks, and simulation. Beckmann has a PhD in computer science from the University of Wisconsin-Madison. Contact him at']}}, {'name': 'William C. Brantley', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ["William C. Brantley is an AMD Fellow at Advanced Micro Devices, where he leads AMD's exascale projects funded by the Department of Energy. His research interests include high-performance computing, system performance, and exascale. Brantley has a PhD in electrical engineering from Carnegie Mellon University. He's a member of the ACM and a life member of IEEE. Contact him at"]}}, {'name': 'Sudhanva Gurumurthi', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ["Sudhanva Gurumurthi is a senior member of the technical staff at Advanced Micro Devices, where he directs research on resiliency and reliability. He is also a visiting associate professor in the Department of Computer Science at the University of Virginia. His research interests include resiliency and reliability, datacenter architectures, and energy-efficient design. Guru-murthi has a PhD in computer science and engineering from Pennsylvania State University. He's a senior member of IEEE and the ACM. Contact him at"]}}, {'name': 'Nuwan Jayasena', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ["Nuwan Jayasena is a principal member of the technical staff at Advanced Micro Devices, where he leads research efforts on processing in memory and multilevel memories. His research interests include memory systems, heterogeneous computing, processor microarchitecture, and emerging technologies and applications. Jayasena has a PhD in electrical engineering from Stanford University. He's a senior member of IEEE. Contact him at"]}}, {'name': 'Indrani Paul', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ["Indrani Paul is a senior member of the technical staff at Advanced Micro Devices, where she leads research on energy utilization in AMD's exascale projects funded by the Department of Energy. Her research interests include power-efficient design, power management and modeling, emerging workloads, and heterogeneous architectures. Paul has a PhD in electrical and computer engineering from the Georgia Institute of Technology. She's a member of IEEE. Contact her at indrani.paul@amd.com."]}}, {'name': 'Steven K. Reinhardt', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ["Steven K. Reinhardt is a senior fellow at Advanced Micro Devices, where he is the principal investigator and technical lead on AMD's DesignForward exascale R&D project. His research interests include high-speed networking, system architecture, and system simulation. Reinhardt has a PhD in computer science from the University of Wisconsin-Madison. He's an IEEE Fellow and an ACM Distinguished Scientist. Contact him at"]}}, {'name': 'Gregory Rodgers', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ['Gregory Rodgers is a principal member of the technical staff at Advanced Micro Devices, where he leads the exascale programmability team. He is also a visiting professor in the Department of Computer and Information Technology at Purdue University. His research interests include heterogeneous system architectures and runtimes. Rodgers has a PhD in computer science from Pennsylvania State University. Contact him at']}} %*Achieving Exascale Capabilities through Heterogeneous Computing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7155462 %f/micro/rhluoaf5tmw8bxqnvxr7ypfygd3mtd9s.pdf %m9d42c5395bf0530733bb822f96d4e748 %cmicro %@[{'name': 'Nikola Markovic', 'affiliation': 'Barcelona Supercomputing Center', 'bio': {'p': ['Nikola Markovic is a PhD candidate at the Universitat Politècnica de Catalunya and a researcher in the Computer Architecture for Parallel Paradigms group at the Barcelona Supercomputing Center. His research focuses on hardware and software design for high-per-formance multithreaded computing on symmetric and asymmetric chip multiprocessors. Markovic has an MSc in computer architecture, networks, and systems from the Universitat Politècnica de Catalunya. Contact him at nikola.markovic@bsc.es.']}}, {'name': 'Daniel Nemirovsky', 'affiliation': 'Barcelona Supercomputing Center', 'bio': {'p': ['Daniel Nemirovsky is a PhD candidate at the Universitat Politècnica de Catalunya and a researcher in the Computer Architecture for Parallel Paradigms group at the Barcelona Supercomputing Center. His research interests include object-oriented computer architecture, exploring cache hier-archies, and scheduling techniques on chip multiprocessors. Nemirovsky has an MSc in computer architecture, networks, and systems from the Universitat Politècnica de Catalunya. Contact him at daniel. nemirovsky@bsc.es.']}}, {'name': 'Osman Unsal', 'affiliation': 'Barcelona Supercomputing Center', 'bio': {'p': ['Osman Unsal is a group manager in the Computer Architecture for Parallel Paradigms group at the Barcelona Supercomputing Center and a researcher at the BSC-Microsoft Research Centre. His research interests include computer architecture, fault tolerance, and transactional memory. Unsal has a PhD in electrical and computer engineering from the University of Massa-chusetts, Amherst. Contact him at osman. unsal@bsc.es.']}}, {'name': 'Mateo Valero', 'affiliation': 'Barcelona Supercomputing Center', 'bio': {'p': ['Mateo Valero is a full professor in the Computer Architecture Department at the Universitat Politècnica de Catalunya and the director of the Barcelona Supercomputing Center. His research focuses oo high-per-formance computer architectures. Valero has a PhD in telecommunications from the Universitat Politècnica de Catalunya. He is a fellow of IEEE and the ACM and is an Intel Distinguished Research Fellow. Contact him at mateo.valero@bsc.es.']}}, {'name': 'Adrian Cristal', 'affiliation': 'Barcelona Supercomputing Center', 'bio': {'p': ['Adrian Cristal is a researcher and comanager of the Computer Architecture for Parallel Paradigms group at the Barcelona Supercomputing Center and the Artificial Intelligence Research Institute, Spanish National Research Council. His research focuses on microarchi-tecture, multicore architectures, and programming models for multicore architectures. Cristal has a PhD in computer science from the Universitat Politècnica de Catalunya. Contact him at adrian.cristal@bsc.es.']}} %*Kernel-to-User-Mode Transition-Aware Hardware Scheduling %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7182246 %f/micro/eojuw7bjqw23qrr9llm0kfm8ybissnng.pdf %mb09d99e0ff31e7db84407176dbdc122e %cmicro %@[{'name': 'Amit Sabne', 'affiliation': 'Purdue University'}, {'name': 'Putt Sakdhnagool', 'affiliation': 'Purdue University'}, {'name': 'Seyong Lee', 'affiliation': 'Oak Ridge National Laboratory'}, {'name': 'Jeffrey S. Vetter', 'affiliation': 'Oak Ridge National Laboratory'} %*Understanding Portability of a High-Level Programming Model on Contemporary Heterogeneous Architectures %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7155420 %f/micro/p6nbcy2tfsdtg8e3i9jcwqloyhqhxvnp.pdf %m2990e2033fd81d94a8d7298baff8933a %cmicro %@[{'name': 'Evgeny Bolotin', 'affiliation': 'Nvidia', 'bio': {'p': ['Evgeny Bolotin is a senior research scientist in the architecture research group at Nvidia. His research interests include computer systems architecture, memory systems, and energy-efficient architectures. Bolotin has a PhD in electrical engineering from the Technion-Israel Institute of Technology. He is a member of IEEE. Contact him at ebolotin@nvidia.com.']}}, {'name': 'David Nellans', 'affiliation': 'Nvidia', 'bio': {'p': ['David Nellans is a senior research scientist in the architecture research group at Nvidia. His research interests include OS and computer architecture interaction, nonvolatile memory, and storage systems. Nellans has a PhD in computer science from the University of Utah. Contact him at dnellans @nvidia.com.']}}, {'name': 'Oreste Villa', 'affiliation': 'Nvidia', 'bio': {'p': ['Oreste Villa is a senior research scientist in the architecture research group at Nvidia. His research interests include system-level computer architecture, high-performance computing, and distributed runtimes. Villa has a PhD in computer science from Politecnico di Milano. Contact him at ovilla @nvidia.com.']}}, {'name': "Mike O'Connor", 'affiliation': 'Nvidia', 'bio': {'p': ["Mike O'Connor is a senior manager and research scientist at Nvidia. His research interests include memory systems for GPUs and heterogeneous processors. O'Connor has an MS in electrical and computer engineering from the University of Texas at Austin. He is a senior member of IEEE and a member of the ACM. Contact him at moconnor@nvidia.com."]}}, {'name': 'Alex Ramirez', 'affiliation': 'Nvidia', 'bio': {'p': ['Alex Ramirez is a principal research scientist in the architecture research group at Nvidia. His research interests include energy-efficient supercomputing, heterogeneous multicore architectures, hardware support for programming models, and simulation techniques. Ramirez has a PhD in computer science from the Universitat Politecnica de Catalunya. He is a member of the ACM. Contact him at aramirez@nvidia.com.']}}, {'name': 'Stephen W. Keckler', 'affiliation': 'Nvidia', 'bio': {'p': ['Stephen W. Keckler is the senior director of architecture research at Nvidia and an adjunct professor of computer science at the University of Texas at Austin. His research interests include parallel computer architectures, memory systems, and accelerator architectures. Keckler has a PhD in computer science from the Massachusetts Institute of Technology. He is a fellow of IEEE and the ACM. Contact him at skeckler @nvidia.com.']}} %*Designing Efficient Heterogeneous Memory Architectures %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7155441 %f/micro/6rshwx89za2isbady3mk0enhv7bfku5o.pdf %m00e99be62767ddb27c14f53505838944 %cmicro %@[{'name': 'Ismail Akturk', 'affiliation': 'University of Minnesota, Twin Cities', 'bio': {'p': ['Ismail Akturk is a PhD student in the Department of Electrical and Computer Engineering at the University of Minnesota, Twin Cities. His research focuses on energy-efficient computer architecture and approximate computing. Akturk has an MS in computer engineering from Bilkent University, Turkey. Contact him at aktur002@umn.edu.']}}, {'name': 'Nam Sung Kim', 'affiliation': 'University of Illinois at Urbana-Champaign', 'bio': {'p': ['Nam Sung Kim is an associate professor in the Department of Electrical and Computer Engineering at the University of Illinois at Urbana—Champaign. His research focuses on devices, circuits, and architectures for power-efficient computing. Kim has a PhD in computer science and engineering from the University of Michigan. Contact him at nskim@illinois.edu.']}}, {'name': 'Ulya R. Karpuzcu', 'affiliation': 'University of Minnesota, Twin Cities', 'bio': {'p': ['Ulya R. Karpuzcu is an assistant professor in the Department of Electrical and Computer Engineering at the University of Minnesota, Twin Cities. Her research focuses on the impact of process technology on computing systems. Karpuzcu has a PhD in computer engineering from the University of Illinois at Urbana—Champaign. Contact her at ukarpuzc@umn.edu.']}} %*Decoupled Control and Data Processing for Approximate Near-Threshold Voltage Computing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7182247 %f/micro/bkt9jpf6pmovwaozeczyblc0alxrrhm1.pdf %m5b10c8ac16ba4088af7821ac5096bcf5 %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'Harvard Business School', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/7182235/7182239/7182239-photo-1-small.gif', 'p': ['Shane Greenstein is a professor at the Harvard Business School. Contact him at sgreenstein@hbs.edu.']}} %*Who Is Gordon Moore, and Why Is There a Law Named for Him? %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7182239 %f/micro/1czoeluharf8jyqkok0g9cwypp5dj2rz.pdf %m4c4b3cdc7c0946570b89fcdc244eca44 %cmicro %@[{'name': 'Lieven Eeckhout', 'affiliation': 'Ghent University', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/7310924/7310925/7310925-photo-1-small.gif', 'p': ['Lieven Eeckhout is a professor in the Department of Electronics and Information Systems at Ghent University. Contact hindi at lieven.eeckhout@ugent.be.']}} %*The Structure of Computer Architecture (R)evolution %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7310925 %f/micro/3grfgpmk8zk7sh1t2ibdcjycbejqxeas.pdf %mba7b28f74e067aec21672195a0a7d4a8 %cmicro %@[{'name': 'Olivier Temam', 'affiliation': 'Google', 'bio': {'p': ['Olivier Temam is an engineer at Google. His research focuses on hardware neural networks. Temam has a PhD in computer science from the University of Rennes. Contact him at temam@google.com.']}}, {'name': 'Luis Ceze', 'affiliation': 'University of Washington', 'bio': {'p': ['Luis Ceze is the Torode Family Associate Professor in the Department of Computer Science and Engineering at the University of Washington. His research focuses on improving the performance and energy efficiency of computer systems, and, more recently, on exploring bioinspired and bio-integrated technologies. Ceze has a PhD in computer science from the University of Illinois at Urbana-Champaign. Contact him at luisceze@cs.washington.edu.']}} %*Alternative Computing Designs and Technologies %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7310938 %f/micro/lceie5vftonhkfzmkvg10r8ubyrqw43x.pdf %mdb9a6a98eb65314ba24b6bffba9c535d %cmicro %@[{'name': 'Daniel Nemirovsky', 'affiliation': 'Barcelona Supercomputing Center', 'bio': {'p': ['Daniel Nemirovsky is a PhD candidate at the Universitat Politècnica de Catalunya and a researcher in the Computer Architecture for Parallel Paradigms Group at the Barcelona Supercomputing Center. His research interests include high-level language architectures, cache hierarchies, and scheduling techniques on heterogeneous chip multiprocessors. Nem-irovsky has an MSc in computer architecture, networks, and systems from the Universitat Politècnica de Catalunya. Contact him at daniel.nemirovsky@bsc.es.']}}, {'name': 'Nikola Markovic', 'affiliation': 'Barcelona Supercomputing Center', 'bio': {'p': ['Nikola Markovic is a PhD candidate at the Universitat Politècnica de Catalunya and a researcher in the Computer Architecture for Parallel Paradigms Group at the Barcelona Supercomputing Center. His research focuses on hardware and software design for highperformance multithreaded computing on symmetric and asymmetric chip multiprocessors. Markovic has an MSc in computer architecture, networks, and systems from the Universitat Politècnica de Catalunya. Contact him at nikola.markovic@bsc.es.']}}, {'name': 'Osman Unsal', 'affiliation': 'Barcelona Supercomputing Center', 'bio': {'p': ['Osman Unsal is a group manager in the Computer Architecture for Parallel Paradigms Group at the Barcelona Supercomputing Center and a researcher at the BSC-Microsoft Research Centre. His research interests include computer architecture, fault tolerance, and transactional memory. Unsal has a PhD in electrical and computer engineering from the University of Massachusetts, Amherst. Contact him at osman.unsal@bsc.es.']}}, {'name': 'Mateo Valero', 'affiliation': 'Barcelona Supercomputing Center', 'bio': {'p': ['Mateo Valero is a full professor in the Computer Architecture Department at the Universitat Politècnica de Catalunya and the director of the Barcelona Supercomputing Center. His research focuses on high-per-formance computer architectures. Valero has a PhD in telecommunications from the Universitat Politècnica de Catalunya. He is a fellow of IEEE and the ACM and is an Intel Distinguished Research Fellow. Contact him at mateo.valero@bsc.es.']}}, {'name': 'Adrian Cristal', 'affiliation': 'Barcelona Supercomputing Center', 'bio': {'p': ['Adrian Cristal is a researcher and comanager of the Computer Architecture for Parallel Paradigms Group at the Barcelona Supercomputing Center and the Artificial Intelligence Research Institute, Spanish National Research Council. His research focuses on microarchitecture, multicore architectures, and programming models for multicore architectures. Cristal has a PhD in computer science from the Universitat Politècnica de Catalunya. Contact him at adrian.cristal@bsc.es.']}} %*Reimagining Heterogeneous Computing: A Functional Instruction-Set Architecture Computing Model %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7310930 %f/micro/tbdeaczwinyl7dgoo0psklv6hk2zxvw3.pdf %m5906b7e84e9a9bab3ced38849891dbf8 %cmicro %@[{'name': 'Divya Mahajan', 'affiliation': 'Georgia Institute of Technology', 'bio': {'p': ['Divya Mahajan is a PhD student in the Computer Science Department at the Georgia Institute of Technology, where she works in the Alternate Computing Technologies Lab. Her research interests include computer architecture, micro architecture design, and hardware acceleration. Mahajan has an MS in electrical and computer engineering from the University of Texas at Austin. Contact her at divya_mahajan@gatech.edu.']}}, {'name': 'Kartik Ramkrishnan', 'affiliation': 'University of Minnesota', 'bio': {'p': ['Kartik Ramkrishnan is a PhD candidate in the Department of Computer Science and Engineering at the University of Minnesota. His research focuses on the development of novel techniques for improving memory system performance and approximate circuit design. Ramkrishnan has an MS in electrical engineering from the University of Minnesota, Minneapolis. Contact him at ramkr004@umn.edu.']}}, {'name': 'Rudra Jariwala', 'affiliation': 'University of Minnesota', 'bio': {'p': ['Rudra Jariwala is a CAD Engineer at Apple. His research interests include approximate hardware design, low-power CAD algorithms, and integrated circuit design. Jariwala has an MS in electrical engineering from the University of Minnesota, Twin Cities, where he completed the work for this article. Contact him at jariw004@umn.edu.']}}, {'name': 'Amir Yazdanbakhsh', 'affiliation': 'Georgia Institute of Technology', 'bio': {'p': ['Amir Yazdanbakhsh is a PhD student in the School of Computer Science at the Georgia Institute of Technology, where he works as a research assistant in the Alternative Computing Technologies Lab. His research interests iqjdftnclude computer architecture, approximate general-purpose computing, mixed-signal accelerator design, machine learning, and neuromorphic computing. Yazdanbakhsh has an MS in computer engineering from the University of Wisconsin-Madison and an MS in electrical and computer engineering from the University of Tehran. He is a student member of IEEE and the ACM. Contact him at a.yazdanbakhsh@gatech.edu.']}}, {'name': 'Jongse Park', 'affiliation': 'Georgia Institute of Technology', 'bio': {'p': ['Jongse Park is a PhD student in the College of Computing at the Georgia Institute of Technology. His research interests include computer architecture, programming languages, and alternative computing technology. Park has an MS in computer science from the Korea Advanced Institute of Science and Technology. Contact him at jspark@gatech.edu.']}}, {'name': 'Bradley Thwaites', 'affiliation': 'Georgia Institute of Technology', 'bio': {'p': ['Bradley Thwaites is a PhD student in the Department ofdm Electrical and Computer Engineering at the Georgia Institute of Technology. His interests are in computer architecture, memory systems, operating systems, acceleration, and machine learning. Thwaites has an MS in electrical and computer engineering from the Georgia Institute of Technology. Contact him at bthwaites@gatech.edu.']}}, {'name': 'Anandhavel Nagendrakumar', 'affiliation': 'Georgia Institute of Technology', 'bio': {'p': ['Anandhavel Nagendrakumar is a product engineer at 1M Flash Technologies. His research interests include VLSI design, computer architetture, and approximate computing. Nagendrakumar has an MS in electrical and computer engineering from the Georgia Institute of Technology, where he completed the work for this article. Contact him at anandhavel@gatech.edu.']}}, {'name': 'Abbas Rahimi', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Abbas Rahimi is a PhD candidate in the Department of Computer Science and Engineering at the University of California, San Diego. His research interests include resilient system design, approximate computing, neuro-inspired computing, and on-chip interconnections. Rahimi has a BS in computer engineering from the School of Electrical and Computer Engineering at the University of Tehran. Contact him at abbas@cs.ucsd.edu.']}}, {'name': 'Hadi Esmaeilzadeh', 'affiliation': 'Georgia Institute of Technology', 'bio': {'p': ['Hadi Esmaeilzadeh is the inaugural holder of the Catherine M. and James E. Allchin Early Career Professorship in the School of Computer Science at the Georgia Institute of Technology. He is also the founder and director of the Alternative Computing Technologies Lab. His research focuses on developing new technologies and cross-stack solutions to improve the performance and energy efficiency of computer systems for emerging applications. Esmaeilzadeh has a PhD in computer science and engineering from the University of Washington. Contact him at hadi@cc.gatech.edu.']}}, {'name': 'Kia Bazargan', 'affiliation': 'University of Minnesota', 'bio': {'p': ['Kia Bazargan is an associate professor in the Electrical and Computer Engineering Department at the University of Minnesota. His research interests include FPGA architectures, physical design, and applications and stochastic computing. Bazargan has a PhD in electrical and computer engineering from Northwestern University. Contact him at kia@umn.edu.']}} %*Axilog: Abstractions for Approximate Hardware Design and Reuse %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7310928 %f/micro/acf6jabprke08z1ncifhmosuvdqzk2ex.pdf %m606ddceb52c5f54e85bdb9be00ed4185 %cmicro %@[{'name': 'Kaisheng Ma', 'affiliation': 'Pennsylvania State University', 'bio': {'p': ['Kaisheng Ma is a PhD student in the Department of Computer Science and Engineering at Pennsylvania State University. His research interests include energy-harvesting architectures, machine learning, and neuromorphic computing. Ma has an ME in microelectronics from Peking University. Contact him at kxm505@cse.psu.edu.']}}, {'name': 'Xueqing Li', 'affiliation': 'Pennsylvania State University', 'bio': {'p': ['Xueqing Li is a postdoctoral researcher in the Department of Computer Science and Engineering at Pennsylvania State University. His research interests include wireless transceivers, high-performance data converters, self-powered nonvolatile systems, and circuits and systems using emerging devices. Li has a PhD in electronics engineering from Tsinghua University. He is a member of IEEE. Contact him at lixueq@cse.psu.edu.']}}, {'name': 'Shuangchen Li', 'affiliation': 'University of California, Santa Barbara', 'bio': {'p': ['Shuangchen Li is a PhD student in the Department of Electrical and Computer Engineering at the University of California, Santa Barbara. His research focuses on computer architecture, especially emerging nonvolatile memory. Li has an MS in electronic engineering from Tsinghua University. Contact him at shuangchenli@ece.ucsb.edu.']}}, {'name': 'Yongpan Liu', 'affiliation': 'Tsinghua University', 'bio': {'p': ['Yongpan Liu is an associate professor in the Department of Electronic Engineering at Tsinghua University. His research interests include nonvolatile computation, low-power VLSI design, emerging circuits and systems, and design automation. Liu has a PhD in electronics engineering from Tsinghua University. He is a member of IEEE, the ACM, and the Institute of Electronics, Information, and Communication Engineers. Contact him at ypliu@tsinghua.edu.cn.']}}, {'name': 'John Jack Sampson', 'affiliation': 'Pennsylvania State University', 'bio': {'p': ['John (Jack) Sampson is an assistant professor in the Department of Computer Science and Engineering at Pennsylvania State U ni-versity. His research interests include energy-efficient computing, architectural adaptations to exploit emerging technologies, and mitigating the impact of dark silicon. Sampson has a PhD in computer engineering from the University of California, San Diego. He is a member of IEEE. Contact him at sampson@cse.psu.edu.']}}, {'name': 'Yuan Xie', 'affiliation': 'University of California, Santa Barbara', 'bio': {'p': ['Yuan Xie is a professor in the Department of Electrical and Computer Engineering at the University of California, Santa Barbara. His research interests include computer architecture, EDA, and VLSI design. Xie has a PhD in electrical engineering from Princeton University. He is a fellow of IEEE. Contact him at yuanxie@ece.ucsb.edu.']}}, {'name': 'Vijaykrishnan Narayanan', 'affiliation': 'Pennsylvania State University', 'bio': {'p': ['Vijaykrishnan Narayanan is a Distinguished Professor of Computer Science and Engineering and Electrical Engineering at Pennsylvania State University. His research focuses on energy-efficient computing. Narayanan has a PhD in computer science from the University of South Florida. He is a fellow of IEEE and the ACM. Contact him at vijay@cse.psu.edu.']}} %*Nonvolatile Processor Architecture Exploration for Energy-Harvesting Applications %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7274242 %f/micro/ycujqm5abguvxwnwoxd7j3pokzbageml.pdf %m559227e9a1677341406561e7d29716e5 %cmicro %@[{'name': 'Dilan Manatunga', 'affiliation': 'Georgia Institute of Technology', 'bio': {'p': ['Dilan Manatunga is a PhD student in the School of Computer Science at the Georgia Institute of Technology. His research focuses on optimizations for mobile operating systems and architectures. Manatunga has a BS in computer science from the Georgia Institute of Technology. He is a member of IEEE and the ACM. Contact him at dmanatunga@gatech.edu.']}}, {'name': 'Hyesoon Kim', 'affiliation': 'Georgia Institute of Technology', 'bio': {'p': ['Hyesoon Kim is an associate professor in the School of Computer Science at the Georgia Institute of Technology. Her research interests include high-performance, energy-efficient heterogeneous architectures, interaction between programmers, compilers, and micro-architectures, and developing tools to help parallel programming. Kim has a PhD in electrical and computer engineering from the University of Texas at Austin. She is a member of IEEE and the ACM. Contact her at hyesoon@cc.gatech.edu.']}}, {'name': 'Saibal Mukhopadhyay', 'affiliation': 'Georgia Institute of Technology', 'bio': {'p': ['Saibal Mukhopadhyay is an associate professor in the School of Electrical and Computer Engineering at the Georgia Institute of Technology. His research interests include neuromorphic computing, low-power digital and mixed-signal systems, voltage regulation, and power and thermal management. Mukhopadhyay has a PhD in electrical and computer engineering from Purdue University. He is a member of IEEE. Contact him at saibal.mukhopadhyay@ece.gatech.edu.']}} %*SP-CNN: A Scalable and Programmable CNN-Based Accelerator %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7310929 %f/micro/bcywtvwiskh6aqqphoymvxli1auc9fz5.pdf %m48ca14d9a3d8f783ec6d1b3732867af0 %cmicro %@[{'name': 'Sergi Abadal', 'affiliation': 'Universitat Politè,cnica de Catalunya', 'bio': {'p': ['Sergi Abadal is a PhD student at the NaNo-Networking Center in Catalonia, Spain, at the Universitat Politècnica de Catalunya. His research interests include on-chip networking, many-core architectures, and graphene-based wireless communications. Abadal has an MSc in information and communication technologies from the Universitat Politècnica de Catalunya. Contact him at abadal@ac.upc.edu.']}}, {'name': 'Benny Sheinman', 'affiliation': 'IBM Research-Haifa', 'bio': {'p': ['Benny Sheinman is a research staff member in the mm Wave Technologies Group at IBM Research-Haifa. His research interests include analog design automation, analog, RF, and mm Wave IC design, and semiconductor device physics. Sheinman has a PhD in electrical engineering from the Techni-on-Israel Institute of Technology. Contact him at bennys@il.ibm.com.']}}, {'name': 'Oded Katz', 'affiliation': 'IBM Research-Haifa', 'bio': {'p': ['Oded Katz is a research staff member in the mm Wave Technologies Group at IBM Research-Haifa. His research interests include analog and RF IC design and mm Wave transceiver architecture. Katz has a PhD in electrical engineering from the Technion-Israel Insti tute of Technology. Contact him at katzo@il.ibm.com.']}}, {'name': 'Ofer Markish', 'affiliation': 'IBM Research-Haifa', 'bio': {'p': ['Ofer Markish is a research staff member in the mm Wave Technologies Group at IBM Research-Haifa. His research interests include antennas and electromagnetic wave propagation from microwave up to THz frequencies. Markish has an MSc in electrical engineering from Tel-Aviv University. Contact him at oferma@il.ibm.com.']}}, {'name': 'Danny Elad', 'affiliation': 'IBM Research-Haifa', 'bio': {'p': ['Danny Elad is a manager in the mm Wave Technologies Group at IBM Research-Haifa. His research interests include active and passive imagers, mm Wave IC design, and advanced packaging and antennas from microwave up to THz frequencies. Elad has a PhD in electrical engineering from the Department of Quality Assurance and Reliability from the Technion-Israel Institute of Technology. Contact him at dannye@il.ibm.com.']}}, {'name': 'Yvan Fournier', 'affiliation': 'EDF', 'bio': {'p': ['Yvan Fournier is a core researcher in R&D at EDF. His research interests include highperformance computing, visualization, and parallel mesh modification. Fournier has an MSc in aeronautical engineering from the Ecole Central Paris. Contact him at yvan.fournier@edf.fr.']}}, {'name': 'Damian Roca', 'affiliation': 'Barcelona Supercomputing Center', 'bio': {'p': ['Damian Roca is a PhD student at the Barcelona Supercomputing Center. His research interests include processor architectures, the Internet of Things, and fog computing. Roca has an MSc in innovation and research in informatics from the Universitat Politècnica de Catalunya. Contact him at damian.roca@bsc.es.']}}, {'name': 'Mauricio Hanzich', 'affiliation': 'Barcelona Supercomputing Center', 'bio': {'p': ['Mauricio Hanzich is a team leader at the Barcelona Supercomputing Center. His research interests include high-performance computing, code optimization, and hardware architecture. Hanzich has a PhD in computer science from the Universitat Autònoma de Barcelona. Contact him at mauricio.hanzich@bsc.es.']}}, {'name': 'Guillaume Houzeaux', 'affiliation': 'Barcelona Supercomputing Center', 'bio': {'p': ['Guillaume Houzeaux is a team leader at the Barcelona Supercomputing Center. His research interests include high-performance computational mechanics, iterative solvers, domain composition methods, and numerical modeling. Houzeaux has a PhD from the Universitat Politècnica de Catalunya. Contact him at guillaume.houzeaux@bsc.es.']}}, {'name': 'Mario Nemirovsky', 'affiliation': 'Barcelona Supercomputing Center', 'bio': {'p': ['Mario Nemirovsky is a Catalan Institution for Research and Advanced Studies (ICREA) Senior Research Professor at the Barcelona Supercomputing Center. His research interests include computer architectures, highperformance computing, the Internet of Things, and emerging on-chip interconnect technologies. Nemirovsky has a PhD from the University of California, Santa Barbara. Contact him at mario.nemirovsky@bsc.es.']}}, {'name': 'Eduard Alarcó,n', 'affiliation': 'Universitat Politè,cnica de Catalunya', 'bio': {'p': ['Eduard Alarcon is an associate professor at the NaNoNetworking Center in Catalonia at the Universitat Politècnica de Catalunya. His research interests include nanocommunications, energy harvesting, and wireless energy transfer. Alarcon has a PhD from the Universitat Politècnica de Catalunya. Contact him at eduard.alarcon@upc.edu.']}}, {'name': 'Albert Cabellos-Aparicio', 'affiliation': 'Universitat Politè,cnica de Catalunya', 'bio': {'p': ['Albert Cabellos-Aparicio is an associate professor at the NaNoNetworking Center in Catalonia at the Universitat Politècnica de Catalunya. His research interests include graphene technology, nanocommunications, and software-defined networking. Cabellos-Aparicio has a PhD in computer science engineering from the Universitat Politècnica de Catalunya. Contact him at acabello@ac.upc.edu.']}} %*Broadcast-Enabled Massive Multicore Architectures: A Wireless RF Approach %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7310933 %f/micro/vxmonrgsfolbwmrkeezfj8qi2uvi0k7l.pdf %mcbe5a0586fbc352d96608d26e599254b %cmicro %@[{'name': 'Qing Guo', 'affiliation': 'University of Rochester', 'bio': {'p': ['Qing Guo is a PhD student in the Department of Computer Science at the University of Rochester. His research interests are in energy-efficient computing and architectures exploiting resistive memory technologies. Guo has an MS in computer science from the University of Rochester. Contact him at qguo@cs.rochester.edu.']}}, {'name': 'Xiaochen Guo', 'affiliation': 'University of Rochester', 'bio': {'p': ['Xiaochen Guo is an assistant professor in the Department of Electrical and Computer Engineering at Lehigh University. Her research focuses on leveraging resistive memories to build energy-efficient processors, memory systems, and accelerators. Guo has a PhD in electrical and computer engineering from the University of Rochester, where she completed the work for this article. Contact her at xig515@lehigh.edu.']}}, {'name': 'Yuxin Bai', 'affiliation': 'University of Rochester', 'bio': {'p': ['Yuxin Bai is a PhD student in the Department of Electrical and Computer Engineering at the University of Rochester. Her research focuses on energy-efficient micro-architectures, including MOS current-mode computing and machine-learning-based power management techniques. Bai has an MS in electrical and computer engineering from the University of Rochester. Contact her at yuxin.bai@rochester.edu.']}}, {'name': 'Ravi Patel', 'affiliation': 'University of Rochester', 'bio': {'p': ['Ravi Patel is a PhD student in the Department of Electrical and Computer Engineering at the University of Rochester. His research interests include memristor, STT-MRAM, and high-performance memories. Patel has an MS in electrical and computer engineering from the University of Rochester. Contact him at rapatel@ece.rochester.edu.']}}, {'name': 'Engin Ipek', 'affiliation': 'University of Rochester', 'bio': {'p': ['Engin Ipek is an associate professor in the Department of Electrical and Computer Engineering and the Department of Computer Science at the University of Rochester. His research interests include energy-efficient architectures, high-performance memory systems, and the application of emerging memory technologies to computer systems. Ipek has a PhD in electrical engineering from Cornell University. Contact him at ipek@cs.rochester.edu.']}}, {'name': 'Eby G. Friedman', 'affiliation': 'University of Rochester', 'bio': {'p': ['Eby G. Friedman is a distinguished professor in the Department of Electrical and Computer Engineering, and the director of the High Performance VLSI/IC Design and Analysis Laboratory, at the University of Rochester. He is also a visiting professor at the Technion-Israel Institute of Technology. His research interests include high-performance synchronous digital and mixed-signal microelectronic design and analysis with application to high-speed portable processors and low-power wireless communications. Friedman has a PhD in electrical engineering from the University of California, Irvine. He is a Senior Fulbright Fellow and an IEEE Fellow. Contact him at friedman@ece.rochester.edu.']}} %*Resistive Ternary Content Addressable Memory Systems for Data-Intensive Computing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7274248 %f/micro/fhjxholmbsv9kqlna8ptnexbgcaz7gi2.pdf %mbf6fba424c8c9e1b054585e2b6697a76 %cmicro %@[{'name': 'Siyang Wang', 'affiliation': 'Duke University', 'bio': {'p': ['Siyang Wang is a PhD candidate in the Department of Electrical and Computer Engineering at Duke University. His research interests include molecular-scale computing and probabilistic computing. Wang has an MS in electrical and computer engineering from Duke University. He is a student member of IEEE. Contact him at siyang.wang@duke.edu.']}}, {'name': 'Alvin R. Lebeck', 'affiliation': 'Duke University', 'bio': {'p': ['Alvin R. Lebeck is a professor in the Departments of Computer Science and Electrical and Computer Engineering at Duke University. His interests include architectures for emerging nanotechnologies, multicore processors, memory systems, and energy-efficient computing. Lebeck has a PhD in computer science from the University of Wisconsin-Madison. He is a senior member of IEEE and a member of the ACM. Contact him at alvy@cs.duke.edu.']}}, {'name': 'Chris Dwyer', 'affiliation': 'Duke University', 'bio': {'p': ['Chris Dwyer is an associate professor in the Departments of Computer Science and Electrical and Computer Engineering at Duke University. His research interests include DNA self-assembly and applications that expand the computational domain with a focus on device-to-systems design, evaluation, and synthesis. Dwyer has a PhD in computer science from the University of North Carolina at Chapel Hill. He is a senior member of IEEE and a member of the ACM. Contact him at c.dwyer @duke.edu.']}} %*Nanoscale Resonance Energy Transfer-Based Devices for Probabilistic Computing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7310943 %f/micro/mkw80qsgdipuf1hl6zexy7flnoqyt3xr.pdf %m3196a8ffb359012fd9f311f74bb6e662 %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'Harvard Business School'} %*Twenty Years of the Commercial Internet, Part 2 %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7310927 %f/micro/mri9fihjcv2gqwslukaxyng0taokted5.pdf %mec84f06d960e09758a484ef4e479bdad %cmicro %@[{'name': 'Lieven Eeckhout', 'affiliation': 'Ghent University', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/7367971/7368001/7368001-photo-1-small.gif', 'p': ['Lieven Eeckhout is a professor in the Department of Electronics and Information Systems at Ghent University. Contact him at lieven.eeckhout@ugent.be.']}} %*Performance Evaluation and Its Impact on Design %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7368001 %f/micro/8ncbkpa1ifwpzef09gnriwv5ubdyjgoa.pdf %meb498565aeb40f73b18de970fb8352e6 %cmicro %@[{'name': 'Tony Nowatzki', 'affiliation': 'University of Wisconsin-Madison', 'bio': {'p': ['Tony Nowatzki is a PhD student in the Department of Computer Sciences at the University of Wisconsin-Madison and a member of the Vertical Research Group. His research interests include architecture and compiler codesign and mathematical modeling. Nowatzki has an MS in computer science from the University of Wisconsin-Madison. He is a student member of IEEE. Contact him at tjn@cs.wisc.edu.']}}, {'name': 'Jaikrishnan Menon', 'affiliation': 'University of Wisconsin-Madison', 'bio': {'p': ['Jaikrishnan Menon is a software engineer at Intel. He has an MS in computer science from the University of Wisconsin-Madison, where he completed the work for this article. Contact him at menon@cs.wisc.edu.']}}, {'name': 'Chen-Han Ho', 'affiliation': 'University of Wisconsin-Madison', 'bio': {'p': ['Chen-Han Ho is a research engineer at Qualcomm. His research focuses on energy-efficient computer architecture, software-hardware codesign of accelerators, RTL design, and FPGA proto typing. Ho has a PhD in computer architecture from the University of Wisconsin-Madison, where he completed the work for this article. Contact him at ho9@wisc.edu.']}}, {'name': 'Karthikeyan Sankaralingam', 'affiliation': 'University of Wisconsin-Madison', 'bio': {'p': ['Karthikeyan Sankaralingam is an associate professor in the Department of Computer Sciences and the Department of Electrical and Computer Engineering at the University of Wisconsin-Madison, where he also leads the Vertical Research Group. His research interests include micro architecture, architecture, and very large-scale integration. Sankaralingam has a PhD in computer science from the University of Texas at Austin. He is a senior member of IEEE. Contact him at karu@cs.wisc.edu.']}} %*Architectural Simulators Considered Harmful %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7155440 %f/micro/9ixvkbuk67foewbxarqyldrgnmceytm0.pdf %m62d80cf6287b1fd7d45c66f1a05f76f4 %cmicro %@[{'name': 'Toshitsugu Sakamoto', 'affiliation': 'Low-power Electronics Association and Project', 'bio': {'p': ["Toshitsugu Sakamoto is a principal researcher at NEC's Green Platform Research Laboratories. His research interests include nonvolatile memory, programmable logic devices, and novel nanodevices. Sakamoto has a PhD in electrical engineering from Osaka University. He completed the research for this article while working for the Low-power Electronics Association and Project. Contact him at t-sakamoto@dp.jp.nec.com."]}}, {'name': 'Yukihide Tsuji', 'affiliation': 'Low-power Electronics Association and Project', 'bio': {'p': ["Yukihide Tsuji is an assistant manager at NEC's Green Platform Research Laboratories. His research interests include design of devices, circuits using nonvolatile memory, and micro-electro-mechanical systems. Tsuji has a PhD in physics from the University of Tokyo. He completed the research for this article while working for the Low-power Electronics Association and Project. Contact him at y-tsuji@az.jp.nec.com."]}}, {'name': 'Munehiro Tada', 'affiliation': 'Low-power Electronics Association and Project', 'bio': {'p': ["Munehiro Tada is a principal researcher at NEC's Green Platform Research Laboratories. His research interests include low-power devices, nonvolatile memory, interconnects, and energy-efficient systems. Tada has a PhD in material science from Keio University. He completed the research for this article while working for the Low-power Electronics Association and Project. Contact him at m-tada@bl.jp.nec.com."]}}, {'name': 'Hideki Makiyama', 'affiliation': 'Low-power Electronics Association and Project', 'bio': {'p': ['Hideki Makiyama is an engineer at Renesas Electronics. His research interests include low-power devices, SOTB fabrication process, and low-voltage operation logic CMOS. Makiyama has an MS in material engineering from Kyushu University. He completed the research for this article while working for the Low-power Electronics Association and Project. Contact him at hideki.makiyama.wx@renesas.com.']}}, {'name': 'Takumi Hasegawa', 'affiliation': 'Low-power Electronics Association and Project', 'bio': {'p': ['Takumi Hasegawa is an engineer at Renesas Electronics. His research interests include low-power devices, device analysis, and yield management. Hasegawa has an MS in electronics from the University of Hyogo. He completed the research for this article while working for the Low-power Electronics Association and Project. Contact him at takumi.hasegawa.wr@renesas.com.']}}, {'name': 'Yoshiki Yamamoto', 'affiliation': 'Low-power Electronics Association and Project', 'bio': {'p': ['Yoshiki Yamamoto is an engineer at Renesas Electronics. His research interests include low-power devices, high-k/metal gate, FDSOI, and ferroelectric devices. Yamamoto has an MS in material sciences from the University of Tokyo. He completed the research for this article while working for the Low-power Electronics Association and Project. Contact him at yoshiki.yamamoto.pc@renvuoneesas.com.']}}, {'name': 'Shinobu Okanishi', 'affiliation': 'Low-power Electronics Association and Project', 'bio': {'p': ['Shinobu Okanishi is an engineer at Renesas Electronics. His research interests include low-power devices and yield analysis. Okanishi has an MS in material engineering from Osaka Industrial University. He completed the research for this article while working for the Low-power Electronics Association and Project. Contact him at shinobu.okanishi.pv@renesas.com.']}}, {'name': 'Keiichi Maekawa', 'affiliation': 'Low-power Electronics Association and Project', 'bio': {'p': ['Keiichi Maekawa is a researcher at Renesas Electronics. His research interests include device analysis and evaluation of low-power devices and nonvolatile memory. Maekawa made a special study of material science from Keio University. He completed the research for this article while working for the Low-power Electronics Association and Project. Contact him at keiichi.maekawa.fn@renesas.com.']}}, {'name': 'Naoki Banno', 'affiliation': 'Low-power Electronics Association and Project', 'bio': {'p': ["Naoki Banno is an assistant manager at NEC's Green Platform Research Laboratories. His research interests include device integration and processes, low-power resistive devices, and nonvolatile field-program-mable logic. Banno has a PhD in material science from the University of Tokyo. He completed the research for this article while working for the Low-power Electronics Association and Project. Contact him at banno@bu.jp.nec.com."]}}, {'name': 'Makoto Miyamura', 'affiliation': 'Low-power Electronics Association and Project', 'bio': {'p': ["Makoto Miyamura is an assistant manager at NEC's Green Platform Research Laboratories. His research interests include SRAM variability, nonvolatile memory, and energy-efficient circuit design. Miyamura has an ME in electrical engineering from the University of Tokyo. He completed the research for this article while working for the Low-power Electronics Association and Project. Contact him at m-miyamura@aj.jp.nec.com."]}}, {'name': 'Koichiro Okamoto', 'affiliation': 'Low-power Electronics Association and Project', 'bio': {'p': ["Koichiro Okamoto is an assistant manager at NEC's Green Platform Research Laboratories. His research interests include nonvolatile memory and integration technology. Okamoto has a PhD in electrical engineering from the University of Tokyo. He completed the research for this article while working for the Low-power Electronics Association and Project. Contact him at k-okamoto@fb.jp.nec.com."]}}, {'name': 'Noriyuki Iguchi', 'affiliation': 'Low-power Electronics Association and Project', 'bio': {'p': ["Noriyuki Iguch is an engineer at NEC's Green Platform Research Laboratories. His research interests include nonvolatile memory and integration technology. Iguchi completed the research for this article while working for the Low-power Electronics Association and Project. Contact him at iguchi@aj.jp.nec.com."]}}, {'name': 'Hidekazu Oda', 'affiliation': 'Low-power Electronics Association and Project', 'bio': {'p': ['Hidekazu Oda completed the research for this article while working for the Low-power Electronics Association and Project. His research interests include low-power devices and SOTB fabrication process. Contact him at hidekazu.oda.yf@renesas.com.']}}, {'name': 'Shiro Kamohara', 'affiliation': 'Low-power Electronics Association and Project', 'bio': {'p': ['Shiro Kamohara is a chief professional at Renesas Electronics. His research interests include low-power devices and the yield ramp-up. Kamohara has a PhD from Tokyo Metropolitan University. He completed the research for this article while working for the Low-power Electronics Association and Project. Contact him at shiro.kamohara.uh@renesas.com.']}}, {'name': 'Yasushi Yamagata', 'affiliation': 'Low-power Electronics Association and Project', 'bio': {'p': ['Yasushi Yamagata is a chief professional at Renesas Electronics. His research interests include memory devices and low-power CMOS devices. Yamagata has a BS in applied physics from the University of Tokyo. He completed the research for this article while working for the Low-power Electronics Association and Project. Contact him at yasushi.yamagata.uh@renesas.com.']}}, {'name': 'Nobuyuki Sugii', 'affiliation': 'Low-power Electronics Association and Project', 'bio': {'p': ['Nobuyuki Sugii is a senior research scientist at the Research and Development Group at Hitachi. His research interests include low-power CMOS devices, advanced electronic devices, material technology, and sensing electronics. Sugli has a PhD in applied chemistry from the University of Tokyo. He completed the research for this article while working for the Low-power Electronics Association and Project. Contact him at nobuyuki.sugii.df@hitachi.com.']}}, {'name': 'Hiromitsu Hada', 'affiliation': 'Low-power Electronics Association and Project', 'bio': {'p': ["Hiromitsu Hada is a senior principal researcher at NEC's Green Platform Research Laboratories. His research interests include low-power devices, nonvolatile memory (FeRAM, MRAM), and nonvolatile field-programmable logic. Hada has an ME in electrical engineering from Mie University. He completed the research for this article while working for the Low-power Electronics Association and Project. Contact him at h-hada@bp.jp.nec.com."]}}, {'name': 'Yasuhiro Ogasahara', 'affiliation': 'National Institute of Advanced Science and Technology', 'bio': {'p': ['Yasuhiro Ogasahara is a researcher at the National Institute of Advanced Science and Technology. His research interests include process variability, ultra-low voltage circuits, power integrity of LSI, and physically uncloneable function. Ogasahara has a PhD in information systems engineering of Osaka University. Contact him at ys.ogasahara@aist.go.jp.']}} %*A Silicon-on-Thin-Buried-Oxide CMOS Microcontroller with Embedded Atom-Switch ROM %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7368039 %f/micro/hatjnf2gkixza46p8ocyeubjrzqq5vgt.pdf %ma4ececeffd905a36d02ab06e32fa93db %cmicro %@[{'name': 'Amir Yazdanbakhsh', 'affiliation': 'Georgia Institute of Technology', 'bio': {'p': ['Arnir Yazdanbakhsh is a PhD student in the School of Computer Science at the Georgia Institute of Technology and a research assistant in the Alternative Computing Technologies (ACT) Lab. His research interests include computer architecture, approximate general-purpose computing, mixed-signal accelerator design, machine learning, and programming languages for hardware design. Yazdanbakhsh has an MS in computer engineering from the University of Wisconsin-Madison and an MS in electrical and computer engineering from the University of Tehran. He is a student member of IEEE. Contact him at a.yazdanbakhsh@gatech.edu.']}}, {'name': 'Raghuraman Balasubramanian', 'affiliation': 'University of Wisconsin-Madison', 'bio': {'p': ['Raghuraman Balasubramanian is a digital design engineer at Google. His research interests include microprocessor architecture and circuit design. Balasubramanian has an MS in computer science from the University of Wisconsin-Madison, where he completed the work for this article. Contact him at raghuraman.b@gmail.com.']}}, {'name': 'Tony Nowatzki', 'affiliation': 'University of Wisconsin-Madison', 'bio': {'p': ['Tony Nowatzki is a PhD student in the Department of Computer Sciences at the University of Wisconsin-Madison and a member of the Vertical Research Group. His research interests include architecture and compiler codesign and mathematical modeling. Nowatzki has an MS in computer science from the University of Wisconsin-Madison. He is a student member of IEEE. Contact him at tjn@cs.wisc.edu.']}}, {'name': 'Karthikeyan Sankaralingam', 'affiliation': 'University of Wisconsin-Madison', 'bio': {'p': ['Karthikeyan Sankaralingam is an associate professor in the Department of Computer Sciences and the Department of Electrical and Computer Engineering at the University of Wisconsin-Madison, where he also leads the Vertical Research Group. His research interests include micro architecture, architecture, and very large-scale integration. Sankaralingam has a PhD in computer science from the University of Texas at Austin. He is a senior member of IEEE. Contact him at karu@cs.wisc.edu.']}} %*Comprehensive Circuit Failure Prediction for Logic and SRAM Using Virtual Aging %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7367972 %f/micro/qfrecukqzgb73ep8yoljmwasbrk6tuix.pdf %m804971ebd381a6bbc2bccb3c9e410ca5 %cmicro %@[{'name': 'Giorgos Passas', 'bio': {'p': ['Giorgos Passas is interested in interconnection-network implementation and performance evaluation, particularly on chip. He wrote a part of this article as a post-doctorate researcher at the Barcelona Supercomputing Center. Passas has a PhD in computer science from the University of Crete. Contact him at gpassas81@gmail.com.']}}, {'name': 'Manolis Katevenis', 'affiliation': 'Foundation for Research &,amp, Technology', 'bio': {'p': ['Manolis Katevenis works at the Foundation for Research & Technology and the Computer Science Department at the University of Crete. His research interests include interconnection networks, interprocessor communication, packet switch architectures, and parallel and cluster computing. Katevenis has a PhD from the University of California, Berkeley. Contact him at kateveni@ics.forth.gr.']}}, {'name': 'Dionisios Pnevmatikatos', 'affiliation': 'Foundation for Research &,amp, Technology', 'bio': {'p': ['Dionisios Pnevmatikatos is a research associate at the Foundation for Research & Technology and a professor in the Department of Electrical and Computer Engineering at the Technical University of Crete. His research interests include the design and implementation of high-performance and cost-effective systems, reliable system design, and reconfigurable computing. Pnevmatikatos has a PhD in computer science from the University of Wisconsin-Ma-dison. He is a member of IEEE. Contact him at pnevmati@ics.forth.gr.']}} %*The Combined Input-Output Queued Crossbar Architecture for High-Radix On-Chip Switches %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6840829 %f/micro/tviqhf2atnyse4xpjn7hpdrwc9s6oyrm.pdf %m24dbc0873a27033f237fc3c12717126f %cmicro %@[{'name': 'Vinod Pangracious', 'affiliation': 'University of Pierre and Marie Curie', 'bio': {'p': ['Vinod Pangracious is an assistant professor in the Electrical and Computer Engineering Department at the American University in Dubai. His research interests include nanoelectronic devices, 3D integration, reconfigurable architectures, VLSI, systems on chip, and embedded system design. Pangracious has a PhD in electrical engineering from the University of Pierre and Marie Curie, where he completed the work for this article. He is a member of IEEE. Contact him at vinod.pangracious@lip6.fr.']}}, {'name': 'Zied Marrakchi', 'affiliation': 'Flexras Technologies', 'bio': {'p': ['Zied Marrakchi is the chief technology officer at Flexras Technologies. His research interests include FPGA CDA tools and system integration. Marrakchi has a PhD in electrical engineering from the University of Pierre and Marie Curie. Contact him at zied.marrakchi@flexras.com.']}}, {'name': 'Habib Mehrez', 'affiliation': 'University of Pierre and Marie Curie', 'bio': {'p': ['Habib Mehrez is a professor in the System on Chip Department at the University of Pierre and Marie Curie. His research interests include RISC architectures and DSP processors, digital signal processing, and reconfigurable FPGA architectures. Mehrez has a PhD in computer science from the University of Pierre and Marie Curie. Contact him at habib.mehrez@lip6.fr.']}} %*Design and Optimization of a Horizontally Partitioned, High-Speed, 3D Tree-Based FPGA %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6866846 %f/micro/3h9cimevy4b8nwrtogb0zkm57jsscofp.pdf %md85e275e1bb67552749d374a0595b8e8 %cmicro %@[{'name': 'Shinpei Kato', 'affiliation': 'Nagoya University', 'bio': {'p': ['Shinpei Kato is an associate professor in the Graduate School of Information Science at Nagoya University. His research interests include operating systems, cyber-physical systems, and parallel and distributed systems. Kato has a PhD in engineering from Keio University. Contact him at shinpei@is.nagoya-u.ac.jp.']}}, {'name': 'Eijiro Takeuchi', 'affiliation': 'Nagoya University', 'bio': {'p': ['Eijiro Takeuchi is a designated associate professor in the Institute of Innovation for Future Society at Nagoya University. His research interests include autonomous mobile robots and intelligent vehicles. Takeuchi has a PhD in engineering from the University of Tsukuba. Contact him at takeuchi@coi.nagoya-u.ac.jp.']}}, {'name': 'Yoshio Ishiguro', 'affiliation': 'Nagoya University', 'bio': {'p': ['Yoshio Ishiguro is an assistant professor in the Institute of Innovation for Future Society at Nagoya University. His research interests include mixed reality, augmented reality, and human-computer integration. Ishiguro has a PhD in information science and studies from the University of Tokyo. Contact him at ishiy@acm.org.']}}, {'name': 'Yoshiki Ninomiya', 'affiliation': 'Nagoya University', 'bio': {'p': ['Yoshiki Ninomiya is a designated professor in the Institute of Innovation for Future Society at Nagoya University. His research interests include machine intelligence and image processing, and its applications. Ninomiya has a PhD in engineering from Nagoya University. Contact him at ninomiya@coi.nagoya-u.ac.jp.']}}, {'name': 'Kazuya Takeda', 'affiliation': 'Nagoya University', 'bio': {'p': ['Kazuya Takeda is a professor in the School of Information Science at Nagoya University. His research interests include media signal processing and its applications. Takeda has a PhD in engineering from Nagoya University. Contact him at kazuya.takeda@nagoya-u.jp.']}}, {'name': 'Tsuyoshi Hamada', 'affiliation': 'Nagasaki University', 'bio': {'p': ['Tsuyoshi Hamada is an associate professor in the Nagasaki Advanced Computing Center at Nagasaki U niversi ty. His research interests include massively parallel architectures based on FPCAs and GPUs. Hamada has a PhD in engineering from the University of Tokyo. Contact him at hamada@nacc.nagasaki-u.ac.jp.']}} %*An Open Approach to Autonomous Vehicles %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7368032 %f/micro/pstyuaoyzrqmakbdste2lxmqi7j5xwrg.pdf %m8067f8664f9593671421220c62844b22 %cmicro %@[{'name': 'Richard Mateosian', 'bio': {'p': ['Richard Mateosian is a freelance technical writer in the San Francisco Bay Area. Contact him at xrmxrm@gmail.com.']}} %*New Tools %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7368005 %f/micro/e1ycgqypz8xhwogdsev4i2rlrmknsfzo.pdf %mbf1985e033c13e9f4ae795ceb701c08b %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'Harvard Business School', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/7367971/7367987/7367987-photo-1-small.gif', 'p': ['Shane Greenstein is a professor at the Harvard Business School.']}} %*Insiders, Outsiders, and an Existentialist %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7367987 %f/micro/dxsifongpjgkjc6emxhlzokuuhpq3riz.pdf %mc47d796ab557e95d7b488394cd49125f %cmicro %@[{'name': 'Erik R. Altman', 'affiliation': 'Thomas J. Watson Research Center', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6774322/6774352/6774352-photo-1-small.gif', 'p': ['Erik R. Altman is the manager of the Dynamic Optimization Group at the Thomas J. Watson Research Center. Contact him at ealtman@us.ibm.com.']}} %*Reconfigurable Computing, 3D Integration, and Recognizing Leaders in our Field %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6774352 %f/micro/uhyd04cmrhd9kfpzbnetuny2lvqbigaz.pdf %mb883d00dbd7793e966ef021ea21d8625 %cmicro %@[{'name': 'Walid A. Najjar', 'affiliation': 'University of California, Riverside', 'bio': {'p': ['Walid A. Najjar is a professor in the Department of Computer Science and Engineering at the University of California, Riverside. His research interests include computer architectures and compilers for parallel and high-performance computing, embedded systems, FPGA-based code acceleration, and reconfigurable computing. Najjar has a PhD in computer engineering from the University of Southern California. He is a fellow of IEEE and the AAAS.']}}, {'name': 'Paolo Ienne', 'affiliation': 'É,cole Polytechnique Fé,dé,rale de Lausanne', 'bio': {'p': ['Paolo Ienne is a professor in the School of Computer and Communication Sciences at Ecole Polytechnique Fédérale de Lausanne. His research interests include computer and processor architecture, electronic design automation, computer arithmetic, FPGAs and reconfigurable computing, and multiprocessor systems-on-chip. Ienne has a PhD in computer science from Ecole Polytechnique Fédérale de Lausanne. He is a senior member of IEEE.', 'Direct questions and comments about the articles in this special section to Paolo Ienne at paolo.ienne@epfl.ch or to Walid Najjar at najjar@cs.ucr.edu.']}} %*Reconfigurable Computing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6774339 %f/micro/6uvxgjkaxk1d5msdi0ne9qw7evbrtybf.pdf %m9f7681c50f845c8094407245f50e3e73 %cmicro %@[{'name': 'Gordon Brebner', 'affiliation': 'Xilinx Labs., San Jose, CA, USA', 'bio': {'p': ['Gordon Brebner is a distinguished engineer at Xilinx Labs. His research interests include reconfigurable computing, domain-specific languages, and high-performance networking. Brebner has a PhD in computer science from the University of Edinburgh.']}}, {'name': ' Weirong Jiang', 'affiliation': 'Xilinx Labs., San Jose, CA, USA', 'bio': {'p': ['Weirong Jiang is a staff research engineer at Xilinx Labs. His research interests include parallel algorithm and architecture design for high-performance, low-power networking. Jiang has a PhD in computer engineering from the University of Southern California. He is a member of the ACM and IEEE.']}} %*High-Speed Packet Processing using Reconfigurable Computing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6774354 %f/micro/ywvaghxzmg0wrnibdlxeypk8v52qij4t.pdf %m43e50ec5460da220210ebbd20b50be56 %cmicro %@[{'name': 'Bharat Sukhwani', 'affiliation': 'IBM Res., Yorktown Heights, NY, USA', 'bio': {'p': ['Bharat Sukhwani is a research staff member at the IBM T.J. Watson Research Center. His research interests include computer architecture, parallel computing, application-specific, high-performance computing systems, and computing using reconfigurable and graphics processors. Sukhwani has a PhD in electrical engineering from Boston University. He is a member of IEEE.']}}, {'name': ' Hong Min', 'affiliation': 'IBM Res., Yorktown Heights, NY, USA', 'bio': {'p': ['Hong Min is a senior technical staff member at the IBM T.J. Watson Research Center. Her research interests include database systems and acceleration technologies for data processing. Min has a PhD in mechanical engineering from Drexel University.']}}, {'name': 'Mathew Thoennes', 'affiliation': 'IBM Res., Yorktown Heights, NY, USA', 'bio': {'p': ["Mathew Thoennes is a senior engineer at the IBM T.J. Watson Research Center. His research interests include software and hardware for Series z systems. Thoennes has an MS in computer science from the University of Massachusetts. He's a member of the ACM and a senior member of IEEE."]}}, {'name': 'Parijat Dube', 'affiliation': 'IBM Res., Yorktown Heights, NY, USA', 'bio': {'p': ['Parijat Dube is a senior engineer at the IBM T.J. Watson Research Center. His research interests include performance modeling, analysis, and optimization of systems. Dube has a PhD in computer science from INRIA.']}}, {'name': 'Bernard Brezzo', 'affiliation': 'IBM Res., Yorktown Heights, NY, USA', 'bio': {'p': ['Bernard Brezzo is a senior engineer at the IBM T.J. Watson Research Center. His research interests include high-performance computing, FPGA emulation, and Synapse. Brezzo has a Diploma in electronics engineering from Conservatoire National des Arts et Metiers, Paris.']}}, {'name': 'Sameh Asaad', 'affiliation': 'IBM Res., Yorktown Heights, NY, USA', 'bio': {'p': ['Sameh Asaad is a research staff member at the IBM T.J. Watson Research Center, where he manages the Digital Design Group in the Communication and Computation Subsystems Department. His research interests include domain-optimized architectures and systems, reconfigurable computing, and FPGA-based application acceleration. Asaad has a PhD in electrical engineering from Vanderbilt University.']}}, {'name': 'Donna Eng Dillenberger', 'affiliation': 'IBM Res., Yorktown Heights, NY, USA', 'bio': {'p': ["Donna Eng Dillenberger leads IBM's global research on enterprise systems at the IBM T.J. Watson Research Center. She's also IBM's Chief Technology Officer of IT Optimization, an IBM Distinguished Engineer and Master Inventor, and an adjunct professor at Columbia University. Her research interests include hybrid architectures, Cloud, and IT optimization. Dillen-berger has an MS in computer science from Columbia University."]}} %*Database Analytics: A Reconfigurable-Computing Approach %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6636300 %f/micro/9o8trevugfa3xzj1n5t0mmbhzrypqgcw.pdf %me4200a3cffc2d6291abf9d237b299030 %cmicro %@[{'name': ' Haohuan Fu', 'affiliation': 'Tsinghua Univ., Beijing, China', 'bio': {'p': ["Haohuan Fu is an associate professor in the Ministry of Education Key Laboratory for Earth System Modeling, and the Center for Earth System Science, at Tsinghua University. His research interests include high-performance computing in earth and environmental sciences, computer architectures, performance optimizations, and programming tools in parallel computing. Fu has a PhD in computing from Imperial College London. He's a member of IEEE."]}}, {'name': ' Lin Gan', 'affiliation': 'Tsinghua Univ., Beijing, China', 'bio': {'p': ["Lin Gan is a PhD candidate in the Department of Computer Science and Technology at Tsinghua University. His research interests include FPGA-based solutions to global atmospheric modeling and exploration geophysics, focusing on algorithmic development and performance optimizations based on hybrid platforms such as CPUs, FPGAs, and GPUs. Gan has a BE in information and communication engineering from the Beijing University of Posts and Telecommunications. He's a student member of IEEE."]}}, {'name': 'Robert G. Clapp', 'affiliation': 'Stanford Univ., Stanford, CA, USA', 'bio': {'p': ["Robert G. Clapp is a senior research engineer in geophysics and the technical director of the Center for Earth and Environmental Science at Stanford University, where he manages the School of Earth Science's Algorithm and Architecture Initiative. His research interests include seismic imaging, tomography, highperformance computing, inversion, and optimization. Clapp has a PhD in geophysics from Stanford University."]}}, {'name': ' Huabin Ruan', 'affiliation': 'Tsinghua Univ., Beijing, China', 'bio': {'p': ["Huabin Ruan is a postdoctoral research fellow in the Department of Computer Science and Technology at Tsinghua University. His research interests include algorithmic acceleration on reconfigurable architectures such as FPGAs, distributed service, and storage. Ruan has a PhD in computer science from Tsinghua University. He's a student member of IEEE."]}}, {'name': 'Oliver Pell', 'bio': {'p': ["Oliver Pell is the vice president of engineering at Maxeler Technologies. His research interests include reverse time migration acceleration, Lattice-Boltzmann simulations, and credit derivatives pricing. Pell has an MSc in advanced computing from Imperial College London. He's a member of IEEE."]}}, {'name': 'Oskar Mencer', 'bio': {'p': ["Oskar Mencer is the CEO and founder of Maxeler Technologies, a senior lecturer in the Computing Department of Imperial College London, and a consulting professor in the Geophysics Department at Stanford University. His research interests include acceleration of computations and number representation. Mencer has a PhD in electrical engineering from Stanford University. He's a member of IEEE and the Society of Exploration Geophysicists."]}}, {'name': 'Michael Flynn', 'affiliation': 'Stanford Univ., Stanford, CA, USA', 'bio': {'p': ["Michael Flynn is the chairman of Maxeler Technologies and professor emeritus in the Electrical Engineering Department at Stanford University. His research interests include computer architecture and computer arithmetic. Flynn has a PhD in electrical engineering from Purdue University. He's a fellow of IEEE and the ACM."]}}, {'name': ' Xiaomeng Huang', 'affiliation': 'Tsinghua Univ., Beijing, China', 'bio': {'p': ["Xiaomeng Huang is an associate professor in the Center for Earth System Science at Tsinghua University. His research focuses on the algorithmic optimization and performance acceleration of the ocean models based on heterogeneous CPU, GPU, and MIC platforms. Huang has a PhD in computer science from Tsinghua University. He's a member of IEEE."]}}, {'name': ' Guangwen Yang', 'affiliation': 'Tsinghua Univ., Beijing, China', 'bio': {'p': ["Guangwen Yang is a professor in the Department of Computer Science and Technology and the director of the Institute of High Performance Computing at Tsinghua University. His research interests include parallel algorithms, cloud computing, and the earth system model. Yang has a PhD in computer science from Tsinghua University. He's a member of IEEE."]}} %*Scaling Reverse Time Migration Performance through Reconfigurable Dataflow Engines %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6636317 %f/micro/nx0apjhzefo3cdzkqrrksqusbdgo6bav.pdf %m507ba1ab2d45df742ec43e5cbb804380 %cmicro %@[{'name': 'James Coole', 'affiliation': 'Univ. of Florida, Gainesville, FL, USA', 'bio': {'p': ['James Coole is a PhD candidate at the University of Florida. His research interests include computer architecture and design automation. Coole has a MS in electrical engineering from the University of Florida.']}}, {'name': 'Greg Stitt', 'affiliation': 'Univ. of Florida, Gainesville, FL, USA', 'bio': {'p': ['Greg Stitt is an associate professor in the Electrical and Computer Engineering Department at the University of Florida. His research interests include reconfigurable computing and embedded systems. Stitt has a PhD in computer science from the University of California, Riverside.']}} %*Fast, Flexible High-Level Synthesis from OpenCL using Reconfiguration Contexts %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6636299 %f/micro/ygs0thbpxuazoy1aescmqrmvzdfn5qko.pdf %m34de3b66e1818ea168dc8c9a338ffa61 %cmicro %@[{'name': 'David Andrews', 'affiliation': 'CSCE Dept., Univ. of Arkansas, Fayetteville, AR, USA', 'bio': {'p': ['David Andrews is the Mullins Endowed Chair of Computer Engineering in the Computer Science and Computer Engineering Department at the University of Arkansas. His research interests include parallel and distributed real-time systems, reconfigurable computing, and operating systems. Andrews has a PhD in computer science from Syracuse University. He is a senior member of IEEE.']}} %*Operating Systems Research for Reconfigurable Computing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6728929 %f/micro/ltscsrhkhnifvfbdonlpbwywdpmavzam.pdf %m81beb96efbc636a706d1ac70a62fadfc %cmicro %@[{'name': 'Andreas Agne', 'bio': {'p': ['Andreas Agne is a PhD student in the Computer Engineering Group at the University of Paderborn. His research interests include reconfigurable computing and operating systems for heterogeneous multicore architectures. Agne has a Diploma in computer science from the University of Paderborn.']}}, {'name': 'Markus Happe', 'bio': {'p': ['Markus Happe is a senior researcher at the Communication Systems Group at ETH Zürich. His research interests include networking architectures, self-adaptation strategies, and reconfigurable systems. Happe has a PhD in computer science from the University of Paderborn.']}}, {'name': 'Ariane Keller', 'bio': {'p': ['Ariane Keller is a PhD student in the Communication Systems Group at ETH Zürich. Her research interests include computer architectures for self-organizing networks. Keller has a Diploma in electrical engineering from ETH Zürich.']}}, {'name': 'Enno Lubbers', 'bio': {'p': ['Enno Lübbers is a senior researcher at the Intel Open Lab in Munich, which is part of Intel Labs Europe. His research interests include adaptive systems and heterogeneous architectures for high-performance, embedded, and safety-critical applications. Lübbers has a PhD in computer engineering from the University of Paderborn.']}}, {'name': 'Bernhard Plattner', 'bio': {'p': ['Bernhard Plattner is a full professor of computer engineering in the Department of Information Technology and Electrical Engineering at ETH Zürich, where he leads the Communication Systems Group. His research interests include self-organizing networks, mobile and opportunistic networking, and practical aspects of information security. Plattner has a PhD in computer engineering from ETH Zürich.']}}, {'name': 'Marco Platzner', 'bio': {'p': ['Marco Platzner is professor of computer engineering in the Department of Computer Science at the University of Paderborn. His research interests include reconfigurable computing, hardware-software codesign, and parallel architectures. Platzner has a PhD in telematics from Graz University of Technology.']}}, {'name': 'Christian Plessl', 'bio': {'p': ['Christian Plessl is assistant professor of custom computing in the Department of Computer Science at the University of Paderborn. His research interests include parallel and reconfigurable computer architectures, high-performance computing, and adaptive computing systems. Plessl has a PhD in computer engineering from ETH Zurich.']}} %*ReconOS: An Operating System Approach for Reconfigurable Computing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6636314 %f/micro/gphv2m9jpneq31vurswlttgiojn6fzkb.pdf %m1246868e6cbea53cb458b0495e29ce1b %cmicro %@[{'name': 'Nick Tredennick', 'bio': {'p': ['Nick Tredennick is a consultant. His research interests include industry trends, microprocessors, and FPGAs. Tredennick has a PhD in electrical engineering from the University of Texas at Austin. He is a life fellow of IEEE.']}}, {'name': 'Brion Shimamoto', 'bio': {'p': ["Brion Shimamoto is a small business owner. His research interests include micro-processors, computing systems, and design methods. Shimamoto has a bachelor's degree in mathematics from the University of California, Los Angeles. He is a member of the ACM.", 'Direct questions and comments about this article to Nick Tredennick, 1625 Sunset Ridge Road, Los Gatos, CA 95033, bozo@computer.org.']}} %*Prospects for Reconfigurable Systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6681868 %f/micro/yjlkw6iyazhfx927eed45pthuanubvcv.pdf %m18d6172a14176c035b984f494b48b892 %cmicro %@[{'name': 'Mohamed S. Abdelfattah', 'affiliation': 'Dept. of Electr. &, Comput. Eng., Univ. of Toronto, Toronto, ON, Canada', 'bio': {'p': ['Mohamed S. Abdelfattah is a PhD candidate in the Department of Electrical and Computer Engineering at the University of Toronto. His research interests include new communication architectures and CAD for high-performance FPGAs. Abdelfattah has an MSc in electrical and computer engineering from the University of Stuttgart.']}}, {'name': 'Vaughn Betz', 'affiliation': 'Dept. of Electr. &, Comput. Eng., Univ. of Toronto, Toronto, ON, Canada', 'bio': {'p': ['Vaughn Betz is an associate professor in the Department of Electrical and Computer Engineering at the University of Toronto. His research interests include FPGA architecture and CAD, and the use of reconfigurable hardware to accelerate computation. He has a PhD in Electrical and Computer Engineering from the University of Toronto.']}} %*The Case for Embedded Networks on Chip on Field-Programmable Gate Arrays %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6679041 %f/micro/y9egdtrx12ocls3sbgduiihhyoacmx5e.pdf %mdb49a128e56f3636392aaaedd6fcecee %cmicro %@[{'name': 'Steve Scott', 'affiliation': 'Google'} %*2013 Maurice Wilkes Award Given to Parthasarathy (Partha) Ranganathan %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6685806 %f/micro/v1y8ubr3ymi6xqoqdfjp9b2cw04uktkn.pdf %md9b69231fee698cab564f475116e5166 %cmicro %@[{'name': 'Margaret Martonosi', 'affiliation': 'Princeton University'} %*2013 International Symposium on Computer Architecture Influential Paper Award %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6681862 %f/micro/q5hjeo6l2dgbn9clbtui4maxfstvhoak.pdf %mf59b0f46e305f3f6114c172cd209543e %cmicro %@[{'name': 'Shane Greenstein', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6774322/6774356/6774356-photo-1-small.gif', 'p': ['Shane Greenstein is the Kellogg Chair in Information Technology at the Kellogg School of Management, Northwestern University. Contact him at greenstein@kellogg.northwestern.edu.']}} %*The Irony of Public Funding %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6774356 %f/micro/umbwgtqiv3auw6nbhlpnkor09faxvkqd.pdf %m308bf788b7bbbb3530f1bb239b9d6dca %cmicro %@[{'name': 'Per Hammarlund', 'affiliation': 'Intel', 'bio': {'p': ['Per Hammarlund is an Intel fellow. His research interests include performance modeling, microarchitecture, SMT, power-performance efficiency and modeling, integration, and SoC design. Hammarlund has a PhD in computer science from the Royal Institute of Technology (KTH), Stockholm.']}}, {'name': 'Alberto J. Martinez', 'affiliation': 'Intel', 'bio': {'p': ['Alberto J. Martinez is a senior principal engineer at Intel and the chief architect for the Embedded Subsystems and IP Group. His research focuses on embedded subsystems software and hardware and PC I/O architectures. Martinez has an MS in electrical engineering from Sacramento State University.']}}, {'name': 'Atiq A. Bajwa', 'affiliation': 'Intel', 'bio': {'p': ["Atiq A. Bajwa is the director of microprocessor architecture at Intel. He is respon- sible for the architectural definition and development of microprocessors for Intel's mobile, desktop, workstation, and server computing segments. Bajwa has an MS in electrical engineering from Yale University."]}}, {'name': 'David L. Hill', 'affiliation': 'Intel', 'bio': {'p': ['David L. Hill is a senior principal engineer at Intel. His research interests include modular high-performance caches, coherent interconnects, and system memory technologies. His team was responsible for the modular uncore architecture sections of the Haswell and Broadwell product families. Hill has a BS in electrical engineering from the University of Minnesota.']}}, {'name': 'Erik Hallnor', 'affiliation': 'Intel', 'bio': {'p': ['Erik Hallnor is a cache and coherent fabric architect, focusing on client and SoC products at Intel. He was the lead architect for the Haswell coherent fabric, consisting of the ring interconnect, LLC, and eDRAM cache integration. Hallnor has a PhD in computer science and engineering from the University of Michigan.']}}, {'name': 'Hong Jiang', 'affiliation': 'Intel', 'bio': {'p': ["Hong Jiang is an Intel Fellow, the chief media architect for the Platform Engineering Group, and the director of the Visual and Parallel Computing Group's Media Architecture Team at Intel. He leads the media architecture of processor graphics and its derivatives. Jiang has a PhD in electrical engineering from the University of Illinois at Urbana-Champaign."]}}, {'name': 'Martin Dixon', 'affiliation': 'Intel', 'bio': {'p': ["Martin Dixon is a principal engineer in the Intel Product Development Group, where he's working to develop and enhance the overall instruction set and SoC architecture. Dixon has a BS in electrical and computer engineering from Carnegie Mellon University."]}}, {'name': 'Michael Derr', 'affiliation': 'Intel', 'bio': {'p': ['Michael Derr is a principal engineer at Intel. His work focuses on power managing PC I/O architectures. Derr has an MS in electrical engineering from the Georgia Institute of Technology.']}}, {'name': 'Mikal Hunsaker', 'affiliation': 'Intel', 'bio': {'p': ['Mikal Hunsaker is a senior principal engineer at Intel. His research interests focus on chipset high-speed serial I/O design, including PCI Express, SATA, and USB3. Hunsaker has an MS in electrical engineering from Utah State University.']}}, {'name': 'Rajesh Kumar', 'affiliation': 'Intel', 'bio': {'p': ["Rajesh Kumar is a senior fellow, director of circuit and power technologies, and the lead interface to process technology at Intel. For Haswell, he guided the development of power delivery integration (FIVR), on-package I/O, and the novel process-technology needs. Kumar has a master's degree in electrical engineering from the California Institute of Technology."]}}, {'name': 'Randy B. Osborne', 'affiliation': 'Intel', 'bio': {'p': ['Randy B. Osborne is a principal engineer working to improve performance of memory hierarchies at Intel. His research interests include memory controllers, memory interconnects, memory devices, and large caches, including the introduction of eDRAM into Intel products. Osborne has a PhD in electrical engineering from the Massachusetts Institute of Technology.']}}, {'name': 'Ravi Rajwar', 'affiliation': 'Intel', 'bio': {'p': ['Ravi Rajwar is a principal engineer in the Intel Product Development Group, working on various aspects of SoC architecture and development. His research interests include the IA synchronization architecture. Rajwar has a PhD in computer science from the University of Wisconsin-Madison.']}}, {'name': 'Ronak Singhal', 'affiliation': 'Intel', 'bio': {'p': ['Ronak Singhal is a senior principal engineer at Intel. His research interests include server architecture development, ISA development, and performance analysis and modeling. Singhal has an MS in electrical and computer engineering from Carnegie Mellon University.']}}, {'name': "Reynold D'Sa", 'affiliation': 'Intel', 'bio': {'p': ["Reynold D'Sa is vice president of the Platform Engineering Group and general manager of the Devices Development Group at Intel. He leads the design engineering teams responsible for designing and developing SoC products for Intel's next-generation client and mobile platforms, including tablets and smartphones. D'Sa has an MS in electrical engineering from Cornell University."]}}, {'name': 'Robert Chappell', 'affiliation': 'Intel', 'bio': {'p': ['Robert Chappell is a CPU architect at Intel, where he works to define the performance, power, reliability, and ISA features of the CPU cores used in various products ranging from phones to servers. He was the lead architect for the Haswell memory execution cluster, the Haswell core in its later stages, and the Haswell follow-on core (Broadwell). Chappell has a PhD in computer science from the University of Michigan.']}}, {'name': 'Shiv Kaushik', 'affiliation': 'Intel', 'bio': {'p': ["Shiv Kaushik is a fellow at Intel, where he leads the Windows OS Division in Intel's Software and Services Group. His research interests include the design of platform hardware and firmware interfaces to operating systems and virtualization software for power management, scaling, performance, and reliability. Kaushik has a PhD in computer science and engineering from Ohio State University."]}}, {'name': 'Srinivas Chennupaty', 'affiliation': 'Intel', 'bio': {'p': ['Srinivas Chennupaty is a CPU and SoC architect at Intel. His research interests include the Intel microprocessor architecture and instruction set development. Chennupaty has an MS in computer engineering from the University of Texas at Austin.']}}, {'name': 'Stephan Jourdan', 'affiliation': 'Intel', 'bio': {'p': ['Stephan Jourdan is a senior principal engineer at Intel, where he leads the architecture engineering teams responsible for defining and developing SoCs for device products. He was the chief architect on HSW ULT. Jourdan has a PhD in computer science from the University of Toulouse.']}}, {'name': 'Steve Gunther', 'affiliation': 'Intel', 'bio': {'p': ["Steve Gunther is a senior principal engineer and a lead power architect for Intel, where he leads a team responsible for defining the power management architecture for Intel's microprocessor product line. His research interests include power analysis, power management, and power reduction. Gunther has a BS in electrical engineering from Oregon State University."]}}, {'name': 'Tom Piazza', 'affiliation': 'Intel', 'bio': {'p': ['Tom Piazza is a senior fellow and director of graphics architecture at Intel. His research interests include computer graphics. Piazza has a BS in electrical engineering from the Pratt Institute.']}}, {'name': 'Ted Burton', 'affiliation': 'Intel', 'bio': {'p': ['Ted Burton is a senior principal engineer working on advanced technologies in the Devices Development Group at Intel. His research interests include power delivery. Burton has a BS in physics from Brigham Young University.', 'Direct questions and comments about this article to Per Hammarlund, Intel, 2111 NE 25th Ave., Hillsboro, OR 97124, per. hammarlund@intel.com.']}} %*Haswell: The Fourth-Generation Intel Core Processor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6762795 %f/micro/oms6boqjxzqfsuwnvyv7it9kpa5ehieg.pdf %m488212de026f40c738fb5673ede61946 %cmicro %@[{'name': 'Dan Bouvier', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ['Dan Bouvier is a senior technical fellow and lead portfolio architect for client products at Advanced Micro Devices, where he leads the SoC definition of all tablet, note-book, and desktop APUs. His research interests include SoC architecture, memory and I/O systems, and microprocessor microarch-itecture. Bouvier has a BS in electrical engineering from Arizona State University.']}}, {'name': 'Brad Cohen', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ['Brad Cohen is a technical fellow and microprocessor architect at Advanced Micro Devices. He is an architect and the register-transfer-level (RTL) lead for microprocessor core development, including the Bobcat family of cores. Cohen has a BS in electrical engineering from the Georgia Institute of Technology.']}}, {'name': 'Walter Fry', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ["Walter Fry is a senior technical fellow, platform architect, and I/O technology strategist at Advanced Micro Devices, where he leads a team of architects and technologists. His research focuses on client platforms, from mobile tablets to high-performance desktops. Fry has a BS in electronics engineering technology from the University of Southern Colorado. He's a member of the Peripheral Component Interconnect Special Interest Group (PCI-SIG), USB Imple-menters' Forum (USB-IF), and the MIPI Alliance."]}}, {'name': 'Sreekanth Godey', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ['Sreekanth Godey is a principal member of the technical staff and a lead SoC architect at Advanced Micro Devices, where he focuses on low-power APUs. His research interests include low-power techniques, SoC security, and mobile wireless technology. Godey has an MS in electrical engineering from Jawaharlal Nehru Technological University.']}}, {'name': 'Michael Mantor', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ["Michael Mantor is a senior technical fellow at Advanced Micro Devices, where he's involved in the development of both GPU technology and heterogeneous systems. His research interests include continued performance and power improvements in the GPU and multithreaded program development to exploit full use of shared memory systems. Mantor has a BS in electrical engineering from San Diego State University. He's a member of IEEE and the ACM."]}} %*Kabini: An AMD Accelerated Processing Unit System on A Chip %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6756712 %f/micro/vhn2qjp8z07skud4wmmftjzfen5dbblo.pdf %m8b1009b519e8827b5baccb71263cc814 %cmicro %@[{'name': 'Lucian Codrescu', 'affiliation': 'Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA', 'bio': {'p': ['Lucian Codrescu is a senior director at Qualcomm, where he leads the Hexagon Architecture team. Codrescu has a PhD in computer engineering from the Georgia Institute of Technology.']}}, {'name': 'Willie Anderson', 'affiliation': 'Phys., Univ. of Texas at Austin, Austin, TX, USA', 'bio': {'p': ['Willie Anderson is a vice president at Qualcomm, where he runs the DSP engineering organization. Anderson has a BS in physics from the University of Texas at Austin.']}}, {'name': 'Suresh Venkumanhanti', 'affiliation': 'Electr. Eng., Univ. of Florida, Gainesville, FL, USA', 'bio': {'p': ['Suresh Venkumanhanti is a principal engineer at Qualcomm, where he is responsible for the DSP core microarchitecture. Venkumanhanti has an MS in electrical engineering from the University of Florida.']}}, {'name': ' Mao Zeng', 'affiliation': 'Electr. Eng., Univ. of Victoria, Victoria, BC, Canada', 'bio': {'p': ['Mao Zeng is a senior staff engineer at Qualcomm and a principal designer of the DSP instruction set architecture. Zeng has a PhD in electrical engineering from the University of Victoria.']}}, {'name': 'Erich Plondke', 'affiliation': 'Electr. Eng., Georgia Inst. of Technol., Atlanta, GA, USA', 'bio': {'p': ['Erich Plondke is a senior staff engineer at Qualcomm, where he leads the system architecture team. Plondke has an MS in electrical engineering from the Georgia Institute of Technology.']}}, {'name': 'Chris Koob', 'affiliation': 'Electr. Eng., Virginia Tech, Blacksburg, VA, USA', 'bio': {'p': ['Chris Koob is a principal engineer at Qualcomm, where he is responsible for the memory system microarchitecture. Koob has an MS in electrical engineering from Virginia Tech.']}}, {'name': 'Ajay Ingle', 'affiliation': 'Electr. Eng., Texas A&,M Univ., College Station, TX, USA', 'bio': {'p': ['Ajay Ingle is a principal engineer at Qualcomm, where he is responsible for DSP architecture support of modem applications. Ingle has an MS in electrical engineering from Texas A&M University.']}}, {'name': 'Charles Tabony', 'affiliation': 'Comput. Eng., Univ. of Texas, Arlington, TX, USA', 'bio': {'p': ['Charles Tabony is a senior engineer at Qualcomm, where he contributes to the instruction set design and performance verification. Tabony has a BS in computer engineering from the University of Texas.']}}, {'name': 'Rick Maule', 'affiliation': 'Electr. Eng., Univ. of Arkansas, Fayetteville, AR, USA', 'bio': {'p': ['Rick Maule is a senior director at Qualcomm, where he is responsible for DSP product management. Maule has an MS in electrical engineering from the University of Arkansas.']}} %*Hexagon DSP: An Architecture Optimized for Mobile Multimedia and Communications %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6762801 %f/micro/yjcltxvu3tzepsm4p8zhlmxadiuofngk.pdf %m51d1ef68c995a23fcc6c08ce8c55b53f %cmicro %@[{'name': 'John Sell', 'affiliation': 'Microsoft', 'bio': {'p': ['John Sell is a hardware architect at Microsoft, and chief architect of the Xbox One SoC. His research interests include computation architecture, memory systems, quality of service (QoS), and security. Sell has an MS in electrical engineering and computer science from the University of California at Berkeley.']}}, {'name': "Patrick O'Connor", 'affiliation': 'Microsoft', 'bio': {'p': ["Patrick O'Connor is a senior director of engineering at Microsoft, where he's responsible for hardware and software development of sensors and custom silicon. His research interests include specification and validation of hardware and algorithms for highly functional natural user interfaces. O'Connor has a BS in electrical engineering from Trinity College, Dublin. He is a member of IEEE.", 'Direct questions and comments about this article to John Sell, Microsoft, 1085 La Avenida, Mountain View, CA 94043, jsell@microsoft.com.']}} %*The Xbox One System on a Chip and Kinect Sensor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6756701 %f/micro/zlhjv8wyfgswfxxbbtrmu592gnjparee.pdf %m3fc19748a4cc9f3055fefdf7749c2363 %cmicro %@[{'name': 'David Kidd', 'affiliation': 'SuVolta', 'bio': {'p': ['David Kidd is the senior director of digital design at SuVolta, where he is responsible for SoC design, CAD, SRAM design, and IP development. His research interests include full-custom and semi-custom microprocessor design and design methodologies. Kidd has an MS in electrical engineering from the University of Michigan.']}} %*Process and Circuit Optimization for Power Reduction Using DDC Transistors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6756700 %f/micro/lflcs0rmozz4iuu82eqjwtvtipbdm9vx.pdf %m8b9fd0f93a8a40d9f107685b98f1a331 %cmicro %@[{'name': 'Erik R. Altman', 'affiliation': 'Thomas J. Watson Research Center', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6828565/6828574/6828574-photo-1-small.gif', 'p': ['Erik R. Altman is the manager of the Dynamic Optimization Group at the Thomas J. Watson Research Center. Contact him at ealtman@us.ibm.com.']}} %*Top Picks from 2013 %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6828574 %f/micro/au9w8qdhzc4rks1zon2rf0ietaijs7ev.pdf %m15884f1e7933f58cfda06a2777a46408 %cmicro %@[{'name': 'Mithuna S. Thottethodi', 'affiliation': 'Purdue University', 'bio': {'p': ['Mithuna S. Thottethodi is an associate professor in the School of Electrical and Computer Engineering at Purdue University. His research interests include parallel programming, parallel architecture, interconnection networks, storage, and multicore memory hierarchies. Thottethodi has a PhD in computer science from Duke University. He is a member of IEEE and the ACM.']}}, {'name': 'Shubu Mukherjee', 'affiliation': 'Cavium', 'bio': {'p': ['Shubu Mukherjee is a distinguished engineer and the lead architect for the ARMv8 processor core at Cavium. His research interests include innovation confluencing and computer architecture. Mukherjee has a PhD in computer science from the University of Wisconsin-Madison. He is a Fellow of IEEE and the ACM.']}} %*Top Picks from the 2013 Computer Architecture Conferences %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6828576 %f/micro/xhvgicuthl2gjpz3furbijyz5ydlnpod.pdf %m83a1214c84e3b878c1b09d4e6e219d16 %cmicro %@[{'name': 'Í,ñ,igo Goiri', 'affiliation': 'Rutgers University', 'bio': {'p': ['Íñigo Goiri is a research associate in the Department of Computer Science at Rutgers University. His research interests include energy-efficient datacenter design and virtualization. Goiri has a PhD in computer science from the Universitat Politecnica de Catalunya.']}}, {'name': 'William Katsak', 'affiliation': 'Rutgers University', 'bio': {'p': ['William Katsak is a PhD student in the Department of Computer Science at Rutgers University. His research focuses on power management of datacenters. Katsak has an MS in computer science from Rutgers University. He is a student member of IEEE and the ACM.']}}, {'name': 'Kien Le', 'affiliation': 'Rutgers University', 'bio': {'p': ['Kien Le is a software engineer at A10 networks. His research focuses on building a cost-aware load distribution framework to reduce energy consumption and promote renewable energy. Le has a PhD in computer science from Rutgers University, where he completed the work for this article.']}}, {'name': 'Thu D. Nguyen', 'affiliation': 'Rutgers University', 'bio': {'p': ['Thu D. Nguyen is an associate professor in the Department of Computer Science at Rutgers University. His research interests include green computing, distributed and parallel systems, operating systems, and information retrieval. Nguyen has a PhD in computer science and engineering from the University of Washington. He is a member of IEEE and the ACM.']}}, {'name': 'Ricardo Bianchini', 'affiliation': 'Rutgers University', 'bio': {'p': ['Ricardo Bianchini is a professor in the Department of Computer Science at Rutgers University. He is currently on leave from Rutgers and working as the chief efficiency strategist at Microsoft. His research interests include the power, energy, and thermal management of servers and datacenters. Bianchini has a PhD in computer science from the University of Rochester. He is an ACM distinguished scientist and a senior member of IEEE.']}} %*Designing and Managing Data centers Powered by Renewable Energy %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6756707 %f/micro/viocmctnyxqmp6webgo0jhy8rlqsp5gr.pdf %m053e9ffc5a9588658428ec99c65f75ed %cmicro %@[{'name': 'Christina Delimitrou', 'affiliation': 'Stanford University', 'bio': {'p': ['Christina Delimitrou is a PhD student in the Department of Electrical Engineering at Stanford University. Her research focuses on large-scale datacenters, specifically on scheduling and resource allocation techniques with quality-of-service guarantees, practical cluster management systems that improve resource efficiency, and datacenter application analysis and modeling. Delimitrou has an MS in electrical engineering from Stanford University. She is a student member of IEEE and the ACM.']}}, {'name': 'Christos Kozyrakis', 'affiliation': 'Stanford University', 'bio': {'p': ['Christos Kozyrakis is an associate professor in the Departments of Electrical Engineering and Computer Science at Stanford University, where he investigates hardware architectures, system software, and programming models for systems ranging from cell phones to warehouse-scale datacenters. His research focuses on resource-efficient cloud computing, energy-efficient multicore systems, and architectural support for security. Kozyrakis has a PhD in computer science from the University of California, Berkeley. He is a senior member of IEEE and the ACM.']}} %*Quality-of-Service-Aware Scheduling in Heterogeneous Data centers with Paragon %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6756704 %f/micro/pbepcrz2kaqk8sn3u6bfy9g70eyouwns.pdf %m5d6beb8d90195a18b1ab3acdd81b87b7 %cmicro %@[{'name': 'Michael Ferdman', 'affiliation': 'Stony Brook University', 'bio': {'p': ['Michael Ferdman is an assistant professor in the Department of Computer Science at Stony Brook University. His research focuses on computer architecture, particularly on server system design. Ferdman has a PhD in electrical and computer engineering from Carnegie Mellon University.']}}, {'name': 'Almutaz Adileh', 'affiliation': 'Ghent University', 'bio': {'p': ['Almutaz Adileh is a PhD candidate in the Department of Computer Science at Ghent University. His research focuses on computer architecture, particularly on improving performance in power-limited chips. Adileh has an MSc in computer engineering from the University of Southern California.']}}, {'name': 'Onur Kocberber', 'affiliation': 'É,cole Polytechnique Fé,dé,rale de Lausanne', 'bio': {'p': ['Onur Kocberber is a PhD candidate in the School of Computer and Communication Sciences at École Polytechnique Fédérale de Lausanne. His research focuses on specialized architectures for server systems. Kocberber has an MSc in computer engineering from TOBB University of Economics and Technology.']}}, {'name': 'Stavros Volos', 'affiliation': 'É,cole Polytechnique Fé,dé,rale de Lausanne', 'bio': {'p': ['Stavros Volos is a PhD candidate in the School of Computer and Communication Sciences at École Polytechnique Fédérale de Lausanne. His research focuses on computer architecture, particularly on memory systems for high-throughput and energy-aware computing. Volos has a DiplIng in electrical and computer engineering from the National Technical University of Athens.']}}, {'name': 'Mohammad Alisafaee', 'affiliation': 'É,cole Polytechnique Fé,dé,rale de Lausanne', 'bio': {'p': ['Mohammad Alisafaee performed the work for this article while he was a researcher in the School of Computer and Communication Sciences at École Polytechnique Fédérale de Lausanne. His research interests include multiprocessor cache coherence and memory system design for commercial workloads. Alisafaee has an MSc in electrical and computer engineering from the University of Tehran.']}}, {'name': 'Djordje Jevdjic', 'affiliation': 'É,cole Polytechnique Fé,dé,rale de Lausanne', 'bio': {'p': ['Djordje Jevdjic is a PhD candidate in the School of Computer and Communication Sciences at École Polytechnique Fédérale de Lausanne. His research focuses on highperformance memory systems for servers, including on-chip DRAM caches and 3D-die stacking, with an emphasis on locality and energy efficiency. Jevdjic has an MSc in electrical and computer engineering from the University of Belgrade.']}}, {'name': 'Cansu Kaynak', 'affiliation': 'É,cole Polytechnique Fé,dé,rale de Lausanne', 'bio': {'p': ['Cansu Kaynak is a PhD candidate in the School of Computer and Communication Sciences at École Polytechnique Fédérale de Lausanne. Her research focuses on server systems, especially memory system design. Kaynak has a BSc in computer engineering from TOBB University of Economics and Technology.']}}, {'name': 'Adrian Daniel Popescu', 'affiliation': 'É,cole Polytechnique Fé,dé,rale de Lausanne', 'bio': {'p': ['Adrian Daniel Popescu is a PhD candidate in the School of Computer and Communication Sciences at École Polytechnique Fédérale de Lausanne. His research focuses on the intersection of database management systems with distributed systems, specifically query performance prediction. Popescu has an MSc in electrical and computer engineering from the University of Toronto.']}}, {'name': 'Anastasia Ailamaki', 'affiliation': 'É,cole Polytechnique Fé,dé,rale de Lausanne', 'bio': {'p': ['Anastasia Ailamaki is a professor in the School of Computer and Communication Sciences at École Polytechnique Fédérale de Lausanne. Her research interests include optimizing database software for emerging hardware and I/O devices and automating database management to support scientific applications. Ailamaki has a PhD in computer science from the University of Wisconsin- Madison.']}}, {'name': 'Babak Falsafi', 'affiliation': 'É,cole Polytechnique Fé,dé,rale de Lausanne', 'bio': {'p': ['Babak Falsafi is a professor in the School of Computer and Communication Sciences at École Polytechnique Fédérale de Lausanne and the founding director of EcoCloud, an interdisciplinary research center targeting robust, economic, and environmentally friendly cloud technologies. Falsafi has a PhD in computer science from the University of Wiseonsin-Madison.', 'Direct questions and comments about this article to Michael Ferdman, Stony Brook University, 1419 Computer Science, Stony Brook, NY 11794, mferdman@cs.stonybrook.edu.']}} %*A Case for Specialized Processors for Scale-Out Workloads %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6828575 %f/micro/7lwrj4hsoronj5h0tepgyzl2dcsuegkv.pdf %m12b208e4caf9e4afc3f8d66b384362b2 %cmicro %@[{'name': 'Tushar Krishna', 'affiliation': 'Massachusetts Inst. of Technol., Cambridge, MA, USA', 'bio': {'p': ['Tushar Krishna is a researcher in the VSSAD group at Intel. His research focuses on on-chip interconnection networks for homogeneous and heterogeneous manycore systems. Krishna has a PhD in electrical engineering and computer science from the Massachusetts Institute of Technology, where he performed the work for this article.']}}, {'name': 'Chia-Hsin Owen Chen', 'affiliation': 'Massachusetts Inst. of Technol., Cambridge, MA, USA', 'bio': {'p': ['Chia-Hsin Owen Chen is a doctoral candidate in the Department of Electrical Engineering and Computer Science at the Massachusetts Institute of Technology. His research interests include system-level power and performance modeling and analysis, and on-chip networks. Chen has an SM in electrical engineering and computer science from the Massachusetts Institute of Technology.']}}, {'name': ' Woo-Cheol Kwon', 'affiliation': 'Massachusetts Inst. of Technol., Cambridge, MA, USA', 'bio': {'p': ['Woo-Cheol Kwon is a doctoral candidate in the Department of Electrical Engineering and Computer Science at the Massachusetts Institute of Technology. His research interests include multicore processor architectures and networks on chip. Kwon has an MS in computer science from the Korea Advanced Institute of Science & Technology (KAIST).']}}, {'name': ' Li-Shiuan Peh', 'affiliation': 'Massachusetts Inst. of Technol., Cambridge, MA, USA', 'bio': {'p': ['Li-Shiuan Peh is a professor in the Department of Electrical Engineering and Computer Science at the Massachusetts Institute of Technology. Her research focuses on networked computing in many-core chips and mobile wireless systems. Peh has a PhD in computer science from Stanford University. She is a member of IEEE and the ACM.', 'Direct questions and comments about this article to Tushar Krishna, 77 Reed Road, HD2–330, Hudson, MA 01749, tushar.krishna@intel.com.']}} %*Smart: Single-Cycle Multihop Traversals over a Shared Network on Chip %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6828577 %f/micro/pnitakuxqyjhc8zoclvieg0nrz1uv5br.pdf %m93135a79678988ae268740875e939e01 %cmicro %@[{'name': 'Hassan M.G. Wassel', 'affiliation': 'Google', 'bio': {'p': ['Hassan M.G. Wassel is a software engineer at Google, working in the Platforms group. His research includes computer architecture and its interaction with software and novel hardware technologies in order to build energy-efficient, high-performance, and reliable systems. Wassel has a PhD in computer science from the University of California, Santa Barbara, where he performed the work for this article. He is a member of IEEE and the ACM.']}}, {'name': 'Ying Gao', 'affiliation': 'University of California, Santa Barbara', 'bio': {'p': ['Ying Gao is a PhD student in computer engineering at the University of California, Santa Barbara. Her research focuses on security computer architectures and improving program security by using intelligent hardware. Gao has a BS in optoelectronics from Tianjin University, China.']}}, {'name': 'Jason K. Oberg', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Jason K. Oberg is a PhD candidate in the Computer Science and Engineering Department at the University of California, San Diego. His research interests include testing and verification methods for secure hardware design and methodologies for identifying timing-based side channels in hardware. Oberg has an MS in computer engineering from the University of California, San Diego.']}}, {'name': 'Ted Huffmire', 'affiliation': 'Naval Postgraduate School', 'bio': {'p': ['Ted Huffmire is an assistant professor of computer science at the Naval Postgraduate School. His research focuses on the intersection of computer architecture and computer security. Huffmire has a PhD in computer science from the University of California, Santa Barbara.']}}, {'name': 'Ryan Kastner', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Ryan Kastner is a professor in the Department of Computer Science and Engineering at the University of California, San Diego. His research focuses on embedded system design, particularly the use of reconfigurable computing devices for digital signal processing as well as hardware security. Kastner has a PhD in computer science from the University of California, Los Angeles.']}}, {'name': 'Frederic T. Chong', 'affiliation': 'University of California, Santa Barbara', 'bio': {'p': ['Frederic T. Chong is the director of the Greenscale Center for Energy-Efficient Computing, director of the Computer Engineering Program, and a professor of computer science at the University of California, Santa Barbara. His research interests include emerging technologies, multicore and embedded architectures, computer security, and sustainable computing. Chong has a PhD in electrical engineering and computer science from the Massachusetts Institute of Technology.']}}, {'name': 'Timothy Sherwood', 'affiliation': 'University of California, Santa Barbara', 'bio': {'p': ['Timothy Sherwood is a professor in the Department of Computer Science at the University of California, Santa Barbara. His research focuses on the development of novel computer architectures for security, introspection, and embedded applications. Sherwood has a PhD in computer science from the University of California, San Diego. He is a member of IEEE and the ACM.']}} %*Networks on Chip with Provable Security Properties %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6828567 %f/micro/qxgjrubtaydw57l1shao39zntc80cjd6.pdf %m7c63c70fb5134301b7fb6f4f985313db %cmicro %@[{'name': 'Inderpreet Singh', 'affiliation': 'Qualcomm', 'bio': {'p': ['Inderpreet Singh is an engineer at Qualcomm. His research interests include memory models and GPU computing. Singh has an MASc in computer engineering from the University of British Columbia.', 'Arrvindh Shriraman is an assistant professor in the School of Computer Science at Simon Fraser University, where he is the faculty coleader of the Systems Networking and Architecture Research (SYNAR) group. His research interests include multiprocessor systems design, hardware-software interface, and memory systems. Shriraman has a PhD in computer science from the University of Rochester.']}}, {'name': 'Arrvindh Shriraman', 'affiliation': 'Simon Fraser University', 'bio': {'p': ['Wilson W.L. Fung is a PhD student in the Department of Electrical and Computer Engineering at the University of British Columbia. His research interests include parallel programming models for GPU-like accelerators. Fung has an MASc in computer engineering from the University of British Columbia. He is a member of IEEE and the ACM.', "Mike O'Connor is a senior research scientist at Nvidia, he performed this work while he was a researcher at AMD Research. O'Connor has an MS in electrical and computer engineering from the University of Texas at Austin. He is a senior member of IEEE and a member of the ACM."]}}, {'name': 'Wilson W.L. Fung', 'affiliation': 'University of British Columbia', 'bio': {'p': ['Tor M. Aamodt is an associate professor in the Department of Electrical and Computer Engineering at the University of British Columbia. His research interests include the architecture of programmable accelerators and energy-efficient computing. Aamodt has a PhD in electrical and computer engineering from the University of Toronto. He is a member of IEEE and the ACM.']}}, {'name': "Mike O'Connor", 'affiliation': 'AMD Research'}, {'name': 'Tor M. Aamodt', 'affiliation': 'University of British Columbia'} %*Cache Coherence for GPU Architectures %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6756705 %f/micro/p8hijfpevti69uzvocgnmwrlbrqaw324.pdf %m5d54c188d8c3d13f9c9c317cd94f352e %cmicro %@[{'name': 'Jaewoong Sim', 'affiliation': 'Georgia Institute of Technology', 'bio': {'p': ['Jaewoong Sim is a PhD candidate in the Department of Electrical and Computer Engineering at the Georgia Institute of Technology. His research focuses on the interactions between microarchitecture, compiler, and operating systems to efficiently enable emerging technologies. Sim has a BS in electrical engineering from Seoul National University. He is a student member of IEEE and the ACM.']}}, {'name': 'Gabriel H. Loh', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ['Gabriel H. Loh is a fellow design engineer at Advanced Micro Devices. His research interests include computer architecture, processor microarchitecture, emerging technologies, and 3D die stacking. Loh has a PhD in computer science from Yale University. He is a senior member of IEEE and the ACM.']}}, {'name': 'Vilas Sridharan', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ['Vilas Sridharan is an RAS architect at Advanced Micro Devices. His research interests include the modeling of hardware faults and architectural and microarchitectural approaches to fault tolerance in highperformance microprocessors. Sridharan has a PhD from Northeastern University. He is a member of IEEE.']}}, {'name': "Mike O'Connor", 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ["Mike O'Connor is a senior research scientist at NVIDIA. He performed the work for this article at Advanced Micro Devices. His research interests include GPU, heterogeneous processors, and memory systems. O'Connor has an MS in electrical and computer engineering from the University of Texas at Austin. He is a senior member of IEEE and a member of the ACM.", 'Direct questions and comments about this article to Jaewoong Sim, 266 Ferst Drive (Klaus Advanced Computing Building), Atlanta, GA 30332, jaewoong.sim@gatech.edu.']}} %*A Configurable and Strong RAS Solution for Die-Stacked DRAM Caches %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6762798 %f/micro/9zkstnqfuawzbgl12veod7ax5rfmpq0c.pdf %mb368edd1220e51c5d81e05f8a3a8fbfc %cmicro %@[{'name': 'Somayeh Sardashti', 'affiliation': 'University of Wisconsin-Madison', 'bio': {'p': ['Somayeh Sardashti is a PhD candidate in the Department of Computer Sciences at the University of Wisconsin-Madison. Her research interest is computer architecture, specifically energy-optimized memory hierarchies. Sardashti has an MS in computer science from the University of Wisconsin-Madison and an MS in computer engineering from the University of Tehran. She is a member of IEEE and the ACM.']}}, {'name': 'David A. Wood', 'affiliation': 'University of Wisconsin-Madison', 'bio': {'p': ['David A. Wood is a professor in the Department of Computer Sciences and the Department of Electrical and Computer Engineering at the University of Wisconsin-Madison. His research interests include techniques for improving the performance and energy efficiency of multiprocessor and heterogeneous computing systems. Wood has a PhD in computer science from the University of California, Berkeley. He is a fellow of IEEE and the ACM, and a member of the IEEE Computer Society.']}} %*Decoupled Compressed Cache: Exploiting Spatial Locality for Energy Optimization %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6828571 %f/micro/5arxkyungut4cjqkope8modcw1vqnxhf.pdf %mea991990e947376c734440228939619a %cmicro %@[{'name': 'Richard Sampson', 'affiliation': 'University of Michigan', 'bio': {'p': ['Richard Sampson is a PhD candidate in the Department of Electrical Engineering and Computer Science at the University of Michigan. His research interests include hardware-system and accelerator design for imaging and computer vision applications. Sampson has an MS in computer science and engineering from the University of Michigan.']}}, {'name': 'Ming Yang', 'affiliation': 'Arizona State University', 'bio': {'p': ['Ming Yang is a PhD student in the School of Electrical, Computer and Energy Engineering at Arizona State University. His research focuses on the development of algorithms and low-power hardware for a handheld 3D ultrasound imaging device. Yang has an MS in electrical engineering from Beijing University of Posts and Telecommunications.']}}, {'name': 'Siyuan Wei', 'affiliation': 'Arizona State University', 'bio': {'p': ['Siyuan Wei is a PhD student in the School of Electrical, Computer and Energy Engineering at Arizona State University. His research focuses on algorithm-architecture codesign of ultrasound imaging systems, especially those based on Doppler imaging. Wei has a BE in electrical engineering from Huazhong University of Technology and Science.']}}, {'name': 'Chaitali Chakrabarti', 'affiliation': 'Arizona State University', 'bio': {'p': ['Chaitali Chakrabarti is a professor in the School of Electrical, Computer and Energy Engineering at Arizona State University. Her research interests include low-power system design, VLSI algorithms, and architectures for signal processing systems. Chakrabarti has a PhD in electrical engineering from the University of Maryland. She is a fellow of IEEE.']}}, {'name': 'Thomas F. Wenisch', 'affiliation': 'University of Michigan', 'bio': {'p': ['Thomas F. Wenisch is an associate professor in the Department of Electrical Engineering and Computer Science at the University of Michigan. His research focuses on computer architecture, particularly multiprocessor and multicore systems, multicore programmability, smartphone architecture, data center architecture, and performance evaluation methodology. Wenisch has a PhD in electrical and computer engineering from Carnegie Mellon University. He is a member of IEEE and the ACM.']}} %*Sonic Millip3De: An Architecture for Handheld 3D Ultrasound %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6828568 %f/micro/ihks1bp0rmmytiqg5ncnopfl46olxehd.pdf %mbe38538be5a13133bead0bbe80c39a82 %cmicro %@[{'name': 'Lisa Wu', 'affiliation': 'Columbia University', 'bio': {'p': ['Lisa Wu is a research staff member at Intel Labs. Her research interests include computer architecture, accelerators, and energy-efficient computing on high-performance computing and big data. Wu has a PhD in computer science from Columbia University, where she performed the work for this article. She is a member of ACM Sigarch.']}}, {'name': 'Raymond J. Barker', 'affiliation': 'Columbia University', 'bio': {'p': ['Raymond J. Barker is a software engineer at Google and an MS student in computer engineering at Columbia University. His research interests include application-specific computer architecture and parallel algorithms. Barker has a BS in computer engineering from Columbia University. He is a member of IEEE.']}}, {'name': 'Martha A. Kim', 'affiliation': 'Columbia University', 'bio': {'p': ['Martha A. Kim is an assistant professor in the Computer Science Department at Columbia University. Her research interests include computer architecture, parallel hardware and software systems, and energy-efficient computation on big data. Kim has a PhD in computer science and engineering from the University of Washington. She is a member of IEEE and the ACM.']}}, {'name': 'Kenneth A. Ross', 'affiliation': 'Columbia University', 'bio': {'p': ['Kenneth A. Ross is a professor of computer science at Columbia University. His research interests include database management systems, particularly their performance on modern multicore machines, GPUs, and other accelerator platforms. Ross has a PhD in computer science from Stanford University. He is a member of the ACM.', 'Direct questions and comments about this article to Lisa Wu, Intel, Building SC 12, 3600 Juliette Ln., M/S 303, Santa Clara, CA 95052, lisa@cs.columbia.edu.']}} %*Hardware Partitioning for Big Data Analytics %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6762799 %f/micro/vqnvaezwpqtalsoojkce6dd7b0ruhgfp.pdf %m5b1d13e0eb5e9960521d4cd37c789850 %cmicro %@[{'name': 'Angshuman Parashar', 'bio': {'p': ['Angshuman Parashar is an architecture research engineer in the VSSAD group at Intel. His research interests include spatial architectures, hardware/software interfaces, and quantitative evaluation of computer systems. Parashar has a PhD in computer science and engineering from the Pennsylvania State University.']}}, {'name': 'Michael Pellauer', 'bio': {'p': ['Michael Pellauer is an architecture research engineer in the VSSAD group at Intel. His research interests include spatial architectures and high-level hardware description languages. Pellauer has a PhD in computer science from the Massachusetts Institute of Technology.']}}, {'name': 'Michael Adler', 'bio': {'p': ['Michael Adler is a principal engineer in the VSSAD group at Intel. His research interests include building flexible microarchitecture timing models of large systems using FPGAs and building OS-like services to simplify FPGA programming. Adler has a BA in philosophy from the University of Pennsylvania.']}}, {'name': 'Bushra Ahsan', 'bio': {'p': ['Bushra Ahsan is a component design engineer at Intel. Her research focuses on memory systems architecture design and workloads for spatial architectures. Ahsan has a PhD in electrical and computer engineering from the City University of New York.']}}, {'name': 'Neal Crago', 'bio': {'p': ['Neal Crago is an architecture research engineer in the VSSAD group at Intel. His research interests include spatial and energy-efficient architectures. Crago has a PhD in computer engineering from the University of Illinois at Urbana-Champaign.']}}, {'name': 'Daniel Lustig', 'bio': {'p': ['Daniel Lustig is a PhD candidate in the Department of Electrical Engineering at Princeton University. His research focuses on the design and verification of memory systems for heterogeneous computing platforms. Lustig has an MA in electrical engineering from Princeton University.']}}, {'name': 'Vladimir Pavlov', 'bio': {'p': ['Vladimir Pavlov is a senior software engineer at Intel. His research focuses on programming and exploration tools for novel programmable accelerators, such as application-specific instruction set processors and spatial architectures. Pavlov has an MS from the State University of Aerospace Instrumentation, Saint Petersburg, Russia.']}}, {'name': 'Antonia Zhai', 'bio': {'p': ['Antonia Zhai is an associate professor in the Department of Computer Science and Engineering at the University of Minnesota. Her research focuses on developing novel compiler optimizations and architecture features to improve both performance and nonperformance features, such as programmability, security, testability, and reliability. Zhai has a PhD in computer science from Carnegie Mellon University.']}}, {'name': 'Mohit Gambhir', 'bio': {'p': ['Mohit Gambhir is an architecture modeling engineer in the VSSAD group at Intel. His research interests include modeling and simulation, performance analysis, and SoC architectures. Gambhir has an MS in computer science from the North Carolina State University.']}}, {'name': 'Aamer Jaleel', 'bio': {'p': ['Aamer Jaleel is a principal engineer in the VSSAD group at Intel. His research interests include memory system optimizations, application scheduling, and performance modeling. Jaleel has a PhD in electrical engineering from the University of Maryland, College Park.']}}, {'name': 'Randy Allmon', 'bio': {'p': ['Rand yAllmon is a senior principal engineer in the VSSAD group at Intel. His research interests include low-power, highperformance circuit and layout design and soft-error mitigation research. Allmon has a BS in electrical engineering from the University of Cincinnati.']}}, {'name': 'Rachid Rayess', 'bio': {'p': ['Rachid Rayess is a silicon architecture engineer in the MMDC group at Intel. His research focuses on memory architecture and memory design automation. Rayess has an MS in electrical engineering from North Carolina State University.']}}, {'name': 'Stephen Maresh', 'bio': {'p': ['Stephen Maresh is a performance modeling engineer at Intel. His research focuses on fabrics, spatial architectures, cache circuit design, and microprocessor design integration. Maresh has an MS in electrical and computer engineering from Northeastern University.']}}, {'name': 'Joel Emer', 'bio': {'p': ['Joel Emer is an Intel Fellow and director of microarchitecture research at Intel, where he leads the VSSAD group. He is also a professor of the practice at the Massachusetts Institute of Technology. His research interests include spatial architectures, performance modeling, and memory hierarchies. Emer has a PhD in electrical engineering from the University of Illinois. He is a Fellow of IEEE.', 'Direct questions and comments about this article to Michael Pellauer, Intel, 77 Reed Road, MS HD2–330, Hudson, MA 01749, michael.i.pellauer@intel.com.']}} %*Efficient Spatial Processing Element Control via Triggered Instructions %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6762794 %f/micro/lzvss7lpgmiuxdn34bq9xutjhpbfq1r0.pdf %mf59f3650a1bc126387f0076a2054afc6 %cmicro %@[{'name': 'Hyojin Sung', 'affiliation': 'University of Illinois at Urbana-Champaign', 'bio': {'p': ['Hyojin Sung is a PhD candidate in the Department of Computer Science at the University of Illinois at Urbana-Champaign. Her research focuses on parallel computer architecture. Sung has an MS in parallelizing compiler from the University of California, San Diego.']}}, {'name': 'Rakesh Komuravelli', 'affiliation': 'University of Illinois at Urbana-Champaign', 'bio': {'p': ['Rakesh Komuravelli is a PhD candidate in the Department of Computer Science at the University of Illinois at Urbana-Champaign. His research interests include computer architecture and parallel computing. Komuravelli has an MS in protocol verification from the University of Illinois at Urbana-Champaign.']}}, {'name': 'Sarita V. Adve', 'affiliation': 'University of Illinois at Urbana-Champaign', 'bio': {'p': ['Sarita V. Adve is a professor in the Department of Computer Science at the University of Illinois at Urbana-Champaign. Her research interests are in computer architecture and systems. Adve has a PhD in computer science from the University of Wisconsin. She is a fellow of IEEE and the ACM.']}} %*DeNovoND: Efficient Hardware for Disciplined Nondeterminism %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6756708 %f/micro/ijftfwrbd2lqrqcn0mxzxmekhei9oc4j.pdf %me9fa42aaa185f4b1be6ce707df19d506 %cmicro %@[{'name': 'James Goodman', 'affiliation': 'University of Auckland'} %*Reflections from the 2013 Eckert-Mauchly Award Recipient %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6828566 %f/micro/wz7x58jjgw3iryllutnzdode0ticokya.pdf %md10fcea75b635f930b8d84fe57b961cc %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'Northwestern University', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6828565/6828572/6828572-photo-1-small.gif', 'p': ['', 'Shane Greenstein is the Kellogg Chair in Information Technology at the Kellogg School of Management, Northwestern University. Contact him at greenstein@kellogg.northwestern.edu.']}} %*The Academic and Business Marriage %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6828572 %f/micro/cyjstnik5lzmbiwajpn6e8uqor3d4uye.pdf %mb200be8937ebfbc172cec6ec812569f7 %cmicro %@[{'name': 'Erik R. Altman', 'affiliation': 'Thomas J. Watson Research Center', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6871686/6871691/6871691-photo-1-small.gif', 'p': ['Erik R. Altman is the manager of the Dynamic Optimization Group at the Thomas J. Watson Research Center. Contact him at ealtman@us.ibm.com.']}} %*Big Data and Democratization [Editorial] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6871691 %f/micro/8xvvporsyq6deasyln7tc9fa4qgrzkwl.pdf %m358cc000a122a4d683e6e37ca22847df %cmicro %@[{'name': 'Babak Falsafi', 'affiliation': 'EPFL', 'bio': {'p': ['Babak Falsafi is a professor of computer and communication sciences at EPFL (Ecole Polytechnique Fédérale de Lausanne), and the founding director of EcoCloud, an interdisciplinary research center targeting robust, economic, and environmentally friendly cloud technologies. Falsafi has a PhD in computer science from the University of Wisconsin-Madison.']}}, {'name': 'Boris Grot', 'affiliation': 'University of Edinburgh', 'bio': {'p': ['Boris Grot is an assistant professor in the School of Informatics at the University of Edinburgh. His research seeks to address efficiency bottlenecks and capability shortcomings of processing platforms for big data. Grot has a PhD in computer science from the University of Texas at Austin.']}} %*Big Data [Guest editors' introduction] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6871717 %f/micro/7j0r8bakvnwffghmduyhblgy9xtqcs4x.pdf %me1ac1c7ba67e9985f34c9b5bcfa3a5f9 %cmicro %@[{'name': 'Raphael Polig', 'bio': {'p': ['Raphael Polig is a predoctoral researcher in the Zurich Research Laboratory of IBM Research. His research focuses on reconfigurable architectures for text-based analytics. Polig has a DiplIng in electrical engineering and information technology from the Technische Universität München.']}}, {'name': 'Kubilay Atasu', 'bio': {'p': ['Kubilay Atasu is a research staff member in the Zurich Research Laboratory of IBM Research, where he works on hardware accelerators. His research focuses on the design of reconfigurable hardware accelerators for big data and analytics applications. Atasu has a PhD in computer engineering from Bo ÄŸaziçi University, Turkey.']}}, {'name': 'Laura Chiticariu', 'bio': {'p': ['Laura Chiticariu is a research staff member in the Infrastructure for Intelligent Information Systems group at IBM Research, where she works on building development support for information extraction systems, using a range of techniques including data provenance, information integration, and natural language processing. Chiticariu has a PhD in computer science from the University of California, Santa Cruz.']}}, {'name': 'Christoph Hagleitner', 'bio': {'p': ['Christoph Hagleitner is a research staff member at IBM Research, where he manages the Accelerator Technologies group. His research focuses on performance- and energy-optimized hardware accelerators for next-generation computing systems. Hagleitner has a PhD in electrical engineering from the Swiss Federal Institute of Technology.']}}, {'name': 'H. Peter Hofstee', 'bio': {'p': ['H. Peter Hofstee is a research staff member at IBM Research. His research focuses on heterogeneous and workload-optimized systems based on the Power architecture. Hofstee has a PhD in computer science from the California Institute of Technology. He is a member of IEEE, the ACM, and the IBM Academy of Technology.']}}, {'name': 'Frederick R. Reiss', 'bio': {'p': ['Frederick R. Reiss is a research staff member at IBM Research. His research interests include information extraction, lossy and lossless data compression, high-performance query processing, streaming query processing, and query optimization. Reiss has a PhD in computer science from the University of California, Berkeley.']}}, {'name': 'Huaiyu Zhu', 'bio': {'p': ['Huaiyu Zhu is a senior engineer at IBM Research. His research interests include machine learning, text analytics, and modes of computation. Zhu has a PhD in statistics and computational mathematics from the University of Liverpool.']}}, {'name': 'Eva Sitaridi', 'bio': {'p': ['Eva Sitaridi is a PhD candidate in the Computer Science Department of Columbia University. Her research focuses on database processing using GPUs. Sitaridi has an MSc in computer science from the University of Athens.']}} %*Giving Text Analytics a Boost %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6871704 %f/micro/sfb6tatgxx3r8nhpr94qpsulgjjdehyo.pdf %m6de9df5084cbc2cb2bb3d39566d53bfa %cmicro %@[{'name': 'Alessandro Morari', 'affiliation': 'Pacific Northwest Nat. Lab., Richland, WA, USA', 'bio': {'p': ['Alessandro Morari is a research scientist in the Data Intensive Scientific Computing group at the Pacific Northwest National Laboratory. His research interests include big data analytics, large-scale runtime systems, system software for high-performance computing, and performance modeling. Morari has a PhD in computer science from Universitat Politècnica de Catalunya, Spain. He is a member of IEEE and the ACM.']}}, {'name': 'Vito Giovanni Castellana', 'affiliation': 'Pacific Northwest Nat. Lab., Richland, WA, USA', 'bio': {'p': ['Vito Giovanni Castellana is a research associate in the High Performance Computing Group at the Pacific Northwest National Laboratory. His research interests include embedded-system design and electronic design automation, code transformation, compilation, and optimization. Castellana has a PhD in computer science and engineering from Politecnico di Milano.']}}, {'name': 'Oreste Villa', 'affiliation': 'Nvidia Res., Santa Clara, CA, USA', 'bio': {'p': ['Oreste Villa is a senior research scientist in the architecture group at Nvidia Research. His research interests include computer architecture and simulation, accelerators for scientific computing, and irregular applications. Villa has a PhD in computer science and engineering from Politecnico di Milano.']}}, {'name': 'Antonino Tumeo', 'affiliation': 'Pacific Northwest Nat. Lab., Richland, WA, USA', 'bio': {'p': ['Antonino Tumeo is a senior research scientist in the High Performance Computing Group at the Pacific Northwest National Laboratory. His research interests include simulation and modeling of computer architectures (high performance and embedded), hardware-software codesign, FPGA prototyping, and GPGPU computing. Tumeo has a PhD in computer science and engineering from Politecnico di Milano. He is a member of IEEE and the ACM.']}}, {'name': 'Jesse Weaver', 'affiliation': 'Pacific Northwest Nat. Lab., Richland, WA, USA', 'bio': {'p': ['Jesse Weaver is a research scientist in the Data Intensive Scientific Computing group at the Pacific Northwest National Laboratory. His research interests include distributed graph and RDF databases, parallel reasoning']}}, {'name': 'David Haglin', 'affiliation': 'Pacific Northwest Nat. Lab., Richland, WA, USA'}, {'name': 'Sutanay Choudhury', 'affiliation': 'Pacific Northwest Nat. Lab., Richland, WA, USA'}, {'name': 'John Feo', 'affiliation': 'Pacific Northwest Nat. Lab., Richland, WA, USA'} %*Scaling Semantic Graph Databases in Size and Performance %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6785922 %f/micro/doa6bgbw2rutywn48gm0ryjpm5dfhilk.pdf %m90e68391f6f9ed9c50f990494dfbd226 %cmicro %@[{'name': ' Van Bui', 'affiliation': 'Columbia Univ., New York, NY, USA', 'bio': {'p': ['Van Bui is a PhD candidate in the Computer Science Department at Columbia University. Her research interests include computer architecture, parallel computing, and high-performance and energy-efficient computing. Bui has an MS in computer science from the University of Houston. She is a member of IEEE.']}}, {'name': 'Martha A. Kim', 'affiliation': 'Columbia Univ., New York, NY, USA', 'bio': {'p': ['Martha A. Kim is an assistant professor in the Computer Science Department at Columbia University. Her research interests include computer architecture, parallel hardware and software systems, and energy-efficient computation on big data. Kim has a PhD in computer science from the University of Washington. She is a member of IEEE and the ACM.', 'Direct questions and comments about this article to Martha Kim, 450 Computer Science Building, 1214 Amsterdam Ave., Mail code: 0401, New York, NY 10027–7003, martha@cs.columbia.edu.']}} %*The Cache and Codec Model for Storing and Manipulating Data %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6820692 %f/micro/rqvkhnjoduauep2m7wcj53adfhvbgzzr.pdf %m490d72e2bdcaa4ca98b5ace958f65df8 %cmicro %@[{'name': 'Rajeev Balasubramonian', 'affiliation': 'University of Utah', 'bio': {'p': ['Rajeev Balasubramonian is an associate professor in the School of Computing at the University of Utah. His research focuses on memory systems and interconnects. Balasubramonian has a PhD in computer science from the University of Rochester. He is a member of IEEE and the ACM.']}}, {'name': 'Jichuan Chang', 'affiliation': 'Google', 'bio': {'p': ['Jichuan Chang is a member of the Platforms Performance team at Google. His research interests include computer system architecture and memory systems, with a focus on codesigning cost- and energy-efficient platforms. Chang has a PhD in computer science from the University of Wisconsin-Madison.']}}, {'name': 'Troy Manning', 'affiliation': 'Micron', 'bio': {'p': ['Troy Manning is director of advanced memory systems in the DRAM Solutions Group at Micron. His research focuses on DRAM design and architecture and solid-state storage systems. Manning has a BS in electrical and computer engineering from the University of Iowa.']}}, {'name': 'Jaime H. Moreno', 'affiliation': 'IBM Thomas J. Watson Research Center', 'bio': {'p': ['Jaime H. Moreno is senior manager of microprocessor architecture at the IBM Thomas J. Watson Research Center. His research focuses on microprocessor architecture and performance analysis topics, with an emphasis on emerging technologies. Moreno has a PhD in computer science from the University of California, Los Angeles. He is a senior member of IEEE and a member of the ACM and the IBM Academy of Technology.']}}, {'name': 'Richard Murphy', 'affiliation': 'Micron', 'bio': {'p': ['Richard Murphy is a senior advanced memory systems architect for the DRAM Solutions Group at Micron. His research focuses on future memory platforms, research and development of computer architecture, advanced memory systems, and supercomputing systems for physics and data-intensive problems. Murphy has a PhD in computer science and engineering from the University of Notre Dame. He is a senior member of IEEE.']}}, {'name': 'Ravi Nair', 'affiliation': 'IBM Thomas J. Watson Research Center', 'bio': {'p': ['Ravi Nair is a researcher at the IBM ThomasJ. Watson Research Center. His research interests include supercomputer design, processor microarchitecture, dynamic compilation, virtual machine technology, and approximate computing. Nair has a PhD in computer science from the University of Illinois at Urbana-Champaign. He is a member of the IBM Academy of Technology and a fellow of IEEE.']}}, {'name': 'Steven Swanson', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Steven Swanson is an associate professor in the Department of Computer Science and Engineering and the director of the Non-Volatile Systems Laboratory at the University of California, San Diego. His research interests include the systems, architecture, security, and reliability issues surrounding nonvolatile, solid-state memories. Swanson has a PhD in computer science and engineering from the University of Washington.']}} %*Near-Data Processing: Insights from a MICRO-46 Workshop %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6871738 %f/micro/wckbidmzotx9r2a1hs7fvvmo6qpphnun.pdf %m50dc211f0720a903a11b62b2fd43c70e %cmicro %@[{'name': 'Seth H. Pugsley', 'affiliation': 'Univ. of Utah, Salt Lake City, UT, USA', 'bio': {'p': ['Seth H. Pugsley is a PhD candidate in computer science at the University of Utah. His research focuses on memory system design, including caching policies, hardware prefetching, main memory system organization, and near-data processing. Pugsley has a BS in computer science from the University of Utah.']}}, {'name': 'Jeffrey Jestes', 'bio': {'p': ['Jeffrey Jestes is a senior software engineer at Cerner. His research interests include summarizing massive data in distributed and parallel frameworks, ranking, monitoring, and tracking big data, and scalable query processing in large databases. Jestes has a PhD in computing from the University of Utah.']}}, {'name': 'Rajeev Balasubramonian', 'affiliation': 'Univ. of Utah, Salt Lake City, UT, USA', 'bio': {'p': ['Rajeev Balasubramonian is an associate professor in the School of Computing at the University of Utah. His research focuses on memory systems and interconnects. Balasubramonian has a PhD in computer science from the University of Rochester. He is a member of IEEE.']}}, {'name': 'Vijayalakshmi Srinivasan', 'affiliation': 'IBM T.J. Watson Res. Center, Yorktown Heights, NY, USA', 'bio': {'p': ['Vijayalakshmi Srinivasan is a research staff member at the IBM Thomas J. Watson Re- search Center. Her research focuses on computer architecture, particularly processor and memory microarchitecture, data-center architectures, and big data analytics. Srinivasan has a PhD in computer science from the University of Michigan. She is a senior member of IEEE.']}}, {'name': 'Alper Buyuktosunoglu', 'affiliation': 'IBM T.J. Watson Res. Center, Yorktown Heights, NY, USA', 'bio': {'p': ['Alper Buyuktosunoglu is a research staff member in the Reliability and Power-Aware Microarchitecture department at the IBM Thomas J. Watson Research Center. His research focuses on high-performance and power- and reliability-aware computer architectures. Buyuktosunoglu has a PhD in electrical and computer engineering from Universi ty of Rochester. He is an IBM Master Inventor, a senior member of IEEE, and an editorial board member of IEEE Micro.']}}, {'name': 'Al Davis', 'affiliation': 'Univ. of Utah, Salt Lake City, UT, USA', 'bio': {'p': ['Al Davis is a professor in the School of Computing at the University of Utah. He is also a part-time visiting scholar at HP Laboratories. His research interests include computer architecture, VLSI, and photonics. Davis has a PhD in computer science from the University of Utah.']}}, {'name': ' Feifei Li', 'affiliation': 'Univ. of Utah, Salt Lake City, UT, USA', 'bio': {'p': ['Feifei Li is an associate professor in the School of Computing at the University of Utah. His research interests include database and data management systems and big data analytics. Li has a PhD in computer science from Boston University.']}} %*Comparing Implementations of Near-Data Computing with In-Memory MapReduce Workloads %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6824681 %f/micro/q9e0fvxc7kgkim18oxrvphg2h5fqazwd.pdf %m01fa122c8dd2d27b5f5a58b9e2dcdfbd %cmicro %@[{'name': 'Richard Mateosian', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6871686/6871714/6871714-photo-1-small.gif', 'p': ['Richard Mateosian is a technical writer in the San Francisco Bay Area. Contact himat xrmxrm@gmail.com.']}} %*How To [3 books reviewed] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6871714 %f/micro/6ens9baoyyafmr2zmjlw3uk5otvuir8x.pdf %mb59d8344df40ed5e0b9b774bdc5e809b %cmicro %@[{'name': 'Shane Greenstein', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6871686/6871702/6871702-photo-1-small.gif', 'p': ['Shane Greenstein is the Kellogg Chair in Information Technology at the Kellogg School of Management, Northwestern University. Contact him at greenstein@kellogg.northwestern.edu.']}} %*Baking the Data Layer [Micro Economics] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6871702 %f/micro/pdpuefnq1ce7blodrgahwytsyck4nzm0.pdf %m367b7cba2265fb4224422cb2191514a5 %cmicro %@[{'name': 'Erik R. Altman', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6915596/6915619/6915619-photo-1-small.gif', 'p': ['Erik R. Altman is the manager of the Dynamic Optimization Group at the Thomas J. Watson Research Center. Contact him at ealtman@us.ibm.com.']}} %*Patents and High-Speed Datacenter Interconnects %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6915619 %f/micro/o7qhq3mlvdaip98ejgo6w5ndbcz0rpry.pdf %m012d1480df959324ca9586da98621912 %cmicro %@[{'name': 'George Porter', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['George Porter is an assistant professor in the Systems and Networking Group in the Department of Computer Science and Engineering at the University of California, San Diego, where he is also the associate director of the Center for Networked Systems. His research interests include computer networks, data-intensive computing, computer systems, and datacenter networking. Porter has a PhD in computer science from the University of California, Berkeley.']}}, {'name': 'Alex C. Snoeren', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Alex C. Snoeren is a professor in the Systems and Networking Group in the Department of Computer Science and Engineering at the University of California, San Diego. His research focuses on computer systems, including operating systems and networking, and particularly on protocols to support secure and robust wide-area mobile computing. Snoeren has a PhD in electrical engineering and computer science from the Massachusetts Institute of Technology.']}}, {'name': 'George Papen', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['George Papen is a professor in the Electrical and Computer Engineering Department at the University of California, San Diego. His research interests include advanced photonic systems, particularly optical communication systems, optical networking, and environmental and atmospheric remote sensing. Papen has a PhD in electrical and computer engineering from the University of Wisconsin.', 'Direct questions and comments about this issue to George Porter at gmporter@cs.ucsd.edu, Alex Snoeren at snoeren@cs.ucsd.edu, and George Papen at gpapen@ucsd.edu.']}} %*High-Speed Datacenter Interconnects [Guest editors' introduction] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6915633 %f/micro/iqovk8nbummxygbxco62q90wlzuhk1cf.pdf %m01573eaf4a7d5c64a37007b4ee790d8c %cmicro %@[{'name': 'Gilmar L. Vassoler', 'affiliation': 'Federal Institute of Esprí,rito Santo', 'bio': {'p': ['Gilmar L. Vassoler is a lecturer in the Department of Informatics at the Federal Institute of Espírito Santo and a doctoral candidate in the Telecommunications Laboratory (LabTel) at the Federal University of Espírito Santo. His research interests include datacenter networks architecture, optical networks for datacenters, cloud computing, and virtualization. Vassoler has an MSc in electrical engineering from the Federal University of Espírito Santo.', 'Direct questions and comments about this article to Gilmar L. Vassoler, Universidade Federal do Espírito Santo, Centro Tecnológico, Departamento de Engenharia Elétrica, Av. Fernando Ferrari, 514—Labo-ratòrio de Telecomunicações, Goiabeiras, 29075–910, Vitória, ES, Brazil, gilmar-vassoler@ifes.edu.br.']}}, {'name': 'Marcia H.M. Paiva', 'affiliation': 'Federal Institute of Esprí,rito Santo', 'bio': {'p': ['Marcia H.M. Paiva is a postdoctoral researcher in the Telecommunications Laboratory at the Federal University of Espírito Santo. Her research interests include network topology, graph theory, and optical networks. Paiva has a PhD in electrical engineering from the Federal University of Espírito Santo.']}}, {'name': 'Moisé,s R.N. Ribeiro', 'affiliation': 'Federal Institute of Esprí,rito Santo', 'bio': {'p': ['Moises R.N. Ribeiro is a professor in the Department of Electrical Engineering at the Federal University of Espírito Santo. His research interests include fiber-optic communication and sensor devices, systems, and networks. Ribeiro has a PhD in electrical engineering from the University of Essex.']}}, {'name': 'Marcelo E.V. Segatto', 'affiliation': 'Federal Institute of Esprí,rito Santo', 'bio': {'p': ['Marcelo E.V. Segatto is a professor in the Department of Electrical Engineering at the Federal University of Espírito Santo. His research interests include fiber-optic communication devices, systems, and networks. Segatto has a PhD in physics from Imperial College London. He is a member of the Optical Society of America.']}} %*Twin Datacenter Interconnection Topology %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6866036 %f/micro/vynxougdub0tjiacjoekqchrlhy1ni3z.pdf %m5fe8c39076e297f11fa2f199bc07b815 %cmicro %@[{'name': 'Avinash Karanth Kodi', 'affiliation': 'Ohio University', 'bio': {'p': ['Avinash Karanth Kodi is an associate professor of electrical engineering and computer science at Ohio University. His research interests include optical interconnects, networks on chips, datacenters, and chip multiprocessors. Kodi has a PhD in electrical and computer engineering from the University of Arizona. He is a senior member of IEEE.']}}, {'name': 'Brian Neel', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ['Brian Neel is an electrical engineer at South Central Power Company. His research interests include optical interconnects, networks on chips, and datacenters. Neel has an MS in electrical engineering and computer science from Ohio University. He completed the work for this article while working as an intern at Advanced Micro Devices. He is a student member of IEEE.']}}, {'name': 'William C. Brantley', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ["William C. Brantley is a Fellow design engineer in the research division at Advanced Micro Devices, where he leads two research areas of AMD's Fast Forward project. His research interests include technologies for meeting the exascale challenge, such as high-bandwidth networks with low latency, power and thermal control, resilience, and techniques that efficiently exploit APUs from standard higher-level languages. Brantley has a PhD in electrical engineering from Carnegie Mellon University. He is a senior member of IEEE.", 'Direct questions and comments about this article to Avinash Karanth Kodi, 322D Stocker Center, Electrical Engineering and Computer Science, Ohio University, Athens, OH 45701, kodi@ohio.edu.']}} %*Photonic Interconnects for Exascale and Datacenter Architectures %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6866037 %f/micro/x0blhun3ernpmzads1q4wfkyce6hyxqv.pdf %m53f8438791c1a93c2ebf6d17192a72c3 %cmicro %@[{'name': 'Noa Zilberman', 'affiliation': 'University of Cambridge', 'bio': {'p': ['Noa Zilberman is a research associate in the Systems Research Group at the University of Cambridge Computer Laboratory. Her research interests include open source research using the NetFPGA platform, switching architectures, high-speed interfaces, Internet measurements, and topology. Zilberman has a PhD in electrical engineering from Tel Aviv University. She is a senior member of IEEE.']}}, {'name': 'Yury Audzevich', 'affiliation': 'University of Cambridge', 'bio': {'p': ['Yury Audzevich is a research associate in the Systems Research Group at the University of Cambridge Computer Laboratory. His research interests include integrated circuit design and energy-efficiency aspects in communication architectures. Audzevich has a PhD in information and telecommunication technologies from the University ofn Trento.']}}, {'name': 'G. Adam Covington', 'affiliation': 'Stanford University', 'bio': {'p': ["G. Adam Covington is a research associate in Nick McKeown's group at Stanford University. His research interests include reconfigurable systems, open source hardware and software, artificial intelligence, and dynamic visualizations of large-scale data. Covington has an MS in computer engineering from Washington University in St. Louis. He is a member of IEEE."]}}, {'name': 'Andrew W. Moore', 'affiliation': 'University of Cambridge', 'bio': {'p': ['Andrew W. Moore is a senior lecturer in the Systems Research Group at the University of Cambridge Computer Laboratory. His research interests include enabling open-network research and education using the NetFPGA platform, low-power, energy-aware networking, and datacenter architectures for novel network and systems. Moore has a PhD in network systems from the University of Cambridge. He is a chartered engineer with the IET and a member of IEEE, the ACM, and USENIX.', 'Direct questions and comments about this article to Noa Zilberman, Computer Laboratory, University of Cambridge, 15 JJ Thomson Ave., Cambridge, UK CB3 0FD, noa.zilberman@cl.cam.ac.uk.']}} %*NetFPGA SUME: Toward 100 Gbps as Research Commodity %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6866035 %f/micro/xcp9yzielms6etojhq8lnmxahwfkv5cs.pdf %m185bb9f107038b687fb8a5dcc0c5284e %cmicro %@[{'name': 'Dawei Zang', 'affiliation': 'Institute of Computing Technology, Chinese Academy of Sciences', 'bio': {'p': ['Dawei Zang is a PhD candidate at the Institute of Computing Technology, Chinese Academy of Sciences. His research interests include computer architecture and datacenter networks. Zang has a BS in computer science from Shandong University.']}}, {'name': 'Zheng Cao', 'affiliation': 'Institute of Computing Technology, Chinese Academy of Sciences', 'bio': {'p': ['Zheng Cao is an associate professor at the High Performance Computer Research Center of the Institute of Computing Technology, Chinese Academy of Sciences. His research interests include high-performance computer architecture and interconnection networks. Cao has a PhD in computer architecture from the University of Chinese Academy of Sciences.']}}, {'name': 'Zhan Wang', 'affiliation': 'Institute of Computing Technology, Chinese Academy of Sciences', 'bio': {'p': ['Zhan Wang is a PhD candidate at the Institute of Computing Technology, Chinese Academy of Sciences. His research interests include virtualization technology and highperformance interconnection networks. Wang has a BS in electrical engineering from Tsinghua University.']}}, {'name': 'Xiaoli Liu', 'affiliation': 'Institute of Computing Technology, Chinese Academy of Sciences', 'bio': {'p': ['Xiaoli Liu is an engineer at the High Performance Computer Research Center at the Institute of Computing Technology, Chinese Academy of Sciences. Her research interests include I/O virtualization and computer architecture. Liu has a MS in electromagnetic fields and microwave technology from the Beijing University of Posts and Telecommunications.']}}, {'name': 'Lin Wang', 'affiliation': 'Institute of Computing Technology, Chinese Academy of Sciences', 'bio': {'p': ['Lin Wang is a PhD candidate at the Institute of Computing Technology, Chinese Academy of Sciences. His research interests include datacenter networks and large-scale data analytics. Wang has a BS in computer science from the Beijing Institute of Technology.']}}, {'name': 'Ninghui Sun', 'affiliation': 'Institute of Computing Technology, Chinese Academy of Sciences', 'bio': {'p': ['Ninghui Sun is a professor and PhD supervisor at the High Performance Computer Research Center at the Institute of Computing Technology, Chinese Academy of Sciences. His research interests include highperformance computer architecture and distributed operating systems. Sun has a PhD in computer architecture from the University of Chinese Academy of Sciences.']}} %*Decentralized NIC-Switching Architecture Using SR-IOV PCI Express Network Device %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6866848 %f/micro/mwodivrvucoy3sxkplse6f5pkhjm0qz1.pdf %m95973d9a4be45f411a5388c01194a92f %cmicro %@[{'name': 'Laurent Schares', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ['Laurent Schares is a researcher at the IBM T.J. Watson Research Center. His research focuses on integrating optical technologies into future datacenter and supercomputer networks. Schares has a PhD in physics from the Swiss Federal Institute of Technology (ETH) Zurich.']}}, {'name': 'Benjamin G. Lee', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ['Benjamin G. Lee is a research staff member at the IBM T.J. Watson Research Center. His research interests include photonic devices, integrated optical-switch fabrics, and highly parallel transceivers. Lee has a PhD in electrical engineering from Columbia University.']}}, {'name': 'Fabio Checconi', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ['Fabio Checconi is a research staff member in the High Performance Analytics Group at the IBM T.J. Watson Research Center. His research interests include distributed graph processing, graph algorithms, and real-time operating systems. Checconi has a PhD in computer engineering from Scuola Superiore S. Anna in Pisa.']}}, {'name': 'Russell Budd', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ['Russell Budd is a senior technical staff member at the IBM T.J. Watson Research Center. His research interests include wafer-debonding technologies, and silicon photonic-device design and packaging for data-center optical interconnects. Budd has a BS in mechanical engineering from Michigan State University.']}}, {'name': 'Alexander Rylyakov', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ['Alexander Rylyakov is a research staff member at the IBM T.J. Watson Research Center. His research focuses on digital phase-locked loops and integrated circuits for wireline and optical communication. Rylyakov has a PhD in physics from the State University of New York at Stony Brook.']}}, {'name': 'Nicolas Dupuis', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ['Nicolas Dupuis is a postdoctoral researcher at the IBM T.J. Watson Research Center. His research interests include silicon photonics and optical-link modeling. Dupuis has a PhD in physics from Universite de Lorraine.']}}, {'name': 'Fabrizio Petrini', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ['Fabrizio Petrini is a researcher and manager of the High Performance Analytics Group at the IBM T.J. Watson Research Center. His research interests include data-intensive algorithms, exascale computing, and highperformance interconnection networks. Petrini has a PhD in computer science from the University of Pisa.']}}, {'name': 'Clint L. Schow', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ['Clint L. Schow manages the Optical Link and System Design Group at the IBM T.J. Watson Research Center. His research focuses on developing high-speed and power-efficient multimode and single-mode optical links, nanophotonic switches, and new system architectures based on low-latency photonic-switching fabrics. Schow has a PhD in electrical engineering from the University of Texas at Austin. He is a senior member of IEEE and the Optical Society of America.']}}, {'name': 'Pablo Fuentes', 'affiliation': 'IBM Research-Zurich', 'bio': {'p': ['Pablo Fuentes is a PhD student in computer science at the University of Cantabria, Spain. His research focuses on the characterization and performance evaluation of system interconnection networks. Fuentes has an MS in telecommunications engineering from the University of Cantabria. He completed the work for this article while working as a research intern at IBM Research-Zurich.']}}, {'name': 'Oliver Mattes', 'affiliation': 'IBM Research-Zurich', 'bio': {'p': ['Oliver Mattes is a PhD student in computer engineering at the Karlsruhe Institute of Technology. His research interests include adaptive computer architectures, memory systems, simulation, parallelization, and high-performance computing. Mattes has a Diploma (MS) in computer science from the Karlsruhe Institute of Technology. He completed the work for this article while working at IBM Research-Zurich.']}}, {'name': 'Cyriel Minkenberg', 'affiliation': 'IBM Research-Zurich', 'bio': {'p': ['Cyriel Minkenberg is a research staff member in the Cloud and Computing Infrastructure Department at IBM Research-Zurich. His research interests include the architecture, design, and performance evaluation of large-scale interconnection networks for cloud datacenters and high-performance computing systems. Minkenberg has a PhD in electrical engineering from the Eindhoven University of Technology.']}} %*A Throughput-Optimized Optical Network for Data-Intensive Computing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6915625 %f/micro/fi9up3or1khhmmbk8t4exewjtybnfnls.pdf %m4185cf4f4d5828c9bf3e0cb2915571d2 %cmicro %@[{'name': 'Richard H. Stern', 'affiliation': 'Kellogg Huber Hansen Todd Evans &,amp, Figel', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6915596/6915631/6915631-photo-1-small.gif', 'p': ['Richard H. Stern is an attorney at Kellogg Huber Hansen Todd Evans & Figel and a law professor at the George Washington University Law School. Contact him at rstern@khhte.com.']}} %*Alice v. CLS Bank: Are US Business-Method and Software Patents Doomed? Part 1 %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6915631 %f/micro/pkr0cgdlyuyo6nzf2wx47s5xjq9op8me.pdf %m91b5a45b9143d955a878ebe1772665e8 %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'Northwestern University', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6915596/6915618/6915618-photo-1-small.gif', 'p': ['Shane Greenstein is the Kellogg Chair in Information Technology at the Kellogg School of Management, Northwestern University. Contact him at greenstein@kellogg.northwestern.edu.']}} %*Enough Variety and Diversity? %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6915618 %f/micro/xvroi2meqy5hskejljnc8hga0lotbdwk.pdf %m2a7e8489bd9c7025c91e1e4cba749d5c %cmicro %@[{'name': 'Erik R. Altman', 'affiliation': 'IBM', 'bio': {'p': ['Erik R. Altman is a member of the corporate technology evaluation team at IBM. Contact him at ealtman@us.ibm.com.']}} %*Harsh Chips, but a Grateful Good-Bye %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6981855 %f/micro/ye8ksz4i1glcu9imnomfzv57alup3hbw.pdf %m5b06248dfdd0a8523049526da8e91d01 %cmicro %@[{'name': 'Augusto Vega', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ['Augusto Vega is a research staff member in the Reliability and Power-Aware Microarchitecture department at the IBM T.J. Watson Research Center. His research interests include high-performance, reliable, and power-efficient computer architectures, distributed and parallel computing, and performance-analysis tools and techniques. Vega has a PhD in computer architecture from the Polytechnic University of Catalonia.']}}, {'name': 'Alper Buyuktosunoglu', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ['Alper Buyuktosunoglu is a research staff member in the Reliability and Power-Aware Microarchitecture department at the IBM T.J. Watson Research Center. His research interests include high-performance, reliable, and power-efficient computer architectures. Buyuktosunoglu has a PhD in electrical and computer engineering from the University of Rochester.']}}, {'name': 'Pradip Bose', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ['Pradip Bose is a distinguished research staff member in the Reliability and Power-Aware Microarchitecture department at the IBM T.J. Watson Research Center. His research interests include high-performance, reliable, and power-efficient computer architectures. Bose has a PhD in electrical and computer engineering from the University of Illinois at Urbana-Champaign.', 'Direct questions and comments about this issue to Augusto Vega at ajvega@us.ibm.com, Alper Buyuktosunoglu at alperb@us.ibm.com, and Pradip Bose at pbose@us.ibm.com.']}} %*Special Series on Harsh Chips [Guest editors' introduction] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6981892 %f/micro/lov4zyayrzepiresmckp6tj9wgwdulc2.pdf %mff214bb3aecdfedf3b707893310514a9 %cmicro %@[{'name': 'Mladen Slijepcevic', 'affiliation': 'Universitat Politè,cnica de Catalunya', 'bio': {'p': ['Mladen Slijepcevic is a PhD student at Universitat Politècnica de Catalunya and a researcher in the Computer Architecture/ Operating System Interface (CAOS) group at the Barcelona Supercomputing Center. His research focuses on hardware design for realtime embedded systems. Slijepcevic has an MSc in electrical engineering and computer science from the University of Belgrade.']}}, {'name': 'Leonidas Kosmidis', 'affiliation': 'Universitat Politè,cnica de Catalunya', 'bio': {'p': ['Leonidas Kosmidis is a PhD student at U niversi tat Poli tecnica de Catal unya and a researcher in the Computer Architecture/ Operating System Interface (CAOS) group at the Barcelona Supercomputing Center. His research focuses on hardware and software design for real-time embedded systems. Kosmidis has an MSc in computer architecture, networks, and systems from the Universitat Politècnica de Catalunya.']}}, {'name': 'Jaume Abella', 'affiliation': 'Barcelona Supercomputing Center', 'bio': {'p': ['Jaume Abella is a senior PhD researcher in the CAOS group at the Barcelona Super-computing Center. His research interests include timing and functional system verification, reliability, and low power designs. Abella has a PhD in computer science from the Universitat Politècnica de Catalunya. He is a member of HiPEAC.']}}, {'name': 'Eduardo Quiñ,ones', 'affiliation': 'Barcelona Supercomputing Center', 'bio': {'p': ['Eduardo Quiñones is a senior PhD researcher at the Barcelona Supercomputing Center. His research focuses on safety-critical systems and high-performance compiler techniques. Quinones has a PhD in computer science from the Universitat Politècnica de Catalunya. He is a member of HiPEAC.']}}, {'name': 'Francisco J. Cazorla', 'affiliation': 'Barcelona Supercomputing Center', 'bio': {'p': ['Francisco J. Cazorla leads the CAOS group at the Barcelona Supercomputing Center. His research focuses on multithreaded computing for both high-performance and realtime systems. Cazorla has a PhD in computer science from the Universitat Politècnica de Catalunya. He is a member of HIPEAC.', 'Direct questions and comments about this article to Mladen Slijepcevic, C/Jordi Girona, 29, Edificio Nexus II, 1st floor, Office 124, 08034 Barcelona, Spain, mladen.slijepcevic@bsc.es.']}} %*Timing Verification of Fault-Tolerant Chips for Safety-Critical Applications in Harsh Environments %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6853246 %f/micro/eyhzbt6mup8l0ahj94kfovrfxnlcossc.pdf %m3aa0d21a72aba02a2ee64eed4b1d8e21 %cmicro %@[{'name': 'Xabier Iturbe', 'affiliation': 'University of Edinburgh', 'bio': {'p': ["Xabier Iturbe is a Marie Curie research fellow at NASA's Jet Propulsion Laboratory and ARM. He is the principal designer of R3TOS. He performed the research for this work while working for IK4-Ikerlan and conducting his PhD research at the University of Edinburgh. His research interests include microprocessors, multicore and system-on-chip processors, reconfigurable computing, hardware abstraction, and runtime management techniques. Iturbe has a PhD in electronics engineering from the University of Edinburgh."]}}, {'name': 'Ali Ebrahim', 'affiliation': 'University of Edinburgh', 'bio': {'p': ['Ali Ebrahim is a PhD student in the System Level Integration Research Group at the University of Edinburgh. His research interests include the use of R3TOS with different objectives, such as improving fault tolerance of FPGA devices, securing intellectual-property integration, and accelerating data-mining algorithms. Ebrahim has an MSc in electronics and electrical engineering from the University of Glasgow.']}}, {'name': 'Khaled Benkrid', 'affiliation': 'University of Edinburgh', 'bio': {'p': ["Khaled Benkrid is a chartered UK engineer and a senior lecturer in electronic engineering at the University of Edinburgh. His research interests include applications of GPUs, multi- and many-core processors, and heterogeneous computer systems in digital-signal processing and communications, bioinformatics, financial computing, and scientific computing. Benkrid has a PhD in computer science from Queen's University Belfast. He is a senior member of IEEE."]}}, {'name': 'Chuan Hong', 'affiliation': 'University of Edinburgh', 'bio': {'p': ["Chuan Hong is a technical content developer of ARM's university program. His research interests include embedded system and system-on-chip design. Hong has a PhD in electronics engineering from the University of Edinburgh, where he helped develop R3TOS and completed the research for this article."]}}, {'name': 'Tughrul Arslan', 'affiliation': 'University of Edinburgh', 'bio': {'p': ['Tughrul Arslan is the chair of Integrated Electronic Systems in the School of Engineering at the University of Edinburgh. He is also a member of the Integrated Micro and Nano Systems Institute and leads the System Level Integration Group at the University of Edinburgh. His research focuses on enhancing personal mobility and the design of high-performance embedded wireless systems. Arslan has a PhD in electronic engineering from the University of Hull. He is a senior member of IEEE.']}}, {'name': 'Jon Perez', 'affiliation': 'IK4-Ikerlan', 'bio': {'p': ['Jon Perez leads the Electronics Department at IK4-Ikerlan. His research focuses on distributed, real-time, and safety-critical embedded systems. Perez has a PhD in computer science from the Vienna University of Technology. He is a member of IEEE.']}}, {'name': 'Didier Keymeulen', 'affiliation': 'Jet Propulsion Laboratory', 'bio': {'p': ['Didier Keymeulen is a principal member of the technical staff at the Jet Propulsion Laboratory, where he is responsible for DoD and NASA applications on adaptive computing that lead to the development of fault-tolerant electronics and autonomous and adaptive instruments technology. He is also the electronics lead for the Tunable Laser Spectrum instrument on the Mars Science Laboratory rover. Keymeulen has a PhD in electrical engineering and computer science from the Free University of Brussels.']}}, {'name': 'Marco D. Santambrogio', 'affiliation': 'Politecnico di Milano', 'bio': {'p': ['Marco D. Santambrogio is an assistant professor at Politecnico di Milano and a research affiliate with the Computer Science and Artificial Intelligence Laboratory (CSAIL) at the Massachusetts Institute of Technology. His research interests include reconfigurable com- puting, self-aware and autonomic systems, hardware-software codesign, and high-performance processors. Santambrogio has a PhD in computing engineering from Politecnico di Milano. He is a senior member of IEEE and a member of the ACM.', 'Direct questions and comments about this article to Xabier Iturbc, 4800 Oak Grove Dr., Pasadena, CA 91109, Xabier.Iturbe@jpl.nasa.gov.']}} %*R3TOS-Based Autonomous Fault-Tolerant Systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6853247 %f/micro/wigedanlb8rocqpvjm7wmzpnf46et5ga.pdf %mbd802ef112188977889a87f5ffc77ba6 %cmicro %@[{'name': 'Gyeonghoon Kim', 'affiliation': 'Korea Advanced Institute of Science and Technology', 'bio': {'p': ['Gyeonghoon Kim is a PhD student in electrical engineering at the Korea Advanced Institute of Science and Technology. His research interests include low-power digital processors with dynamic resource management for computer vision and NoC-based system-on-chip (SoC) design. Kim has an MS in electrical engineering from the Korea Advanced Institute of Science and Technology. He is a student member of IEEE.']}}, {'name': 'Donghyun Kim', 'affiliation': 'Korea Advanced Institute of Science and Technology', 'bio': {'p': ['Donghyun Kim is a research professor in the Mobile Software Platform Research Center at the Korea Advanced Institute of Science and Technology. His research interests include low-power image processing SoCs, NoCs, and DRAM memory controllers. Kim has a PhD in electrical engineering from the Korea Advanced Institute of Science and Technology.']}}, {'name': 'Seongwook Park', 'affiliation': 'Korea Advanced Institute of Science and Technology', 'bio': {'p': ['Seongwook Park is a PhD student in electrical engineering at the Korea Advanced Institute of Science and Technology. His research interests include VLSI implementation for deep machine learning, and cognitive computing for artificial intelligence. Park has an MS in electrical engineering from the Korea Advanced Institute of Science and Technology. He is a student member of IEEE.']}}, {'name': 'Youchang Kim', 'affiliation': 'Korea Advanced Institute of Science and Technology', 'bio': {'p': ['Youchang Kim is a PhD student in electrical engineering at the Korea Advanced Institute of Science and Technology. His research interests include low-power heterogeneous multicore systems, especially energy-efficient NoCs. Kim has an MS in electrical engineering from the Korea Advanced Institute of Science and Technology. He is a student member of IEEE.']}}, {'name': 'Kyuho Lee', 'affiliation': 'Korea Advanced Institute of Science and Technology', 'bio': {'p': ['Kyuho Lee is a PhD student in electrical engineering at the Korea Advanced Institute of Science and Technology. His research interests include development of analog/ digital mixed-mode neural network SoC design, object matching processors, and intelligent vision processors. Lee has an MS in electrical engineering from the Korea Advanced Institute of Science and Technology. He is a student member of IEEE.']}}, {'name': 'Injoon Hong', 'affiliation': 'Korea Advanced Institute of Science and Technology', 'bio': {'p': ['Injoon Hong is a PhD student in electrical engineering at the Korea Advanced Institute of Science and Technology. His research interests include low-power digital processors for computer vision and NoC-based SoC design. Hong has an MS in electrical engineering from the Korea Advanced Institute of Science and Technology. He is a student member of IEEE.']}}, {'name': 'Kyeongryeol Bong', 'affiliation': 'Korea Advanced Institute of Science and Technology', 'bio': {'p': ['Kyeongryeol Bong is a PhD student in electrical engineering at the Korea Advanced Institute of Science and Technology. His research focuses on intelligent vision SoCs. Bong has an MS in electrical engineering from the Korea Advanced Institute of Science and Technology. He is a student member of IEEE.']}}, {'name': 'Hoi-Jun Yoo', 'affiliation': 'Korea Advanced Institute of Science and Technology', 'bio': {'p': ['Hoi-Jun Yoo is a full professor in the Department of Electrical Engineering at the Korea Advanced Institute of Science and Technology. His research interests include NoCs, 3D graphics, bioinspired vision processors, body area networks, biomedical devices and circuits, and memory circuits and systems. Yoo has a PhD in electrical engineering from the Korea Advanced Institute of Science and Technology. He is a fellow of IEEE.', 'Direct questions and comments about this article to Gyeonghoon Kim, #1233, Department of Electrical Engineering, KAIST, 335 Gwahangno, Yuseong-gu, Daejeon 305–701, Korea, ghoon@kaist.ac.kr.']}} %*An Augmented Reality Processor with a Congestion-Aware Network-on-Chip Scheduler %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6981852 %f/micro/5iwibjpxbkmymrtp2sqdclzvadneegjr.pdf %m03cfb706edccb39b397727ddb27cf309 %cmicro %@[{'name': 'Hikaru Tamura', 'affiliation': 'Semiconductor Energy Laboratory', 'bio': {'p': ['Hikaru Tamura is an engineer in the Circuit Design Division at Semiconductor Energy Laboratory, where he is developing low-power processors. Tamura has an AS in electrical engineering from Oyama National College of Technology.']}}, {'name': 'Kiyoshi Kato', 'affiliation': 'Semiconductor Energy Laboratory', 'bio': {'p': ['Kiyoshi Kato is a manager in the Circuit Design Division at Semiconductor Energy Laboratory, where he is developing low-power memories and processors. Kato has a PhD in physics from the University of Tokyo.']}}, {'name': 'Takahiko Ishizu', 'affiliation': 'Semiconductor Energy Laboratory', 'bio': {'p': ['Takahiko Ishizu is an engineer in the Circuit Design Division at Semiconductor Energy Laboratory, where he is developing low-power memories. Ishizu has an ME in engineering from Osaka Prefecture University.']}}, {'name': 'Wataru Uesugi', 'affiliation': 'Semiconductor Energy Laboratory', 'bio': {'p': ['Wataru Uesugi is an engineer in the Circuit Design Division at Semiconductor Energy Laboratory, where he is developing low-power processors. Uesugi has an ME in electrical engineering from Yokohama National University.']}}, {'name': 'Atsuo Isobe', 'affiliation': 'Semiconductor Energy Laboratory', 'bio': {'p': ['Atsuo Isobe is an engineer in the Circuit Design Division at Semiconductor Energy Laboratory, where he is developing low-power processors. Isobe has an ME in materials science and engineering from Nagoya Institute of Technology.']}}, {'name': 'Naoaki Tsutsui', 'affiliation': 'Semiconductor Energy Laboratory', 'bio': {'p': ['Naoaki Tsutsui is a staff engineer in the Circuit Design Division at Semiconductor Energy Laboratory, where he is developing low-power processors. Tsutsui has an MS in computer science from the University of Aizu.']}}, {'name': 'Yasutaka Suzuki', 'affiliation': 'Semiconductor Energy Laboratory', 'bio': {'p': ['Yasutaka Suzuki is an engineer in the Process Management Division at Semiconductor Energy Laboratory, where he is developing process technology for crystalline In-Ga-Zn oxide (CAAC-IGZO). Suzuki has an ME in electronic engineering from University of Electro-Communications.']}}, {'name': 'Yutaka Okazaki', 'affiliation': 'Semiconductor Energy Laboratory', 'bio': {'p': ['Yutaka Okazaki is an engineer in the Process Management Division at Semiconductor Energy Laboratory, where he is developing process technology for CAAC-IGZO. Okazaki has an ME in science and engineering from Nagoya Institute of Technology.']}}, {'name': 'Yukio Maehashi', 'affiliation': 'Semiconductor Energy Laboratory', 'bio': {'p': ['Yukio Maehashi is an adviser at Semiconductor Energy Laboratory, where he has been advising research and development of low-power microcomputer systems. Maehashi has a BE in electrical engineering from Iwate University.']}}, {'name': 'Jun Koyama', 'affiliation': 'Semiconductor Energy Laboratory', 'bio': {'p': ['Jun Koyama is a general manager in the Circuit Design Division at Semiconductor Energy Laboratory, where he is developing thin-film transistors and circuits. Koyama has a BS in physics from Rikkyo University.']}}, {'name': 'Yoshitaka Yamamoto', 'affiliation': 'Semiconductor Energy Laboratory', 'bio': {'p': ['Yoshitaka Yamamoto is a corporate officer and the general manager of Process Management Division at Semiconductor Energy Laboratory. Yamamoto has an ME in applied chemistry from Osaka Prefecture University.']}}, {'name': 'Shunpei Yamazaki', 'affiliation': 'Semiconductor Energy Laboratory', 'bio': {'p': ['Shunpei Yamazaki is the founder and president of Semiconductor Energy Laboratory. Yamazaki has a PhD from Doshisha University. He is a life fellow of IEEE, a member of the Japan Society of Applied Physics, and a foreign member of Royal Swedish Academy of Engineering Sciences.']}}, {'name': 'Masahiro Fujita', 'affiliation': 'University of Tokyo', 'bio': {'p': ['Masahiro Fujita is a professor in the VLSI Design and Education Center (VDEC) at the University of Tokyo, and a technical advisor at Semiconductor Energy Laboratory. His research interests include synthesis and verification of SoC and embedded system designs. Fujita has a PhD in information engineering from the University of Tokyo.']}}, {'name': 'James Myers', 'affiliation': 'ARM', 'bio': {'p': ['James Myers is a staff engineer in the Silicon R&D group at ARM, where he leads research into energy-constrained wireless sensor nodes for the Internet of Things. Myers has an ME in electrical and electronic engineering from Imperial College, London.']}}, {'name': 'Pekka Korpinen', 'affiliation': 'Nokia', 'bio': {'p': ['Pekka Korpinen is a senior researcher at Nokia. His research interests include ultra low-power computing covering both hardware and software. Korpinen has an MS in microelectronic circuit design and a Licentiate of Science in signal processing technology from the Helsinki University of Technology.', 'Direct questions and comments about this article to Hikaru Tamura, Semiconductor Energy Laboratory, 398 Hase, Atsugi-shi, Kanagawa, 243–0036, Japan, ht0898@ sel.co.jp.']}} %*Embedded SRAM and Cortex-M0 Core Using a 60-nm Crystalline Oxide Semiconductor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6981853 %f/micro/ulftmmo01rhrxv3dui4q8fpcykztkjng.pdf %m9bbe8c3c309f3b7c4224bf3e9fb297e7 %cmicro %@[{'name': 'Jun Yao', 'affiliation': 'Nara Institute of Science and Technology', 'bio': {'p': ['Jun Yao is an associate professor in the Graduate School of Information Science at the Nara Institute of Science and Technology. His research focuses on computer architecture, especially low-power consumption and highly reliable architectures. Yao has a PhD in informatics from Kyoto University. He is a member of IEEE, the ACM, the Institute of Electronics, Information and Communication Engineers (IEICE), and the Information Processing Society of Japan (IPSJ).']}}, {'name': 'Yasuhiko Nakashima', 'affiliation': 'Nara Institute of Science and Technology', 'bio': {'p': ['Yasuhiko Nakashima is a professor in the Graduate School of Information Science at the Nara Institute of Science and Technology. His research interests include processor architecture, emulation, CMOS circuit design, and evolutionary computation. Nakashima has a PhD in computer engineering from Kyoto University. He is a member of the IEEE Computer Society, the ACM, the IEICE, and the IPSJ.']}}, {'name': 'Mitsutoshi Saito', 'affiliation': 'Nara Institute of Science and Technology', 'bio': {'p': ['Mitsutoshi Saito is an associate professor at the Niigata University of Management. His research interests include computer architecture, integrated circuit design, and low-power A/D converters. Saito has a PhD in engineering from the Kyushu Institute of Technology, Japan. He is a member of IEEE. He performed the research for the article as a research associate at the Nara Institute of Science and Technology.']}}, {'name': 'Yohei Hazama', 'affiliation': 'Nara Institute of Science and Technology', 'bio': {'p': ['Yohei Hazama is an engineer at Hitachi. His research interests include processor architecture and fault tolerance. Hazama has an MS in engineering from the Nara Institute of Science and Technology, where he performed the work for this article.']}}, {'name': 'Ryosuke Yamanaka', 'affiliation': 'Nara Institute of Science and Technology', 'bio': {'p': ['Ryosuke Yamanaka is an engineer at Fujitsu Laboratories. His research focuses on fault-tolerance techniques. Yamanaka has an MS in engineering from the Nara Institute of Science and Technology, where he performed the work for this article.', 'Direct questions and comments about this article to Jun Yao, Graduate School of Information Science, Nara Institute of Science and Technology, 8916-5 Takayama-Cho, Ikoma 630-0192, Japan, yaojun@is.naist.jp.']}} %*A Flexible, Self-Tuning, Fault-Tolerant Functional Unit Array Processor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6981851 %f/micro/zxf3t8wktq7opabq4gdklclyjunps5of.pdf %m84135b2e86fd4d01b21415d56f34031a %cmicro %@[{'name': 'Shuming Chen', 'affiliation': 'National University of Defense Technology, China', 'bio': {'p': ['Shuming Chen is a professor at the National University of Defense Technology, China. His research interests focus on VLSI design and the effects of radiation on integrated circuits. Chen has a PhD in computer science from the National University of Defense Technology, China.']}}, {'name': 'Yaohua Wang', 'affiliation': 'National University of Defense Technology, China', 'bio': {'p': ['Yaohna Wang is an associated professor at the National University of Defense Technology, China. His research interests include microarchitecture and signal processing. Wang has a PhD in electronic science and technology from the National University of Defense Technology, China.']}}, {'name': 'Sheng Liu', 'affiliation': 'National University of Defense Technology, China', 'bio': {'p': ['Sheng Liu is an associated professor at the National University of Defense Technology, China. His research focuses on memory systems. Liu has a PhD in electronic science and technology from the National University of Defense Technology, China.']}}, {'name': 'Jianghua Wan', 'affiliation': 'National University of Defense Technology, China', 'bio': {'p': ['Jianghua Wan is an associated professor at the National University of Defense Technology, China. His research focuses on VLSI design. Wan has a PhD in computer science from the National University of Defense Technology, China.']}}, {'name': 'Haiyan Chen', 'affiliation': 'National University of Defense Technology, China', 'bio': {'p': ['Haiyan Chen is a professor at the National University of Defense Technology, China. Her research focuses on memory design. Chen has an MS in computer science from the National University of Defense Technology, China.']}}, {'name': 'Hengzhu Liu', 'affiliation': 'National University of Defense Technology, China', 'bio': {'p': ['Hengzhu Liu is a professor at the National University of Defense Technology, China. His research interests include VLSI design and built-in self-test. Liu has a PhD in computer science from the National University of Defense Technology, China.']}}, {'name': 'Kai Zhang', 'affiliation': 'National University of Defense Technology, China', 'bio': {'p': ['Kai Zhang is a PhD student at the National University of Defense Technology, China. His research focuses on VLSI design. Zhang has a PhD in electronic science and technology from the National University of Defense Technology, China.']}}, {'name': 'Xiangyuan Liu', 'affiliation': 'National University of Defense Technology, China', 'bio': {'p': ['Xiangyuan Liu is an associated professor at the National University of Defense Technology, China. His research focuses on circuit design. Liu has a PhD in electronic science and technology from the National University of Defense Technology, China.']}}, {'name': 'Xi Ning', 'affiliation': 'National University of Defense Technology, China', 'bio': {'p': ['Xi Ning is a PhD student at the National University of Defense Technology, China. His research focuses on microwave solid-circuit design. Ning has an MS in electronic science and technology from the National University of Defense Technology, China.', 'Direct questions and comments about this article to Shuming Chen, College of Computer Science and Technology on Parallel and Distributed Processing Laboratory, National University of Defense Technology, Changsha, Hunan, P.R. China, 410073, smchen@nudt.edu.cn.']}} %*FT-Matrix: A Coordination-Aware Architecture for Signal Processing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6679043 %f/micro/waqyf70ncebpokjpr1zg8k2qmie6cwht.pdf %m517506b07765a20f95689fb65aeb3582 %cmicro %@[{'name': 'Xiaofei Wang', 'affiliation': 'University of Minnesota', 'bio': {'p': ['Xiaofei Wang is a design engineer with Advanced Design in the Logic Technology Development group at Intel, where he is involved in the development of embedded memory circuits in advanced CMOS technologies. Wang has a PhD in electrical and computer engineering at the University of Minnesota, where he completed the research for this work. He is a member of IEEE.']}}, {'name': 'John Keane', 'affiliation': 'Intel', 'bio': {'p': ['John Keane is a design engineer with Advanced Design in the Logic Technology Development group at Intel, where he is working on test chip designs for future process technology development. Keane has a PhD in electrical engineering from the University of Minnesota. He is a member of IEEE.']}}, {'name': 'Tony Tae-Hyoung Kim', 'affiliation': 'Nanyang Technological University', 'bio': {'p': ['Tony Tae-Hyoung Kim is an assistant professor in the Department of Electrical and Electronic Engineering at Nanyang Technological University. His research interests include ultra low-power, mixed-mode, digital, and memory circuits in nanoscale CMOS. Kim has a PhD in electrical and computer engineering from the University of Minnesota. He is a member of IEEE.']}}, {'name': 'Pulkit Jain', 'affiliation': 'Intel', 'bio': {'p': ['Pulkit Jain is a design engineer with Advanced Design in the Logic Technology Development group at Intel, where he is working on embedded memories. Jain has a PhD in electrical engineering from the University of Minnesota. He is a member of IEEE.']}}, {'name': 'Qianying Tang', 'affiliation': 'University of Minnesota', 'bio': {'p': ['Qianying Tang is a PhD student in electrical and computer engineering at the University of Minnesota. Her research focuses on the impact of transistor reliability, including aging and random telegraph noise on circuit and system-level performance. Tang has a BS in electrical engineering from the University of Electronic Science and Technology of China. She is a student member of IEEE.']}}, {'name': 'Chris H. Kim', 'affiliation': 'University of Minnesota', 'bio': {'p': ['Chris H. Kim is an associate professor of in the Department of Electrical and Computer Engineering at the University of Minnesota. His research interests include digital, mixed-signal, and memory-circuit design for silicon and nonsilicon technologies, such as spintronics and organic TFTs. Kim has a PhD in electrical and computer engineering from Purdue University. He is a senior member of IEEE.', 'Direct questions and comments about this article to Chris H. Kim, Department of Electrical and Computer Engineering, University of Minnesota, 200 Union Street SE, Minneapolis, MN 55455, chriskim@umn.edu.']}} %*Silicon Odometers: Compact In Situ Aging Sensors for Robust System Design %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6728928 %f/micro/zib03sax6b25rsyopzv8tamhqlxf9ei4.pdf %mf173502f9a9ddb8b6b1cc63b08eb8642 %cmicro %@[{'name': 'Dan Wang', 'affiliation': 'University of Waterloo', 'bio': {'p': ['Dan Wang is a research associate in the Department of Electrical and Computer Engineering at the University of Waterloo. Her research focuses on fault-tolerant computer architectures. Wang has an MS in computer engineering from the Polytechnic Institute of New York University and an MS in microelectronics and solid-state electronics from Xidian University.']}}, {'name': 'Aravindkumar Rajendiran', 'affiliation': 'University of Waterloo', 'bio': {'p': ['Aravindkumar Rajendiran is an Android engineer at Remind. Rajendiran has a BASc in electrical and computer engineering from the University of Waterloo, where he completed the work for this article.']}}, {'name': 'Sundaram Ananthanarayanan', 'affiliation': 'Stanford University', 'bio': {'p': ['Sundaram Ananthanarayanan is a graduate student at the Department of Electrical Engineering at Stanford University. His research interests include computer architecture and real-time embedded systems. Ananthanarayanan has a BE in computer science from Anna University, Guindy.']}}, {'name': 'Hiren Patel', 'affiliation': 'University of Waterloo', 'bio': {'p': ['Hiren Patel is an assistant professor in the Department of Electrical and Computer Engineering at the University of Waterloo. His research focuses on embedded software and hardware systems, including computation, real-time systems, computer architecture, and system-level design. Patel has a PhD in computer engineering from Virginia Tech.']}}, {'name': 'Mahesh V. Tripunitara', 'affiliation': 'University of Waterloo', 'bio': {'p': ['Mahesh V. Tripunitara is an assistant professor in the Department of Electrical and Computer Engineering at the University of Waterloo. His research focuses on security and reliability, including access control, conditional payments, and ultra-reduced instruction set computing. Tripunitara has a PhD in computer science from Purdue University.']}}, {'name': 'Siddharth Garg', 'affiliation': 'New York University', 'bio': {'p': ['Siddharth Garg is an assistant professor in the Department of Electrical and Computer Engineering at New York University. His research focuses on computer hardware and digital system design. Garg has a PhD in electrical and computer engineering from Carnegie Mellon University.', 'Direct questions and comments about this article to Hiren Patel, University of Waterloo, Department of Electrical and Computer Engineering, 200 University Ave W, Waterloo, ON, N2L 3G1, Canada, h.patel@ece.uwaterloo.ca.']}} %*Reliable Computing with Ultra-Reduced Instruction Set Coprocessors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6679035 %f/micro/8kiphvs1u2jc4waro6zgsukzhyeabyx7.pdf %m594b1bca18de3214739c19b5586e2e64 %cmicro %@[{'name': 'Stephen W. Keckler', 'affiliation': 'Nvidia'}, {'name': 'Dean Tullsen', 'affiliation': 'University of California, San Diego'} %*2014 International Symposium on Computer Architecture Influential Paper Award; 2014 Maurice Wilkes Award Given to Ravi Rajwar %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6981854 %f/micro/jkzpm8e4tahzwesw9m6udlxg3dnakuio.pdf %made67872b3bce6993de818e4ac442b70 %cmicro %@[{'name': 'Richard H. Stern', 'affiliation': 'Kellogg Huber Hansen Todd Evans &,amp, Figel', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6981849/6981850/6981850-photo-1-small.gif', 'p': ['Richard H. Stern is an attorney at Kellogg Huber Hansen Todd Evans & Figel and a law professor at George Washington University Law School. Contact him at rstern@khhte.com or rstern@law.gwu.edu.']}} %*Alice v. CLS Bank: Are US Business-Method and Software Patents Doomed? Part 2 %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6981850 %f/micro/0cnb9wpkinutlqsafh4satqrgywdjeer.pdf %mb560f6613a91300068aeca176de50f75 %cmicro %@[{'name': 'Erik R. Altman', 'affiliation': 'Thomas J. Watson Research Center', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6493291/6493295/6493295-photo-1-small.gif', 'p': ['Erik R. Altman is the manager of the Dynamic Optimization Group at the Thomas J. Watson Research Center. Contact him at ealtman@us.ibm.com.']}} %*Hot Chips and the Incomplete Job of Exploiting Them %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6493295 %f/micro/ecfkqgsw8xsubyqikcnyh9l4jmu3r5j6.pdf %mb98252d2d9db2f1dff20a19d4bd46659 %cmicro %@[{'name': 'Christos Kozyrakis', 'affiliation': 'Stanford University', 'bio': {'p': ['Christos Kozyrakis is an associate professor of electrical engineering and computer science at Stanford University. He specializes in architectures, runtime environments, and programming models for parallel computer systems. His research focuses on improving resource efficiency in largescale datacenters and on the design and management of energy-efficient memory and storage systems. Kozyrakis has a PhD in computer science from the University of California at Berkeley. He is a senior member of IEEE and the ACM.']}}, {'name': 'Rumi Zahir', 'affiliation': 'Intel', 'bio': {'p': ['Rumi Zahir leads the Intel Atom System-on-Chip (SoC) architecture team that develops low-power SoCs for handheld form factors. He was also one of the Intel Itanium Processor instruction set architects contributing to privileged instruction set, multiprocessing, memory ordering, and interrupt architecture. Zahir has a PhD in electrical engineering from the Swiss Federal Institute of Technology in Zurich, Switzerland.', 'Direct questions and comments to Christos Kozyrakis at christos@ee.stanford.edu.']}} %*Selected Research from Hot Chips 24 %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6493296 %f/micro/8crlsmble1yshk5j3f7g6rgqxhoewcmt.pdf %mf022cbfdfd40c7a493ad239ed4c568b1 %cmicro %@[{'name': 'Ronald G. Dreslinski', 'affiliation': 'University of Michigan', 'bio': {'p': ['Ronald G. Dreslinski is a research scientist at the University of Michigan. His research focuses on architectures that enable emerging low-power circuit techniques. Dreslinski has a PhD in computer science and engineering from the University of Michigan.']}}, {'name': 'David Fick', 'affiliation': 'University of Michigan', 'bio': {'p': ['David Fick is a research associate at the Michigan Integrated Circuits Lab at the University of Michigan. His research interests include fault tolerance, adaptive circuits and systems, and 3D integrated circuits. Fick has a PhD in computer science and engineering from the University of Michigan.']}}, {'name': 'Bharan Giridhar', 'affiliation': 'University of Michigan', 'bio': {'p': ['Bharan Giridhar is a PhD candidate in the Department of Electrical Engineering at the University of Michigan. His research interests include adaptive computing, robust synchronizer design, and circuit techniques for high performance and low power. Giridhar has an MS in electrical engineering from the University of Michigan.']}}, {'name': 'Gyouho Kim', 'affiliation': 'University of Michigan', 'bio': {'p': ['Gyouho Kim is a PhD candidate in the Department of Electrical Engineering at the University of Michigan. His research interests include ultra low-power and energy-efficient VLSI design. Kim has an MS in electrical engineering from the University of Michigan.']}}, {'name': 'Sangwon Seo', 'affiliation': 'University of Michigan', 'bio': {'p': ['Sangwon Seo is a senior hardware engineer at Qualcomm. His research interests include low-power microarchitecture, parallel computing, and wireless signal processing. Seo has a PhD in electrical engineering and computer science from the University of Michigan, where he performed the work for this article.']}}, {'name': 'Matthew Fojtik', 'affiliation': 'University of Michigan', 'bio': {'p': ['Matthew Fojtik is a PhD candidate in the Department of Electrical Engineering at the University of Michigan. His research interests include architecture-independent timing-speculation techniques and the design of several ultra low-power VLSI systems. Fojtik has an MS in electrical engineering from the University of Michigan.']}}, {'name': 'Sudhir Satpathy', 'affiliation': 'University of Michigan', 'bio': {'p': ["Sudhir Satpathy is a research scientist at Intel's Circuits Research Labs, where he is developing novel high-performance and low-power circuit techniques for next-generation microprocessors. His research interests include on-die interconnect fabrics and hardware security. Satpathy has a PhD in electrical engineering from the University of Michigan, where he performed the work for this article."]}}, {'name': 'Yoonmyung Lee', 'affiliation': 'University of Michigan', 'bio': {'p': ['Yoonmyung Lee is a research fellow at the University of Michigan, where he researches energy-efficient ultra low-power integrated circuits for low-power, highperformance VLSI systems and millimeter-scale wireless sensor systems. Lee has a PhD in electrical engineering from the University of Michigan.']}}, {'name': 'Daeyeon Kim', 'affiliation': 'University of Michigan', 'bio': {'p': ["Daeyeon Kim is a research scientist in Intel's Advanced Design Group, where he works on low-power, high-performance SRAM design, statistical yield analysis, and process variation mitigation techniques. Kim has a PhD in electrical engineering from the University of Michigan, where he performed the work for this article."]}}, {'name': 'Nurrachman Liu', 'affiliation': 'University of Michigan', 'bio': {'p': ['Nurrachman Liu was most recently at Qualcomm Research. His research interests include high-performance digital and custom circuit design, ultra low-power sub- and near-threshold circuit design, VLSI design automation, and EDA for circuit designers and digital design. Liu has a PhD in electrical engineering from the University of Michigan, where he performed the work for this article.']}}, {'name': 'Michael Wieckowski', 'affiliation': 'University of Michigan', 'bio': {'p': ['Michael Wieckowski is a senior research engineer at Mala Geoscience, where he designs high-speed mixed-signal circuits for applications in ground-penetrating radar. Wieckowski has a PhD in electrical and computer engineering from the University of Rochester. He performed the work for this article as a research fellow at the University of Michigan']}}, {'name': 'Gregory Chen', 'affiliation': 'University of Michigan', 'bio': {'p': ["Gregory Chen is a member of Intel's High-Performance Circuits research group. His research interests include networks-on-chip, security, and power management. Chen has a PhD in electrical engineering from the University of Michigan, where he performed the work for this article."]}}, {'name': 'Dennis Sylvester', 'affiliation': 'University of Michigan', 'bio': {'p': ['Dennis Sylvester is a professor in the Electrical Engineering and Computer Science Departments at the University of Michigan and is the director of the Michigan Integrated Circuits Laboratory. His research interests include the design of millimeter-scale computing systems and energy-efficient near-threshold computing for a range of applications. Sylvester has a PhD in electrical engineering from the University of California, Berkeley.']}}, {'name': 'David Blaauw', 'affiliation': 'University of Michigan', 'bio': {'p': ['David Blaauw is a professor in the Electrical Engineering and Computer Science Departments at the University of Michigan. His research focuses on VLSI design, particularly on ultra low-power and high-performance design. Blaauw has a PhD in computer science from the University of Illinois at Urbana-Champaign. He is an IEEE Fellow.']}}, {'name': 'Trevor Mudge', 'affiliation': 'University of Michigan', 'bio': {'p': ['Trevor Mudge is the Bredt Professor of Engineering at the University of Michigan. His research interests include computer architecture, programming languages, VLSI design, and computer vision. Mudge has a PhD in computer science from the University of Illinois. He is a fellow of IEEE and a member of the ACM, the IET, and the British Computer Society.', 'Direct questions and comments about this article to Ronald Dreslinski, University of Michigan, 2260 Hayword Ave., Ann Arbor, MI 48109, rdreslin@umich.edu.']}} %*Centip3De: A 64-Core, 3D Stacked Near-Threshold System %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6415891 %f/micro/o6vlfmqmi2cjwdzx7b0a5xuwrsj1yefk.pdf %me03b895d929f9cfa2370723987cd2377 %cmicro %@[{'name': 'Robert Rogenmoser', 'affiliation': 'SuVolta', 'bio': {'p': ["Robert Rogenmoser is the senior vice president of product development and engineering at SuVolta, where he is responsible for developing the company's design and circuit IP as well as customer enablement. Rogenmoser has a PhD in electrical engineering from ETH Zurich."]}}, {'name': 'Lawrence T. Clark', 'affiliation': 'SuVolta', 'bio': {'p': ['Lawrence T. Clark is the chief architect at Su Volta and a professor in the School of Electrical, Computer, and Energy Engineering at Arizona State University. His research interests include circuits and architectures for low-power and high-performance very-large-scale integration (VLSI), integrated circuit radiation hardening, and computer-aided design for VLSI. Clark has a PhD in electrical engineering from Arizona State University.', 'Direct questions and comments about this article to Robert Rogenmoser, 130-D Knowles Dr., Los Gatos, CA 95032, roro@suvolta.com.']}} %*Reducing Transistor Variability for High Performance Low Power Chips %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6461870 %f/micro/uogtrjawkp0bh62lvoshz5fijfbldu47.pdf %mc82914e3d7d2fe6e244c11b7406313ae %cmicro %@[{'name': 'Gregory Ruhl', 'affiliation': 'Intel', 'bio': {'p': ["Gregory Ruhl is a senior design engineer in the Compute Component Development Organization at Intel, where he works on designing Intel's next-generation processors. His research interests include energy-efficient computing and circuits and microarchitectures for enabling exascale supercomputers. Ruhl has an MS in electrical and computer engineering from the Georgia Institute of Technology."]}}, {'name': 'Saurabh Dighe', 'affiliation': 'Intel', 'bio': {'p': ['Saurabh Dighe is a member of the Advanced Microprocessor Research Team at Intel, where he is involved in the definition, implementation, and validation of future terascale computing technologies. His research interests are in energy-efficient computing and low-power, high-performance circuits. Dighe has an MS in computer engineering from the University of Minnesota.']}}, {'name': 'Shailendra Jain', 'affiliation': 'Intel', 'bio': {'p': ['Shailendra Jain is a technical lead in the Bangalore Design Lab at Intel. His research interests include near-threshold-voltage-range digital circuit design, energy-efficient design techniques for teraflops network-on-chip processors, floating-point arithmetic units, and many-core advance prototyping. Jain has an MTech in microelectronics and VLSI design from the Indian Institute of Technology Madras.']}}, {'name': 'Surhud Khare', 'affiliation': 'Intel', 'bio': {'p': ['Surhud Khare is a research scientist at Intel, where he works on research, development, and prototyping of exascale computing technologies. His research interests include energy-efficient circuits, fine-grained power management techniques, and many-core systems design. Khare has an MS in electrical and computer engineering from the Georgia Institute of Technology.']}}, {'name': 'Sriram R. Vangal', 'affiliation': 'Intel', 'bio': {'p': ['Sriram R. Vangal is a principal research scientist in the Microprocessor Research Labs at Intel, where he has played a lead role in multicore CPU development. His research interests include energy-efficient computing and circuits and microarchitectures for enabling exascale supercomputers. Vangal has a PhD in electrical engineering from Linköping University, Sweden.', 'Direct questions and comments about this article to Gregory Ruhl, JF4–451, 2111 NE 25th Ave., Hillsboro, OR 97124, gregory.e.ruhl@intel.com.']}} %*IA-32 Processor with a Wide-Voltage-Operating Range in 32-nm CMOS %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6461371 %f/micro/53lxnrhfpec1eqidnofoayh6s2xszjkv.pdf %m0648d5c24b1981c597780e6ce12eaa4a %cmicro %@[{'name': 'C. Kevin Shum', 'affiliation': 'IBM', 'bio': {'p': ["C. Kevin Shum is a senior technical staff member in IBM Poughkeepsie's System and Technology Group, and he was the chief architect and design lead of the processor cores for both the System z10 and zEC12. Shum has an MS in electrical engineering from Columbia University. He is a senior member of IEEE and the IEEE Computer Society."]}}, {'name': 'Fadi Busaba', 'affiliation': 'IBM', 'bio': {'p': ["Fadi Busaba is a senior engineer in IBM Poughkeepsie's System and Technology Group. His research interests include microprocessor architecture design and verification and server virtualization. Busaba has a PhD in computer engineering from North Carolina State University. He is a senior member of IEEE and the IEEE Computer Society."]}}, {'name': 'Christian Jacobi', 'affiliation': 'IBM', 'bio': {'p': ["Christian Jacobi is a senior technical staff member in IBM Poughkeepsie's System and Technology Group, where he was responsible for the zEC12's architectural definition and the implementation of the processor-cache hierarchy and the transactional execution facility. Jacobi has a PhD in computer science from Saarland University, Germany.", 'Direct questions and comments about this article to C. Kevin Shum, IBM, Bldg. 705 (MS/312), 2455 South Road, Poughkeepsie, NY 12601, cshum@us.ibm.com.']}} %*IBM zEC12: The Third-Generation High-Frequency Mainframe Microprocessor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6461370 %f/micro/idjo8qj594p2qsan07cxkgmzfxlni6pu.pdf %m29a26adfd93a25e4918c0e3e3d54bcce %cmicro %@[{'name': 'John Feehrer', 'affiliation': 'Oracle', 'bio': {'p': ['John Feehrer is a senior staff engineer at Oracle. His research interests include I/O subsystem architecture, distributed computing, and optical interconnects and switching. Feehrer has a PhD in electrical engineering from the University of Colorado Boulder.']}}, {'name': 'Sumti Jairath', 'affiliation': 'Oracle', 'bio': {'p': ['Sumti Jairath is a senior hardware architect at Oracle. His research interests include hardware-software interaction, software-specific hardware design, and coherence scaling. Jairath has a BTech in electronics and communication engineering from National Institute of Technology, Kurukshetra, India.']}}, {'name': 'Paul Loewenstein', 'affiliation': 'Oracle', 'bio': {'p': ['Paul Loewenstein is a senior principal hardware engineer at Oracle. His research interests include multiprocessor cache coherence protocols, formal memory models, deadlock and livelock avoidance, and error detection and correction. Loewenstein has a PhD in computer science from the University of Cambridge.']}}, {'name': 'Ram Sivaramakrishnan', 'affiliation': 'Oracle', 'bio': {'p': ['Ram Sivaramakrishnan is the director of hardware at Oracle. His research interests include low-power cache design for high throughput multithreaded architectures and low-overhead multiprocessor coherency protocols. Sivaramakrishnan has an MS in electrical engineering from the University of Nevada, Las Vegas.']}}, {'name': 'David Smentek', 'affiliation': 'Oracle', 'bio': {'p': ['David Smentek is a senior hardware architect at Oracle. His research interests include computer architecture, computer arithmetic, performance modeling, and on-chip networks for multicore architectures. Smentek has an MS in electrical engineering from Stanford University.']}}, {'name': 'Sebastian Turullols', 'affiliation': 'Oracle', 'bio': {'p': ['Sebastian Turullols is a hardware director at Oracle. His research interests include high-speed interchip interconnect, power efficiency, and multiprocessor performance scaling. Turullols has an MS in electrical engineering from Stanford University.']}}, {'name': 'Ali Vahidsafa', 'affiliation': 'Oracle', 'bio': {'p': ['Ali Vahidsafa is a senior principal hardware engineer at Oracle. His research interests include characterization and testability of analog-digital interfaces and improving the efficiency of dynamic voltage scaling. Vahidsafa has an MS in electrical engineering from San Diego State University.', 'Direct questions and comments about this article to Sebastian Turullols, Oracle, Floor 3,4120 Network Circle, Santa Clara, CA 95054, sebastian.turullols@oracle.com.']}} %*The Oracle Sparc T5 16-Core Processor Scales to Eight Sockets %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6493301 %f/micro/okzd0e2mw9hs6yiglxjrhufoztaj578l.pdf %m915bdc29dc0b7131c608cba2b0f24778 %cmicro %@[{'name': 'Richard Mateosian', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6493291/6493305/6493305-photo-1-small.gif', 'p': ['Richard Mateosian is a freelance technical writer in the San Francisco Bay Area. Contact him at xrmxrm@gmail.com.']}} %*Ethics of Big Data %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6493305 %f/micro/rujtgwdsevexn5foklyqgpk2y6tmc3qc.pdf %m7124bf6780cbd964a93361f3dbb0995c %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'Kellogg School of Management, Northwestern University', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6493291/6493306/6493306-photo-1-small.gif', 'p': ['Shane Greenstein is the Kellogg Chair in Information Technology at the Kellogg School of Management, Northwestern University. Contact him at greenstein@kellogg.northwestern.']}} %*The Online Honesty Box %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6493306 %f/micro/wyvoasburinuaqnzhkslwk1l5rditp2m.pdf %m865d349682c4c2bad06aef430388e99b %cmicro %@[{'name': 'Erik R. Altman', 'affiliation': 'Thomas J. Watson Research Center', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6523923/6523928/6523928-photo-1-small.gif', 'p': ['', 'Erik R. Altman is the manager of the Dynamic Optimization Group at the Thomas J. Watson Research Center. Contact him at ealtman@us.ibm.com.']}} %*Ten Years of Top Picks %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6523928 %f/micro/shg63ntfuidzwqxzlrmcvjdtlueg82ev.pdf %m71b836610c5676e95e00d837ab608140 %cmicro %@[{'name': 'Babak Falsafi', 'affiliation': 'EPFL', 'bio': {'p': ['Babak Falsafi is a professor of computer and communication sciences at EPFL, and the founding director of EcoCloud, an interdisciplinary research center targeting robust, economic, and environmentally friendly cloud technologies. Falsafi has a PhD in computer science from the University of Wisconsin-Madison. He is a fellow of IEEE.']}}, {'name': 'Gabriel H. Loh', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ['Gabriel H. Loh is a fellow design engineer at AMD Research, the research and advanced development lab for Advanced Micro Devices. His research interests include computer architecture, processor microarchitecture, memory systems, emerging technologies, and 3D die stacking. Loh has a PhD in computer science from Yale University. He is a senior member of IEEE.']}} %*Top Picks from the 2012 Computer Architecture Conferences %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6523926 %f/micro/j3tm1mpfhbkb4uurwyhiopaqtloqfgdx.pdf %m97634e66f63274bacda2ea21a0bf04aa %cmicro %@[{'name': 'Arun Raghavan', 'affiliation': 'University of Pennsylvania', 'bio': {'p': ['Arun Raghavan is a PhD candidate in the Department of Computer and Information Science at the University of Pennsylvania. His research interests are in parallel computer architectures and programming models. Raghavan has a BEng in electronics and communications engineering from R.V. College of Engineering, India.']}}, {'name': 'Yixin Luo', 'affiliation': 'University of Michigan', 'bio': {'p': ['Yixin Luo is a PhD candidate in the Computer Science Department at Carnegie Mellon University. His research interests include parallel computer architecture and efficient storage and memory systems. Luo has a BS in computer engineering from the University of Michigan, where he performed the research for this article.']}}, {'name': 'Anuj Chandawalla', 'affiliation': 'University of Michigan', 'bio': {'p': ['Anuj Chandawalla is an engineer at Qualcomm Technologies. His research interests include low-power circuit design and highperformance applications. Chandawalla has an MS in electrical engineering from the University of Michigan, where he performed the research for this article.']}}, {'name': 'Marios Papaefthymiou', 'affiliation': 'University of Michigan', 'bio': {'p': ['Marios Papaefthymiou is a professor in the Department of Electrical Engineering and Computer Science and Chair of Computer Science and Engineering at the University of Michigan. He is also a cofounder and chief scientist of Cyclos Semiconductor, a start-up company specializing in energy-efficient chips for power-critical applications. Papaefthymiou has a PhD in electrical engineering and computer science from the Massachusetts Institute of Technology.']}}, {'name': 'Kevin P. Pipe', 'affiliation': 'University of Michigan', 'bio': {'p': ['Kevin P. Pipe is an associate professor in the Department of Mechanical Engineering and holds joint appointments with the Department of Electrical Engineering and Computer Science and the Applied Physics Program at the University of Michigan. His research interests include microscale heat transfer, optoelectronic devices, thermoelectric energy conversion, scanning probe techniques, photovoltaic energy conversion, and organic and hybrid organic/inorganic devices. Pipe has a PhD in electrical engineering from the Massachusetts Institute of Technology.']}}, {'name': 'Thomas F. Wenisch', 'affiliation': 'University of Michigan', 'bio': {'p': ['Thomas F. Wenisch is the Morris Wellman Faculty Development Assistant Professor of Electrical Engineering and Computer Science at the University of Michigan and a member of the Advanced Computer Architecture Lab. His research interests focus on computer architecture with emphasis on multiprocessor and multicore systems, multicore programmability, smartphone architecture, datacenter architecture, and performance evaluation methodology. Wenisch has a PhD in electrical and computer engineering from Carnegie Mellon University.']}}, {'name': 'Milo M.K. Martin', 'affiliation': 'University of Pennsylvania', 'bio': {'p': ["Milo M. K. Martin is an associate professor in the Department of Computer and Information Science at the University of Pennsylvania. He coleads Penn's Computer Architecture and Compilers Group. His research interests include multiprocessor and multicore computer architecture, compiler and hardware support for security, and programming models for next-generation architectures. Martin has a PhD in computer science from the University of Wisconsin-Madison."]}} %*Designing for Responsiveness with Computational Sprinting %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6497034 %f/micro/evjocsnr7xipy9y6roq3f5atj0uczvme.pdf %m89b3d545185cc97336a0f67e23325605 %cmicro %@[{'name': 'Hadi Esmaeilzadeh', 'affiliation': 'University of Washington', 'bio': {'p': ['Hadi Esmaeilzadeh is a PhD candidate in the Department of Computer Science and Engineering at the University of Washington. His research interests include developing new technologies and cross-stack solutions to improve the performance and energy efficiency of computer systems for emerging applications. Esmaeilzadeh has an MS in computer science from the University of Texas at Austin and an MS in electrical and computer engineering from the University of Tehran.']}}, {'name': 'Adrian Sampson', 'affiliation': 'University of Washington', 'bio': {'p': ['Adrian Sampson is a PhD student in the Department of Computer Science and Engineering at the University of Washington, where he works on architecture and programming languages. His research focuses on disciplined approximate computing, a set of techniques that safely trade accuracy for efficiency. Sampson has an MS in computer science from the University of Washington.']}}, {'name': 'Luis Ceze', 'affiliation': 'University of Washington', 'bio': {'p': ["Luis Ceze is an associate professor in the Computer Science and Engineering Department at the University of Washington. His research focuses on computer architecture, programming languages, and operating systems to improve multiprocessor systems' programmability, reliability, and energy efficiency. Ceze has a PhD in computer science from the University of Illinois at Urbana-Champaign. He is a member of IEEE, the ACM, and Usenix."]}}, {'name': 'Doug Burger', 'affiliation': 'Microsoft Research', 'bio': {'p': ['Doug Burger is the director of client and cloud applications at Microsoft Research, where he manages strategic research projects covering new user interfaces, datacenter specialization, cloud architectures, and platforms that support personalized online services. Burger has a PhD in computer science from the University of Wisconsin. He is a fellow of IEEE and the ACM.', 'Direct questions and comments about this article to Hadi Esmaeilzadeh, Computer Science and Engineering, Box 352350, Seattle, WA 98195, hadianeh@ cs.washington.edu.', 'cn Selected CS articles and columns are also available for free at http.//ComputingNow.computer.org.']}} %*Neural Acceleration for General-Purpose Approximate Programs %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6487481 %f/micro/jfykjphx2s8zlz3w6fuvmav1bkxerwi4.pdf %m3117379fe8920953b288f91298dd96e5 %cmicro %@[{'name': 'Daniel Wong', 'affiliation': 'University of Southern California', 'bio': {'p': ['Daniel Wong is a PhD student in the Department of Electrical Engineering at the University of Southern California. His research interests include server and datacenter energy efficiency and computer architecture. Wong has a MS in electrical engineering from the University of Southern California. He is a student member of IEEE and the ACM.']}}, {'name': 'Murali Annavaram', 'affiliation': 'University of Southern California', 'bio': {'p': ['Murali Annavaram is an associate professor and Lane Early Career Chair in the Department of Electrical Engineering at the University of Southern California. His research interests include energy efficiency and reliability of computing platforms. Annavaram has a PhD in computer engineering from the University of Michigan. He is a senior member of IEEE and the ACM.']}} %*Scaling the Energy Proportionality Wall with KnightShift %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6487477 %f/micro/xv6tahbq0lgnisudnt4paysow1exo8mm.pdf %m7ec10adb1e6de661e94289ecb408ca4b %cmicro %@[{'name': 'Santosh Nagarakatte', 'affiliation': 'Rutgers University', 'bio': {'p': ['Santosh Nagarakatte is an assistant professor in the Department of Computer Science at Rutgers University. His research interests include hardware-software interfaces spanning compilers, programming languages, and computer architecture. Nagarakatte has a PhD in computer science from the University of Pennsylvania.']}}, {'name': 'Milo M.K. Martin', 'affiliation': 'University of Pennsylvania', 'bio': {'p': ["Milo M. K. Martin is an associate professor in the Department of Computer and Information Science at the University of Pennsylvania. He is also the faculty coleader of Penn's Computer Architecture and Compilers Group. His research interests include scalable microarchitectures, multiprocessor computer architectures, memory systems, and verification. Martin has a PhD in computer science from the University of Wisconsin-Madison."]}}, {'name': 'Steve Zdancewic', 'affiliation': 'University of Pennsylvania', 'bio': {'p': ['Steve Zdancewic is an associate professor in the Department of Computer and Information Science at the University of Pennsylvania. His research interests include programming languages, type systems, theorem proving for verified compilers, and linear logics. Zdan-cewic has a PhD in computer science from Cornell University.', 'Direct questions and comments about this article to Santosh Nagarakatte, Department of Computer Science, Rutgers University, SAS-Computer Science, 110 Frelinghuysen Road, Piscataway, NJ, 08854, santosh.nagarakatte@cs.rutgers.edu.']}} %*Hardware-Enforced Comprehensive Memory Safety %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6487479 %f/micro/47oui2xcesgryualdkcohq8rwdzybjkv.pdf %maf24f206725665c6a2969ab162c80ee7 %cmicro %@[{'name': 'Jonathan Kaveh Valamehr', 'affiliation': 'University of California, Santa Barbara', 'bio': {'p': ['Jonathan Kaveh Valamehr is a PhD candidate in the Department of Electrical and Computer Engineering at the University of California, Santa Barbara. His research interests include using hardware and emerging technologies in computer architecture to develop secure microprocessors. Valamehr has an MS in electrical and computer engineering from the University of California, Santa Barbara. He is a student member of IEEE and the ACM.']}}, {'name': 'Melissa Chase', 'affiliation': 'Microsoft Research', 'bio': {'p': ['Melissa Chase is a researcher in the Cryptography Group at Microsoft Research, focusing on provably secure privacy. Her research interests include cryptography, including anonymous credentials, electronic cash, attribute-based encryption, and re-encryption, as well as more theoretical topics such as zero knowledge proofs and size-hiding computation. Chase has a PhD in computer science from Brown University.']}}, {'name': 'Seny Kamara', 'affiliation': 'Microsoft Research', 'bio': {'p': ['Seny Kamara is a researcher in the Cryptography group at Microsoft Research. His research interests include cloud computing, security, cryptography, and privacy. Kamara has a PhD in computer science from Johns Hopkins University.']}}, {'name': 'Andrew Putnam', 'affiliation': 'Microsoft Research', 'bio': {'p': ['Andrew Putnam is a senior research hardware development engineer in the eXtreme Computing Group at Microsoft Research. His research interests include field-programmable gate arrays (FPGAs), reconfigurable computing, and computer architecture. Putnam has a PhD in computer science from the University of Washington.']}}, {'name': 'Daniel Shumow', 'affiliation': 'Microsoft Research', 'bio': {'p': ['Daniel Shumow is a senior software development engineer specializing in cryptography in the eXtreme Computing Group at Microsoft Research. His research interests include side-channel resistant algorithm design and implementation, and arithmetic geometry applied to cryptography. Shumow has an MS in mathematics from the University of Washington.']}}, {'name': 'Vinod Vaikuntanathan', 'affiliation': 'University of Toronto', 'bio': {'p': ['Vinod Vaikuntanathan is an assistant professor in the Computer Science Department at the University of Toronto. His research interests include cryptography and privacy. Vaikuntanathan has a PhD in computer science from the Massachusetts Institute of Technology.']}}, {'name': 'Timothy Sherwood', 'affiliation': 'University of California, Santa Barbara', 'bio': {'p': ['Timothy Sherwood is a professor in the Computer Science Department at the University of California, Santa Barbara. His research interests include high-performance and high-assurance embedded systems. Sherwood has a PhD in computer science and engineering from the University of California, San Diego.', 'cn Selected CS articles and columns are also available for free at http://ComputingNow.computer.org.']}} %*Inspection-Resistant Memory Architectures %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6487482 %f/micro/q7lafjv1lowp98euszbbdinqyjxuzetm.pdf %mfb77076c5905b057089a40b480a628fe %cmicro %@[{'name': 'Siva Kumar Sastry Hari', 'affiliation': 'University of Illinois at Urbana-Champaign', 'bio': {'p': ['Siva Kumar Sastry Hari is a PhD student in the Department of Computer Science at the University of Illinois at Urbana-Champaign. His research interests include computer architecture, reliability-aware systems, and energy-efficient computing. Hari has an MS in computer science from the University of Illinois at Urbana-Champaign.']}}, {'name': 'Sarita V. Adve', 'affiliation': 'University of Illinois at Urbana-Champaign', 'bio': {'p': ['Sarita V. Adve is a professor in the Department of Computer Science at the University of Illinois at Urbana-Champaign. Her research interests include computer architecture and systems, parallel computing, and power and reliability-aware systems. Adve has a PhD in computer science from the University of Wisconsin-Madison. She is a fellow of IEEE and the ACM.']}}, {'name': 'Helia Naeimi', 'affiliation': 'Intel', 'bio': {'p': ['Helia Naeimi is a research scientist at Intel. Her research interests lie at the intersection of reliability, low power, and efficient computing. Naeimi has a PhD in computer science from the California Institute of Technology.']}}, {'name': 'Pradeep Ramachandran', 'affiliation': 'Intel', 'bio': {'p': ['Pradeep Ramachandran is a performance architect at Intel, focusing on challenges in platform-level performance for future client and SoC processors. His research interests include architectures for hardware reliability, quality of service in the memory subsystem, and the performance and reliability of platform-level components. Ramachandran has a PhD in computer science from the University of Illinois at Urbana-Champaign.']}} %*Relyzer: Application Resiliency Analyzer for Transient Faults %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6487478 %f/micro/2krddfz9ovbtplcvhjgwt1a7awi5qhpn.pdf %m3535cc27a19d1bbdf4f33095865f255e %cmicro %@[{'name': 'John Demme', 'affiliation': 'Columbia University', 'bio': {'p': ['John Demme is a PhD candidate in the Computer Architecture and Security Technologies Lab at Columbia University. His research interests include program characterization and data-intensive computing systems. Demme has an MS in computer science from Columbia University. He is a member of the ACM.']}}, {'name': 'Robert Martin', 'affiliation': 'Columbia University', 'bio': {'p': ['Robert Martin is a software engineer at Google. His research interests include computer architecture security and systems architecture. Martin has an MS in computer science from Columbia University, where he performed the work for this article.']}}, {'name': 'Adam Waksman', 'affiliation': 'Columbia University', 'bio': {'p': ['Adam Waksman is a PhD candidate in the Computer Architecture and Security Technologies Lab at Columbia University. His research interests include computer architecture and hardware and computer systems security. Waksman has an MPhil in computer science from Columbia University.']}}, {'name': 'Simha Sethumadhavan', 'affiliation': 'Columbia University', 'bio': {'p': ['Simha Sethumadhavan is an associate professor of computer science at Columbia University, where he leads the Computer Architecture and Security Technologies Lab. His research interests include hardware support for security and energy-efficient computer architectures. Sethumadhavan has a PhD in computer science from the University of Texas at Austin.']}} %*A Quantitative, Experimental Approach to Measuring Processor Side-Channel Security %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6484049 %f/micro/mzqjrhx4aluj2xfonloe6i73qv0i1kps.pdf %me3e4313dd3474aa9860077741cea7193 %cmicro %@[{'name': 'Timothy G. Rogers', 'affiliation': 'University of British Columbia', 'bio': {'p': ['Timothy G. Rogers is a PhD candidate in the Department of Electrical and Computer Engineering at the University of British Columbia. His research interests include many-core accelerators. Rogers has a BEng in electrical engineering from McGill University.']}}, {'name': "Mike O'Connor", 'affiliation': 'AMD Research', 'bio': {'p': ["Mike O'Connor is a Senior Research Scientist at NVIDIA. This work was performed while he was at AMD Research. O'Connor has an MS in electrical engineering from the University of Texas at Austin. He is a senior member of IEEE and a member of the ACM."]}}, {'name': 'Tor M. Aamodt', 'affiliation': 'University of British Columbia', 'bio': {'p': ['Tor M. Aamodt is an associate professor in the Department of Electrical and Computer Engineering at the University of British Columbia. His research interests include many-core accelerators, heterogeneous multicore processors, and analytical performance modeling of processor architectures. Aamodt has a PhD in electrical and computer engineering from the University of Toronto. He is a member of IEEE and the ACM.', 'Direct questions and comments about this article to Timothy G. Rogers, 2332 Main Mall, Vancouver, BC, Canada V6T 1 Z4, tgrogers@ece.ubc.ca.']}} %*Cache-Conscious Thread Scheduling for Massively Multithreaded Processors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6487475 %f/micro/osusnrkf8ybtg7vb9yciile6jmx2qhvo.pdf %ma2c2608d32061df9632237d261ce2db4 %cmicro %@[{'name': 'Melanie Kambadur', 'affiliation': 'Columbia University', 'bio': {'p': ['Melanie Kambadur is a PhD candidate in the Computer Science Department at Columbia University. Her research interests include hardware and software performance interactions and compilers. Kambadur has an MS in computer science from Columbia University.']}}, {'name': 'Kui Tang', 'affiliation': 'Columbia University', 'bio': {'p': ['Kui Tang is an undergraduate student in the Applied Physics and Applied Mathematics Department at Columbia University. His research interests include parallel programming models and large-scale machine learning. He is a member of the ACM and SIAM.']}}, {'name': 'Martha A. Kim', 'affiliation': 'Columbia University', 'bio': {'p': ['Martha A. Kim is an assistant professor in the Computer Science Department at Columbia University. Her research interests include computer architecture, parallel hardware and software systems, and energy-efficient computation on big data. Kim has a PhD in computer science from the University of Washington. She is a member of IEEE and the ACM.']}} %*Parallel Block Vectors: Collection, Analysis, and Uses %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6487476 %f/micro/ytbry0mpvnsofpiec13evuwd7aohanjq.pdf %m697cb056eb51741abb3c80e9b29e5348 %cmicro %@[{'name': 'Abhayendra Singh', 'affiliation': 'University of Michigan', 'bio': {'p': ['Abhayendra Singh is a graduate student in the Department of Electrical Engineering and Computer Science at the University of Michigan. His research interests include parallel programming models, software-hardware interface, and parallel architecture. Singh has an MTech in computer science and engineering from the Indian Institute of Technology, Kanpur. He is a member of the ACM.']}}, {'name': 'Satish Narayanasamy', 'affiliation': 'University of Michigan', 'bio': {'p': ['Satish Narayanasamy is an assistant professor in the Department of Electrical Engineering and Computer Science at the University of Michigan. His research interests include computer architecture and systems, with a special focus on concurrency. Narayanasamy has a PhD in computer science and engineering from the University of California, San Diego.']}}, {'name': 'Daniel Marino', 'affiliation': 'Symantec Research Labs', 'bio': {'p': ['Daniel Marino is a researcher at Symantec Research Labs. His research interests include programming languages, parallel programming models, and security. Marino has a PhD in computer science from the University of California, Los Angeles.']}}, {'name': 'Todd Millstein', 'affiliation': 'University of California', 'bio': {'p': ['Todd Millstein is an associate professor in the Computer Science Department at the University of California, Los Angeles. His research focuses on making software systems easier to create, maintain, understand, and validate. Millstein has a PhD in computer science from the University of Washington.']}}, {'name': 'Madanlal Musuvathi', 'affiliation': 'Microsoft Research', 'bio': {'p': ['Madanlal Musuvathi is a senior researcher at Microsoft Research, where he works on various aspects of concurrent and parallel systems, including program analysis, testing, verification, model checking, and memory consistency models. Musuvathi has a PhD in computer science from Stanford University.', 'Direct questions and comments about this article to Satish Narayanasamy, Bob and Betty Beyster Building, Room 4721, 2260 Hayward St., Ann Arbor, MI 48109–2121, nsatish@umich.edu.', 'cn Selected CS articles and columns are also available for free at http://ComputingNow.computer.org.']}} %*A Safety-First Approach to Memory Models %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6493304 %f/micro/jox6rfwsuozv7lyge3yflhbqwbuzjivm.pdf %m594127926258bf40afb3b61632c34ffa %cmicro %@[{'name': 'Mahdi Nazm Bojnordi', 'affiliation': 'University of Rochester', 'bio': {'p': ['Mahdi Nazm Bojnordi is a doctoral candidate in electrical and computer engineering at the University of Rochester. His research focuses on designing main memory controllers capable of performing application-specific performance and energy-efficiency optimizations. Nazm Bojnordi has an MS in electrical and computer engineering from the University of Tehran.']}}, {'name': 'Engin Ipek', 'affiliation': 'University of Rochester', 'bio': {'p': ['Engin Ipek is an assistant professor in the Departments of Computer Science and Electrical and Computer Engineering at the University of Rochester. His research focuses on computer architecture, with an emphasis on multicore architectures, hardware-software interaction, and highperformance memory systems. Ipek has a PhD in electrical and computer engineering from Cornell University.']}} %*Programmable DDRx Controllers %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6487474 %f/micro/lr9jjxpvhydayxncib1uungoa0pmfq72.pdf %ma25a4d0f09ae1a6b93f3d8c27631558a %cmicro %@[{'name': 'Richard Mateosian', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6523923/6523932/6523932-photo-1-small.gif', 'p': ['Richard Mateosian is a freelance technical writer in the San Francisco Bay Area. Contact him at xrmxrm@gmail.com.']}} %*Unconscious Meaning [review of "A User's Guide to Thought and Meaning"; Jackendoff, R.; 2012)] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6523932 %f/micro/qr5ngagih8evkm2f4ylh9pltp6yjsxs7.pdf %m2c84c0c5ef6ffaa01fb0681f5f6c9f78 %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'Kellogg School of Management', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6523923/6523929/6523929-photo-1-small.gif', 'p': ['Shane Greenstein is the Kellogg Chair in Information Technology at the Kellogg School of Management, Northwestern University. Contact him at greenstein@kellogg.northwestern.edu.']}} %*Differentiated Platforms %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6523929 %f/micro/rxyf2uaaolltp5jhsq1qjzwomm8gzf6e.pdf %mda2872e04d1383f9a1d41c477b3e23d3 %cmicro %@[{'name': 'Erik R. Altman', 'affiliation': 'Thomas J. Watson Research Center', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6585307/6585410/6585410-photo-1-small.gif', 'p': ['', 'Erik R. Altman is the manager of the Dynamic Optimization Group at the Thomas J. Watson Research Center. Contact him at ealtman@us.ibm.com.']}} %*Reliability, Theme Issues, and Plagiarism %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6585410 %f/micro/gxrwngvkjbj71qr9uk2abz3t46dm5ixs.pdf %m6d1862938cee087f148102e1e1ee085b %cmicro %@[{'name': 'Vijay Janapa Reddi', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ['Vijay Janapa Reddi is an assistant professor in the Department of Electrical and Computer Engineering at the University of Texas at Austin. His research interests focus on the interactions between hardware and software to explore new opportunities and synergies for cross-layer solutions that improve processor-and system-level power, performance, and reliability. Dr. Janapa Reddi has a PhD in computer science from Harvard University.', 'Please direct questions and comments about the articles in this special issue to Vijay Janapa Reddi, 2501 Speedway, ENS 530, University of Texas at Austin, C0803, Austin, TX 78712, vj@ece.utexas.edu.']}} %*Reliability-Aware Microarchitecture Design [Guest editor's introduction] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6585396 %f/micro/u39zdxmpjl61wgotf2a5b87bqfrtvmjp.pdf %m4bbdf316861652f0f4faf73a9c736e0e %cmicro %@[{'name': 'Ulya R. Karpuzcu', 'affiliation': 'University of Minnesota', 'bio': {'p': ["Ulya R. Karpuzcu is an assistant professor in the Department of Electrical and Computer Engineering at the University of Minnesota. Her research focuses on the impact of process technology on computer architecture. Karpuzcu has a PhD in electrical and computer engineering from the University of Illinois at Urbana-Champaign. She's a member of IEEE."]}}, {'name': 'Nam Sung Kim', 'affiliation': 'University of Wisconsin-Madison', 'bio': {'p': ["Nam Sung Kim is an associate professor in the Department of Electrical and Computer Engineering at the University of Wisconsin-Madison. His research interests include low-power and high-performance circuits, circuit-microarchitecture codesigns, CAD algorithms, and bio-inspired computing systems. Kim has a PhD in computer science and engineering from the University of Michigan, Ann Arbor. He's a senior member of IEEE."]}}, {'name': 'Josep Torrellas', 'affiliation': 'University of Illinois at Urbana-Champaign', 'bio': {'p': ["Josep Torrellas is a professor in the Department of Computer Science at the University of Illinois at Urbana-Champaign. His research interests include multiprocessor computer architecture, thread-level speculation, low-power design, and hardware and software reliability. Torrellas has a PhD in electrical engineering from Stanford University. He's a fellow of IEEE and the ACM.", 'Direct questions and comments about this article to Ulya R. Karpuzcu, 4–174 Keller Hall, 200 Union Street S.E., Minneapolis, MN 55455, ukarpuzc@umn.edu.']}} %*Coping with Parametric Variation at Near-Threshold Voltages %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6527886 %f/micro/pksifvlr7duifmctmcxjw3q6tyogjz0h.pdf %me19f2c4f2dc34286640a661dd4ad017b %cmicro %@[{'name': 'Hao Wang', 'affiliation': 'University of Wisconsin-Madison', 'bio': {'p': ['Hao Wang is a PhD student in the Department of Electrical and Computer Engineering at the University of Wisconsin-Madison. His research focuses on architecting power-efficient computing systems. Wang has a BS in microelectronics from Peking University.']}}, {'name': 'Nam Sung Kim', 'affiliation': 'University of Wisconsin-Madison', 'bio': {'p': ["Nam Sung Kim is an associate professor in the Department of Electrical and Computer Engineering at the University of Wisconsin-Madison. His research interests include low-power and high-performance circuits, circuit-microarchitecture codesigns, CAD algorithms, and bio-inspired computing systems. Kim has a PhD in computer science and engineering from the University of Michigan, Ann Arbor. He's a senior member of IEEE.", 'Direct questions and comments about this article to Nam Sung Kim, University of Wisconsin-Madison, 1415 Engineering Dr., Madison, WI 53706, nskim@engr.wisc.edu.']}} %*Improving Throughput of Power-Constrained Many-Core Processors Based on Unreliable Devices %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6527885 %f/micro/nr0zu2sqbpaey6gxjddvuglobtaswij3.pdf %md245b8afc94fe4c735005ffd51cc60de %cmicro %@[{'name': 'David J. Palframan', 'affiliation': 'University of Wisconsin-Madison', 'bio': {'p': ["David J. Palframan is a research assistant in the Department of Electrical and Computer Engineering at the University of Wisconsin-Madison. His research interests include low-cost error mitigation and reliable computer architectures. Palframan has an MS in computer engineering from the University of Wisconsin-Madison. He's a student member of IEEE."]}}, {'name': 'Nam Sung Kim', 'affiliation': 'University of Wisconsin-Madison', 'bio': {'p': ["Nam Sung Kim is an associate professor in the Department of Electrical and Computer Engineering at the University of Wisconsin-Madison. His research interests include low-power and high-performance circuits, circuit-microarchitecture codesigns, CAD algorithms, and bio-inspired computing systems. Kim has a PhD in computer science and engineering from the University of Michigan, Ann Arbor. He's a senior member of IEEE."]}}, {'name': 'Mikko H. Lipasti', 'affiliation': 'University of Wisconsin-Madison', 'bio': {'p': ["Mikko H. Lipasti is the Philip Dunham Reed Professor of Electrical and Computer Engineering at the University of Wisconsin-Madison. His research interests include high-performance, low-power, and reliable processor cores, networks on chips (NoCs) for many-core processors, and fundamentally new, biologically inspired computation models. Lipasti has a PhD in computer engineering from Carnegie Mellon University. He's a fellow of IEEE.", 'Direct questions and comments about this article to David Palframan, 1415 Engineering Drive, Madison, WI, 53705, palframan@wisc.edu.']}} %*Resilient High-Performance Processors with Spare RIBs %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6527888 %f/micro/ks4lr0yc25pxtbe97mfcetxayvzimfjv.pdf %m4007fe5c5872944fd9903af019311ece %cmicro %@[{'name': 'Charles R. Lefurgy', 'affiliation': 'IBM', 'bio': {'p': ['Charles R. Lefurgy is a research staff member and master inventor at the IBM Austin Research Lab, where he focuses on power management for servers and data centers. He contributed to the power management firmware in Power6 and Power7 servers and the IBM Active Energy Manager product used to monitor data center power. Lefurgy has a PhD in computer science and engineering from the University of Michigan. He is a senior member of IEEE and the ACM.']}}, {'name': 'Alan J. Drake', 'affiliation': 'IBM', 'bio': {'p': ['Alan J. Drake is a research staff member at the IBM Austin Research Lab. His research focuses on developing sensors that measure timing margin in real time in microprocessors. Drake has a PhD in electrical engineering from the University of Michigan. He is a member of IEEE.']}}, {'name': 'Michael S. Floyd', 'affiliation': 'IBM', 'bio': {'p': ['Michael S. Floyd is the architect and lead for the Power7+ EnergyScale design at the IBM Austin Server and Technology Group. His work has focused on IBM server development, including hardware bring-up, test, debug, and RAS, along with design, lead, and microarchitect roles on the Power4, Power5, and Power6 processors and support chips. Floyd has an MS in electrical engineering from Stanford University. He is an IBM master inventor.']}}, {'name': 'Malcolm S. Allen-Ware', 'affiliation': 'IBM', 'bio': {'p': ['Malcolm S. Allen-Ware is a distinguished engineer and master inventor reporting to the director of the IBM Austin Research Lab. His research interests include memory sub-systems, IBM flash storage systems, and dynamic power, performance, and reliability optimization across all IBM systems using Intel, Power, and mainframe z processors. Allen-Ware has an MS in communications theory, digital signal processing, and computer architecture from North Carolina State University.']}}, {'name': 'Bishop Brock', 'affiliation': 'IBM', 'bio': {'p': ['Bishop Brock is a senior scientist in the IBM Systems and Technology Group. His work on the Power7 project has included the development of hardware verification, micro-architectural validation, and power and performance prediction methodologies for power management hardware and firmware systems. Brock has an MS in computer science from the University of Texas at Austin. He is a member of the ACM.']}}, {'name': 'José, A. Tierno', 'affiliation': 'Apple', 'bio': {'p': ['José A. Tierno is a research scientist at Apple. His research interests include self-timed digital circuits and digital replacement of analog circuits. Tierno has a PhD in computer science from the California Institute of Technology.']}}, {'name': 'John B. Carter', 'affiliation': 'IBM', 'bio': {'p': ['John B. Carter leads the Future Systems half of IBM Research Austin, with an emphasis on energy-efficient system design, distributed systems, runtime environments for cloud-delivered mobile services, storage, and data center networking. Carter has a PhD in computer science from Rice University. He is a senior member of IEEE.']}}, {'name': 'Robert W. Berry', 'affiliation': 'IBM', 'bio': {'p': ['Robert W. Berry Jr. is the system characterization lead for Power systems at the IBM Austin Server and Technology Group. His previous work has focused on validation for PowerPC processors and design and test of mainframe multichip modules. Berry has an MSE in computer engineering from Syracuse University. He is an IBM master inventor.', 'Direct questions and comments about this article to Charles R. Lefurgy, IBM, 11501 Burnet Rd., Austin, TX 78758, lefurgy@us.ibm.com.']}} %*Active Guardband Management in Power7+ to Save Energy and Maintain Reliability %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6509881 %f/micro/mqpvyax71trbhcf8jldgqgoxwvn50luo.pdf %m503f78368d817dd6068a2a4148f9697c %cmicro %@[{'name': 'Veit B. Kleeberger', 'affiliation': 'TU Mü,nchen', 'bio': {'p': ['Veit B. Kleeberger is a research assistant in the Institute for Electronic Design Automation at TU München. His research focuses on EDA methods supporting cross-layer reliability design. Kleeberger has a Dipl.-Ing. in information technology from TU München.']}}, {'name': 'Christina Gimmler-Dumont', 'affiliation': 'TU Kaiserslautern', 'bio': {'p': ['Christina Gimmler-Dumont is a research assistant in the Microelectronic Systems Design Research Group at TU Kaiserslautern. Her research interests include algorithms and very large-scale integration (VLSI) architectures for MIMO-BICM systems, iteration control methods, and hardware reliability issues in systems on chips (SoCs). Gimmler-Dumont has a Diploma in electrical engineering from TU Kaiserslautern.']}}, {'name': 'Christian Weis', 'affiliation': 'TU Kaiserslautern', 'bio': {'p': ['Christian Weis is a research assistant In the Microelectronic Systems Design Research Group at TU Kaiserslautern. His research interests include 3D-integrated DRAM, DRAM controller design, and heterogeneous multiprocessor SoCs. Weis has a Diploma in electrical engineering from TU Kaiserslautern.']}}, {'name': 'Andreas Herkersdorf', 'affiliation': 'TU Mü,nchen', 'bio': {'p': ["Andreas Herkersdorf is the chair professor for integrated systems in the Department of Electrical Engineering and Information Technology at TU München. His research interests include application-specific multiprocessor architectures, IP network processing, networks on chips (NoCs), system-level SoC modeling and design space exploration methods, and self-adaptive fault-tolerant computing. Herkersdorf has a Dr.sc.techn. in electrical engineering from ETH Zurich. He's a senior member of IEEE."]}}, {'name': 'Daniel Mueller-Gritschneder', 'affiliation': 'TU Mü,nchen', 'bio': {'p': ['Daniel Mueller-Gritschneder is a postdoctoral researcher at the Institute for Electronic Design Automation at TU München. His research interests include embedded-system modeling and application-specific NoC synthesis. Mueller-Gritschneder has a Dr.-Ing. in electrical engineering from TU München.']}}, {'name': 'Sani R. Nassif', 'affiliation': 'IBM Research Austin', 'bio': {'p': ['Sani R. Nassif is a senior research staff member at IBM Research Austin. His research focuses on applying VLSI know-how to the area of cancer radiation therapy. Nassif has a PhD in electrical and computer engineering from Carnegie Mellon University.']}}, {'name': 'Ulf Schlichtmann', 'affiliation': 'TU Mü,nchen', 'bio': {'p': ['Ulf Schlichtmann is the chair professor for Electronic Design Automation at TU München. His research interests include computer-aided design of electronic circuits and systems, with an emphasis on designing robust systems. Schlichtmann has a Dr.-Ing. in electrical engineering from TU München.']}}, {'name': 'Norbert Wehn', 'affiliation': 'TU Kaiserslautern', 'bio': {'p': ["Norbert Wehn is the microelectronic systems design chair in the Department of Electrical Engineering and Information Technology at TU Kaiserslautern. His research interests include VLSI architectures for mobile communication, forward error correction techniques, low-power, advanced SoC architectures, and reliability issues in SoCs. Wehn has a Dr.- Ing. in electrical engineering from TU Darmstadt. He's a senior member and golden core member of IEEE.", 'Direct questions and comments about this article to Veit B. Kleeberger, TU München Institute for Electronic Design Automation, Arcisstr. 21, D-80333 Munich, Germany, kleeberger@tum.de.']}} %*A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6527887 %f/micro/wbj5krwf9enh8czivzxovpnueglgk47m.pdf %m233da943b2d10168be9c0af39fb9dd41 %cmicro %@[{'name': 'Lukasz G. Szafaryn', 'affiliation': 'University of Virginia', 'bio': {'p': ['Lukasz G. Szafaryn is a PhD student in the Department of Computer Engineering at the University of Virginia. His research focuses on the architecture of resilient and highperformance computer systems. Szafaryn has an MS in electrical engineering from the University of Alabama at Birmingham. He is a member of IEEE.']}}, {'name': 'Brett H. Meyer', 'affiliation': 'McGill University', 'bio': {'p': ["Brett H. Meyer is an assistant professor in the Department of Electrical and Computer Engineering at McGill University. His research focuses on the design and architecture of resilient computer systems. Meyer has a PhD in electrical and computer engineering from Carnegie Mellon University. He's a member of IEEE."]}}, {'name': 'Kevin Skadron', 'affiliation': 'University of Virginia', 'bio': {'p': ["Kevin Skadron is a professor in and chair of the Department of Computer Science at the University of Virginia. His research focuses on architectures for power, thermal, and reliability management. Skadron has a PhD in computer science from Princeton University. He's a fellow of IEEE."]}} %*Evaluating Overheads of Multibit Soft-Error Protection in the Processor Core %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6527889 %f/micro/2s3oycxmaahppjjwnrzwqezgn0mebb4f.pdf %m9a5f8da120187657379e29186c913ea6 %cmicro %@[{'name': 'Youngtaek Kim', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ['Youngtaek Kim is a graphics hardware engineer in the Visual and Parallel Computing Group at Intel. His research interests include reliability aware microprocessor design, performance and power optimization, and system level design methodology. Kim has a PhD in computer engineering from the University of Texas at Austin. He completed the work for this article while he was a PhD student at the University of Texas at Austin and a graduate intern at Advanced Micro Devices.']}}, {'name': 'Lizy Kurian John', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ["Lizy Kurian John is the B.N. Gafford Professor in Electrical Engineering at the University of Texas at Austin. Her research interests include high-performance processor and memory architectures, low-power design, reconfigurable architectures, and workload characterization. John has a PhD in computer engineering from Pennsylvania State University. She's a fellow of IEEE."]}}, {'name': 'Sanjay Pant', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ['Sanjay Pant is a senior hardware engineer in the Global Circuits Group at Nvidia. His research interests include low-power circuit design and power management. Pant has a PhD in electrical engineering from the University of Michigan, Ann Arbor. He completed the work for this article while at Advanced Micro Devices.']}}, {'name': 'Srilatha Manne', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ["Srilatha Manne is a principal member of the technical staff at Advanced Micro Devices, where she leads the energy utilization effort on AMD's Exascale FastForward project. Her research focuses on low-power, highperformance processor architectures. Manne has a PhD in electrical engineering from the University of Colorado, Boulder."]}}, {'name': 'Michael Schulte', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ["Michael Schulte is a senior fellow with Advanced Micro Devices, where he is a principal investigator and technical lead on AMD's FastForward Extreme-Scale Computing Research and Development Project. His research interests include power-efficient processor design, heterogeneous processor architectures, and high-performance computing. Schulte has a PhD in electrical engineering from the University of Texas at Austin."]}}, {'name': 'W. Lloyd Bircher', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ['W. Lloyd Bircher is the head of the Advanced System Power Modeling Group at Advanced Micro Devices. His research interests include thermal and power-constrained computing, software-and hardware-directed power management, and performance evaluation. Bircher has a PhD in computer engineering from the University of Texas at Austin.']}}, {'name': 'Madhu Saravana Sibi Govindan', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ['Madhu Saravana Sibi Govindan is a senior design engineer at Advanced Micro Devices. His research interests include architectural power modeling for CPUs, GPUs, and fullsystem power modeling, and novel power management techniques. Govindan has a PhD in computer science from the University of Texas at Austin.']}} %*Automating Stressmark Generation for Testing Processor Voltage Fluctuations %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6527881 %f/micro/5rrzftaeqlmsw19nugwus6dtgqjay0co.pdf %mffcbe591552a934d8a135a5923951f79 %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'Northwestern University', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6585307/6585392/6585392-photo-1-small.gif', 'p': ['Shane Greenstein is the Kellogg Chair in Information Technology at the Kellogg School of Management, Northwestern University. Contact him at greenstein@kellogg.northwestern.edu.']}} %*Platform Conflicts [Micro Economics] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6585392 %f/micro/vqhu4mdehsp9xm0znaxtbefw6ukojlwa.pdf %mf4a4bbd3029359a14fd074ef9b9f6b28 %cmicro %@[{'name': 'Erik R. Altman', 'affiliation': 'Thomas J. Watson Research Center', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6629996/6630023/6630023-photo-1-small.gif', 'p': ['Erik R. Altman is the manager of the Dynamic Optimization Group at the Thomas J. Watson Research Center. Contact him at ealtman@us.ibm.com.']}} %*Dark Silicon and Dangerous Predictions %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6630023 %f/micro/ap5gsjl9ex8ox2c4sykj3ohdkgda6emf.pdf %mccdb448d5e55416f8d497201d69330e4 %cmicro %@[{'name': 'Michael B. Taylor', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Michael B. Taylor is an associate professor in the Department of Computer Science and Engineering at the University of California, San Diego, where he leads the Center for Dark Silicon. His research interests include dark silicon, chip design, parallelization tools, and Bitcoin computing systems. Taylor has a PhD in electrical engineering and computer science from the Massachusetts Institute of Technology.']}}, {'name': 'Steven Swanson', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Steven Swanson is an associate professor in the Computer Science and Engineering Department at the University of California, San Diego, where he leads the Non-Volatile Systems Laboratory. His research interests include architectural systems and security issues surrounding nonvolatile, solid-state memories as well as dark silicon architecture and multithreading. Swanson has a PhD in computer science from the University of Washington.', 'Direct questions and comments about this article to Michael B. Taylor at mbtaylor@ucsd.edu or to Steven Swanson at swanson@cs.ucsd.edu.']}} %*Dark Silicon [Guest editors' introduction] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6630021 %f/micro/mtpbnsg7lwruq0yfp3w5cdrmo8djcbu2.pdf %mae1813c78f056060fd6fdbec0f8e131a %cmicro %@[{'name': 'Michael B. Taylor', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Michael B. Taylor is an associate professor in the Department of Computer Science and Engineering at the University of California, San Diego, where he leads the Center for Dark Silicon. His research interests include dark silicon, chip design, parallelization tools, and Bitcoin computing systems. Taylor has a PhD in electrical engineering and computer science from the Massachusetts Institute of Technology.', 'Direct questions and comments about this article to Michael B. Taylor, 9500 Gilman Drive, MC 0404 EBU 3B 3202, La Jolla, CA 92093–0404, mbtaylor@ucsd.edu.']}} %*A Landscape of the New Dark Silicon Design Regime %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6583151 %f/micro/uhljegrip0pbgh8txidwqc9comx1kntn.pdf %mc5893d0c71e4b07c6f3a2a23ee1885bb %cmicro %@[{'name': 'Arun Raghavan', 'affiliation': 'University of Pennsylvania', 'bio': {'p': ['Arun Raghavan is a PhD candidate in the Department of Computer and Information Science at the University of Pennsylvania. His research interests include parallel-computer architectures and programming models. Raghavan has a BEng in electronics and communications engineering from R.V. College of Engineering, India.']}}, {'name': 'Laurel Emurian', 'affiliation': 'University of Pennsylvania', 'bio': {'p': ['Laurel Emurian is a PhD candidate in the Department of Computer and Information Science at the University of Pennsylvania. Her research interests include energy-efficient systems and mobile architecture. Emurian has an MSE in computer and information science from the University of Pennsylvania.']}}, {'name': 'Lei Shao', 'affiliation': 'University of Michigan', 'bio': {'p': ['Lei Shao is a PhD candidate in the Department of Mechanical Engineering at the University of Michigan. His research interests include microscale heat transfer and energy conversion. Shao has an MS in mechanical engineering from the University of Michigan.']}}, {'name': 'Marios Papaefthymiou', 'affiliation': 'University of Michigan', 'bio': {'p': ['Marios Papaefthymiou is a professor in the Department of Electrical Engineering and Computer Science and Chair of Computer Science and Engineering at the University of Michigan. He is also a cofounder and chief scientist of Cyclos Semiconductor, a start-up company specializing in energy-efficient chips for power-critical applications. Papaefthymiou has a PhD in electrical engineering and computer science from the Massachusetts Institute of Technology.']}}, {'name': 'Kevin P. Pipe', 'affiliation': 'University of Michigan', 'bio': {'p': ['Kevin P. Pipe is an associate professor in the Department of Mechanical Engineering and holds joint appointments with the Applied Physics Program and Electrical Engineering and Computer Science Department at the University of Michigan. His research interests include microscale heat transfer, optoelectronic devices, thermoelectric energy conversion, scanning-probe techniques, photovoltaic energy conversion, and organic and hybrid organic and inorganic devices. Pipe has a PhD in electrical engineering from the Massachusetts Institute of Technology.']}}, {'name': 'Thomas F. Wenisch', 'affiliation': 'University of Michigan', 'bio': {'p': ['Thomas F. Wenisch is the Morris Wellman Faculty Development Assistant Professor of Electrical Engineering and Computer Science at the University of Michigan and a member of the Advanced Computer Architecture Lab. His research focuses on computer architecture with emphasis on multiprocessor and multicore systems, multicore programmability, smartphone architecture, datacenter architecture, and performance evaluation methodology. Wenisch has a PhD in electrical and computer engineering from Carnegie Mellon University.']}}, {'name': 'Milo M. K. Martin', 'affiliation': 'University of Pennsylvania', 'bio': {'p': ["Milo M. K. Martin is an associate professor in the Department of Computer and Information Science at the University of Pennsylvania. He coleads Penn's Computer Architecture and Compilers Group. His research interests include multiprocessor and multicore computer architecture, compiler and hardware support for security, and programming models for next-generation architectures. Martin has a PhD in computer science from the University of Wisconsin-Madison.", 'Direct questions and comments about this article to Arun Raghavan, LVN 302, 3330 Walnut St., Philadelphia, PA 19104, arraghav@cis.upenn.edu.', 'cn Selected CS articles and columns are also available for free at http://ComputingNow.computer.org.']}} %*Utilizing Dark Silicon to Save Energy with Computational Sprinting %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6576750 %f/micro/hioebfbewvnm1ojglka437rw0r82uqzc.pdf %m188b8a7d211fe4e0d0064e5c1018b249 %cmicro %@[{'name': 'Nathaniel Pinckney', 'affiliation': 'University of Michigan', 'bio': {'p': ['Nathaniel Pinckney is a PhD student in electrical engineering at the University of Michigan. His research interests include low-power VLSI design and cryptographic accelerators. Pinckney has an MS in electrical engineering from the University of Michigan.']}}, {'name': 'Ronald G. Dreslinski', 'affiliation': 'University of Michigan', 'bio': {'p': ['Ronald G. Dreslinski is a research scientist at the University of Michigan. His research focuses on architectures that enable emerging low-power circuit techniques. Dreslinski has a PhD in computer science and engineering from the University of Michigan.']}}, {'name': 'Korey Sewell', 'affiliation': 'University of Michigan', 'bio': {'p': ['Korey Sewell is a senior engineer at Qualcomm. His research interests include on-chip interconnect and memory controller design, high-performance microprocessors, many-core systems, and simulation modeling. Sewell has a PhD in computer science and engineering from the University of Michigan, where he performed the work for this article.']}}, {'name': 'David Fick', 'affiliation': 'University of Michigan', 'bio': {'p': ['David Fick is a research associate at the Michigan Integrated Circuits Laboratory, within the Department of Electrical Engineering and Computer Science at the University of Michigan. His research interests include fault tolerance, adaptive circuits and systems, and 3D integrated circuits. Fick has a PhD in computer science and engineering from the University of Michigan.']}}, {'name': 'Trevor Mudge', 'affiliation': 'University of Michigan', 'bio': {'p': ['Trevor Mudge is the Bredt Professor of Engineering at the University of Michigan. His research interests include computer architecture, programming languages, VLSI design, and computer vision. Mudge has a PhD in computer science from the University of Illinois. He is a fellow of IEEE and a member of the ACM, the IET, and the British Computer Society.']}}, {'name': 'Dennis Sylvester', 'affiliation': 'University of Michigan', 'bio': {'p': ['Dennis Sylvester is a professor in the Department of Electrical Engineering and Computer Science at the University of Michigan, and the director of the Michigan Integrated Circuits Laboratory. His research interests include the design of millimeter-scale computing systems and energy-efficient near-threshold computing for a range of applications. Sylvester has a PhD in electrical engineering from the University of California, Berkeley. He is a fellow of IEEE.']}}, {'name': 'David Blaauw', 'affiliation': 'University of Michigan', 'bio': {'p': ['David Blaauw is a professor in the Department of Electrical Engineering and Computer Science at the University of Michigan. His research focuses on VLSI design, particularly on ultra low-power and high-performance design. Blaauw has a PhD in computer science from the University of Illinois at Urbana-Champaign. He is a fellow of IEEE.']}} %*Limits of Parallelism and Boosting in Dim Silicon %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6560066 %f/micro/cn31gtlo5tzp06leuwirqmvkaprvzjsi.pdf %m7ce55c711c369b54d26aa1ab90c24504 %cmicro %@[{'name': 'Liang Wang', 'affiliation': 'University of Virginia', 'bio': {'p': ['Liang Wang is a PhD student in the Department of Computer Science at the University of Virginia. His research interests include power-efficient and resilient heterogeneous architectures. Wang has an MS in computer science from Peking University.']}}, {'name': 'Kevin Skadron', 'affiliation': 'University of Virginia', 'bio': {'p': ["Kevin Skadron is a professor in and chair of the Department of Computer Science at the University of Virginia. His research focuses on heterogeneous architecture and physical constraints such as power, temperature, and reliability. Skadron has a PhD in computer science from Princeton University. He's a fellow of IEEE.", "Direct questions and comments about this article to Liang Wang, 85 Engineer's Way, Rice Hall, Box 400740, Charlottesville, VA 22904–4740, lw2aw@virginia.edu."]}} %*Implications of the Power Wall: Dim Cores and Reconfigurable Logic %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6576752 %f/micro/qipnyj9wxtn1g4suvgfo7v0ak6yrcpdt.pdf %mdd8d658c69b1a3f87b37e4a327e93249 %cmicro %@[{'name': 'Karthik Swaminathan', 'affiliation': 'Pennsylvania State University', 'bio': {'p': ["Karthik Swaminathan is a PhD student in the Computer Science and Engineering Department at Pennsylvania State University. His research focuses on power-aware computer architectures. He is currently working on leveraging emerging device technologies in the architectural domain to improve performance, power, and reliability. Swaminathan has a bachelor's and master's degree in electrical engineering from the Indian Institute of Technology, Madras."]}}, {'name': 'Emre Kultursay', 'affiliation': 'Pennsylvania State University', 'bio': {'p': ['Emre Kultursay is a PhD student in the Computer Science and Engineering Department at Pennsylvania State University. His research interests include compiler optimizations for high-performance computing systems, energy-efficient multicore architectures, and heterogeneous processors and systems. Kultursay has a BS in electrical engineering and computer engineering from the Middle East Technical University, Turkey.']}}, {'name': 'Vinay Saripalli', 'affiliation': 'Pennsylvania State University', 'bio': {'p': ['Vinay Saripalli is a design, technology, and CAD services engineer at Intel. His research interests involve development of CAD automation flows for analog circuit design productivity improvement, and process migration methods for analog circuits. Saripalli has a PhD in computer science and engineering from Pennsylvania State University, where he completed the work for this article.']}}, {'name': 'Vijaykrishnan Narayanan', 'affiliation': 'Pennsylvania State University', 'bio': {'p': ['Vijaykrishnan Narayanan is a professor in the Departments of Computer Science and Engineering and Electrical Engineering at Pennsylvania State University. His research interests include power-aware and reliable systems, embedded systems, nanoscale devices and interactions with system architectures, reconfigurable systems, networks-on-chips, and domain-specific computing. Narayanan has a PhD in computer science and engineering from the University of South Florida.']}}, {'name': 'Mahmut T. Kandemir', 'affiliation': 'Pennsylvania State University', 'bio': {'p': ['Mahmut T. Kandemir is a professor in the Computer Science and Engineering Department at Pennsylvania State University. His research interests include optimizing compilers, runtime systems, embedded systems, I/O and high-performance storage, and power-aware computing. Kandemir has a PhD in computer science and engineering from Syracuse University.']}}, {'name': 'Suman Datta', 'affiliation': 'Pennsylvania State University', 'bio': {'p': ['Suman Datta is a professor in the Department of Electrical Engineering at Pennsylvania State University. His research interests include exploring new materials, novel nano-fabrication techniques, and device structures for CMOS enhancement and replacement for future energy-efficient, high-performance information processing systems. Datta has a PhD in electrical and computer engineering from the University of Cincinnati.', 'Direct questions and comments about this article to Karthik Swaminathan, 111, Information Sciences and Technology Building, Pennsylvania State University, University Park, PA 16802, kvs120@cse.psu.edu.']}} %*Steep-Slope Devices: From Dark to Dim Silicon %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6576745 %f/micro/oqr89szmzpigovljiafly1gtcqwxh5be.pdf %mb44341aae279b85d8162ca29ed28e619 %cmicro %@[{'name': 'Rich Belgard'} %*Joseph A. (Josh) Fisher Receives the 2012 IEEE B. Ramakrishna Rau Award %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6630033 %f/micro/rgoqbxbzfxcfs82icu4t7pyekojmdwrm.pdf %m757f7ddbc8827a378e3f164ae04d7df5 %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'Northwestern University', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6629996/6630005/6630005-photo-1-small.gif', 'p': ['Shane Greenstein is the Kellogg Chair in Information Technology at the Kellogg School of Management, Northwestern University. Contact him at greenstein@kellogg.northwestern.edu.']}} %*Digital Public Goods %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6630005 %f/micro/vcdisrbaosa5x2ugk7p6rwx0qc3febgk.pdf %maa0c3cf35cf7942867bd15f19f3c18e7 %cmicro %@[{'name': 'Erik R. Altman', 'affiliation': 'Thomas J. Watson Research Center', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6684176/6684182/6684182-photo-1-small.gif', 'p': ['', 'Erik R. Altman is the manager of the Dynamic Optimization Group at the Thomas J. Watson Research Center. Contact him at ealtman@us.ibm.com.']}} %*Cool Chips, Mobile Devices, Memory, and IEEE Micro Going Digital %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6684182 %f/micro/b906pvrllyxc8oez4gfysbqzugacmedi.pdf %m902914fd7042c1dd5964dad7698f13f9 %cmicro %@[{'name': 'Makoto Ikeda', 'affiliation': 'University of Tokyo', 'bio': {'p': ['Makoto Ikeda is a professor in Department of Electrical Engineering and Information Systems at the University of Tokyo. His research interests include high-performance, low-power, and reliable digital circuit and smart image sensor design. Ikeda has a PhD in electronic engineering from the University of Tokyo. He is a member of IEEE, the ACM, the Institute of Electronics, Information and Communication Engineers (IEICE), and the Information Processing Society of Japan (IPSJ).']}}, {'name': 'Fumio Arakawa', 'affiliation': 'Nagoya University', 'bio': {'p': ["Fumio Arakawa is a designated professor in the Center for Embedded Computing Systems at the Graduate School of Information Science at Nagoya University. His research interests include architecture and microarchitecture of low-power and high-performance microprocessors. Arakawa has a PhD in electrical engineering from the University of Tokyo. He's a member of IEEE and the Institute of Electronics, Information, and Communication Engineers (IEICE)."]}} %*Cool Chips [Guest editors' introduction] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6684185 %f/micro/hg0cnjiaxtqw42koqedv3lpfh7pm8xnf.pdf %m959cacd24ff781f0a50114b14db312d9 %cmicro %@[{'name': 'Noriyuki Miura', 'affiliation': 'Keio Univ., Yokohama, Japan', 'bio': {'p': ['Noriyuki Miura is an assistant professor at the Graduate School of System Informatics at Kobe University, working on mixed-signal sensor design including 3D heterogeneous integration. Miura has a PhD in electrical engineering from Keio University, where he completed the work for this article.']}}, {'name': 'Yusuke Koizumi', 'affiliation': 'Keio Univ., Yokohama, Japan', 'bio': {'p': ["Yusuke Koizumi is a master's student of computer science at Keio University. His research focuses on computer architecture. Koizumi has a BS in science and engineering from Keio University."]}}, {'name': 'Yasuhiro Take', 'affiliation': 'Keio Univ., Yokohama, Japan', 'bio': {'p': ['Yasuhiro Take is a doctoral student in electrical engineering at Keio University. Take has an MS in electrical engineering from Keio University.']}}, {'name': 'Hiroki Matsutani', 'affiliation': 'Keio Univ., Yokohama, Japan', 'bio': {'p': ['Hiroki Matsutani is an assistant professor in the Department of Information and Computer Science at Keio University. His research interests include computer architecture and interconnection networks. Matsutani has a PhD from Keio University.']}}, {'name': 'Tadahiro Kuroda', 'affiliation': 'Keio Univ., Yokohama, Japan', 'bio': {'p': ['Tadahiro Kuroda is a professor at Keio University. His research interests include low-power CMOS design, proximity com-munications, and image recognition. Kuroda has a PhD in electrical engineering from the University of Tokyo.']}}, {'name': 'Hideharu Amano', 'affiliation': 'Keio Univ., Yokohama, Japan', 'bio': {'p': ['Hideharu Amano is a professor in the Department of Information and Computer Science at Keio University. His research interests include parallel architectures and reconfigurable computing. Amano has a PhD in electric engineering from Keio University.']}}, {'name': 'Ryuichi Sakamoto', 'affiliation': 'Tokyo Univ. of Agric. &, Technol., Koganei, Japan', 'bio': {'p': ['Ryuichi Sakamoto is a doctoral student of computer science and engineering at the Tokyo University of Agriculture and Tech-nology. Sakamoto has an MS in computer science from the Tokyo University of Agriculture and Technology.']}}, {'name': 'Mitaro Namiki', 'affiliation': 'Tokyo Univ. of Agric. &, Technol., Koganei, Japan', 'bio': {'p': ['Mitaro Namiki is a professor in the Faculty of Computer Science and Engineering at the Tokyo University of Agriculture and Technology. His research interests include operating systems, programming languages, parallel processing, and computer networks. Namiki has a PhD in computer science from the Tokyo University of Agriculture and Technology.']}}, {'name': 'Kimiyoshi Usami', 'affiliation': 'Shibaura Inst. of Technol., Tokyo, Japan', 'bio': {'p': ['Kimiyoshi Usami is a professor in the Department of Information Science and Engineering at the Shibaura Institute of Technology. His research interests include energy-aware computing and ultra-low-power voltage design. Usami has a PhD in electric engineering from Waseda University.']}}, {'name': 'Masaaki Kondo', 'affiliation': 'Univ. of Electro-Commun. in Tokyo, Tokyo, Japan', 'bio': {'p': ['Masaaki Kondo is an associate professor in the Graduate School of Information Systems at the University of Electro-Communications in Tokyo. His research interests include computer architectures, high-performance computing, and dependable computing. Kondo has a PhD in electrical engineering from the University of Tokyo.']}}, {'name': 'Hiroshi Nakamura', 'affiliation': 'Univ. of Tokyo, Tokyo, Japan', 'bio': {'p': ['Hiroshi Nakamura is a professor in the Department of Information Physics and Computing at the University of Tokyo. His research interests include low-power VLSI design, power-aware computing, high-performance computer systems, and dependable computing. Nakamura has a PhD in electrical engineering from the University of Tokyo.']}} %*A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6684194 %f/micro/lnhduvgjgp2dz5tfsnqbyyvqb1uckimz.pdf %mb12533ba051e4b6e08f1e4493e1ae559 %cmicro %@[{'name': 'Toshio Yoshida', 'bio': {'p': ['Toshio Yoshida is a director of the LSI Development Division in the Next Generation Technical Computing Unit at Fujitsu. His research interests include microprocessor architecture. Yoshida has an MS in physics from the University of Tokyo.']}}, {'name': 'Takumi Maruyama', 'bio': {'p': ['Takumi Maruyama is an assistant vice president in the Enterprise Server Business Unit at Fujitsu. His research interests include microprocessor architecture and VLSI design. Maruyama has a BE in mathematical engineering and instrumentation physics from the University of Tokyo.']}}, {'name': 'Yasunobu Akizuki', 'bio': {'p': ['Yasunobu Akizuki is an engineer in the Processor Development Division in the Enterprise Server Business Unit at Fujitsu. His research interests include processor micro architecture. Akizuki has a BS in information technology from the University of Electro-Communications in Tokyo, Japan.']}}, {'name': 'Ryuji Kan', 'bio': {'p': ['Ryuji Kan is a manager in the Enterprise Server Business Unit at Fujitsu. His research interests focus on integrating hardware and software. Kan has an MS in communications and computer engineering from Kyoto University.']}}, {'name': 'Naohiro Kiyota', 'bio': {'p': ['Naohiro Kiyota is a manager in the Enterprise Server Business Unit at Fujitsu. His research interests focus on cache architecture for processors. Kiyota has a BE in electronic engineering from Kyoto University.']}}, {'name': 'Kiyoshi Ikenishi', 'bio': {'p': ["Kiyoshi Ikenishi is an engineer in the Processor Development Division in the Enterprise Server Business Unit at Fujitsu. His research interests include low-power IC design and methodology. Ikenishi has an associate's degree in electrical engineering from the Niihama National College of Technology."]}}, {'name': 'Shigeki Itou', 'bio': {'p': ["Shigeki Itou is a PA project engineer in the Next Generation Technical Computing Unit at Fujitsu. His research interests focus on microprocessor performance. Itou has a master's degree in information engineering from Nagoya University."]}}, {'name': 'Tomoyuki Watahiki', 'bio': {'p': ['Tomoyuki Watahiki is a PA project engineer in the Next Generation Technical Computing Unit at Fujitsu. His research interests focus on microprocessor architecture. Wata-hiki has an MS in quantum science and technology from Nihon University.']}}, {'name': 'Hiroshi Okano', 'bio': {'p': ['Hiroshi Okano is a research manager in the Server Technologies Laboratory at Fujitsu Laboratories. His research interests focus on high-performance techniques for microprocessors under power constraints. Okano has an ME in electrical engineering from Hiroshima University.', 'Direct questions and comments about this article to Toshio Yoshida, Fujitsu Limited, 1–1, Kamikodanaka 4-chome, Nakaharaku, Kawasaki, 211–8588, Japan, yoshida.toshio@jp.fujitsu.com.']}} %*Sparc64 X: Fujitsu's New-Generation 16-Core Processor for Unix Servers %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6684205 %f/micro/xkwyqea8fivzrd07riuyl43fdnpbvjcm.pdf %mf0b2936484f36a073d74e56b3bff447b %cmicro %@[{'name': 'Kazuki Fukuoka', 'bio': {'p': ['Kazuki Fukuoka is a principal engineer in the technology development unit at Renesas Electronics, where he is engaged in power-management architecture. Fukuoka has a PhD in electrical and electronic engineering from Kobe University.']}}, {'name': 'Noriaki Maeda', 'bio': {'p': ['Noriaki Maeda is a principal engineer at Renesas Electronics, where he is working on the research and development of deep-sub-micron embedded SRAM. Maeda has an MS in electronic engineering from Hiroshima University.']}}, {'name': 'Koji Nii', 'bio': {'p': ['Koji Nii is a chief professional at Renesas Electronics, where he works on the research and development of 28-nm embedded SRAM and low-power design techniques. Nii has a PhD in informatics and electronics engineering from Kobe University.']}}, {'name': 'Masaki Fujigaya', 'bio': {'p': ['Masaki Fujigaya is a principal engineer at Renesas Mobile, where he has been working on ASIC and system-on-chip (SoC) design for mobile phone devices. Fujigaya has an ME in energy engineering and science from Nagoya University.']}}, {'name': 'Noriaki Sakamoto', 'bio': {'p': ['Noriaki Sakamoto is a section manager at Renesas Mobile, where he engages in SoC design for mobile phones. Sakamoto has a PhD in information systems engineering from Osaka University.']}}, {'name': 'Takao Koike', 'bio': {'p': ['Takao Koike is a principal engineer at Renesas Mobile, where he has been developing low-power and high-performance SoCs. Koike has an MS in electrical and electronic engineering from Kyoto University.']}}, {'name': 'Takahiro Irita', 'bio': {'p': ['Takahiro Irita is a senior manager at Renesas Mobile, where he works on SoC design for mobile phones. Irita has a PhD in information and communication engineering from the University of Tokyo.']}}, {'name': 'Kohei Wakahara', 'bio': {'p': ['Kohei Wakahara is a senior engineer at Renesas Mobile, where he has been working on ASIC and SoC design for mobile phones. Wakahara has an ME in electronics and information engineering from Yamanashi University.']}}, {'name': 'Tsugio Matsuyama', 'bio': {'p': ['Tsugio Matsuyama is an engineer at Renesas Mobile, where is working on a mobile SoC development. Matsuyama has an ME in electrical engineering from Hosei University.']}}, {'name': 'Keiji Hasegawa', 'bio': {'p': ['Keiji Hasegawa is a principal engineer at Renesas Mobile, where he is designing power-management of mobile SoC products. Hasegawa has an ME in industrial science and technology from the Tokyo University of Science.']}}, {'name': 'Toshiharu Saito', 'bio': {'p': ['Toshiharu Saito is a principal engineer at Renesas Mobile, where he has been developing power-management system design for mobile SoC. Saito has an MS in physics from Nihon University.']}}, {'name': 'Akira Fukuda', 'bio': {'p': ['Akira Fukuda is a senior engineer at Renesas Mobile, where he has been designing the power-management system of mobile SoC. Fukuda has a BE in electronic engineering from Kumamoto Institute of Technology.']}}, {'name': 'Kaname Teranishi', 'bio': {'p': ['Kaname Teranishi is a principal engineer at Renesas Mobile, where he works on integrating the modem parts of the R-Mobile U series. Teranishi has an MS in information engineering from Tohoku University.']}}, {'name': 'Takeshi Kataoka', 'bio': {'p': ["Takeshi Kataoka is a director at Renesas Mobile, where he's engaged in development and business of SoC for mobile application and baseband field. Kataoka has an ME in applied physics from the University of Tokyo and an MS in electrical engineering from Stanford University."]}}, {'name': 'Toshihiro Hattori', 'bio': {'p': ['Toshihiro Hattori is a vice president of SoC design at Renesas Mobile. Hattori has a PhD in informatics from Kyoto University.', 'Direct questions and comments about this article to Kazuki Fukuoka, Low Power System Development Dept., Renesas Electronics, 5–20-1, J osuihon-cho, Kodaira-shi, Tokyo 187–8588, Japan, kazuki.fukuoka.xn@renesas.com.', 'Selected CS articles and columns are also available for free at http/IComputingNow.computer.org.']}} %*Power-Management Features of R-Mobile U2, an Integrated Application Processor and Baseband Processor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6636316 %f/micro/kdex5kanbczpfehwur89143haoptgsvl.pdf %mca9a51e57d1f91ad96fa1675d1c67d0a %cmicro %@[{'name': 'Rumi Zahir'}, {'name': 'Mark Ewert'}, {'name': 'Hari Seshadri'} %*The Medfield Smartphone: Intel Architecture in a Handheld Form Factor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6477031 %f/micro/mxtbwcaeye0m5yj1ujplnv8frkfwktsv.pdf %m50a843aa2d2385de1a761417d3869ec2 %cmicro %@[{'name': 'Todor Cooklev', 'bio': {'p': ['Todor Cooklev is the ITT Associate Professor of Wireless Communication and Applied Research and founding director of the Wireless Technology Center at Indiana University-Purdue University Fort Wayne. His research interests include signal processing, radio architectures, and software-defined radio. Cooklev has a PhD in electrical engineering from the Tokyo Institute of Technology. He is a senior member of IEEE and the IEEE Standards Association.']}}, {'name': 'Akinori Nishihara', 'bio': {'p': ['Akinori Nishihara is a professor at the Tokyo Institute of Technology, where he has held several academic appointments. His research interests include digital signal processing, circuits and systems, and educational technology. Nishihara has a PhD from the Tokyo Institute of Technology. He is a fellow of IEEE and the IEICE.']}} %*An Open RF-Digital Interface for Software-Defined Radios %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6684203 %f/micro/xtvo41bgq3iwjnrqp7ykdhr2j0lahdae.pdf %m013687f27f0a05d36d282a64b12eacb9 %cmicro %@[{'name': 'Bendik Kleveland', 'bio': {'p': ["Bendik Kleveland is a senior director of engineering at MoSys, where he led design and silicon validation for the first-generation Bandwidth Engine device. His technical interests include robust design and fault tolerance, design for test, and high speed on-chip and package interconnects. Kleveland has a PhD in electrical engineering from Stanford University. He's a member of IEEE."]}}, {'name': 'Michael John Miller', 'bio': {'p': ['Michael John Miller is vice president of technology innovation and system applications at MoSys, where he is responsible for system architecture and applications for the Bandwidth Engine family. His technical interests include processor and network system architecture, memory subsystems, and the application of algorithms. Miller has a BS in computer science from California Polytechnic State University.']}}, {'name': 'Ronald B. David', 'bio': {'p': ["Ronald B. David is a staff technical writer at MoSys, where he does technical writing and applications engineering for the Bandwidth Engine family. His technical interests include interconnection networks and processor and system architecture. David studied computer architecture at the University of California, Berkeley and has a BA in physics from the University of California, San Diego. He's a member of the IEEE Computer Society."]}}, {'name': 'Jay Patel', 'bio': {'p': ['Jay Patel is a principal engineer at MoSys, where he is the lead microarchitect and logic designer for the Bandwidth Engine family. His technical interests include computer microarchitecture and computer programming. Patel has an MS in computer engineering from Syracuse University.']}}, {'name': 'Rajesh Chopra', 'bio': {'p': ['Rajesh Chopra is a principal engineer at MoSys, where he led design verification and timing for the first-generation Bandwidth Engine device. His technical interests include CPU and network classification architectures. Chopra has a BS in electronics from Pune University, India.']}}, {'name': 'Dipak K. Sikdar', 'bio': {'p': ["Dipak K. Sikdar is a director of engineering at MoSys, where he leads memory design. His technical interests include high-speed and low-power memory architectures and circuit design. Sikdar has a master's degree in electronics and telecommunication engineering from Jadavpur University, India."]}}, {'name': 'Jeff Kumala', 'bio': {'p': ['Jeff Kumala is a senior engineering manager at MoSys, where he leads memory verification.', "His technical interests include high-speed/low-power SRAM and gain-cell design. Kumala has an MS in electrical engineering from Oklahoma State University. He's a member of IEEE."]}}, {'name': 'Socrates D. Vamvakos', 'bio': {'p': ['Socrates D. Vamvakos is a staff engineer at MoSys, where he works on architectures and circuit design for high-speed SerDes. His technical interests include circuits and architectures for high-speed SerDes and PLLs. Vamvakos has a PhD in electrical engineering from the University of California, Berkeley.']}}, {'name': 'Mike Morrison', 'bio': {'p': ['Mike Morrison is a principal engineer at MoSys, where he does protocol architecture, logic design, and verification for the Bandwidth Engine family. His technical interests include computer and network processor architecture and microarchitecture. Morrison has a BS in electrical engineering and computer science from the University of California, Berkeley.']}}, {'name': 'Ming Liu', 'bio': {'p': ['Ming Liu is a director of engineering at MoSys, where he leads DFT and software/firmware development. His technical interests include system architectures and hardware/software for embedded systems. Liu has a PhD in physical sciences from Brown University.']}}, {'name': 'Jayaprakash Balachandran', 'bio': {'p': ['Jayaprakash Balachandran is a staff engineer at MoSys, where he is responsible for packaging and signal integrity. His technical interests include high-speed memory links and 3D packaging. Balachandran has a PhD from IMEC/Katholieke Universiteit Leuven.', 'Direct questions and comments about this article to Bendik Kleveland, MoSys, 3301 Olcott St., Santa Clara, CA 95054, bkleveland@mosys.com.']}} %*An Intelligent RAM with Serial I/Os %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6419689 %f/micro/3tnidh0qydkpa2peivzmao1ublv5fogj.pdf %m9f39a5c7153d357f5233f8ed517a87d2 %cmicro %@[{'name': ' Jing Guo', 'affiliation': 'Harbin Inst. of Technol., Harbin, China', 'bio': {'p': ['Jing Guo is a PhD candidate in microelectronics and solid-state electronics at Harbin Institute of Technology, China. His research interests include fault tolerance in VLSI designs and reliability in memories. Guo has an MS in electronic science and technology from Hei Longjiang University.']}}, {'name': ' Liyi Xiao', 'affiliation': 'Harbin Inst. of Technol., Harbin, China', 'bio': {'p': ["Li yi Xiao is a professor in the Department of Electronic Science and Technology at Harbin Institute of Technology, China. Her research focuses on reliability in semiconductor devices and extra-low-power design in VLSI. Liyi has a PhD in microelectronics and solid-state electronics from the Harbin Institute of Technology. She's a member of IEEE."]}}, {'name': ' Zhigang Mao', 'affiliation': 'Harbin Inst. of Technol., Harbin, China', 'bio': {'p': ["Zhigang Mao is a professor in the Microelectronics Center at Harbin Institute of Technology, China. His research interests include VLSI design methodology, high-speed digital circuit design technology, and reliability in semiconductor devices. Mao has a PhD in electronic science and technology from Rennes University. He's a member of IEEE."]}}, {'name': ' Qiang Zhao', 'affiliation': 'Harbin Inst. of Technol., Harbin, China', 'bio': {'p': ["Qiang Zhao is a master's student in microelectronics and solid-state electronics at Harbin Institute of Technology, China. His research interests include high-speed and low-power VLSI design and reliability in semiconductor devices. Zhao has a BS in electronic science and technology from the Harbin Institute of Technology.", 'Direct questions and comments about this article to Jing Guo, Microelectronics Center, Harbin Institute of Technology, Harbin, HLJ 150001, China,']}} %*Novel Mixed Codes for Multiple-Cell Upsets Mitigation in Static RAMs %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6684181 %f/micro/wqx2tikuprxjpn6c1jatnbholcaeusrb.pdf %m8b9062fb56ba5e537728836ebfc1a225 %cmicro %@[{'name': 'Richard Mateosian', 'affiliation': 'Cogility Software', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6684176/6684207/6684207-photo-1-small.gif', 'p': ['Richard Mateosian is a technical writer at Cogility Software. Contact him at xrmxrm@gmail.com.']}} %*Technical Design [Two books reviewed] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6684207 %f/micro/llrjsnde3yfshto7hanqx8e0k5bcmcwj.pdf %m891369a5bce04a0aff671cacf254c11d %cmicro %@[{'name': 'Shane Greenstein', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6684176/6684178/6684178-photo-1-small.gif', 'p': ['Shane Greenstein']}} %*How Much Apache? %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6684178 %f/micro/6yp0kglwesczza25vtn8qjomncriokwb.pdf %mda51c81c0f4eae7382d65ecd0081abf7 %cmicro %@[{'name': 'Min Xie', 'affiliation': 'National University of Defense Technology, China', 'bio': {'p': ['Min Xie is an associate professor in the School of Computer at the National University of Defense Technology, China. His research interests include high-speed interconnects and parallel and distributed computing. Xie has a PhD in computer science from the National University of Defense Technology.']}}, {'name': 'Yutong Lu', 'affiliation': 'National University of Defense Technology, China', 'bio': {'p': ['Yutong Lu is a professor in the School of Computer at the National University of Defense Technology, China. Her research interests include parallel and distributed computing and operating systems. Lu has a PhD in computer science from the National University of Defense Technology.']}}, {'name': 'Kefei Wang', 'affiliation': 'National University of Defense Technology, China', 'bio': {'p': ['Kefei Wang is an associate professor in the School of Computer at the National University of Defense Technology, China. His research interests include high-speed interconnects and high-performance computing. Wang has a PhD in computer science from the National University of Defense Technology.']}}, {'name': 'Lu Liu', 'affiliation': 'National University of Defense Technology, China', 'bio': {'p': ['Lu Liu is an associate professor in the School of Computer at the National University of Defense Technology, China. His research interests include high-speed interconnects and high-performance computing. Liu has an MS in automatic control from the National University of Defense Technology.']}}, {'name': 'Hongjia Cao', 'affiliation': 'National University of Defense Technology, China', 'bio': {'p': ['Hongjia Cao is an associate professor in the School of Computer at the National University of Defense Technology, China. His research interests include high-performance computing and resource management. Cao has a PhD in computer science from the National University of Defense Technology.']}}, {'name': 'xuejun yang', 'affiliation': 'National University of Defense Technology, China', 'bio': {'p': ['Xuejun Yang is a professor in the School of Computer at the National University of Defense Technology, China. His research interests include computer architecture, high-performance computing, and compiler design. Yang has a PhD in computer science from the National University of Defense Technology. He is a member of IEEE.']}} %*Tianhe-1A Interconnect and Message-Passing Services %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6086529 %f/micro/ojtvg6kfdsrrev1xfppdxk7qqlhcseiy.pdf %m2b5762f5510621132cb512fe0e25f20f %cmicro %@[{'name': 'Yuichiro Ajima', 'affiliation': 'Fujitsu', 'bio': {'p': ['Yuichiro Ajima is a system architect in the Next-Generation Technical Computing Unit at Fujitsu. His research focuses on high-performance computing system architecture. Ajima has a PhD in information engineering from the University of Tokyo. He is a member of the Information Processing Society of Japan and IEEE.']}}, {'name': 'Tomohiro Inoue', 'affiliation': 'Fujitsu', 'bio': {'p': ['Tomohiro Inoue is an engineer in the Next-Generation Technical Computing Unit at Fujitsu. His research focuses on computer networks. Inoue has a PhD in information engineering from Hiroshima City University.']}}, {'name': 'Shinya Hiramoto', 'affiliation': 'Fujitsu', 'bio': {'p': ['Shinya Hiramoto is an engineer in the Next-Generation Technical Computing Unit at Fujitsu. His research focuses on high-performance computing system architecture. Hiramoto has an ME in information engineering from Nara Institute of Science and Technology. He is a member of the Information Processing Society of Japan.']}}, {'name': 'Yuzo Takagi', 'affiliation': 'DeNA', 'bio': {'p': ['Toshiyuki Shimizu is a director of the Next-Generation Technical Computing Development Unit at Fujitsu. His research focuses on high-performance computing system architecture, particularly interconnect architecture for highly scalable systems. Shimizu has an MS in computer engineering from the Tokyo Institute of Technology.']}}, {'name': 'Toshiyuki Shimizu', 'affiliation': 'Fujitsu', 'bio': {'p': ['Yuzo Takagi is a former engineer in the Next-Generation Technical Computing Unit at Fujitsu. He currently is a business planner, product manager, and data-mining analyst at DeNA Corporation. His research interests include astrophysics, plasma physics, fluid dynamics, Internet services, parallel computing, and high-performance computing system architecture. Takagi has an MS in astrophysics from the University of Tokyo.']}} %*The Tofu Interconnect %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6086528 %f/micro/ed8ixns76aabbvcok4l205wflzpzrfiq.pdf %m1651f3d82bcfc8d0cf8266afdaa60ff4 %cmicro %@[{'name': 'Dong Chen', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ['Dong Chen is a research staff member on the Blue Gene supercomputer project at the IBM T.J. Watson Research Center in Yorktown Heights, New York. His research interests include the architecture and design of Blue Gene systems and their applications. Chen has a PhD in physics from Columbia University. He is a member of IEEE.']}}, {'name': 'Noel Eisley', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ['Noel A. Eisley is a research staff member on the Blue Gene supercomputer project at the IBM T.J. Watson Research Center. His research interests include interconnection networks, chip multiprocessors, and networks on chips. Eisley has a PhD in electrical engineering from Princeton University. He is a member of IEEE and the American Association for the Advancement of Science (AAAS).']}}, {'name': 'Philip Heidelberger', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ['Philip Heidelberger is a research staff member on the Blue Gene supercomputer project hardware team at the IBM T.J. Watson Research Center. His research focuses on various aspects of Blue Gene, including network architecture and design, logic verification, hardware bring-up, network software interfaces, and efficient communications algorithms. Heidelberger has a PhD in operations research from Stanford University. He is an IBM master inventor, a member of the IBM Academy of Technology, and a fellow of IEEE and the ACM.']}}, {'name': 'Robert Senger', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ['Robert M. Senger is a research staff member on the Blue Gene supercomputer project at the IBM T.J. Watson Research Center. His research interests include low-power architectures and circuits, interconnection network design, and messaging hardware interfaces. Senger has a PhD in electrical engineering from the University of Michigan, Ann Arbor. He is a member of IEEE.']}}, {'name': 'Yutaka Sugawara', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ['Yutaka Sugawara is a research staff member on the Blue Gene supercomputer project at the IBM T.J. Watson Research Center. His research focuses on interconnect and host interface architecture for high-performance computing systems. Sugawara has a PhD in computer science and technology from the University of Tokyo. He is a member of IEEE.']}}, {'name': 'Sameer Kumar', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ['Sameer Kumar is a research staff member and the research lead of the messaging-software stack for Blue Gene/Q at the IBM T.J. Watson Research Center. His research interests include designing message-passing software on million-processor machines, optimizing performance for parallel applications, and designing next-generation supercomputer interconnection networks. Kumar has a PhD in computer science from the University of Illinois at Urbana-Champaign.']}}, {'name': 'Valentina Salapura', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ['Valentina Salapura is a system architect at the IBM T.J. Watson Research Center, where she works in the Services Innovation Lab. Her research interests include cloud computing, data center design and operation, virtualization and virtual-machine provisioning, multiprocessor interconnects, multiprocessor synchronization, and multi-threaded, multicore architecture design and evaluation. Salapura has a PhD in computer science from Technische Universität Wien in Vienna. She is an IBM master inventor, a member of the IBM Academy of Technology and the ACM, and a fellow of IEEE.']}}, {'name': 'David Satterfield', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ['David L. Satterfield is a senior engineer on the Blue Gene supercomputer project at the IBM T.J. Watson Research Center. His research interests include the architecture and design of Blue Gene systems and their applications. Satterfield has a BS in electrical engineering from Tufts University.']}}, {'name': 'Burkhard Steinmacher-Burow', 'affiliation': 'IBM Germany Research and Development', 'bio': {'p': ['Burkhard Steinmacher-Burow is a senior technical staff member at IBM Germany Research & Development. His research interests include Blue Gene hardware and software systems, particularly network and memory systems. Steinmacher-Burow has a PhD in physics from the University of Toronto.']}}, {'name': 'Jeffrey Parker', 'affiliation': 'IBM Systems &, Technology Group', 'bio': {'p': ['Jeffrey J. Parker is an operating-system software engineer at the IBM Systems & Technology Group in Rochester, Minnesota. His technical interests include the IBM System/36 and iSeries systems, Blue Gene/L I/O performance, and Blue Gene/P and Blue Gene/Q messaging software. Parker has a BS in computer science from the University of Minnesota.']}} %*The IBM Blue Gene/Q Interconnection Fabric %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6086530 %f/micro/giqztrfbkpbzvjlsis0v6wquupnyed8l.pdf %m224271a9f05c3b8fbe931d53acedfa17 %cmicro %@[{'name': 'Ismael Gomez', 'affiliation': 'Universitat Politecnica de Catalunya', 'bio': {'p': ['Ismael Gómez Miguelez is a PhD candidate at the Department of Signal Theory and Communications at the Universitat Politecnica de Catalunya (UPC). His research interests include radio and computing resource management with special emphasis on energy efficiency and software-defined radio. Gómez has an MS in electrical engineering from the UPC.']}}, {'name': 'Vuk Marojevic', 'affiliation': 'Universitat Politecnica de Catalunya', 'bio': {'p': ['Vuk Marojevic is an assistant professor at the Department of Signal Theory and Communications at the Universitat Politècnica de Catalunya (UPC). His research efforts are on software-defined and cognitive radio architectures and algorithms for an efficient and flexible computing resource management. Marojevic has a PhD in electrical engineering from the UPC.']}}, {'name': 'Antoni Gelonch', 'affiliation': 'Universitat Politecnica de Catalunya', 'bio': {'p': ['Antoni Gelonch Bosch is an associate professor at the Department of Signal Theory and Communications at the Universitat Politècnica de Catalunya (UPC). His research focuses on implementation methodologies supporting cognitive resource management strategies and algorithms for flexible wireless communications systems and networks. Gelonch has a PhD in electrical engineering from the UPC.']}} %*Resource Management for Software-Defined Radio Clouds %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6012545 %f/micro/ligr6onp8jwnbdj7zsqvvdhtyawckeiy.pdf %mce8e68e6f89be9ebff22cf9ad26d9c97 %cmicro %@[{'name': 'Fabrice Harrouet', 'affiliation': 'National Engineering School of Brest', 'bio': {'p': ['Fabrice Harrouet is a lecturer at the National Engineering School of Brest, France, where he conducts research in the Computer Sciences for Complex Systems Laboratory and the European Center for Virtual Reality. His research focuses on interactive multiagent simulations, particularly parallel computing and 3D rendering. Harrouet has a PhD in computer science from the University of Western Brittany.', 'Direct questions and comments about this article to Fabrice Harrouet, Centre Europeen de Realite Virtuelle, Technopôle Brest-Iroise, CS 73862, 29238 Brest Cedex 3, France, harrouet@enib.fr.']}} %*Designing a Multicore and Multiprocessor Individual-Based Simulation Engine %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5989785 %f/micro/dked3xrfyowucefzpvq4ap71hn92v5tg.pdf %me12ca3a1d36f496c05a8bdc151e258b4 %cmicro %@[{'name': 'Parthasarathy Ranganathan', 'affiliation': 'HP Labs', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6144277/6144283/6144283-photo-1-small.gif', 'p': ['Parthasarathy Ranganathan is a Fellow at HP Labs. His research interests include system architecture and energy-efficient design. Ranganathan received his PhD in electrical and computer engineering from Rice University. He is also an IEEE Fellow.']}}, {'name': 'Jichuan Chang', 'affiliation': 'HP Labs', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6144277/6144283/6144283-photo-2-small.gif', 'p': ['Jichuan Chang is a senior research scientist at HP Labs. His research interests include computer system architecture and memory systems. Chang received his PhD in computer sciences from the University of Wisconsin-Madison. He is a senior member of IEEE.']}} %*(Re)Designing Data-Centric Data Centers %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6144283 %f/micro/scifapxet8nqtv9kuoysrofbjre7w1j6.pdf %mbd496471d597e306b5bb645fef066823 %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'greenstein@kellogg.northwestern.edu', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6144277/6144284/6144284-photo-1-small.gif', 'p': []}} %*The Range of Linus' Law %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6144284 %f/micro/upkgwortrbcpk7mfnxux4jclzhgszvfh.pdf %me8eb7e7a15b460688d495e5ff33aa2cf %cmicro %@[{'name': 'Erik R. Altman', 'affiliation': 'ealtman@us.ibm.com', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6177300/6177304/6177304-photo-1-small.gif', 'p': []}} %*Micro Evolution %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6177304 %f/micro/iduaawyz4rhjnhsme0x85lspcubwlkqm.pdf %mad6de04fb617c8f4c48a71b3d06bd286 %cmicro %@[{'name': 'Richard H. Stern', 'affiliation': 'r.stern@computer.org'} %*Standardization Skullduggery Never Ends: Apple v. Motorola %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6177305 %f/micro/dzlpae9bdsknnv6loiaukxqqyc5hhmyf.pdf %m11fa68b4164b91410c24294e5c769038 %cmicro %@[{'name': 'Allen Baum', 'affiliation': 'Intel', 'bio': {'p': ["Allen Baum is a computer architect at Intel. He has worked in the industry for 40 years on products ranging from the Apple I and II to HP's HP45 and PA-RISC, ARM and StrongArm, and Alpha, Itanium, and x86 server processors. Baum has an MS in electrical engineering from the Massachusetts Institute of Technology. He is a senior member of IEEE and a member of the ACM and the IEEE Computer Society."]}}, {'name': 'Bevan Bass', 'affiliation': 'University of California, Davis', 'bio': {'p': ['Bevan Baas is an associate professor in the Department of Electrical and Computer Engineering at the University of California, Davis. His research interests include algorithms, architectures, circuits, and VLSI design for high-performance, energy-efficient, and area-efficient computation. Recent projects include the 36-processor and 167-processor AsAP chips and applications. Baas has a PhD in electrical engineering from Stanford University. He is a senior member of IEEE.']}} %*Hot Chips 23 %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6177306 %f/micro/4tsw5dcijxnr7uiq8vrdfhho1gbtvpnb.pdf %m09da4148b5117cf6b031794f9db49649 %cmicro %@[{'name': 'Manish Shah', 'affiliation': 'Oracle', 'bio': {'p': ['Manish Shah is a senior principal engineer and member of the processor core development team at Oracle. His research interests include high performance computer architectures, branch prediction, and high-speed multithreaded processor designs. Shah has an MS in electrical engineering from Oklahoma State University.']}}, {'name': 'Robert Golla', 'affiliation': 'Oracle', 'bio': {'p': ["Robert Golla is a senior hardware architect at Oracle, where he oversees the architecture of Oracle's processor cores. His research interests include high-performance computer architecture, microprocessor design, and throughput computing. Golla has an MS in electrical engineering from the University of Texas."]}}, {'name': 'Gregory Grohoski', 'affiliation': 'Oracle', 'bio': {'p': ["Greg Grohoski is a senior director at Oracle, where he oversees the development of Oracle's processor cores. His research interests include computer architecture and parallel computing. Grohoski has an MS in electrical engineering from the University of Illinois."]}}, {'name': 'Paul Jordan', 'affiliation': 'Oracle', 'bio': {'p': ['Paul Jordan is a senior principal hardware engineer and member of the core RTL development team at Oracle. His research interests include high-performance computer architectures and memory management. Jordan has a BS in electrical engineering from Rice University.']}}, {'name': 'Jama Barreh', 'affiliation': 'Oracle', 'bio': {'p': ['Jama Barreh is a principal engineer and member of the RTL development team at Oracle. His research interests include high-speed processor design and computer architecture. Barreh has an MS in electrical engineering from the Illinois Institute of Technology.']}}, {'name': 'Jeffrey Brooks', 'affiliation': 'Oracle', 'bio': {'p': ['Jeff Brooks is a senior principal engineer and member of the processor core development team at Oracle. His research interests include microprocessor architecture and design and computer arithmetic. Brooks has a BS in electrical engineering from the University of Memphis.']}}, {'name': 'Mark Greenberg', 'affiliation': 'Oracle', 'bio': {'p': ['Mark Greenberg is a principal engineer and member of the RTL development team at Oracle. His research interests include highperformance computer architectures, processor physical design, and simulation. Greenberg has a PhD in computer engineering from the University of Manchester, England.']}}, {'name': 'Gideon Levinsky', 'affiliation': 'Oracle', 'bio': {'p': ['Gideon Levinsky is a principal engineer and member of the RTL development team at Oracle. His research interests include microprocessor design, cache hierarchy, and computer architecture. Levinsky has an MS in electrical engineering from Stanford University.']}}, {'name': 'Mark Luttrell', 'affiliation': 'Oracle', 'bio': {'p': ['Mark Luttrell is a senior principal engineer and member of the processor core design team at Oracle. His research interests include high-speed microprocessor design, cache hierarchy, and computer architecture. Lut-trell has an MS in electrical engineering from Stanford University.']}}, {'name': 'Christopher Olson', 'affiliation': 'Oracle', 'bio': {'p': ['Christopher Olson is a principal engineer and member of the RTL development team at Oracle. His research interests include microprocessor architecture and design, computer arithmetic, and hardware cryptographic acceleration. Olson has a BS in electrical engineering from the University of Wisconsin.']}}, {'name': 'Zeid Samoail', 'affiliation': 'Oracle', 'bio': {'p': ['Zeid Samoail is a senior hardware engineer and member of the RTL design team at Oracle. His research interests include high performance computer architecture. Samoail has a BS in computer engineering from the State University of New York at Stony Brook.']}}, {'name': 'Matt Smittle', 'affiliation': 'Oracle', 'bio': {'p': ['Matt Smittle is a principal engineer and member of the RTL development team at Oracle. His research interests include thread hog mitigation in multithreaded processor designs and power-aware designs. Smittle has an MS in electrical engineering from Southern Methodist University.']}}, {'name': 'Thomas Ziaja', 'affiliation': 'Oracle', 'bio': {'p': ['Tom Ziaja is a principal engineer and member of the RTL development team at Oracle. His research interests include Memory Test, Built-in Self Test, and DFT architecture. Ziaja has a PhD in computer engineering from the University of Texas.']}} %*Sparc T4: A Dynamically Threaded Server-on-a-Chip %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6133263 %f/micro/yfwadl7mzmscbdz1osu4rcapgiryb0fl.pdf %m8da1ac9f50f525b9dcccc6540a5e2f3c %cmicro %@[{'name': 'Efraim Rotem', 'affiliation': 'Intel', 'bio': {'p': ["Efraim Rotem is a senior principal engineer in the client microprocessor group at Intel, where he's working on next-generation power-management features. His interests include CPUs, systems on chip, and platform power management. Rotem has MSc in electrical engineering from the Technion, Israeli Institute of Technology."]}}, {'name': 'Alon Naveh', 'affiliation': 'Intel', 'bio': {'p': ['Alon Naveh is a principal engineer in the client microprocessor group at Intel. His work focuses on processor and platform power management. Naveh has a BS in electrical engineering from the Technion, Israel Institute of Technology, and an MBA from San Jose State University.']}}, {'name': 'Avinash Ananthakrishnan', 'affiliation': 'Intel', 'bio': {'p': ['Doron Rajwan is a power-management architect in the client microprocessor group at Intel. His work has included power-management algorithms and firmware de-sign. Rajwan has an MSc in electronic engineering from Tel Aviv University.']}}, {'name': 'Eliezer Weissmann', 'affiliation': 'Intel', 'bio': {'p': ['Avinash Ananthakrishnan is a power-management architect in the client microprocessor group at Intel. His work focuses on P-state optimization, turbo, package power sharing, platform power delivery, and power-performance projections on client CPU platforms. Ananthakrishnan has an MSc in electrical engineering from the University of Michigan.']}}, {'name': 'Doron Rajwan', 'affiliation': 'Intel, Haifa', 'bio': {'p': ["Eliezer Weissmann is a principal engineer in the software and service group at Intel, where he's working on next-generation power-management features. His interests include the architecture definition of power-management features, optimization of idle and performance states, and software and hardware optimization for CPU and graphics compu-tation. Weissmann has an MSc in computer science from the Technion, Israel Institute of Technology."]}} %*Power-Management Architecture of the Intel Microarchitecture Code-Named Sandy Bridge %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6148200 %f/micro/m6iq0einwwb4loudv8nssp9pfzma1v5k.pdf %ma51d57fe3226b909e92f60cf072a427a %cmicro %@[{'name': 'Alexander Branover', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ['Alexander Branover is an Advanced Micro Devices principal staff member involved in system-on-chip (SoC) architecture and power management. His research interests include SoC architecture, design, power management, and 1/0 protocols. Branover has an MS in computer engineering from the Technion (Institute of Technology), Israel. He is a member of the Peripheral Component Interconnect Special Interest Group (PCI-SIG).']}}, {'name': 'Denis Foley', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ["Denis Foley is an Advanced Micro Devices senior fellow. He is a chief SoC architect for AMD's low-power designs, including Zacate and Llano APUs. His research interests include client, server, game-console, and hand-held system and SoC architecture. Foley has a BS in electrical engineering from University College, Cork. He is a member of IEEE."]}}, {'name': 'Maurice Steinman', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ['Maurice Steinman is an Advanced Micro Devices fellow involved in NorthBridge and SoC architecture and power management. His research interests include client and server SoC architecture, design, and power management. Steinman has a BS in computer and systems engineering from Rensselaer Polytechnic Institute. He is a member of the Peripheral Component Interconnect Special Interest Group (PCI-SIG). Direct questions and comments about this article to Alexander Branover, 783 Newton St., Chestnut Hill, MA, 02467, alex.branover@amd.com.']}} %*AMD Fusion APU: Llano %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6138843 %f/micro/4gtob0hworm2iae3lkcql59hsdzdymxy.pdf %mf130dc9f012f9da7ae996d18a8f7c935 %cmicro %@[{'name': 'Dongrui Fan', 'affiliation': 'Institute of Computing Technology, Chinese Academy of Sciences', 'bio': {'p': ['Dongrui Fan is an associate professor in the State Key Laboratory of Computer Architecture of China at the Institute of Computing Technology, Chinese Academy of Sciences, and the chief architect of the Godson-T manycore processor. His research interests include computer microarchitecture design, low-power technologies, and VLSI design. Fan has a PhD in computer science from ICT.']}}, {'name': 'Hao Zhang', 'affiliation': 'Institute of Computing Technology, Chinese Academy of Sciences', 'bio': {'p': ['Hao Zhang is an assistant professor in the State Key Laboratory of Computer Architecture of China at the Institute of Computing Technology, Chinese Academy of Sciences, and an architect of the Godson-T many-core processor. His research interests include high-throughput CPU microarchitecture. Zhang has a PhD in computer science from ICT.']}}, {'name': 'Da Wang', 'affiliation': 'Institute of Computing Technology, Chinese Academy of Sciences', 'bio': {'p': ['Da Wang is an assistant professor in the State Key Laboratory of Computer Architecture of China at the Institute of Computing Technology, Chinese Academy of Sciences, and a member of the Godson-T research team. Her research interests include reconfigurable computing, reliability design, and VLSI design and test. Wang has a PhD in computer science from ICT.']}}, {'name': 'Xiaochun Ye', 'affiliation': 'Institute of Computing Technology, Chinese Academy of Sciences', 'bio': {'p': ['Xiaochun Ye is an assistant professor in the State Key Laboratory of Computer Architecture of China at the Institute of Computing Technology, Chinese Academy of Sciences, and a member of the Godson-T research team. His research interests include multicore and many-core design, parallel computing, and simulation. Ye has a PhD in computer science from ICT.']}}, {'name': 'Fenglong Song', 'affiliation': 'Institute of Computing Technology, Chinese Academy of Sciences', 'bio': {'p': ['Fenglong Song is an assistant professor in the State Key Laboratory of Computer Architecture of China at the Institute of Computing Technology, Chinese Academy of Sciences, and a member of the Godson-T research team. His research interests include high-performance and throughput microprocessors and memory subsystems design. Song has a PhD in computer science from ICT.']}}, {'name': 'Guojie Li', 'affiliation': 'Institute of Computing Technology, Chinese Academy of Sciences', 'bio': {'p': ['Guojie Li is the chief scientist of the Godson-T project at the Institute of Computing Technology, Chinese Academy of Sciences, and a fellow of the Chinese Academy of Engineering. His research interests include CPU microarchitecture, social computing, grid computing, and highperformance computer architecture. Li has a PhD in electrical engineering from Purdue University.']}}, {'name': 'Ninghui Sun', 'affiliation': 'Institute of Computing Technology, Chinese Academy of Sciences', 'bio': {'p': ['Ninghui Sun is a professor and the president of the Institute of Computing Technology, Chinese Academy of Sciences. His research interests include computer architecture, operating systems, and parallel algorithms. Sun has a PhD in computer science from the Institute of Computing Technology.', 'Direct questions and comments about this article to Da Wang, State Key Laboratory of Computer Architecture of China, Institute of Computing Technology, Chinese Academy of Sciences, PO Box 2704, Beijing, China, 100190, wangda@ict.ac.cn.']}} %*Godson-T: An Efficient Many-Core Processor Exploring Thread-Level Parallelism %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6177307 %f/micro/afbhepy7r8cn3opz5djhewvfw10zk9om.pdf %m531b3aa81b90a07364309079eb94b3ac %cmicro %@[{'name': 'Ruud Haring', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ['Ruud A. Haring is a research staff member and manager of Blue Gene Chip Design at the IBM T.J. Watson Research Center, where he is responsible for the synthesis, physical design, and design for test of the Blue Gene chip designs, as well as for functional diagnostics of Blue Gene cards and systems. His research interests include electronic circuit design on microprocessors and application-specific integrated circuits (ASICs). Haring has a PhD in physics from Leyden University (the Netherlands). He is a senior member of IEEE.']}}, {'name': 'Martin Ohmacht', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ['Martin Ohmacht is a research staff member and manager at the IBM T.J. Watson Research Center, where he has worked on memory subsystem architecture and implementation for all Blue Gene supercomputer systems. His research interests include computer architecture, memory subsystems, speculative execution, design and verification of multiprocessor systems, and compiler optimizations. Ohmacht has a Dr-Ing in electrical engineering from the University of Hanover, Germany. He is a member of IEEE and the ACM.']}}, {'name': 'Thomas Fox', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ['Thomas W. Fox is a senior engineer at the IBM T.J. Watson Research Center, where he has worked on digital signal processors, domain-specific graphics processors, PowerPC general-purpose processors, and the Blue Gene/Q Quad floating-point unit. His professional interests include processor architectures, floating-point arithmetic, and 3D graphics. Fox has an MEE in electrical engineering from Rensselaer Polytechnic Institute.']}}, {'name': 'Michael Gschwind', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ["Michael K. Gschwind is a senior technical staff member and senior manager of system architecture in the IBM Systems and Technology Group in Poughkeepsie, where his team defines the architecture of IBM's mainframe System z and Power systems. He previously served as Blue Gene/Q floating-point chief architect and lead at the IBM T.J. Watson Research Center. Gschwind has a PhD in computer engineering from Technische Universitaet Wien. He is an IEEE fellow, an IBM Master Inventor, and a member of the IBM Academy of Technology."]}}, {'name': 'David Satterfield', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ["David L. Satterfield is a senior engineer at the IBM T.J. Watson Research Center, where he works on the design, verification, and bring-up of the Blue Gene/Q supercomputer. His professional interests have included the design, verification, and bring-up of the Blue Gene/P network interconnect ASIC, and the design of the microprocessors used in the XBOX 360 and of a low-power floating-point unit for IBM's embedded PowerPC processor line. Satterfield has a BS in electrical engineering from Tufts University."]}}, {'name': 'Krishnan Sugavanam', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ['Krishnan Sugavanam is a senior engineer at the IBM T.J. Watson Research Center. His research interests are in computer architecture, with emphasis on cache design. Suga-vanam has an MS in computer engineering from the University of Louisiana at Lafayette and an MS in applied electronics from Anna University, Chennai, India.']}}, {'name': 'Paul Coteus', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ["Paul W. Coteus is a research staff member and the chief engineer of Blue Gene systems at the IBM T.J. Watson Research Center, where he leads the system design and packaging of these supercomputers. He manages the Systems Packaging Group, where he directs and designs advanced packaging for high-speed electronics, including I/O circuits, memory system design and standardization of high-speed DRAM, and high-performance system packaging. Coteus has a PhD in physics from Columbia University. He is a senior member of IEEE, a member of IBM's Academy of Technology, and an IBM Master Inventor."]}}, {'name': 'Philip Heidelberger', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ["Philip Heidelberger is a research staff member at the IBM T.J. Watson Research Center. He is a member of IBM Research's Blue Gene supercomputer hardware team, where he has been involved in network architecture and design, logic verification, hardware bring-up, network software inter-faces, and efficient communications algo-rithms. Heidelberger has a PhD in operations research from Stanford University. He is a member of the IBM Academy of Technology and a fellow of IEEE and the ACM."]}}, {'name': 'Matthias Blumrich', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ['Matthias A. Blumrich is a research staff member and member of the Blue Gene hardware team at the IBM T.J. Watson Research Center, where he has worked on the architecture and design of the Blue Gene/L, Blue Gene/P, and Blue Gene/Q systems. Blumrich has a PhD in computer science from Princeton University.']}}, {'name': 'Robert Wisniewski', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ['Robert W. Wisniewski is the chief software architect for Blue Gene and manager of the Blue Gene and Exascale Research Software Team at the IBM T.J. Watson Research Center. His research interests include experimental scalable systems with the goal of achieving high performance by cooperation between system and application, as well as studying how to structure and design systems to perform well on parallel machines, and how to design those systems to allow user customization. Wisniewski has a PhD in computer science from the University of Rochester. He is an IBM Master Inventor and ACM Distinguished Member.']}}, {'name': 'alan gara', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ['Alan Gara is an Intel fellow. He was previously the chief architect of the IBM Blue Gene systems at the IBM T.J. Watson Research Center. His research interests include the design and realization of power-efficient high-performance supercomputers. Gara has a PhD in physics from the University of Wisconsin, Madison.']}}, {'name': 'George Chiu', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ['George Liang-Tai Chiu is the senior manager of Advanced High Performance Systems in the Systems Department at the IBM T.J. Watson Research Center, where he is responsible for the overall hardware and software of the Blue Gene Platform. Chiu is one of the three cofounders of the Blue Gene project, and he has been in charge of the Blue Gene supercomputer designs. Chiu has a PhD in astrophysics from the University of California, Berkeley. He is a member of the International', 'Astronomical Union and the IBM Academy of Technology and a fellow of IEEE.']}}, {'name': 'Peter Boyle', 'affiliation': 'University of Edinburgh', 'bio': {'p': ['Peter A. Boyle is a reader in theoretical particle physics at the University of Edinburgh. His research interests are in quantum field theory, lattice quantum chromodynamics (QCD), and supercomputer codesign for QCD simulation. Boyle has a PhD in theoretical particle physics from the Uni-versity of Edinburgh.']}}, {'name': 'Norman Chist', 'affiliation': 'Columbia University', 'bio': {'p': ['Norman H. Christ is the Gildor Professor of Physics at Columbia University. His research interests include particle physics, lattice gauge theory, and quantum field theory. Christ has a PhD in physics from Columbia University. He is a fellow of the American Physical Society.']}}, {'name': 'Changhoan Kim', 'affiliation': 'AIKEN BNL Research Center', 'bio': {'p': ['Changhoan Kim is a research staff member at the IBM T.J. Watson Research Center.', 'He designed the prefetch unit for Blue Gene/Q while at Columbia University and RIKEN BNL Research Center. His research interests include supercomputer chip design, algorithm development, application performance optimization on massively parallel super-computers, and extending the utility of highperformance computing beyond academia. Kim has a PhD in physics from Columbia University.', 'Direct questions and comments about this article to Ruud A. Haring, IBM T.J. Watson Research Center, PO Box 218, Yorktown Heights, NY 10598, ruud@us.ibm.com.', 'Selected CS articles and columns are also ${\\ssr cn}$ available for free at http://ComputingNow.computer.org.']}} %*The IBM Blue Gene/Q Compute Chip %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6109225 %f/micro/3y8qz71klaufpb5ihpdeouvwni2bqmdf.pdf %m762a3e0795694eed2596786b0f074178 %cmicro %@[{'name': 'Richard Mateosian', 'affiliation': 'xrm@pacbell.net', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6177300/6177308/6177308-photo-1-small.gif', 'p': []}} %*Miscellany %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6177308 %f/micro/1kvjcctda8bwxz6rs27kup34fqmyifdu.pdf %me001105ab7140ab1b1f4921c34db4b08 %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'greenstein@kellogg.northwestern.edu'} %*A Big Payoff %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6177309 %f/micro/nywjl3leyqm9g8fw5aanocitiexhpbds.pdf %mf7edc7401dd08fe3ca4bc0e6a9e83d1f %cmicro %@[{'name': 'Erik R. Altman', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6208901/6208905/6208905-photo-1-small.gif', 'p': []}} %*Top Picks, Columnists, and Artists %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6208905 %f/micro/qmps7k6apoora1nb8bdiuyxkttqw5ell.pdf %me0892e4d793a718356c0b2914236a73b %cmicro %@[{'name': 'Paolo Faraboschi', 'affiliation': 'Hewlett-Packard Labs', 'bio': {'p': ['Paolo Faraboschi is a distinguished technologist in the Intelligent Infrastructure Lab at Hewlett-Packard Labs. His research interests are at the intersection of computer architecture and systems and software, and include energy-efficient servers, system-on-chip architectures, modeling and simulation, and very long instruction word (VLIW) cores and compilers. Faraboschi has a PhD in electrical engineering from the University of Genoa.']}}, {'name': 'T.N. Vijaykumar', 'affiliation': 'Purdue University', 'bio': {'p': ['T.N. Vijaykumar is an associate professor in the School of Electrical and Computer Engineering at Purdue University. His research is in computer architecture, focusing on performance, power, programmability, and reliability of general-purpose microprocessors and systems, including multicores and datacenter-scale clusters, power and performance optimizations for Internet router hardware, and architectures and compilers for software-programmable micro-fluidics. Vijaykumar has a PhD in computer science from the University of Wisconsin-Madison.']}} %*Top Picks from the 2011 Computer Architecture Conferences %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6208906 %f/micro/gwpizj7yhxkbjvzxch24mpdfn563nq0r.pdf %m92d1442fe1df6e19197b714b315dc662 %cmicro %@[{'name': 'Wilson Wai Lun Fung', 'affiliation': 'University of British Columbia', 'bio': {'p': ['Wilson W.L. Fung is a PhD student in the Department of Electrical and Computer Engineering at the University of British Columbia. His research interests include parallel-programming models and manycore accelerators. Fung has an MASc in computer engineering from the University of British Columbia.']}}, {'name': 'Inderpreet Singh', 'affiliation': 'University of British Columbia', 'bio': {'p': ['Inderpreet Singh is pursuing an MASc in the Department of Electrical and Computer Engineering at the University of British Columbia. His research interests include programming models for many-core accelerators. Singh has a BASc in engineering physics from the University of British Columbia.']}}, {'name': 'Andrew Brownsword', 'affiliation': 'Electronic Arts', 'bio': {'p': ['Andrew Brownsword is a software architect at Intel. He performed the work described in this article while he was a senior software engineer at Electronic Arts. His research interests include improving parallel-programming models on massively parallel machines. Brownsword has a BSc in computer science from the University of British Columbia.']}}, {'name': 'Tor Aamodt', 'affiliation': 'University of British Columbia', 'bio': {'p': ['Tor M. Aamodt is an associate professor in the Department of Electrical and Computer Engineering at the University of British Columbia. His research interests include many-core accelerators (such as GPUs), heterogeneous multicore processors, and analytical performance modeling of processor architectures. Aamodt has a PhD in electrical and computer engineering from the University of Toronto. He is a member of IEEE and the ACM.']}} %*Kilo TM: Hardware Transactional Memory for GPU Architectures %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6174995 %f/micro/cakue9lu8ydpenlaso4qvsj1zhqfw3kn.pdf %mec44563d50e8089f47f7162f94dddbb8 %cmicro %@[{'name': 'Boris Grot', 'affiliation': 'É,cole Polytechnique Fé,dé,rale de Lausanne', 'bio': {'p': ['Boris Grot is a postdoctoral researcher at Ecole Polytechnique Fédérale de Lausanne. His research focuses on processor architectures, memory systems, and interconnection networks for high-throughput, energy-aware computing. Grot has a PhD in computer science from the University of Texas at Austin.']}}, {'name': 'Joel Hestness', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ['Joel Hestness is a PhD student in computer science at the University of Texas at Austin. His research interests include future highly integrated chips, on-chip networks, and communication. Hestness has a BS in computer science and in mathematics from the University of Wisconsin—Madison.']}}, {'name': 'Stephen Keckler', 'affiliation': 'Nvidia', 'bio': {'p': ['Stephen W. Keckler is the senior director of architecture research at Nvidia and a professor in the Department of Computer Science at the University of Texas at Austin. His research interests include parallel computer architectures, memory systems, and interconnection networks. Keckler has a PhD in computer science from the Massachusetts Institute of Technology.']}}, {'name': 'Onur Mutlu', 'affiliation': 'Carnegie Mellon University', 'bio': {'p': ['Onur Mutlu is an assistant professor in the Electrical and Computer Engineering Department at Carnegie Mellon University. His research interests include computer architecture, hardware/software cooperation, and memory and communication systems. Mutlu has a PhD in electrical and computer engineering from the University of Texas at Austin.']}} %*A QoS-Enabled On-Die Interconnect Fabric for Kilo-Node Chips %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6175881 %f/micro/ry1fc0onmctgmerlqhqdu2fsb8zkz5yi.pdf %mc994954c8c66fd1f83f40d46804298e7 %cmicro %@[{'name': 'Daniel Sanchez', 'affiliation': 'Stanford University', 'bio': {'p': ['Daniel Sanchez is a PhD student in the Department of Electrical Engineering at Stanford University. His research focuses on large-scale chip multiprocessors, specifically on scalable and dynamic fine-grained runtimes and schedulers, hardware support for scheduling, scalable and efficient memory hierarchies, and architectures with quality-of-service guarantees. Sanchez has an MS in electrical engineering from Stanford University. He is a student member of IEEE.']}}, {'name': 'Christos Kozyrakis', 'affiliation': 'Stanford University', 'bio': {'p': ['Christos Kozyrakis is an associate professor of electrical engineering and computer science and the Willard R. and Inez Kerr Bell faculty scholar at Stanford University. His research interests include energy-efficient data centers, architecture and runtime environments for large-scale chip multiprocessors, hardware and software techniques for transactional memory, and security systems. Kozyrakis has a PhD in computer science from the University of California, Berkeley. He is a senior member of IEEE and ACM.']}} %*Scalable and Efficient Fine-Grained Cache Partitioning with Vantage %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6175882 %f/micro/hcn23qrvwauxxtkesz9u8av4ggibzocw.pdf %m6342105b92ac5d5abb873e2a4f7d6005 %cmicro %@[{'name': 'Hung-Wei Tseng', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Hung-Wei Tseng is a PhD candidate in the Department of Computer Science and Engineering at the University of California, San Diego. His research interests include programming models, system design and architecture for parallel computing, multicore processors, and nonvolatile, solid-state memories. Tseng has an MS in computer science from N ational Taiwan University.']}}, {'name': 'Dean M. Tullsen', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Dean Tullsen is a professor in the Department of Computer Science and Engineering at the University of California, San Diego. His research interests include architecture and compilers for multicore and multithreaded architectures. T ullsen has a PhD in computer science from the University of Washington. He is a fellow of IEEE and the ACM.', 'Direct questions and comments about this article to Hung-Wei Tseng, Dept. of Computer Science and Engineering, University of California, San Diego, 9500 Gilman Dr., Mail Code 0404, La Jolla, CA 92093–0404, h1tseng@cs.ucsd.edu.']}} %*Eliminating Redundant Computation and Exposing Parallelism through Data-Triggered Threads %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6174997 %f/micro/xvspsfgetj8khop01rwhq9adbevtlbyo.pdf %mccb564e4679d171d0eac20824ee771a9 %cmicro %@[{'name': 'Niket Choudhary', 'affiliation': 'North Carolina State University', 'bio': {'p': ['Niket K. Choudhary is a PhD student in the Department of Electrical and Computer Engineering at North Carolina State Uni-versity. His research interests include computer architecture, superscalar processor design automation, and heterogeneous multicore architecture design. Choudhary has an MS in computer engineering from North Carolina State University. He is a student member of the ACM.']}}, {'name': 'Salil Wadhavkar', 'affiliation': 'North Carolina State University', 'bio': {'p': ['Salil V. Wadhavkar is a PhD student in the Department of Electrical and Computer Engineering at North Carolina State Uni-versity. His research interests are heterogeneous multicore architectures, energy-efficient processor design, and workload analysis. Wadhavkar has an MSE in electrical engineering from Temple University. He is a student member of IEEE.']}}, {'name': 'Tanmay Shah', 'affiliation': 'North Carolina State University', 'bio': {'p': ['Tanmay A. Shah is a video ASIC design engineer at Qualcomm. His research interests include VLSI design and microarchitecture. Shah has an MS in computer engineering from North Carolina State University.', 'We honor the bright life and memory of Hiran Mayukh, who left us too soon. He received his BTech in electronics and communication engineering from National Institute of Technology, Karnataka, India, in 2008. He received his MS in computer engineering from North Carolina State University in 2010 and subsequently joined the Department of Electrical and Computer Engineering at the University of Wiscon-sin-Madison. His friendship and scholarly achievements will always be cherished.']}}, {'name': 'Hiran Mayukh', 'affiliation': 'North Carolina State University', 'bio': {'p': ['Jayneel Gandhi is a PhD student in the Department of Electrical and Computer Engineering at the University of Wisconsin-Madison. His research interests include computer architecture and VLSI design. Gandhi has an MS in computer engineering from North Carolina State University.']}}, {'name': 'Jayneel Gandhi', 'affiliation': 'North Carolina State University', 'bio': {'p': ['Brandon H. Dwiel is a PhD student in the Department of Electrical and Computer Engineering at North Carolina State Uni-versity. His research interests include adaptive processors and 3D-enabled computer archi-tectures. Dwiel has an MS in computer engineering from North Carolina State Uni-versity. He is a student member of the ACM.']}}, {'name': 'Brandon Dwiel', 'affiliation': 'North Carolina State University', 'bio': {'p': ['Sandeep Navada is a PhD student in the Department of Electrical and Computer Engineering at North Carolina State Uni-versity. His research interests include processor microarchi tectures, bottleneck analysis, application steering in heterogeneous multicore processors, machine learning, and embedded systems. Navada has a BTech in electrical engineering from the Indian Institute of Technology.']}}, {'name': 'Sandeep Navada', 'affiliation': 'North Carolina State University', 'bio': {'p': ['Hashem H. Najaf-abadi is a graphics hardware engineer at Intel, where he works on streaming architectures. His research interests include asymmetry in multicore and streaming architectures. Najaf-abadi has a PhD in computer engineering from North Carolina State University. He is a member of IEEE and the ACM.']}}, {'name': 'Hashem Najaf-abadi', 'affiliation': 'North Carolina State University', 'bio': {'p': ['Eric Rotenberg is a professor in the Department of Electrical and Computer Engineering at North Carolina State Uni-versity. His research interests include superscalar processor design automation, heterogeneous multicore processors, and novel microarchitectures. Rotenberg has a PhD in computer sciences from the Uni-versity of Wisconsin-Madison. He is a senior member of IEEE.']}}, {'name': 'Eric Rotenberg', 'affiliation': 'North Carolina State University'} %*FabScalar: Automating Superscalar Core Design %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6178201 %f/micro/hcaq3tquoclnpjymwj2fvpbt89gi5ydx.pdf %m2b7ed7c3354bd8b256ffb73fc7458e04 %cmicro %@[{'name': 'Qingyuan Deng', 'affiliation': 'Rutgers University', 'bio': {'p': ['Qingyuan Deng is a PhD candidate in the Department of Computer Science at Rutgers University. His research interests include memory systems, server and data center energy efficiency, and computer architecture. Deng has a BS in computer science and engineering from Beihang University, China. He is a student member of IEEE and the ACM.']}}, {'name': 'Luiz Ramos', 'affiliation': 'Rutgers University', 'bio': {'p': ['Luiz Ramos is a postdoctoral fellow at the Federal University of Minas Gerais. His research interests include power, energy, and temperature management for data centers, parallel processing, algorithms, and architectures. Ramos has a PhD from Rutgers University. He is a member of the IEEE and the Brazilian Computer Society.']}}, {'name': 'Ricardo Bianchini', 'affiliation': 'Rutgers University', 'bio': {'p': ['Ricardo Bianchiniis a professor in the Department of Computer Science at Rutgers University. His research interests include the power, energy, and thermal management of servers and data centers. Bianchini has a PhD in computer science from the University of Rochester. He is an ACM distinguished scientist and a member of IEEE.']}}, {'name': 'David Meisner', 'affiliation': 'University of Michigan, Ann Arbor', 'bio': {'p': ['David Meisner is a PhD candidate in the Department of Computer Science and Engineering at the University of Michigan. His research interests include energy-efficient data center design and server power-performance modeling. Meisner has a MSE in computer science and engineering from University of Michigan. He is a student member of the ACM.']}}, {'name': 'Thomas Wenisch', 'affiliation': 'University of Michigan, Ann Arbor', 'bio': {'p': ['Thomas F. Wenisch is the Morris Wellman Faculty Development Assistant Professor of electrical engineering and computer science at the Universi ty of Michigan. His research interests include computer architecture, server and data center energy efficiency, smartphone architecture, and multiprocessor systems. Wenisch has a PhD in electrical and computer engineering from Carnegie Mellon University. He is a member of IEEE and the ACM.', 'Direct questions and comments about this article to Qingy uan Deng, Rutgers University, 110 Frelinghuysen Rd., Dept. of Computer Science, Piscataway, NJ 08854, qdeng@cs.rutgers.edu.']}} %*Active Low-Power Modes for Main Memory with MemScale %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6178197 %f/micro/8usx76jxsmt2brypnkepmqak0wii15hd.pdf %m72d48eb9d30ff9f6562aeaf7d46fad58 %cmicro %@[{'name': 'Gabriel Loh', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ['Gabriel H. Loh is a principal researcher at Advanced Micro Devices. His research interests include computer architecture, processor microarchitecture, emerging technologies, and 3D die stacking. Loh has a PhD in computer science from Yale University. He is a senior member of IEEE and the ACM.']}}, {'name': 'Mark D. Hill', 'affiliation': 'University of Wisconsin—,Madison', 'bio': {'p': ['Mark D. Hill is a professor in both the Computer Sciences Department and the Electrical and Computer Engineering Department at the University of Wisconsin—Madison. This work was performed largely while Hill was on sabbatical leave at Advanced Micro Devices. His research interests include parallel-computer system design, memory system design, computer simulation, deterministic replay, and transactional memory. Hill has a PhD in computer science from the University of California, Berkeley. He is a fellow of IEEE and the ACM.', 'Direct questions and comments about this article to Gabriel H. Loh, Advanced Micro Devices, 2002 156th Ave. NE, Suite 300, Bellevue, WA 98007, gabriel.loh@amd.com.']}} %*Supporting Very Large DRAM Caches with Compound-Access Scheduling and MissMap %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6180161 %f/micro/f6a1cosp5nr0qhwujqldxtfiykzgtcve.pdf %mbc1efe9e7b44a6d8c084bf39c84135e5 %cmicro %@[{'name': 'Doe Hyun Yoon', 'affiliation': 'Hewlett-Packard Labs', 'bio': {'p': ['Doe Hyun Yoon is a postdoctoral researcher at Hewlett-Packard Labs. His research includes power efficiency and reliability in memory systems, including caches, DRAM, and nonvolatile memory. Y oon has a PhD in electrical and computer engineering from the University of Texas at Austin.']}}, {'name': 'Naveen Muralimanohar', 'affiliation': 'Hewlett-Packard Labs', 'bio': {'p': ['Naveen Muralimanohar is a researcher at Hewlett-Packard Labs. His research interests include designing and modeling next-generation memory systems, building communication fabrics for future servers and data centers, and solving reliability challenges associated with large compute clusters. Muralimanohar has a PhD in computer science from the University of Utah. He is a member of IEEE and ACM.']}}, {'name': 'Jichuan Chang', 'affiliation': 'Hewlett-Packard Labs', 'bio': {'p': ['Jichuan Chang is a principal research scientist at Hewlett-Packard Labs. His research interests include computer system architecture and memory systems. Chang has a PhD in computer sciences from the University of Wisconsin-Madison. He is a senior member of IEEE.']}}, {'name': 'Parthasarathy Ranganathan', 'affiliation': 'Hewlett-Packard Labs', 'bio': {'p': ['Parthasarathy Ranganathan is a corporate fellow at Hewlett-Packard Labs. His research interests include server and datacenter architectures and energy efficiency. Ranganathan has a PhD in electrical and computer engineering from Rice University. He is an IEEE Fellow.']}}, {'name': 'Norman Jouppi', 'affiliation': 'Hewlett Packard', 'bio': {'p': ['Norman P. Jouppi is an HP Senior Fellow and director of the Intelligent Infrastructure Lab at Hewlett-Packard Labs. His research interests include stream prefetch buffers, victim caching, multilevel exclusive caching, and modeling cache timing, area, and power. J ouppi has a PhD in electrical engineering from Stanford University. He is a fellow of IEEE and the ACM.']}}, {'name': 'Mattan Erez', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ['Mattan Erez is an assistant professor in the Electrical and Computer Engineering Department at the University of Texas at Austin. His research interests include computer architecture and programming models. Erez has a PhD in electrical engineering from Stanford University.']}} %*Free-p: A Practical End-to-End Nonvolatile Memory Protection Mechanism %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6174996 %f/micro/l5ayuj2qijh7bnmfpmeywrciwlbznxtk.pdf %m0d3bb9d158646f58407352e26967004f %cmicro %@[{'name': 'Jason Mars', 'affiliation': 'University of Virginia', 'bio': {'p': ['Jason Mars is a PhD candidate in the Computer Science Department at the University of Virginia. His research interests include adaptive systems in software and hardware, warehouse-scale computer architecture, and software/hardware codesigned architectures. Mars has an MS in computer science from the University of Virginia. He is a member of IEEE and the ACM.']}}, {'name': 'Lingjia Tang', 'affiliation': 'University of Virginia', 'bio': {'p': ['Lingjia Tang is a PhD candidate in the Computer Science Department at the University of Virginia. Her research interests include compilers, runtime systems, and computer architecture. Tang has an MS in computer science from the University of Virginia.']}}, {'name': 'Kevin Skadron', 'affiliation': 'University of Virginia', 'bio': {'p': ['Kevin Skadron is a professor in the Computer Science Department at the Uni-versi ty of Virginia. His research interests focus on parallel and accelerator architectures in the presence of physical constraints such as temperature and power. Skadron has a PhD in computer science from Princeton University. He is a senior member of IEEE and the IEEE Computer Society and a distinguished member of the ACM.']}}, {'name': 'Mary Lou Soffa', 'affiliation': 'University of Virginia', 'bio': {'p': ['Mary Lou Soffa is the Owen R. Cheatham Professor and department chair of the Computer Science Department at the Uni-versi ty of Virginia. Her research interests include optimizing compilers, virtual execution environments, software testing, program analysis, instruction-level parallelism, and multicore architectures. Soffa has a PhD in computer science from the University of Pittsburgh. She is an ACM Fellow.']}}, {'name': 'Robert Hundt', 'affiliation': 'Google', 'bio': {'p': ["Robert Hundt is a tech lead at Google, where he's working on compiler optimization datacenter performance, and Gmail performance. Hundt has a Diplom Univ. in informatik from the Technical University in Munich. He is a senior member of IEEE.", 'Direct questions and comments about this article to Jason Mars, 2000 Jefferson Park Ave., Apt. 12, Charlottesville, VA, 22903, mars.ninja@gmail.com.']}} %*Increasing Utilization in Modern Warehouse-Scale Computers Using Bubble-Up %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6178199 %f/micro/jlmitdc58iob34vds02fjtruzrql9qey.pdf %m183128593823a6c2b7e4b4f8a1f3503f %cmicro %@[{'name': 'Nathan Binkert', 'affiliation': 'Nou Data', 'bio': {'p': ['Nathan Binkert is a cofounder of Nou Data, where he is developing a next-generation distributed, flexible SQL engine targeted at NoSQL data. His research interests include computer architecture, operating systems, and networking. Binkert has a PhD in computer engineering from the University of Michigan, Ann Arbor. He is a member of IEEE and the ACM.']}}, {'name': 'Al Davis', 'affiliation': 'Hewlett-Packard Labs', 'bio': {'p': ['Al Davis is a professor and director of the School of Computing at the University of Utah and a part-time visiting scientist at the Intelligent Infrastructure Laboratory at Hewlett-Packard Labs. His research interests include very large-scale integration (VLSI) circuit design, asynchronous circuits, electronic design automation (EDA) CAD tool design, and computer architecture. Davis has a PhD in computer science from the University of Utah. He is a member of IEEE.']}}, {'name': 'Norman Jouppi', 'affiliation': 'Hewlett-Packard Labs', 'bio': {'p': ['Norman P. Jouppi is a Hewlett-Packard senior fellow and director of the Intelligent Infrastructure Lab at Hewlett-Packard Labs. His research focuses on computer memory systems, including stream prefetch buffers, victim caching, multilevel exclusive caching, and development of the Cacti tool for modeling cache timing, area, and power. Jouppi has a PhD in electrical engineering from Stanford University. He is a coauthor of Multi-Core Cache Hierarchies (Morgan & Claypool, 2011) and a fellow of IEEE and the ACM.']}}, {'name': 'Moray McLaren', 'affiliation': 'Hewlett-Packard Labs', 'bio': {'p': ['Moray McLaren is a distinguished technologist in the Intelligent Infrastructure Lab at Hewlett-Packard Labs. His research has focused on the impact of nanophotonics on future computer architectures, specifically high-speed networking and memory architectures. McLaren has a first-class honors degree in microelectronics from the University of Edinburgh.']}}, {'name': 'Naveen Muralimanohar', 'affiliation': 'Hewlett-Packard Labs', 'bio': {'p': ['Naveen Muralimanohar is a senior researcher in the Intelligent Infrastructure Lab at Hewlett-Packard Labs. His research interests include designing reliable and efficient memory hierarchy and communication fabrics for high-performance systems. Muralimanohar has a PhD in computer science from the University of Utah. He is a coauthor of Multi-Core Cache Hierarchies (Morgan & Claypool, 2011) and a member of IEEE and the ACM.']}}, {'name': 'Robert schreiber', 'affiliation': 'Hewlett-Packard Labs', 'bio': {'p': ['Robert Schreiber is a researcher at Hewlett-Packard Labs, where he investigates the architectures, software, and algorithms needed to push the performance of supercomputing from peta-to exaflops. His research interests include parallel-matrix computation, sparse matrices, and the interface between algorithms and architectures. Schreiber has a PhD in computer science from Yale University. He is a member of IEEE, an ACM Distinguished Scientist, and a fellow of the Society for Industrial and Applied Mathematics (SIAM).']}}, {'name': 'Jung Ho Ahn', 'affiliation': 'Seoul National University', 'bio': {'p': ['Jung Ho Ahn is an assistant professor in the Graduate School of Convergence Science and Technology at Seoul National University, where he leads the Scalable Computer Architecture Laboratory. His research interests include designing high-performance and high-efficiency memory systems and interconnection networks, as well as bridging the gap between the performance demand of emerging applications and the performance potential of modern and future massively parallel systems. Ahn has a PhD in electrical engineering from Stanford University.', 'Direct questions and comments about this article to Naveen Muralimanohar, Hewlett Packard Labs, 1501 Page Mill Rd., Bldg. 3, MS 1183, Palo Alto, CA 94304, naveen.muralimanohar@hp.com.']}} %*Optical high radix switch design %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6175883 %f/micro/olvttqryc3djzaugwwm0zr6cgxij2fvf.pdf %m42707a974551c5d06f31be578af57386 %cmicro %@[{'name': 'Hadi Esmaeilzadeh', 'affiliation': 'University of Washington', 'bio': {'p': ['Hadi Esmaeilzadeh is a PhD student in the Department of Computer Science and Engineering at the University of Washington. His research interests include power-efficient architectures, approximate general-purpose computing, mixed-signal architectures, machine learning, and compilers. Esmaeilzadeh has an MS in computer science from the University of Texas at Austin and an MS in electrical and computer engineering from the University of Tehran.']}}, {'name': 'Ting Cao', 'affiliation': 'Australian National University', 'bio': {'p': ['Ting Cao is a PhD student in the Department of Computer Science at the Australian National University. Her research interests include architecture and programming language implementation. Cao has an MS in computer science from National University of Defense Technology, China.']}}, {'name': 'Xi Yang', 'affiliation': 'Australian National University', 'bio': {'p': ['Xi Yang is a PhD student in the Department of Computer Science at the Australian National University. His research interests include architecture, operating systems, and runtime systems. Yang has an MPhil in computer science from the Australian National University.']}}, {'name': 'Stephen Blackburn', 'affiliation': 'Australian National University', 'bio': {'p': ['Stephen M. Blackburn is a professor in the Research School of Computer Science at the Australian National University. His research interests include programming language implementation, architecture, and performance analysis. Blackburn has a PhD in computer science from the Australian National University. He is a Distinguished Scientist of the ACM.']}}, {'name': 'Kathryn McKinley', 'affiliation': 'Microsoft Research', 'bio': {'p': ['Kathryn S. McKinley is a principal researcher at Microsoft Research and an endowed professor of computer science at the University of Texas at Austin. Her research interests span architecture, programming language implementation, reliability, and security. McKinley has a PhD in computer science from Rice University. She is a fellow of IEEE and the ACM.', 'Direct questions and comments about this article to Stephen M. Blackburn, School of Computer Science, Bldg. 108, Australian National University, Acton, ACT, 0200, Australia, Steve. Blackburn@anu.edu.au.']}} %*What is Happening to Power, Performance, and Software? %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6175880 %f/micro/qdfjohkuar1w8vmk5qapgu2e6fh7gtbt.pdf %mac6418a280aa11ec0604c07066635c5e %cmicro %@[{'name': 'H. Esmaeilzadeh', 'affiliation': 'Univ. of Washington, Seattle, WA, USA', 'bio': {'p': ['Hadi Esmaeilzadeh is a PhD student in the Department of Computer Science and Engineering at the University of Washing-ton. His research interests include power-efficient architectures, approximate general-purpose computing, mixed-signal architectures, machine learning, and compilers. Esmaeilzadeh has an MS in computer science from the University of Texas at Austin and an MS in electrical and computer engineering from the University of Tehran.']}}, {'name': 'E. Blem', 'affiliation': 'Univ. of Wisconsin-Madison, Madison, WI, USA', 'bio': {'p': ['Emily Blem is a PhD student in the Department of Computer Sciences at the University of Wisconsin-Madison. Her research interests include energy and performance tradeoffs in computer architecture and quantifying them using analytic performance modeling. Blem has an MS in computer science from the University of Wisconsin-Madison.']}}, {'name': 'R. St. Amant', 'affiliation': 'Univ. of Texas at Austin, Austin, TX, USA', 'bio': {'p': ['Renee St. Amant is a PhD student in the Department of Computer Science at the University of Texas at Austin. Her research interests include computer architecture, low-power microarchitectures, mixed-signal approximate computation, new computing technologies, and storage design for approximate computing. St. Amant has an MS in computer science from the University of Texas at Austin.']}}, {'name': 'K. Sankaralingam', 'affiliation': 'Univ. of Wisconsin-Madison, Madison, WI, USA', 'bio': {'p': ['Karthikeyan Sankaralingam is an assistant professor in the Department of Computer Sciences at the University of Wisconsin-Madison, where he also leads the Vertical Research Group. His research interests include microarchitecture, architecture, and very-large-scale integration (VLSI). Sankaralingam has a PhD in computer science from the University of Texas at Austin.']}}, {'name': 'D. Burger', 'bio': {'p': ['Doug Burger is the director of client and cloud applications at Microsoft Research, where he manages multiple strategic research projects covering new user interfaces, datacenter specialization, cloud architectures, and platforms that support personalized online services. Burger has a PhD in computer science from the University of Wisconsin. He is a fellow of IEEE and the ACM.', 'Direct questions and comments about this article to Hadi Esmaeilzadeh, University of Washington, Computer Science & Engi-neering, Box 352350, AC 101, 185 Stevens Way, Seattle, WA 98195, hadianeh@cs.washington.edu.']}} %*Dark Silicon and the End of Multicore Scaling %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6175879 %f/micro/xzmv2ojgf4aebdsrnhhj6qewyumsfr3p.pdf %m12210801ae1f3ee6484e038f09122160 %cmicro %@[{'name': 'Michael Doggett', 'affiliation': 'Lund University', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6208901/6208908/6208908-photo-1-small.gif', 'p': ['Michael Doggett is an associate professor in the Lund University Graphics Group (LUGG) at Lund University. His research interests focus on image synthesis, graphics hardware, and parallel architectures. Doggett has a PhD in computer science and engineering from the University of New South Wales.', 'Direct questions or comments about this article to Michael Doggett at mike@cs.lth.se']}} %*Texture Caches %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6208908 %f/micro/hlnudxo8d6gyejtxsfoa04jrsrzwyli5.pdf %mb7e9bd1a687df2c875a0d82ad571c080 %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'greenstein@kellogg.northwestern.edu', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6208901/6208909/6208909-photo-1-small.gif', 'p': []}} %*The Secret Life of Wally Madhavani %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6208909 %f/micro/anfvypscuiehdrgbvpnxmqe0ywqkzohz.pdf %m511cd95de3d424e12be8d6bfa3535098 %cmicro %@[{'name': 'Erik R. Altman', 'affiliation': 'IBM', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6290317/6290320/6290320-photo-1-small.gif', 'p': []}} %*The Odd Couple: Hardware and Software %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6290320 %f/micro/hqnjavnbdwjxolbwccastzf2ymyp31vk.pdf %m53b151df5b903b8f99f92b1e2754f04c %cmicro %@[{'name': 'Doug Burger', 'affiliation': 'Microsoft Research', 'bio': {'p': ['Doug Burger is the director of client and cloud applications in the Extreme Computing Group at Microsoft Research and an affiliate professor of computer science and engineering at the University of Washington.']}}, {'name': 'Stephen W. Keckler', 'affiliation': 'Nvidia', 'bio': {'p': ['Stephen W. Keckler is the senior director of architecture research at Nvidia and an adjunct professor of computer science at the University of Texas at Austin.']}}, {'name': 'Mark Papermaster', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ['Mark Papermaster is a senior vice president and the chief technology officer at Advanced Micro Devices.']}} %*Charles R. (Chuck) Moore (1961&#x2014;2012) %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6290321 %f/micro/pfprod2xx0mggnkinjoktevlyw6zeczi.pdf %mab6acf8e81ba8e0e901db673cedc8921 %cmicro %@[{'name': 'David I. August', 'affiliation': 'Princeton University', 'bio': {'p': ['David I. August is a professor of computer science at Princeton University. His research interests are in synergistic compiler and micro architecture design. August has a PhD in electrical and computer engineering from the University of Illinois at Urbana-Champaign. He is a member of IEEE and the ACM.', 'Direct questions and comments about this article to David I. August at august@princeton.edu.']}} %*Parallelizing Sequential Code %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6290322 %f/micro/of7mnrt456rtbddg9gojvpcfsh20hyw3.pdf %m899da55cde731da895d3d0810316a737 %cmicro %@[{'name': 'Simone Campanoni', 'affiliation': 'Harvard University', 'bio': {'p': ['Simone Campanoni is a postdoctoral fellow in the School of Engineering and Applied Sciences at Harvard University. His research interests include code compilation challenges, static and dynamic compilation, runtime optimization, and advanced code analysis to extract coarse-grained parallelism for many-core architectures from general-purpose sequential code. Campanoni has a PhD in information engineering from Politecnico di Milano University.']}}, {'name': 'Timothy M. Jones', 'affiliation': 'University of Cambridge', 'bio': {'p': ['Timothy M. Jones is a postdoctoral researcher in the Computer Laboratory at the University of Cambridge, where he holds a research fellowship from the Engineering and Physical Sciences Research Council and the Royal Academy of Engineering. His research interests include computer architecture and compiler optimization, with an emphasis on automatic parallelization, power reduction, and the application of machine learning to compiler and microarchitectural design. Jones has a PhD in informatics from the University of Edinburgh. He is a member of IEEE and the ACM.']}}, {'name': 'Glenn Holloway', 'affiliation': 'Harvard University', 'bio': {'p': ['Glenn Holloway is a systems programmer in the School of Engineering and Applied Sciences at Harvard University. His research interests include static and dynamic code optimization, register allocation, and automatic parallelization. Holloway has an AM in physics from Harvard University.']}}, {'name': 'Gu-Yeon Wei', 'affiliation': 'Harvard University', 'bio': {'p': ['Gu-Yeon Wei is a Gordon McKay Professor of Electrical Engineering and Computer Science in the School of Engineering and Applied Sciences (SEAS) at Harvard University. He also serves as the associate dean for academic programs in the SEAS. His research interests span multiple layers of a computing system, including mixed-signal integrated circuits, computer architecture, and runtime software for automatic code parallelization. Wei has a PhD in electrical engineering from Stanford University.']}}, {'name': 'David Brooks', 'affiliation': 'Harvard University', 'bio': {'p': ['David Brooks is a Gordon McKay Professor of Computer Science in the School of Engineering and Applied Sciences at Harvard University. His research interests include power-efficient computer system design, variation-tolerant computer architectures, and embedded-system design. Brooks has a PhD in electrical engineering from Princeton University. He is a member of IEEE and the ACM.']}} %*Helix: Making the Extraction of Thread-Level Parallelism Mainstream %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6226338 %f/micro/xf4rjigas0uzitkqk6hvvdbpwoglxwje.pdf %m2e65820fe3a10ecd3f416235b047d505 %cmicro %@[{'name': 'Feng Li', 'affiliation': 'INRIA', 'bio': {'p': ["Feng Li is a PhD student at INRIA and University Pierre et Marie Curie, working in the Departement d'Informatique at Ecole Normale Supérieure. His research interests include compiler optimization, automatic parallelization, and data-flow programming and execution models. Li has an MS in electrical engineering from Xi'an Jiaotong University. He is a student member of the ACM."]}}, {'name': 'Antoniu Pop', 'affiliation': 'INRIA', 'bio': {'p': ['Antoniu Pop is a postdoctoral researcher at INRIA and Ecole Normale Supérieure, His research interests include stream programming languages, deterministic parallelization, code generation, and compiler optimization. Pop has a PhD in computer science from the Ecole Nationale Supérieure des Mines de Paris. He is a member of the ACM.']}}, {'name': 'Albert Cohen', 'affiliation': 'INRIA', 'bio': {'p': ['Albert Cohen is a senior research scientist at INRIA and Ecole Normale Supérieure and a part-time associate professor at Ecole Polytechnique. His research interests include compiler optimization for highperformance and embedded systems, automatic parallelization, and parallel data-flow and synchronous programming. Cohen has a PhD in computer science from the University of Versailles. He is a member of the ACM.', 'Selected CS articles and columns are also available for free at http://ComputingNow.computer.org.']}} %*Automatic Extraction of Coarse-Grained Data-Flow Threads from Imperative Programs %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6216345 %f/micro/z6umnq8seo0gindhvbf5awblqcpxtkwa.pdf %mfc799ed0dd71955f336dc73740afce48 %cmicro %@[{'name': 'Md Kamruzzaman', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Md Kamruzzaman is a PhD candidate in the Computer Science and Engineering Department at the University of California, San Diego. His research interests include software optimization techniques for highperformance and energy-efficient computing in parallel architecture, locality-aware programming models, and runtime systems. Kamruzzaman has a BS in computer science and engineering from Bangladesh University of Engineering and Technology. He is a member of the ACM.']}}, {'name': 'Steven Swanson', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Steven Swanson is an associate professor in the Computer Science and Engineering Department at the University of California, San Diego, where he leads the Non-Volatile Systems Laboratory. His research interests include architectural, systems, and security issues surrounding nonvolatile, solid-state memories as well as dark silicon architectures and multithreading. Swanson has a PhD in computer science from the University of Washington. He is a member of the ACM.']}}, {'name': 'Dean M. Tullsen', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Dean M. Tullsen is a professor in the Computer Science and Engineering Department at the University of California, San Diego. His research interests include architecture and compilers for multicore and multithreaded architectures. Tullsen has a PhD in computer science from the University of Washington. He is a fellow of IEEE and the ACM.']}} %*Underclocked Software Prefetching: More Cores, Less Energy %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6243130 %f/micro/57aceol4tgzp1bxfaeokriq3iswv6gjn.pdf %m90f01633df93bde4a32f5bcc10e6d33b %cmicro %@[{'name': 'Saturnino Garcia', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Saturnino Garcia is a visiting assistant professor in the Department of Mathematics and Computer Science at the University of San Diego. His research interests include program analysis, parallel software engineering, and computer science education. Garcia has a PhD in computer science from the University of California, San Diego.']}}, {'name': 'Donghwan Jeon', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Donghwan Jeon is a software engineer at Google. He completed the work described in this article while pursuing graduate studies at the University of California, San Diego. His research interests include software engineering tools for parallelization, dynamic program analysis, and parallel software systems. Jeon has a PhD from the University of California, San Diego.']}}, {'name': 'Christopher Louie', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Christopher Louie is a server and systems engineer at Gazillion Entertainment. He completed the work described in this article while pursuing graduate studies at the University of California, San Diego. His research interests include tools for software engineering and parallel systems. Louie has an MS in computer science from the University of California, San Diego.']}}, {'name': 'Michael Bedford Taylor', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Michael Bedford Taylor is a professor in the Department of Computer Science and Engineering at the University of California, San Diego, and he jointly leads the Kremlin and GreenDroid projects. His research interests include dark silicon, multicore processor design, and software tools for leveraging parallelism. Taylor has a PhD in electrical engineering and computer science from the Massachusetts Institute of Technology.']}} %*The Kremlin Oracle for Sequential Code Parallelization %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6235946 %f/micro/w35v4oketplwzsdu7fshyhyxzunaripd.pdf %m5dc477a61539ecf239e6765ea8e239bc %cmicro %@[{'name': 'Hengjie Li', 'affiliation': 'Institute of Computing Technology, CAS', 'bio': {'p': ['Hengjie Li is a PhD student in the State Key Laboratory of Computer Architecture of the Institute of Computing Technology, CAS (Chinese Academy of Sciences), and in the Graduate University of the Chinese Academy of Sciences. His research interests include performance optimization and parallelization. Li has an undergraduate degree in computer science and technology from Harbin Institute of Technology.']}}, {'name': 'Wenting He', 'affiliation': 'Institute of Computing Technology, CAS', 'bio': {'p': ['Wenting He is a PhD student in the State Key Laboratory of Computer Architecture of the Institute of Computing Technology, CAS (Chinese Academy of Sciences), and in the Graduate University of the Chinese Academy of Sciences. Her research interests include performance optimization and approximate computation. He has an undergraduate degree in computer science from Fuzhou University.']}}, {'name': 'Yang Chen', 'affiliation': 'Institute of Computing Technology, CAS', 'bio': {'p': ['Yang Chen is a postdoctoral researcher in the State Key Laboratory of Computer Architecture of the Institute of Computing Technology, CAS (Chinese Academy of Sciences). His research interests include performance optimization and iterative optimization. Chen has a PhD in computer science from the Institute of Computing Technology at the Chinese Academy of Sciences.']}}, {'name': 'Lieven Eeckhout', 'affiliation': 'Ghent University', 'bio': {'p': ['Lieven Eeckhout is an associate professor in the Electronics and Information Systems Department at Ghent University. His research interests include computer architecture and the hardware-software interface, with a focus on performance analysis, evaluation and modeling, and workload characterization. Eeckhout has a PhD in computer science and engineering from Ghent University. He is a member of IEEE and the ACM and the Associate Editor in Chief of IEEE Micro.']}}, {'name': 'Olivier Temam', 'affiliation': 'INRIA Saclay', 'bio': {'p': ['Olivier Temam is a senior research fellow at INRIA Saclay in Paris, where he heads the ByMoore Group, and an adjunct professor at Ecole Polytechnique. His research interests include processor architecture and simulation, program optimization, alternative technologies, and computing paradigms. Temam has a PhD in computer science from the University of Rennes.']}}, {'name': 'Chengyong Wu', 'affiliation': 'Institute of Computing Technology, CAS', 'bio': {'p': ["Chengyong Wu is a professor in the Institute of Computing Technology, CAS (Chinese Academy of Sciences). His research interests include parallel-programming environments and iterative optimization. Wu has a PhD in computer science from the Chinese Academy of Sciences. He's a member of the ACM and a senior member of the China Computer Federation (CCF)."]}} %*SWAP: Parallelization through Algorithm Substitution %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6235945 %f/micro/rxjjklsdnuoclvo2if9vqyhi6zcan3tb.pdf %m68055096a24bbe209e92a3f99e907f99 %cmicro %@[{'name': 'Rich Belgard'} %*Yale N. Patt Receives the Inaugural IEEE B. Ramakrishna Rau Award %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6290323 %f/micro/68c1sf5q9m3yfzu4batwhoholmnbrtza.pdf %m37071bdae4cbbadbd71d4a33c244ce79 %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'Northwestern University', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6290317/6290325/6290325-photo-1-small.gif', 'p': []}} %*Calm Economics %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6290325 %f/micro/ifexhmq0bao6dubfgois5uwctklg871c.pdf %m6d81b290501caaeb3048715f9f5fe738 %cmicro %@[{'name': 'Erik R. Altman', 'affiliation': 'IBM', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6336701/6336702/6336702-photo-1-small.gif', 'p': []}} %*Power- and Energy-Aware Computing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6336702 %f/micro/afampj89v4dmnipv1gfgrl65i027nhhs.pdf %m418510e0d14c1f90d99ae57452a7737f %cmicro %@[{'name': 'Josep Torrellas', 'affiliation': 'University of Illinois at Urbana-Champaign, Urbana'} %*2012 International Symposium on Computer Architecture Influential Paper Award %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6301664 %f/micro/uhzliavvoqskl7r6nejciwb5huxjzmds.pdf %m47716da36139fcb544aa62839fd117f6 %cmicro %@[{'name': 'Thomas F. Wenisch', 'affiliation': 'University of Michigan', 'bio': {'p': ['Thomas F. Wenisch is the Morris Wellman Faculty Development Assistant Professor of electrical engineering and computer science at the University of Michigan. His research interests include computer architecture, server and data-center energy efficiency, smart-phone architecture, and multiprocessor systems. Wenisch has a PhD in electrical and computer engineering from Carnegie Mellon University. He is a member of IEEE and the ACM.']}}, {'name': 'Alper Buyuktosunoglu', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ['Alper Buyuktosunoglu is a research staff member at the IBM T.J. Watson Research Center. His research interests include computer architecture, especially power-aware processor microarchitecture, and multicore and multiprocessor systems. Buyukt osunoglu has a PhD in electrical and computer engineering from the University of Roche-ster. He is a senior member of IEEE and serves on the editorial board of IEEE Micro.', 'Direct questions and comments about this article to Thomas F. Wenisch at twenisch@umich.edu or to Alper Buyukt osunoglu at alperb@us.ibm.com.']}} %*Energy-Aware Computing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6336704 %f/micro/c4gum2otahzp7dy5hopl30tiu8dbxgmn.pdf %m0fd13b7037b69222d67b4f69355d3bbb %cmicro %@[{'name': 'Vibhu Sharma', 'affiliation': 'Katholieke Universiteit Leuven', 'bio': {'p': ['Vibhu Sharma performed the work for this article at the ESAT-MICAS Laboratory at the Karholieke Universiteit Leuven, in collaboration with Imec (the Interuniversity Microelectronics Centre). His research interests include variability-resilient and low-power circuit-design techniques. Sharma has a PhD in electrical engineering from the Katholieke Universiteit Leuven.']}}, {'name': 'Stefan Cosemans', 'affiliation': 'Katholieke Universiteit Leuven', 'bio': {'p': ['Stefan Cosemans is a researcher at Imec. His research interests include variability-aware design of low-power SRAM memories and circuit analysis and design for existing and emerging memories. Cosemans has a PhD in electrical engineering from Katholieke Universiteit Leuven. He performed the work for this article while at the ESAT-MICAS Laboratory at the Katholieke Universiteit Leuven.']}}, {'name': 'Maryam Ashouie', 'affiliation': 'imec', 'bio': {'p': ['Maryam Ashouie is a researcher at Imec. Her research interests include biomedical signal processing. Ashouie has a PhD in electrical engineering from the Georgia Institute of Technology.']}}, {'name': 'Jos Huisken', 'affiliation': 'Imec', 'bio': {'p': ['Jos Huisken is a principal researcher leading the ultra low-power digital-signal processing (ULP-DSP) group at Imec. His research interests include low-power system design. Huisken has an MS in electrical engineering from the University of Twente.']}}, {'name': 'Francky Catthoor', 'affiliation': 'Katholieke Universiteit Leuven', 'bio': {'p': ['Francky Catthoor is a fellow at Imec and a part-time full professor in the Department of Electrical Engineering at the Katholieke Universiteit Leuven. His research interests include high-level and system synthesis techniques and architectural methodologies, including related applications and deep-submicron technology aspects. Catthoor has a PhD in electrical engineering from the Katholieke Universiteit Leuven. He is a fellow of IEEE.']}}, {'name': 'Wim Dehaene', 'affiliation': 'Katholieke Universiteit Leuven', 'bio': {'p': ['Wim Dehaene is a full professor in the ESAT-MICAS Laboratory at the Katholieke Universiteit Leuven and a part-time principal scientist at Imec. His research interests include circuit-level design of digital circuits, specifically ultra low-power signal processing and memories in advanced CMOS technologies. Dehaene has a PhD in electrical engineering from the Katholieke Universiteit Leuven. He is a senior member of IEEE.', 'Selected CS articles and columns are also available for free at http://ComputingNow.computer.org']}} %*Ultra Low-Energy SRAM Design for Smart Ubiquitous Sensors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6266670 %f/micro/73jhb46l0odtrgepmdvqcfnslwovziz1.pdf %m1f3adf49d9a6efbb75afdc84368466df %cmicro %@[{'name': 'David Burgess', 'affiliation': 'Freescale', 'bio': {'p': ['David Burgess is a distinguished member of the technical staff at Freescale and chief microarchitect of the e6500. His research interests include power-efficient performance and maintainable design. Burgess has an MS in electrical engineering from the University of Texas at Austin.']}}, {'name': 'Edmund Gieske', 'affiliation': 'Freescale', 'bio': {'p': ['Edmund Gieske is a performance and power modeling and validation engineer of the e6500 and is contributing to the architecture of a future processor at Freescale. His research interests include power-efficient processors, cache memory, and branch prediction microarchitecture. Gieske has a PhD in computer engineering from the University of Cincinnati.']}}, {'name': 'James Holt', 'affiliation': 'Freescale', 'bio': {'p': ["James Holt is a managing member of the technical staff at Freescale and led the processor architecture team during the e6500's development. He is also a research affiliate with the Massachusetts Institute of Technology's Computer Science and Artificial Intelligence Laboratory. His research interests include computer architecture, software architecture, and self-aware computing systems. Holt has a PhD in electrical and computer engineering from the University of Texas at Austin. He is a senior member of IEEE."]}}, {'name': 'Thomas Hoy', 'affiliation': 'Freescale', 'bio': {'p': ['Thomas Hoy is a managing member of the technical staff at Freescale and an e6500 core and cluster logic lead. His research interests include power-aware computing and design efficiency. Hoy has an MSE in computer engineering from University of Michigan.']}}, {'name': 'Gary Whisenhunt', 'affiliation': 'Freescale', 'bio': {'p': ['Gary Whisenhunt is a distinguished member of the technical staff at Freescale and the chief architect of the e6500 and future cores. His research interests include computer architecture, operating-system kernel design, and virtualization.', 'Direct questions and comments about this article to Edmund Gieske, Freescale Semiconductor, PL51, 7700 W. Parmer Ln., Austin, TX 78729, egieske@freescale.com.']}} %*e6500: Freescale's Low-Power, High-Performance Multithreaded Embedded Processor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6253195 %f/micro/gdyp5vjldlfi8v2ukmuny46ahtfbxmi3.pdf %m3c13d2afd7de805fd3066a74447da9d1 %cmicro %@[{'name': 'Venkatraman Govindaraju', 'affiliation': 'University of Wisconsin&,#x2013,Madison', 'bio': {'p': ['Venkatraman Govindaraju is a PhD student in the Department of Computer Sciences at the University of Wisconsin–Madison. His research interests include energy-efficient computer architecture and compiler techniques for hardware specialization. Govindaraju has an MS in computer science from the University of Wisconsin–Madison. He is a student member of IEEE and the ACM.']}}, {'name': 'Chen-Han Ho', 'affiliation': 'University of Wisconsin&,#x2013,Madison', 'bio': {'p': ['Chen-Han Ho is a PhD student in the Department of Computer Sciences at the University of Wisconsin–Madison. His research interests include computer architecture, register-transfer level (RTL) design, and field-programmable gate array (FPGA) prototyping. Ho has a BS in electrical engineering from National Taiwan University. He is a student member of IEEE.']}}, {'name': 'Tony Nowatzki', 'affiliation': 'University of Wisconsin&,#x2013,Madison', 'bio': {'p': ['Tony Nowatzki is a PhD student in the Department of Computer Sciences at the University of Wisconsin–Madison. His research interests include architectural specialization, dynamic optimization, and parallelizing compilers. Nowatzki has a BS in computer science and computer engineering from the University of Minnesota. He is a student member of IEEE and the ACM.']}}, {'name': 'Jatin Chhugani', 'affiliation': 'Intel', 'bio': {'p': ['Jatin Chhugani is a researcher in the Parallel Computing Lab at Intel. His research interests include developing parallel algorithms for modern architectures. Chhugani has a PhD in computer science from Johns Hopkins University.']}}, {'name': 'Nadathur Satish', 'affiliation': 'Intel', 'bio': {'p': ['Nadathur Satish is a research scientist in the Parallel Computing Lab at Intel. His research interests include next-generation parallel applications and architectures. Satish has a PhD in electrical engineering and computer sciences from the University of California, Berkeley.']}}, {'name': 'Karthikeyan Sankaralingam', 'affiliation': 'University of Wisconsin&,#x2013,Madison', 'bio': {'p': ['Karthikeyan Sankaralingam is an assistant professor in the Departments of Computer Sciences and Electrical and Computer Engineering at the University of Wisconsin–Madison, where he also leads the Vertical Research Group. His research interests include microarchitecture, architecture, and very large-scale integration (VLSI). Sankaralingam has a PhD in computer science from the University of Texas at Austin. He is a senior member of IEEE.']}}, {'name': 'Changkyu Kim', 'affiliation': 'Intel', 'bio': {'p': ['Changkyu Kim is a research scientist at Intel. His research interests include highperformance computing, memory systems, and databases on modern parallel architectures. Kim has a PhD in computer science from the University of Texas at Austin.']}} %*DySER: Unifying Functionality and Parallelism Specialization for Energy-Efficient Computing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6235947 %f/micro/zepfngxizotyfum1jpelaakmd5wdclhb.pdf %m7cb52bd4687d3263f27b0a2df7174b38 %cmicro %@[{'name': 'Boris Grot', 'affiliation': 'EPFL', 'bio': {'p': ['Boris Grot is a postdoctoral researcher at EPFL (Ecole Polytechnique Federale de Lausanne). His research interests include processor architectures, memory systems, and interconnection networks for high-throughput, energy-aware computing. Grot has a PhD in computer science from the University of Texas at Austin. He is a member of IEEE and the ACM.']}}, {'name': 'Damien Hardy', 'affiliation': 'University of Cyprus', 'bio': {'p': ['Damien Hardy is a postdoctoral researcher at the University of Cyprus. His research interests include computer architecture, reliability, embedded and real-time systems, and data center modeling. Hardy has a PhD in computer science from the University of Rennes, France.']}}, {'name': 'Pejman Lotfi-Kamran', 'affiliation': 'EPFL', 'bio': {'p': ['Pejman Lotfi-Kamran is a fifth-year PhD candidate at EPFL. His research interests include processor architecture and interconnection networks for high-throughput and energy-efficient data centers. Lotfi-Kamran has an MSc in computer architecture from the University of Tehran. He is a member of IEEE and the ACM.']}}, {'name': 'Babak Falsafi', 'affiliation': 'EPFL', 'bio': {'p': ['Bahak Falsafi is a professor of computer and communication sciences at EPFL, and the founding director of EcoCloud, an interdisciplinary research center targeting robust, economic, and environmentally friendly cloud technologies. Falsafi has a PhD in computer science from the University of Wisconsin-Madison. He is a fellow of IEEE and a senior member of the ACM.']}}, {'name': 'Chrysostomos Nicopoulos', 'affiliation': 'University of Cyprus', 'bio': {'p': ['Chrysostomos Nicopoulos is a lecturer in the Department of Electrical and Computer Engineering at the University of Cyprus. His research interests include networks on chip (NoCs), computer architecture, multi-and many-core microprocessor and system design, and architectural support for massively parallel computing. Nicopoulos has a PhD in electrical engineering from Pennsylvania State University. He is a member of IEEE and the ACM.']}}, {'name': 'Yiannakis Sazeides', 'affiliation': 'University of Cyprus', 'bio': {'p': ['Yiannakis Sazeides is an associate professor in the Department of Computer Science at the University of Cyprus. His research focuses on computer architectures, particularly reliability, data-center modeling, memory hierarchy, temperature, and analysis of dynamic program behavior. Sazeides has a PhD in electrical engineering from the University of Wisconsin—Madison. He is a member of IEEE.']}} %*Optimizing Data-Center TCO with Scale-Out Processors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6290314 %f/micro/wfb15knydropm6hgjqsen9gcpm7c3v0o.pdf %m91ec99638b95ca97721733df25bbfb3c %cmicro %@[{'name': 'Sherief Reda', 'affiliation': 'Brown University', 'bio': {'p': ['Sherief Reda is an assistant professor in the School of Engineering at Brown University. His research interests include thermal and power modeling, management, and physical design. Reda has a PhD in computer science and engineering from the University of California, San Diego. He is a member of IEEE and the ACM.']}}, {'name': 'Ryan Cochran', 'affiliation': 'Brown University', 'bio': {'p': ['Ryan Cochran is a PhD student at Brown University. His research areas include thermal modeling, management, and energy-proportional computing for large-scale data centers. Cochran has a BSC from Brown University. He is a member of IEEE.']}}, {'name': 'Ayse K. Coskun', 'affiliation': 'Boston University', 'bio': {'p': ['Ayse K. Coskun is an assistant professor in the Electrical and Computer Engineering Department at Boston University. Her research interests include energy-efficient computing, multicore architectures, and 3D stacked architectures. Coskun has a PhD in computer science and engineering from the University of California, San Diego. She is a member of IEEE and the ACM.']}} %*Adaptive Power Capping for Servers with Multithreaded Workloads %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6266671 %f/micro/35ybzca01simviqoe9kgelppr4nbug7d.pdf %maecc140e9f21adcb9ed8c11a29b42834 %cmicro %@[{'name': 'Richard Mateosian', 'affiliation': 'xrm@pacbell.net', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6336701/6336708/6336708-photo-1-small.gif', 'p': []}} %*Forewords by Celebrities %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6336708 %f/micro/9grdq0jyzz7bviqtfylosk8u3lhxdvbp.pdf %m4ab62e9f10c0741afeb14ab53e64d98f %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'Northwestern University', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6336701/6336710/6336710-photo-1-small.gif', 'p': []}} %*The Prevailing View %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6336710 %f/micro/kojrw2jaxzxzhvcay7egm6siuogplf85.pdf %m50ba73f68e87e1d01f6744f7297ff7b4 %cmicro %@[{'name': 'Manish Arora', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Manish Arora is a PhD student in computer science and engineering at the University of California, San Diego. His research interests include heterogeneous GPU-CPU systems and computer architecture for irregular computations. Arora has an MS in computer engineering from the University of Texas at Austin.']}}, {'name': 'Siddhartha Nath', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Siddhartha Nath is a PhD student in the VLSI CAD lab at the University of California, San Diego. His research interests include network-on-chip modeling for area and power estimation and reliability mechanisms for deep-submicron technologies. Nath has a BE in electrical engineering from the Birla Institute of Technology & Science.']}}, {'name': 'Subhra Mazumdar', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Subhra Mazumdar is a software engineer in the Solaris kernel group at Oracle. His research interests include memory architecture and power management. Mazumdar has an MS in computer engineering from the University of California, San Diego, where he performed the work for this article.']}}, {'name': 'Scott B. Baden', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Scott B. Baden is a professor in the Computer Science and Engineering Department at the University of California, San Diego. His research interests include highperformance and parallel computation, focusing on programming abstractions, domain-specific translation, performance programming, adaptive and data-centric applications, and algorithm design. Baden has a PhD in computer science from the University of California, Berkeley. He is a senior member of IEEE and the Society for Industrial and Applied Mathematics (SIAM) and a senior fellow at the San Diego Supercomputer Center.']}}, {'name': 'Dean M. Tullsen', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Dean M. Tullsen is a professor in the Computer Science and Engineering Department at the University of California, San Diego. His research interests include architecture and compilers for multicore and multithreaded architectures. Tullsen has a PhD in computer science from the Uni-versity of Washington. He is a fellow of IEEE and the ACM.', 'Direct questions and comments about this article to Manish Arora at the University of California, San Diego, Computer Science and Engineering Department, 9500 Gilman Drive, #0404, La Jolla, CA 92093–0404, marora@eng.ucsd.edu.']}} %*Redefining the Role of the CPU in the Era of CPU-GPU Integration %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6266669 %f/micro/fhovdcbmt7p0ay2kizyia6jmbxwchrzn.pdf %m480048562a4efc7dc5a533b999de838d %cmicro %@[{'name': 'Javier Verd&,#x00FA,', 'affiliation': 'Technical University of Catalonia', 'bio': {'p': ['Javier Verdú is a tenure-track lecturer in the Computer Architecture Department at the Technical University of Catalonia. His research interests include parallel architectures, optimization of multithreaded applications, and complex computing-demanding 3D visualization applications. Verdú has a PhD in computer science from the Technical University of Catalonia.']}}, {'name': 'Alex Pajuelo', 'affiliation': 'Technical University of Catalonia', 'bio': {'p': ['Alex Pajuelo is an associate professor in the Computer Architecture Department at the Technical University of Catalonia. His research interests include performance evaluation methodologies, dynamic binary optimization, and complex computationally demanding 3D visualization applications. Pajuelo has a PhD in computer science from the Technical University of Catalonia.']}}, {'name': 'Mateo Valero', 'affiliation': 'Technical University of Catalonia', 'bio': {'p': ['Mateo Valero is a full professor in the Computer Architecture Department at the Technical University of Catalonia and the director of the Barcelona Super-computing Center (the National Center of Supercomputing in Spain). His research focuses on high-performance computer architectures. Valero has a PhD in telecommunications from the Technical University of Catalonia. He is a fellow of IEEE and the ACM and an Intel Distinguished Research Fellow.', 'Direct questions and comments about this article to Javier Verdú, C/ Jordi Girona, 1–3, Mòdul D6-Despatx 109, Campus Nord, UPC, 08034 Barcelona, Spain, jverdu@ac.upc.edu.']}} %*The Problem of Evaluating CPU-GPU Systems with 3D Visualization Applications %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6158631 %f/micro/ofin4hyfuup2sh6mcbdeadl7pyv0x9i5.pdf %mac947af5c7bf479dd7e8e9616de789dd %cmicro %@[{'name': 'David May', 'affiliation': 'XMOS', 'bio': {'p': ['David May is the CTO of XMOS and a professor in the Computer Science Department at Bristol University. His current interests include computer architecture, programming languages for real-time and highly parallel processors, robotics, and the history of computing. May graduated in computer science from Kings College, Cambridge University. He is a fellow of the Royal Society of London and the UK Royal Academy of Engineering.']}} %*The XMOS Architecture and XS1 Chips %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6341002 %f/micro/4icqgu2osn9sbgn7wdrhto0vemfawxfk.pdf %m5d4ac40251dc6d304b37689b20ddfeba %cmicro %@[{'name': 'Jinwook Oh', 'affiliation': 'Korea Advanced Institute of Science and Technology', 'bio': {'p': ["Jinwook Oh is a PhD student in electrical engineering at the Korea Advanced Institute of Science and Technology. His research interests include low-power digital signal processors for computer vision and, more recently, very-large-scale integration (VLSI) implementation of network-on-chip (NoC)-based heterogeneous multicore architectures. Oh has an MS in electrical engineering from the Korea Advanced Institute of Science and Technology. He's a student member of IEEE."]}}, {'name': 'Gyeonghoon Kim', 'affiliation': 'Korea Advanced Institute of Science and Technology', 'bio': {'p': ["Gyeonghoon Kim is a PhD student in electrical engineering at the Korea Advanced Institute of Science and Technology. His research interests include low-power digital processors with dynamic resource management for computer vision and NoC-based system-on-chip (SoC) design. Kim has an MS in electrical engineering from the Korea Advanced Institute of Science and Technology. He's a student member of IEEE."]}}, {'name': 'Injoon Hong', 'affiliation': 'Korea Advanced Institute of Science and Technology', 'bio': {'p': ["Injoon Hong is an MS student in electrical engineering at the Korea Advanced Institute of Science and Technology. His research interests include development of the digital accelerator and microarchitecture for computer vision, and VLSI implementation for machine learning algorithms. Hong has a BS in electrical engineering from the Korea Advanced Institute of Science and Technology. He's a student member of IEEE."]}}, {'name': 'Junyoung Park', 'affiliation': 'Korea Advanced Institute of Science and Technology', 'bio': {'p': ["Junyoung Park is a PhD student in electrical engineering at the Korea Advanced Institute of Science and Technology. His research interests include development of parallel processors for computer vision and manycore architecture and VLSI implementation for bioinspired vision processors. Park has an MS in electrical engineering from the Korea Advanced Institute of Science and Technology. He's a student member of IEEE."]}}, {'name': 'Seungjin Lee', 'affiliation': 'Korea Advanced Institute of Science and Technology', 'bio': {'p': ["Seungjin Lee is a researcher in the Department of Electrical Engineering at the Korea Advanced Institute of Science and Technology. His research focuses on efficient heterogeneous system-on-chip architectures for computer vision processing. Lee has a PhD in electrical engineering from the Korea Advanced Institute of Science and Technology. He's a member of IEEE."]}}, {'name': 'Joo-Young Kim', 'affiliation': 'Korea Advanced Institute of Science and Technology', 'bio': {'p': ["Joo-Young Kim is a researcher and hardware design engineer at the eXtreme Computing Group (XCG) at Microsoft Research. His research interests include multicore architecture, parallel programming, field-programmable gate array (FPGA) acceleration, and SoC implementation. Kim has a PhD in electrical engineering from the Korea Advanced Institute of Science and Technology, where he performed the work for this article. He's a member of IEEE."]}}, {'name': 'Jeong-Ho Woo', 'affiliation': 'Korea Advanced Institute of Science and Technology', 'bio': {'p': ["Jeong-Ho Woo is an OMAP multimedia architect at Texas Instruments. His research interests include low-power, high-performance digital circuits and multimedia system design, particularly 3D computer graphics and multimedia processing architecture. Woo has a PhD in electrical engineering from the Korea Advanced Institute of Science and Technology, where he performed the work for this article. He's a member of IEEE."]}}, {'name': 'Hoi-Jun Yoo', 'affiliation': 'Korea Advanced Institute of Science and Technology', 'bio': {'p': ["Hoi-Jun Yoo is a full professor in the Department of Electrical Engineering at the Korea Advanced Institute of Science and Technology. His research interests include networks on chips, 3D graphics, bioinspired vision processors, body area networks, biomedical devices and circuits, and memory circuits and systems. Yoo has a PhD in electrical engineering from the Korea Advanced Institute of Science and Technology. He's a fellow of IEEE.", 'Direct questions and comments about this article to Jinwook Oh, Dept. of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), 373–1, Guseong-dong, Yuseong-gu, Daejeon, 305–701, Republic of Korea, jinwook.oh.0913@gmail.com.']}} %*Low-Power, Real-Time Object-Recognition Processors for Mobile Vision Systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6353416 %f/micro/deqmard5ir3hce7plhwv6wbkx0zfgijs.pdf %mc3f3e2b1649857d9b76821d90db4bd5b %cmicro %@[{'name': 'Kazutoshi Suito', 'affiliation': 'Keio University', 'bio': {'p': ["Kazutoshi Suito is a PhD student in computer science at Keio University. His research interests include real-time processing and communication. Suito has an ME in computer science from Keio University. He's a member of the Information Processing Society of Japan (IPSJ)."]}}, {'name': 'Rikuhei Ueda', 'affiliation': 'Keio University', 'bio': {'p': ["Rikuhei Ueda is a master's student in computer science at Keio University. His research interests include real-time operating systems. Ueda has a BE from Keio University. He's a member of IPSJ."]}}, {'name': 'Kei Fujii', 'affiliation': 'Keio University', 'bio': {'p': ['Kei Fujii is working at NTT Data. His research interests include real-time scheduling and DVFS. Fujii has an ME in computer science from Keio University, where he performed the work for this article.']}}, {'name': 'Takuma Kogo', 'affiliation': 'Keio University', 'bio': {'p': ['Takuma Kogo is working in the Smart Energy Research Laboratories at NEC. His research interests focus on microgrids. Kogo has an ME in computer science from Keio University, where he performed the work for this article.']}}, {'name': 'Hiroki Matsutani', 'affiliation': 'Keio University', 'bio': {'p': ["Hiroki Matsutani is an assistant professor in the Department of Information and Computer Science at Keio University. His research interests focus on computer architecture and interconnection networks. Matsutani has a PhD in engineering from Keio University. He's a member of IEEE."]}}, {'name': 'Nobuyuki Yamasaki', 'affiliation': 'Keio University', 'bio': {'p': ["Nobuyuki Yamasaki is an associate professor in the Department of Information and Computer Science at Keio University. His research interests include real-time processing and communication, parallel and distributed processing, computer architecture, operating systems, robotics, and SoC. Yamasaki has a PhD in engineering from Keio University. He's a member of IEEE, IPSJ, IEICE, and the Robotics Society of Japan.", 'Direct questions and comments about this article to Kazutoshi Suito, 3–14-1, Hiyoshi, Kohoku-ku Yokohama, Kanagawa, 223–8522, Japan, suito@ny.ics.keio.ac.jp.']}} %*The Dependable Responsive Multithreaded Processor for Distributed Real-Time Systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6353408 %f/micro/xgozk950vuq4pmfndsbtg3yomel8vej6.pdf %ma32d23511e74747859aeb565d200981b %cmicro %@[{'name': 'Erik R. Altman', 'affiliation': 'ealtman@us.ibm.com', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/5713314/5713320/5713320-photo-1-small.gif', 'p': ['']}} %*A Solid Past, A Vital Future %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5713320 %f/micro/hzra6mdp0i8gy13jckuumaertnvxwnfp.pdf %m90329b6cc326689d257a1f9b5faad454 %cmicro %@[{'name': 'Yale N. Patt', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ["Yale N. Patt is the Ernest Cockrell Jr. Centennial Chair in Engineering at the University of Texas at Austin. His research interests include harnessing the expected fruits of future process technology into more effective microarchitectures for future micro-processors. He has a PhD in electrical engineering from Stanford University. His honors include the 1996 IEEE/ACM Eckert-Mauchly Award and the 2000 ACM Karl V. Karlstrom Award. He coauthored Introduction to Computing Systems: From Bits and Gates to C and Beyond (McGraw-Hill, 2003). He's a Fellow of IEEE and the ACM."]}}, {'name': 'Onur Mutlu', 'affiliation': 'Carnegie Mellon University', 'bio': {'p': ["Onur Mutlu is an assistant professor in the Department of Electrical and Computer Engineering at Carnegie Mellon University. His research interests include computer architecture and systems. He has a PhD in electrical and computer engineering from the University of Texas at Austin. Some of his coauthored works were chosen as best papers at ASPLOS and HPCA conferences and as Top Picks by IEEE Micro. Also, he is the recipient of an NSF CAREER Award. He's a member of IEEE and the ACM.", 'Direct questions and comments about this article to Yale N. Patt at pattyn@austin. utexas.edu or to Onur Mutlu at onur@cmu.edu.']}} %*Top Picks [Guest editors' introduction] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5713321 %f/micro/0zmoqxozvajnktf16bl8twvpwek9fgsr.pdf %m8ffa3a2f47a07943fe1ecb7d02c36572 %cmicro %@[{'name': 'Doe Hyun Yoon', 'affiliation': 'The University of Texas at Austin', 'bio': {'p': ['Doe Hyun Yoon is a PhD candidate in the Electrical and Computer Engineering Department at the University of Texas at Austin. His research focuses on reliability issues in the memory hierarchy, including caches, DRAM, and emerging nonvolatile memories. He has an MS in electrical engineering from Stanford University.']}}, {'name': 'Mattan Erez', 'affiliation': 'The University of Texas at Austin', 'bio': {'p': ['Mattan Erez is an assistant professor in the Electrical and Computer Engineering Department at the University of Texas at Austin. His research interests include computer architecture and programming models. He has a PhD in electrical engineering from Stanford University. Direct questions and comments to Doe Hyun Yoon, 1 Univ. Station, Mailcode C0803, Eng. Science Bldg., Room 526E, Austin, TX 78712–0240, doehyun.yoon@gmail.com.']}} %*Virtualized ECC: Flexible Reliability in Main Memory %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5661755 %f/micro/qpw60qbgilfoaz52dcmcvxnxthrsm7kv.pdf %mb958449c2b152d528a450e7087b552c8 %cmicro %@[{'name': 'Vijay Janapa Reddi', 'affiliation': 'Harvard University', 'bio': {'p': ['Vijay Janapa Reddi is a researcher in the Research and Advanced Development Laboratories at Advanced Micro Devices (AMD). His research interests are in the area of computer systems, specifically in applying virtual machines, runtime compiler systems, and architecture to address processor power and reliability challenges via hardware-software codesign. He has a PhD in computer science from Harvard University.']}}, {'name': 'Svilen Kanev', 'affiliation': 'Harvard University', 'bio': {'p': ["Svilen Kanev is a bachelor's student of computer science at Harvard University. His research interests include power-performance modeling and architecture of small cores."]}}, {'name': 'Wonyoung Kim', 'affiliation': 'Harvard University', 'bio': {'p': ['Wonyoung Kim is a PhD candidate in engineering sciences at Harvard University. His research interests are in power management of multicore processors, with specific interest in on-chip DC-DC converter design for fine-grain dynamic voltage and frequency scaling. He has a BS in electrical engineering from KAIST (Korea Advanced Institute of Science and Technology).']}}, {'name': 'Simone Campanoni', 'affiliation': 'Harvard University', 'bio': {'p': ['Simone Campanoni is a postdoc in computer science at Harvard University. His work focuses on the boundary between hardware and software, relying on dynamic compilation, runtime optimizations, and virtual execution environments for investigating opportunities on auto-parallelization. He has a PhD in computer science from Politecnico di Milano University.']}}, {'name': 'Michael D. Smith', 'affiliation': 'Harvard University', 'bio': {'p': ['Michael D. Smith is a John H. Finley, Jr. Professor of Engineering and Applied Sciences, as well as the Dean of the Faculty of Arts and Sciences, at Harvard University. His research interests include dynamic optimization, machine-specific and profile-driven compilation, high-performance computer architecture, and practical applications of security. He has a PhD in electrical engineering from Stanford University.']}}, {'name': 'Gu-Yeon Wei', 'affiliation': 'Harvard University', 'bio': {'p': ['Gu-Yeon Wei is a Gordon McKay Professor of Electrical Engineering in the School of Engineering and Applied Sciences at Harvard University. His research interests include high-speed, low-power link design, mixed-signal circuits for communications, and power regulation circuitry and management. He has a PhD in electrical engineering from Stanford University.']}}, {'name': 'David Brooks', 'affiliation': 'Harvard University', 'bio': {'p': ['David Brooks is a Gordon McKay Professor of Computer Science at Harvard University. His research interests include architectural and software approaches to address power, thermal, and reliability issues for embedded and high-performance computing systems. He has a PhD in electrical engineering from Princeton University.', 'Direct questions and comments to Vijay Janapa Reddi, 90 Central St., AMD, Boxborough, MA, vijay.reddi@amd.com.', 'Selected CS articles and columns are also cn available for free at http://ComputingNow.computer.org.']}} %*Voltage Noise in Production Processors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5661758 %f/micro/gsq9xckpldfw4aey0tt5jk3bvrw1jxa8.pdf %m6eabbdb8fd5545c36b56d75c7c8366b2 %cmicro %@[{'name': 'Reetuparna Das', 'affiliation': 'Pennsylvania State University', 'bio': {'p': ['Reetuparna Das is a research scientist at Intel Labs. Her research interests include computer architecture, especially interconnection networks. She has a PhD in computer science and engineering from Pennsylvania State University.']}}, {'name': 'Onur Mutlu', 'affiliation': 'Carnegie Mellon University', 'bio': {'p': ["Onur Mutlu is an assistant professor in the Electrical and Computer Engineering Department at Carnegie Mellon University. His research interests include computer architecture and systems. He has a PhD in electrical and computer engineering from the University of Texas at Austin. He's a member of IEEE and the ACM."]}}, {'name': 'Thomas Moscibroda', 'affiliation': 'Microsoft Research', 'bio': {'p': ["Thomas Moscibroda is a researcher in the distributed systems research group at Microsoft Research. His research interests include distributed computing, networking, and algorithmic aspects of computer architecture. He has a PhD in computer science from ETH Zurich. He's a member of IEEE and the ACM."]}}, {'name': 'Chita Das', 'affiliation': 'Pennsylvania State University', 'bio': {'p': ["Chita R. Das is a distinguished professor in the Department of Computer Science and Engineering at Pennsylvania State University. His research interests include parallel and distributed computing, performance evaluation, and fault-tolerant computing. He has a PhD in computer science from the University of Louisiana, Lafayette. He's a fellow of IEEE.", 'Direct questions and comments to Reetu-parna Das, Intel Labs, Intel Corp., SC-12, 3600 Juliette Ln., Santa Clara, CA, reetuparna. das@intel.com.']}} %*A&#x00E9;rgia: A Network-on-Chip Exploiting Packet Latency Slack %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5661757 %f/micro/qotfrcbrh7kcns1wmlzhl5ufdgs60uiv.pdf %ma0dd4d5c9a7c801ffddfa4e02a060b76 %cmicro %@[{'name': 'John H. Kelm', 'affiliation': 'University of Illinois at Urbana-Champaign', 'bio': {'p': ["John H. Kelm is a software engineer at Intel. His research interests include parallel archi-tectures, memory system design, and cache coherence protocols. He has a PhD in computer engineering from the University of Illinois at Urbana-Champaign. He's a member of IEEE and the ACM."]}}, {'name': 'Daniel R. Johnson', 'affiliation': 'University of Illinois at Urbana-Champaign', 'bio': {'p': ["Daniel R. Johnson is a doctoral candidate in the Electrical and Computer Engineering Department at the University of Illinois at Urbana-Champaign. His research interests include parallel accelerators and domain-specific architectures. He has a BS in electrical engineering from the University of Texas at Austin. He's a member of IEEE and the ACM."]}}, {'name': 'William Tuohy', 'affiliation': 'University of Illinois at Urbana-Champaign', 'bio': {'p': ["William Tuohy is a doctoral candidate in the Electrical and Computer Engineering Department at the University of Illinois at Urbana-Champaign. His research interests include parallel architectures, compiler and hardware interactions and codesign, and memory systems for heterogeneous architectures. He has a BS in electrical engineering and computer science from the University of California, Berkeley. He's a member of IEEE and the ACM."]}}, {'name': 'Steven S. Lumetta', 'affiliation': 'University of Illinois at Urbana-Champaign', 'bio': {'p': ["Steven S. Lumetta is an associate professor in the Electrical and Computer Engineering Department at the University of Illinois at Urbana-Champaign. His research interests include high-performance networking and computing, hierarchical systems, and parallel runtime software. He has a PhD in computer science from the University of California, Berkeley. He's a member of IEEE and the ACM."]}}, {'name': 'Sanjay J. Patel', 'affiliation': 'University of Illinois at Urbana-Champaign', 'bio': {'p': ["Sanjay J. Patel is an associate professor in the Electrical and Computer Engineering Department and the Sony Faculty Scholar at the University of Illinois at U rbana-Champaign. His research interests include high-throughput chip architectures and visual computing. He has a PhD in computer science and engineering from the University of Michigan, Ann Arbor. He's a member of IEEE."]}} %*Cohesion: An Adaptive Hybrid Memory Model for Accelerators %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5713322 %f/micro/ysyu9tzqxfrhbhs5xku0vw8vlcppzori.pdf %m2a57ab5b5be9f0057c781dcc1d57a102 %cmicro %@[{'name': 'M. Aater Suleman', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ["M. Aater Suleman is a computer architect at Intel. His research interests include chip multiprocessor architectures and parallel programming. He has a PhD in electrical and computer engineering from the University of Texas at Austin. He's a member of IEEE, the ACM, and Eta Kappa Nu."]}}, {'name': 'Onur Mutlu', 'affiliation': 'Carnegie Mellon University', 'bio': {'p': ["Onur Mutlu is an assistant professor in the Electrical and Computer Engineering Department at Carnegie Mellon University. His research interests include computer architecture and systems. He has a PhD in electrical and computer engineering from the University of Texas at Austin. He's a member of IEEE and the ACM."]}}, {'name': 'Jose Joao', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ["José A. Joao is a doctoral student in Electrical and Computer Engineering at the University of Texas at Austin. His research interests include high-performance microarchitectures and compiler-runtime-architecture interaction. He has a master's degree in electrical and computer engineering from the University of Texas at Austin. He's a student member of IEEE and the ACM."]}}, {'name': 'Khubaib Khubaib', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ["Khubaib is a doctoral student in electrical and computer engineering at the University of Texas at Austin. His research interests include microarchitecture and highperformance memory system design. He has a master's degree in Electrical and Computer Engineering from the University of Texas at Austin. He's a member of IEEE and the ACM."]}}, {'name': 'Yale N. Patt', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ["Yale N. Patt is the Ernest Cockrell, Jr. Centennial Chair in Engineering at the University of Texas at Austin. His research interests include harnessing the expected fruits of future process technology into more effective microarchitectures for future microprocessors. He has a PhD in electrical engineering from Stanford University. He coauthored Introduction to Computing Systems: From Bits and Gates to C and Beyond (McGraw-Hill, 2003). He's a Fellow of IEEE and the ACM.", 'Direct questions and comments to M. Aater Suleman, 11932 Rosethorn Dr., Austin, TX 78758, suleman@hps.utexas.edu.']}} %*Data Marshaling for Multicore Systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5669243 %f/micro/3qpimstzxe71gyjuj0cpxqybnzl6bfda.pdf %m872ac7911029fedb11d1c2fd108ad876 %cmicro %@[{'name': 'Matthew A. Watkins', 'affiliation': 'Harvey Mudd College', 'bio': {'p': ["Matthew A. Watkins is a visiting assistant professor in the Engineering Department at Harvey Mudd College. His research interests include reconfigurable architectures for chip multiprocessors and the design of large multicore systems. He received his PhD in electrical and computer engineering from Cornell University. He's a member of IEEE and the ACM."]}}, {'name': 'David H. Albonesi', 'affiliation': 'Cornell University', 'bio': {'p': ["David H. Albonesi is a professor in the School of Electrical and Computer Engineering and a member of the Computer Systems Laboratory at Cornell University. His research interests include adaptive and reconfigurable architectures, power and reliability-aware computing, and high-performance interconnect architectures using silicon nanopho-tonics. He received his PhD in computer engineering from the University of Massa-chusetts, Amherst. He's a Fellow of IEEE.", 'Direct questions and comments to Matthew A. Watkins, Engineering Dept., Harvey Mudd College, 301 Platt Blvd., Claremont, CA 91711, mwatkins@csl.cornell.edu.']}} %*ReMAP: A Reconfigurable Architecture for Chip Multiprocessors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5713323 %f/micro/o4zsnaj2iojkz1u5diarxheq3pb0dpfb.pdf %m12900fe6df75866f00f3d5a3af6a2df4 %cmicro %@[{'name': 'Yoongu Kim', 'affiliation': 'Carnegie Mellon University', 'bio': {'p': ['Yoongu Kim is a PhD student in the Department of Electrical and Computer Engineering at Carnegie Mellon University. His research interests include scheduling problems that arise in computer architecture. He has a BS in electrical engineering from Seoul National University.']}}, {'name': 'Michael Papamichael', 'affiliation': 'Carnegie Mellon University', 'bio': {'p': ['Michael Papamichael is a PhD candidate in the Department of Computer Science at Carnegie Mellon University. His research interests include computer architecture, particularly uncore modeling and FPGA (field-programmable gate array)-accelerated simulation and instrumentation for multiprocessor architectures. He has an MS in computer science from the University of Crete.']}}, {'name': 'Onur Mutlu', 'affiliation': 'Carnegie Mellon University', 'bio': {'p': ["Onur Mutlu is an assistant professor in the Department of Electrical and Computer Engineering at Carnegie Mellon University. His research interests include computer architecture and systems. He has a PhD in electrical and computer engineering from the University of Texas at Austin. He's a member of IEEE and the ACM."]}}, {'name': 'Mor Harchol-Balter', 'affiliation': 'Carnegie Mellon University', 'bio': {'p': ["Mor Harchol-Balter is an associate professor in the Department of Computer Science at Carnegie Mellon University. Her research interests include designing new resource allocation policies, power management po-licies, and scheduling policies for server farms and distributed systems. She has a PhD in computer science from the University of California, Berkeley. She's a member of IEEE, the ACM, and Informs (the Institute for Operations Research and the Management Sciences).", 'Direct questions and comments to Yoongu Kim at Carnegie Mellon Univ., 5000 Forbes Ave., Hamerschlag Hall, A-313, Pittsburgh, PA 15213, yoonguk@ece.cmu.edu.']}} %*Thread Cluster Memory Scheduling %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5713324 %f/micro/snt92lrxhguodxfaefhk4cz87ayw6gby.pdf %me5c256d69354730236eef2ea67b7274f %cmicro %@[{'name': 'Jeffrey Stuecheli', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ["Jeffrey Stuecheli works for the IBM server development group in Austin developing Power-based server microprocessors. His responsibilities cover architecture of the storage subsystem, which includes caches, prefetch hardware, coherence, and the memory controller. He is a PhD candidate in computer engineering at the University of Texas at Austin, where he received a master's degree in computer engineering. He is a member of IEEE."]}}, {'name': 'Dimitris Kaseridis', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ["Dimitris Kaseridis is a PhD candidate in computer engineering at the University of Texas at Austin. His research interests include high-performance, power-efficient, and scalable last-level caches, and memory controller designs for large, multicore microarchitectures. He has an MS in computer engineering and informatics from the University of Patras, Greece. He's a member of IEEE and the ACM."]}}, {'name': 'David Daly', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ["Lizy K. John is a professor in the Electrical and Computer Engineering Department at the University of Texas at Austin and holds the B.N. Gafford Professorship. Her research interests include high-performance processor and memory architectures, low-power design, workload characterization, and reconfigurable architectures. She has a PhD in computer engineering from Pennsylvania State University. She's an IEEE Fellow."]}}, {'name': 'Hillery Hunter', 'affiliation': 'IBM Thomas J. Watson Research Center', 'bio': {'p': ['David Daly is a research staff member at the IBM Thomas]. Watson Research Center. His work focuses on next-generation Power processor design, especially the design and performance analysis of the memory sub-system, using detailed simulation, queueing models, and analytical analysis. He has a PhD in electrical engineering from the University of Illinois at Urbana-Champaign. He is a senior member of the IEEE and the IEEE Computer Society.']}}, {'name': 'Lizy John', 'affiliation': 'IBM Thomas J. Watson Research Center', 'bio': {'p': ['Hillery C. Hunter is a research staff member in the Exploratory Systems Architecture Department at the IBM Thomas]. Watson Research Center. Her research takes an end-to-end approach to power and performance optimization of energy-efficient memory systems, spanning emerging technologies through systems hardware and management software. She has a PhD in electrical engineering from the University of Illinois at Urbana-Champaign.']}} %*Coordinating DRAM and Last-Level-Cache Policies with the Virtual Write Queue %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5661752 %f/micro/nuois2cpayctbg80nbqmf163eshrxpyx.pdf %m445efa7a5c92de2bfe76f8d2f42eb4be %cmicro %@[{'name': 'Xiaowei Jiang', 'affiliation': 'Intel', 'bio': {'p': ['Xiaowei Jiang is a research scientist at Intel. His research interests include system-on-chip (SoC) and heterogeneous-core architectures. He has a PhD in computer engineering from North Carolina State University.']}}, {'name': 'Niti Madan', 'affiliation': 'IBM Thomas J. Watson Research Center', 'bio': {'p': ['Niti Madan is a National Science Foundation and Computing Research Association Computing Innovation Fellow at the IBM Thomas J. Watson Research Center. Her research interests include power and reliability-aware architectures and the use of emerging technologies such as 3D die stacking. She has a PhD in computer science from the University of Utah.']}}, {'name': 'Li Zhao', 'affiliation': 'Intel', 'bio': {'p': ['Li Zhao is a research scientist at Intel. Her research interests include SoC architectures and cache memory systems. She has a PhD in computer science from the University of California, Riverside.']}}, {'name': 'Mike Upton', 'affiliation': 'Intel', 'bio': {'p': ['Mike Upton is a principal engineer at Intel. His research interests include graphics processor architectures and many-core architectures. He has a PhD in computer architecture from the University of Michi-gan, Ann Arbor.']}}, {'name': 'Ravi Iyer', 'affiliation': 'Intel', 'bio': {'p': ['Ravi Iyer is a principal engineer at Intel. His research interests include SoC and hetero-geneous-core architectures, cache memory systems, and accelerator architectures. He has a PhD in computer science from Texas A&M University.']}}, {'name': 'Srihari Makineni', 'affiliation': 'Intel', 'bio': {'p': ['Srihari Makineni is a senior researcher at Intel. His research interests include cache and memory subsystems, interconnects, networking, and large-scale chip multiprocessor (CMP) architectures. He has an MS in electrical and computer engineering from Lamar University, Texas.']}}, {'name': 'Don Newell', 'affiliation': 'Intel', 'bio': {'p': ['Donald Newell is the CTO of the Server Product Group at AMD. His research interests include server architectures, cache memory systems, and networking. He has a BS in computer science from the University of Oregon.']}}, {'name': 'Yan Solihin', 'affiliation': 'North Carolina State University', 'bio': {'p': ['Yan Solihin is an associate professor in the Department of Electrical and Computer Engineering at North Carolina State Uni-versity. His research interests include cache memory systems, performance modeling, security, and reliability. He has a PhD in computer science from the University of Illinois at Urbana-Champaign.']}}, {'name': 'Rajeev Balasubramonian', 'affiliation': 'University of Utah', 'bio': {'p': ['Rajeev Balasubramonian is an associate professor in the School of Computing at the University of Utah. His research interests include memory systems, interconnect design, large-cache design, transactional memory, and reliability. He has a PhD in computer science from the University of Rochester.', 'Direct questions and comments about this article to Xiaowei Jiang, JF2, Intel, 2111 NE 25th Ave., Hillsboro, OR 97124, xiaowei. jiang@intel.com.', 'CnSelected CS articles and columns are also available for free at http://ComputingNow.computer.org.']}} %*CHOP: Integrating DRAM Caches for CMP Server Platforms %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5661754 %f/micro/zmpaxtkeevwjk0z6hf9vboaidfc2glhr.pdf %mf17efc19528177a41ac077a3ff0b8807 %cmicro %@[{'name': 'Bogdan Romanescu', 'affiliation': 'Duke University', 'bio': {'p': ['Bogdan F. Romanescu is a member of the Online Services Division at Microsoft. His research interests include memory consis-tency, memory coherence, and scalable communication protocols in large-scale systems. He has a PhD in electrical and computer engineering from Duke University.']}}, {'name': 'Alvin Lebeck', 'affiliation': 'Duke University', 'bio': {'p': ["Alvin R. Lebeck is a professor in the Departments of Electrical and Computer Engineering and of Computer Science at Duke University. His interests include architectures for emerging nanotechnologies, multicore processors, memory systems, and energy-efficient computing. He has a PhD in computer science from the University of Wisconsin, Madison. He's a senior member of IEEE and a member of the ACM."]}}, {'name': 'Daniel J. Sorin', 'affiliation': 'Duke University', 'bio': {'p': ["Daniel J. Sorin is an associate professor in the Departments of Electrical and Computer Engineering and of Computer Science at Duke University. His research interests include computer architecture, fault toler-ance, memory systems, and design for verifiability. He has a PhD in electrical engineering from the University of Wiscon-sin, Madison. He's a senior member of IEEE and the ACM."]}} %*Address Translation Aware Memory Consistency %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5661753 %f/micro/mtkpmtcvbhd27njozrqbsl9nfa3fviul.pdf %md268811eb167fcc7d78219e64802f96d %cmicro %@[{'name': 'Nak Hee Seong', 'affiliation': 'Georgia Institute of Technology', 'bio': {'p': ['Nak Hee Seong is a PhD candidate in electrical and computer engineering at the Georgia Institute of Technology. His research interests include emerging memory technologies, main memory scheduling, and 3D integration. He has an MSE in computer engineering from the Seoul National University. Contact him at nhseong@ece. gatech.edu.']}}, {'name': 'Dong Hyuk Woo', 'affiliation': 'Intel Labs', 'bio': {'p': ['Dong Hyuk Woo is a research scientist at Intel Labs. His research interests include heterogeneous computing, 3D integration, emerging memory technologies, and cloud computing. He has a PhD in electrical and computer engineering from the Georgia Institute of Technology.']}}, {'name': 'Hsien-Hsin Lee', 'affiliation': 'Georgia Institute of Technology', 'bio': {'p': ['Hsien-Hsin S. Lee is an associate professor in the School of Electrical and Computer Engineering at the Georgia Institute of Technology. His research interests include computer architecture, cyber security, and 3D integration. He has a PhD in computer science and engineering from the University of Michigan at Ann Arbor.', 'Direct questions and comments to Nak Hee Seong, 4504 Madison Dr., Atlanta, GA 30346, nhseong@ece.gatech.edu.', 'Selected CS articles and columns are also available for free at http//ComputingNow.computer.org.']}} %*Security Refresh: Protecting Phase-Change Memory against Malicious Wear Out %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5661756 %f/micro/5p3zmf8u90qebyzqsndji1xwfv6kaagv.pdf %m17a4b6181681dfbbcfac70fb563499d4 %cmicro %@[{'name': 'Shane Greenstein'} %*Digital Dark Matter %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5713325 %f/micro/s5zgskielwk8can41lye69jbirujo72h.pdf %m4402f94fb3d213798bb9a8ca25383b7a %cmicro %@[{'name': 'Erik R. Altman', 'affiliation': 'ealtman@us.ibm.com', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/5751930/5751935/5751935-photo-1-small.gif', 'p': []}} %*Hot Chips and Remembering a Pioneer %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5751935 %f/micro/t3uxzmo602pgunwvjgsldvcmfseyxbjr.pdf %mf275de32a87b70dce54350356bfc8224 %cmicro %@[{'name': 'Jose Renau', 'affiliation': 'University of California, Santa Cruz', 'bio': {'p': ["Jose Renau is an assistant professor in the Computer Engineering Department at the University of California, Santa Cruz. He's also the project leader of the MASC (Micro Architecture at Santa Cruz) group. His research interests include computer architecture complexity, temperature, and relia-bility, FPGAs, and ASICs. Renau has a PhD in computer science from the University of Illinois at Urbana Champaign. He's a member of IEEE and the ACM."]}}, {'name': 'Will Eatherton', 'affiliation': 'Juniper Networks', 'bio': {'p': ['Will Eatherton is a vice president of engineering at Juniper Networks, leading product lines in IP core as well as optical. He led architecture for two generations of Cisco System Network processing chipsets, including the Quantum Flow Processor. His research interests include scalable distributed systems software, VLSI, and optical technol-ogies. Eatherton has an MS in electrical engineering from Washington University in St. Louis.', 'Direct questions and comments about this article to Jose Renau at renau@soe.ucsc.edu or to Will Eatherton at willeatherton@gmail.com.']}} %*Hot Chips 22 %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5751936 %f/micro/9lbrnqzhaog5idfhecp1qmzjv0n8wx6l.pdf %m805067033accd930c301d3ceb7e62286 %cmicro %@[{'name': 'Michael Butler', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ['Michael Butler is a fellow and chief architect of the Bulldozer core at Advanced Micro Devices. His research interests include highperformance CPU microarchitectures. Butler has a PhD in computer science and engineering from the University of Michigan, Ann Arbor.']}}, {'name': 'Leslie Barnes', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ['Leslie Barnes is a fellow in the performance, architecture, and modeling group at Advanced Micro Devices. His work has included performance analysis and modeling of the Bulldozer microprocessor. Barnes has a PhD in theoretical chemistry from the University of Western Australia.']}}, {'name': 'Debjit Das Sarma', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ['Debjit Das Sarma is a fellow and lead architect at Advanced Micro Devices. His work has included microprocessor architecture and design and computer arithmetic. Das Sarma has a PhD in computer science and engineering from Southern Methodist University.']}}, {'name': 'Bob Gelinas', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ['Bob Gelinas is a member of the Bulldozer RTL development team at Advanced Micro Devices. His research interests include cache hierarchy and bus architectures for symmetric multiprocessing and cache-coherent nonuniform memory access systems. Gelinas has a BS in electrical engineering from the University of Maine.']}} %*Bulldozer: An Approach to Multithreaded Compute Performance %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5751937 %f/micro/hikyx2fvflyznrpmn1cjtoeuqrlbkaha.pdf %mcd0d83e3389197ac0121418b43673ca3 %cmicro %@[{'name': 'Brad Burgess', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ['Brad Burgess is a fellow at Advanced Micro Devices and chief architect for the Cat family of processor cores. Burgess has an MS in electrical engineering from Texas A&M University. He is a member of IEEE.']}}, {'name': 'Brad Cohen', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ['Brad Cohen is a principal member of the technical staff at Advanced Micro Devices. He leads the Bobcat family architecture/ RTL team. Cohen has a BS in electrical engineering from the Georgia Institute of Technology.']}}, {'name': 'Marvin Denman', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ['Marvin Denman is a principal member of the technical staff at Advanced Micro Devices, working on Cat family cores. He is responsible for RTL development for a future CAT family core and leads a portion of the RTL team for a next-generation CAT family core. Denman has a BS in computer science from Texas A&M University.']}}, {'name': 'Jim Dundas', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ['Jim Dundas is a senior member of the technical staff at Advanced Micro Devices. He is the branch prediction architect for Bobcat and the branch prediction and instruction cache architect for the AMD Cat family of processors. Dundas has a PhD in electrical engineering from the University of Michigan, Ann Arbor.']}}, {'name': 'David Kaplan', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ['David Kaplan is a member of the technical staff at Advanced Micro Devices. He is part of the Bobcat architecture team and helped design the microcode and load/store unit. Kaplan has a BS in computer engineering from the University of Illinois at Urbana-Champaign.']}}, {'name': 'Jeff Rupley', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ['Jeff Rupley is a principal member of the technical staff at Advanced Micro Devices, working in low-power core design for Bobcat, and chief architect on a follow-on core. Rupley has an MS in electrical engineering from Purdue University. He is a member of IEEE and ACM.']}} %*Bobcat: AMD's Low-Power x86 Processor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5686872 %f/micro/al5bvcipxye9wotxrdgz87tsijmusvbg.pdf %mfc56bfc725841ae5d97b8baeb735de4c %cmicro %@[{'name': 'Brian W. Curran', 'affiliation': 'IBM', 'bio': {'p': ['Brian W. Curran is a distinguished engineer and master inventor in the IBM Systems and Technology Group. He led the multisite, z196 microprocessor design from conception through implementation. His research interests include high-frequency CMOS circuit design and high-performance microarchitectures. Curran has a BS in electrical engineering from the University of Wisconsin-Madison.']}}, {'name': 'Lee E. Eisen', 'affiliation': 'IBM', 'bio': {'p': ['Lee E. Eisen is a senior technical staff member and master inventor in the highperformance processor design team of the IBM Systems and Technology Group. His research interests include power-efficient logic design and high-performance microarchitectures. Eisen has a BS in electrical engineering from Texas A&M University.']}}, {'name': 'Eric M. Schwarz', 'affiliation': 'IBM', 'bio': {'p': ["Eric M. Schwarz is a distinguished engineer in the IBM Systems and Technology Group, where he is the core architect on future mainframe designs. His research interests include computer arithmetic and architecture. Schwarz has a PhD in electrical engineering from Stanford University. He's a senior member of IEEE and the IEEE Computer Society."]}}, {'name': 'Pak-kin Mak', 'affiliation': 'IBM', 'bio': {'p': ['Pak-kin Mak is a development engineer in the IBM Systems and Technology Group, where he is the lead symmetric multiprocessing (SMP) architect on the System z Processor Subsystem development team. His research interests include cache design, high-performance cache hierarchy, and SMP designs. Mak has a BS in engineering science from the Polytechnic Institute of New York.']}}, {'name': 'James Warnock', 'affiliation': 'IBM', 'bio': {'p': ["James Warnock is a distinguished engineer in the IBM Systems and Technology Group, where he has worked on high-speed micro-processors, including the Power4, the Cell Broadband Engine, the Power7, and the zEnterprise 196. His research interests include VLSI circuit design and methodology, clocked storage elements, design for test, and design-technology interactions. Warnock has a PhD in physics from the Massachusetts Institute of Technology. He's a senior member of IEEE, and a member of the IBM Academy of Technology, the IEEE Solid State Circuits Society, the IEEE Electron Devices Society, and the American Physical Society."]}}, {'name': 'Patrick J. Meaney', 'affiliation': 'IBM', 'bio': {'p': ['Patrick J. Meaney is a senior technical staff member and master inventor in the IBM Systems and Technology Group, where he is the zSeries memory subsystem leader. His research interests include architecture and delivery of the RAIM (redundant array of independent memory) design for the zEnterprise system, cache logic design, timing, and reliability, availability, and serviceability (RAS). Meaney has an MS in computer engineering from Syracuse University.']}}, {'name': 'Michael Fee', 'affiliation': 'IBM', 'bio': {'p': ['Michael Fee is a senior engineer in the IBM Systems and Technology Group, where he specializes in zSeries nest custom hardware design. His research interests include high-performance shared-cache architectures, and performance measurement support for future system designs. Fee has a BS in electrical engineering from Manhattan College.']}} %*The zEnterprise 196 System and Microprocessor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5751938 %f/micro/l4ozqvuwtgkhumjlxm1b3dsajpe5bdr7.pdf %m249400a675ea9348aa987460bba85115 %cmicro %@[{'name': 'Olav Lindtjorn', 'affiliation': 'Schlumberger Stanford, Los Altos Stanford', 'bio': {'p': ["Olav Lindtjorn is a visiting scholar at the School of Earth Science at Stanford University. He has experience developing seismic acquisition systems, down-hole tools for oil and gas exploration, and advanced imaging algorithms running on large HPC installations. Lindtjorn has an MSc in electrical engineering from the Norwegian University of Science and Technology. He's a member of IEEE and the Society of Exploration Geophysicists (SEG)."]}}, {'name': 'Robert Clapp', 'affiliation': 'Stanford University, Stanford', 'bio': {'p': ["Robert G. Clapp is a senior research engineer in geophysics and the technical director of the Center for Earth and Environmental Science at Stanford University, where he manages the School of Earth Science's Algorithm and Architecture Initiative. His research interests include seismic imaging, tomography, HPC, inversion, and optimization. Clapp has a PhD in geophysics from Stanford University. He's a member of the SEG."]}}, {'name': 'Oliver Pell', 'affiliation': 'Maxeler Technologies, London', 'bio': {'p': ["Oliver Pell is vice president of engineering at Maxeler Technologies. His experience ranges from accelerating Reverse Time Migration and Lattice-Boltzmann simulations to credit derivatives pricing. He's responsible for the technical architecture and project management of acceleration efforts for clients including Tier 1 oil companies and investment banks. Pell has an MSc in advanced computing from Imperial College London. He's a member of IEEE."]}}, {'name': 'Haohuan Fu', 'affiliation': 'Stanford University Tsinghua University, Stanford Beijing', 'bio': {'p': ["Oskar Mencer is CEO and founder of Maxeler Technologies. He is also a senior lecturer in the Computing Department of Imperial College London and a consulting professor in the Geophysics Department at Stanford University. His research interests include acceleration of computations and number representation. Mencer has a PhD isn electrical engineering from Stanford University. He's a member of IEEE and the SEG."]}}, {'name': 'Michael Flynn', 'affiliation': 'Maxeler Technologies, London', 'bio': {'p': ["Michael J. Flynn is the chairman of Maxeler Technologies and professor emeritus in the Electrical Engineering Department at Stanford University. His research interests include computer architecture and computer arithmetic. Flynn has a PhD in electrical engineering from Purdue University. He's a fellow of IEEE and the ACM."]}}, {'name': 'Oskar Mencer', 'affiliation': 'Maxeler Technologies, London', 'bio': {'p': ["Haohuan Fu is an associate professor in the Center of Earth System Science in Tsinghua University. His research interests include HPC in earth and environmental sciences, computer architectures, performance optimizations, and programming tools in parallel computing. Fu has a PhD in computing from Imperial College London. He's a member of IEEE."]}} %*Beyond Traditional Microprocessors for Geoscience High-Performance Computing Applications %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5719584 %f/micro/zfov2v0rky4tut6o3cqhmbs9luexwgri.pdf %me603ffefa44aa40e9a056ded004d628d %cmicro %@[{'name': 'Craig M. Wittenbrink', 'affiliation': 'Nvidia', 'bio': {'p': ["Craig M. Wittenbrink is an architecture director of 3D computer graphics at Nvidia. He has worked in computer architecture, scientific visualization, and CPU architecture and is currently managing CPU architecture design. Wittenbrink has a PhD in electrical engineering from the University of Washington. He's a member of ACM Siggraph, a senior member of IEEE, and a member of the IEEE Computer Society."]}}, {'name': 'Emmett Kilgariff', 'affiliation': 'Nvidia', 'bio': {'p': ['Emmett Kilgariff is a vice president of architecture in the CPU group at Nvidia, where he has been responsible for the design of many GeForce chips, including the GF1xx/Fermi product family. Kilgariff has a BS in electrical engineering from Purdue University.']}}, {'name': 'Arjun Prabhu', 'affiliation': 'Nvidia', 'bio': {'p': ["Arjun Prabhu is a vice president of CPU ASIC engineering at Nvidia, where he's responsible for the microarchitecture, logic design, and chip definitions for the Kepler product family for GeForce, Quadro, and Tesla. Prabhu has an MS in electrical engineering from Stanford University."]}} %*Fermi GF100 GPU Architecture %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5751939 %f/micro/colhexmq2vetwhbz34ksmgy8xp5n0guu.pdf %m99f293d5a8ff2a8263a3c7aaaa2ace2c %cmicro %@[{'name': 'Michael Floyd', 'affiliation': 'IBM', 'bio': {'p': ['Michael Floyd is the architect and lead for the Power7 EnergyScale design in the IBM Systems and Technology Group. His work in IBM server development has included hardware bring-up, test, debug, and reliability, in addition to design, lead, and microarchitect roles on the Power4, Power5, and Power6 processors and support chips. Floyd has an MS in electrical engineering from Stanford University.']}}, {'name': 'Malcolm Allen-Ware', 'affiliation': 'IBM', 'bio': {'p': ['Malcolm Allen-Ware is a member of the Power-Aware Systems Department at the IBM Austin Research Lab. His work has included researching dynamic power management for all classes of IBM servers, including Intel, Power6, Power7, and z196 processors. Ware has an MS in communications theory and computer architecture from North Carolina State University.']}}, {'name': 'Karthick Rajamani', 'affiliation': 'IBM', 'bio': {'p': ['Karthick Rajamani is a research staff member and manager of the Power-Aware Systems Department at the IBM Austin Research Lab. His work has driven dynamic power management architectures, including designs of the Power6 and Power7 processors and systems for EnergyScale research in energy-efficient memory subsystems and energy-aware systems software. Rajamani has a PhD in electrical and computer engineering from Rice University.']}}, {'name': 'Bishop Brock', 'affiliation': 'IBM', 'bio': {'p': ['Bishop Brock is a senior engineer in the IBM Systems and Technology Group. His work on the Power7 project has included the development of hardware verification, microarchitectural validation, and power/ performance prediction methodologies for power management hardware and firmware systems. Brock has an MS in computer science from the University of Texas at Austin.']}}, {'name': 'Charles Lefurgy', 'affiliation': 'IBM', 'bio': {'p': ["Charles Lefurgy is a research staff member at the IBM Austin Research Lab. His work has included energy management features found in IBM System p and x servers. Lefurgy has a PhD in computer science and engineering from the University of Michigan. He's a member of IEEE and the ACM."]}}, {'name': 'Alan J. Drake', 'affiliation': 'IBM', 'bio': {'p': ['Alan J. Drake is a member of the exploratory VLSI group at the IBM Austin Research Lab. His work has included designing critical path monitors and other integrated sensors used for noise detection in high-performance microprocessors. Drake has a PhD in electrical engineering from the University of Michigan.']}}, {'name': 'Lorena Pesantez', 'affiliation': 'IBM', 'bio': {'p': ['Lorena Pesantez is a member of the server hardware performance team in the IBM Systems and Technology Group, where she specializes in Power systems instrumentation. Her work has included the definition, hardware data collection, and tuning of the power proxy for the Power7 chip. Pesantez has a BS in electrical engineering from the University of Texas at Austin.']}}, {'name': 'Tilman Gloekler', 'affiliation': 'IBM', 'bio': {'p': ['Tilman Gloekler is the design lead for the Power7 chip power management implementation in the IBM Systems and Technology Group. His work has included design, verification, and bring-up for signal processing and high-performance microprocessor chips. Gloekler has a PhD in electrical engineering from Aachen University of Technology, Germany.']}}, {'name': 'Jose A. Tierno', 'affiliation': 'IBM', 'bio': {'p': ['Jose A. Tierno is a research staff member and manager of the mixed signal design group at IBM Research. His interests include the design of digital replacements for analog circuits, in particular all-digital phase-locked loops, and the design of self-timed digital circuits. Tierno has a PhD in computer science from the California Institute of Technology.']}}, {'name': 'Pradip Bose', 'affiliation': 'IBM', 'bio': {'p': ["Pradip Bose is a research staff member and manager of the Reliability and Power-Aware Microarchitecture Department at the IBM T.J. Watson Research Center. His work has included pre-silicon modeling and definition of IBM Power-series microarchitectures, beginning with the research precursor of the first RS/6000 product. Bose has a PhD in electrical and computer engineering from the University of Illinois at Urbana-Champaign. He's a fellow of IEEE and an advisory board member of IEEE Micro."]}}, {'name': 'Alper Buyuktosunoglu', 'affiliation': 'IBM', 'bio': {'p': ["Alper Buyuktosunoglu is a research staff member in the Reliability and Power-Aware Microarchitecture Department at the IBM T.J. Watson Research Center. His work has included the design of IBM p-Series and z-Series microprocessors in the areas of power-aware computer architectures, dynamic power management, and high-level power-performance modeling. Buyuktosunoglu has a PhD in electrical and computer engineering from the University of Rochester. He's a senior member of IEEE and an editorial board member of IEEE Micro."]}} %*Introducing the Adaptive Energy Management Features of the Power7 Chip %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5751940 %f/micro/vzdg9i5cokneqvhf08ikrwtxz4gh6tu2.pdf %m18e5976d06fee4fc7e4ebd9a6cc8ae6f %cmicro %@[{'name': 'Jeffrey Brown', 'affiliation': 'IBM', 'bio': {'p': ["Jeffrey D. Brown is a distinguished engineer in emerging product development at IBM. He's also the chief engineer for PowerEN processors. His research interests include the development of system on a chip (SoC), microprocessors, and memory and I/O subsystems. Brown has an MS in electrical engineering from Washington State University. He's a member of IEEE and the IBM Academy of Technology."]}}, {'name': 'Sandra Woodward', 'affiliation': 'IBM', 'bio': {'p': ['Sandra Woodward is a senior technical staff member at IBM and is the chip technical lead for the PowerEN processor chip. Her research interests include microprocessor and memory hierarchy architecture, design, and methodology, SoC design, application-specific integrated circuit design, Power architecture, and cache and coherency function design. Woodward has an MS in electrical engineering from Syracuse University.']}}, {'name': 'Brian Bass', 'affiliation': 'IBM', 'bio': {'p': ["Brian M. Bass is a senior technical staff member in the PowerPC Processor Development department at IBM. He's also the PowerPC accelerator architect and lab bring-up design lead for the PowerEN processor chip. His research interests include networking, internal bus designs, and hardware acceleration. Bass has an MS in electrical engineering from Clemson University."]}}, {'name': 'Charlie Johnson', 'affiliation': 'IBM', 'bio': {'p': ["Charles L. Johnson is a fellow in the Next-Generation Computing Systems Department at IBM. He's also the chief architect for PowerEN processors. His research interests include power-performance efficient computing and 3D silicon technology. Johnson has a BS in electrical engineering from the University of Minnesota. He's a member of the IBM Academy of Technology."]}} %*IBM Power Edge of Network Processor: A Wire-Speed System on a Chip %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5708124 %f/micro/ymrynadtdlox6izphsvefsoam5cwcxkz.pdf %m30ace8df3ae730f04992b172a22888e5 %cmicro %@[{'name': 'Nathan Goulding-Hotta', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Nathan Goulding-Hotta is a PhD student in the Department of Computer Science and Engineering at the University of California, San Diego. His research interests include building low-power chips incorporating heterogeneous architectures. He has a BS in electrical engineering and a BS in computer science, both from the New Mexico Institute of Mining and Technology.']}}, {'name': 'Jack Sampson', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Jack Sampson is a postdoctoral scholar in the Department of Computer Science and Engineering at the University of California, San Diego. His research interests include heterogeneous architectures, automatically generated coprocessors, and scalable memory systems. Sampson has a PhD in computer engineering from the University of California, San Diego.']}}, {'name': 'Ganesh Venkatesh', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Ganesh Venkatesh is a PhD candidate in the Department of Computer Science and Engineering at the University of California, San Diego. His research interests include core architecture, program analysis for designing specialized coprocessors, and algorithmic optimizations to address system bottlenecks. Venkatesh has an MS in computer science from the University of California, San Diego.']}}, {'name': 'Saturnino Garcia', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Saturnino Garcia is a PhD candidate in the Department of Computer Science and Engineering at the University of California, San Diego. His research interests include program analysis, multicore architectures, and software engineering for parallel systems. Garcia has an MS in computer science from the University of California, San Diego.']}}, {'name': 'Joe Auricchio', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Joe Auricchio is a graduate student in the Department of Computer Science and Engineering at the University of California, San Diego. His research interests include computer architecture, embedded systems, networking, security, and programmable logic. Auricchio has a BS in computer science from the University of California, San Diego.']}}, {'name': 'Po-Chao Huang', 'affiliation': 'Dept. of Comput. Sci. &, Eng., Univ. of California, San Diego, CA, USA', 'bio': {'p': ['Po-Chao Huang is a graduate student in the Department of Electrical and Computer Engineering at the University of California, San Diego. His research interests include computer architecture and VLSI digitalsignal processing. Huang has a BS in electronics engineering from National Chiao Tung University, Taiwan.']}}, {'name': 'Manish Arora', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Manish Arora is a PhD student in the Department of Computer Science and Engineering at the University of California, San Diego. His research interests include low-power computer architecture for irregular computations, heterogeneous architecture, and parallel systems. Arora has an MS in computer engineering from the University of Texas at Austin.']}}, {'name': 'Siddhartha Nath', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Siddhartha Nath is a PhD student in the Department of Computer Science and Engineering at the University of California, San Diego. His research interests include low-power reconfigurable and heterogeneous architectures. Nath has a BE in electrical engineering from the Birla Institute of Technology and Science, Pilani, India.']}}, {'name': 'Vikram Bhatt', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Vikram Bhatt is a graduate student in the Department of Computer Science and Engineering at the University of California, San Diego. His research interests include physical design automation and low-power design techniques. Bhatt has a BE in electronics and communications engineering from Sri Jaya-chamarajendra College of Engineering, India.']}}, {'name': 'Jonathan Babb', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Jonathan Babb is a postdoctoral researcher at the Massachusetts Institute of Technology. His research interests include extending the life of silicon technology and creating the next generation of carbon-based computing platforms in the emerging fields of synthetic biology and bio-CAD. Babb has a PhD in electrical engineering and computer science from the Massachusetts Institute of Technology.']}}, {'name': 'Steven Swanson', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Steven Swanson is an assistant professor in the Department of Computer Science and Engineering at the University of California, San Diego, and he jointly leads the Green-Droid project. His research interests include specialized architectures for low-power computing and system-level applications for nonvolatile, solid-state memories. Swanson has a PhD in computer science and engineering from the University of Washington.']}}, {'name': 'Michael Taylor', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Michael Bedford Taylor is an assistant professor in the Department of Computer Science and Engineering at the University of California, San Diego, and he jointly leads the GreenDroid project. His research interests include tiled multicore processor design, specialized architectures for smartphones, and software engineering tools that simplify parallelization. Taylor has a PhD in electrical engineering and computer science from the Massachusetts Institute of Technology.']}} %*The GreenDroid Mobile Application Processor: An Architecture for Silicon's Dark Future %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5719585 %f/micro/1gxdthypuq0ejcvhi4gmks753zae8bfj.pdf %mdda6bdc18ce00198c0106a49c1995859 %cmicro %@[{'name': 'Richard H. Stern', 'affiliation': 'r.stern@computer.org', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/5751930/5751941/5751941-photo-1-small.gif', 'p': ['']}} %*Standardization Skullduggery Revisited %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5751941 %f/micro/pj1doxu9t48nkzuvyfg2rsqpm7wty3cm.pdf %m78eef0de87a720218f7bea172df216f1 %cmicro %@[{'name': 'Richard Mateosian', 'affiliation': 'xrm@pacbell.net'} %*Technology %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5751942 %f/micro/ckbthwsym4zif1olpzdektajxunri0yj.pdf %m74a1c56de90dc141611bb788a9ea3240 %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'greenstein@kellogg.northwestern.edu', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/5751930/5751943/5751943-photo-1-small.gif', 'p': ['']}} %*The Direction of Broadband Spillovers %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5751943 %f/micro/tl2ixyhzwcnobdumfygh8soapke7vlfu.pdf %m968d3779e697b35f49687e54c0f5965a %cmicro %@[{'name': 'Erik R. Altman', 'affiliation': 'ealtman@us.ibm.com'} %*Very Large-Scale Systems and Some History %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5875955 %f/micro/2tnvvpgjc3hf4nsrdtp8fequbekwjxyz.pdf %m61018d96f89c685dffe4a6f6542f0c37 %cmicro %@[{'name': 'Natalie Enright Jerger', 'affiliation': 'University of Toronto', 'bio': {'p': ["Natalie Enright Jerger is an assistant professor in the Edward S. Rogers Department of Electrical and Computer Engineering at the University of Toronto. Her research interests include many-core and multicore architectures, on-chip networks, and cache coherence protocols. Enright Jerger has a PhD in electrical engineering from the University of Wisconsin-Madison. She's a member of IEEE, the IEEE Computer Society, and the ACM."]}}, {'name': 'Mikko Lipasti', 'affiliation': 'University of Wisconsin-Madison', 'bio': {'p': ["Mikko Lipasti is the Philip Dunham Reed Professor in Electrical and Computer Engineering at the University of Wisconsin–Madison. His research interests include improving performance and power efficiency, reducing bandwidth and complexity, and masking memory and interprocessor communication latencies in conventional computing systems, as well as novel biologically inspired computing systems modeled after the human neocortex. Lipasti received his PhD in electrical and computer engineering from Carnegie Mellon University. He's a senior member of IEEE.", 'Direct questions and comments about this article to Natalie Enright Jerger at enright@eecg.toronto.edu or Mikko Lipasti at mikko@engr.wisc.edu.']}} %*Systems for Very Large-Scale Computing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5875956 %f/micro/ykojpwdczdnpeesgi1amq509fjft4ngi.pdf %m2322b10cf97cbc08b4b1d1bdd61fd49b %cmicro %@[{'name': 'Ron Dror', 'affiliation': 'D.E. Shaw Research', 'bio': {'p': ['Ron O. Dror has managed and contributed to various research projects involving algorithms, computer architecture, and structural biology since joining D. E. Shaw Research as its first hire. Dror has a PhD in electrical engineering and computer science from the Massachusetts Institute of Technology.']}}, {'name': 'J.P. Grossman', 'affiliation': 'D.E. Shaw Research', 'bio': {'p': ['J. P. Grossman works on architecture, design, simulation, and implementation for Anton at D. E. Shaw Research. Grossman has a PhD in electrical engineering and computer science from the Massachusetts Institute of Technology.']}}, {'name': 'Kenneth Mackenzie', 'affiliation': 'D.E. Shaw Research', 'bio': {'p': ['Kenneth M. Mackenzie works on architectural simulation and software for Anton at D. E. Shaw Research. Mackenzie has a PhD in electrical engineering and computer science from the Massachusetts Institute of Technology.']}}, {'name': 'Brian Towles', 'affiliation': 'D.E. Shaw Research', 'bio': {'p': ['Brian Towles works on architecture, design, and implementation for Anton at D. E. Shaw Research. Towles has a PhD in electrical engineering from Stanford University.']}}, {'name': 'Edmond Chow', 'affiliation': 'D.E. Shaw Research', 'bio': {'p': ['Edmond Chow previously worked on software for Anton at D. E. Shaw Research. He is an associate professor at the Georgia Institute of Technology. Chow has a PhD in computer science from the University of Minnesota.']}}, {'name': 'John Salmon', 'affiliation': 'D.E. Shaw Research', 'bio': {'p': ['John K. Salmon is involved in algorithm design, software development, and computer architecture for Anton at D. E. Shaw Research. Salmon has a PhD in physics from the California Institute of Technology.']}}, {'name': 'Cliff Young', 'affiliation': 'D.E. Shaw Research', 'bio': {'p': ['Cliff Young works on architectural simulation, architecture design, and software for Anton at D. E. Shaw Research. Young has a PhD in computer science from Harvard University.']}}, {'name': 'Joseph Bank', 'affiliation': 'D.E. Shaw Research', 'bio': {'p': ['Joseph A. Bank is involved in architectural simulation, architecture design, and software for Anton at D. E. Shaw Research. Bank has an MEng in electrical engineering and computer science from the Massachusetts Institute of Technology.']}}, {'name': 'Brannon Batson', 'affiliation': 'D.E. Shaw Research', 'bio': {'p': ['Brannon Batson works on hardware architecture, design, and implementation for Anton at D. E. Shaw Research. Batson has an MS in electrical engineering from Purdue University.']}}, {'name': 'David Shaw', 'affiliation': 'D.E. Shaw Research', 'bio': {'p': ['Martin M. Deneroff previously led the hardware design and engineering team at D. E. Shaw Research. Deneroff has a BS in electrical engineering from the Massachusetts Institute of Technology.']}}, {'name': 'Jeffrey S. Kuskin', 'affiliation': 'D.E. Shaw Research', 'bio': {'p': ['Jeffrey S. Kuskin works on hardware architecture, design, and implementation for Anton at D. E. Shaw Research. Kuskin has a PhD in electrical engineering from Stanford University.']}}, {'name': 'Richard H. Larson', 'affiliation': 'D.E. Shaw Research', 'bio': {'p': ['Richard H. Larson works on hardware architecture, design, and implementation for Anton at D. E. Shaw Research. Larson has a BS in electrical engineering from the University of Illinois at Urbana-Champaign.']}}, {'name': 'Mark A. Moraes', 'affiliation': 'D.E. Shaw Research', 'bio': {'p': ['Mark A. Moraes heads the Anton software development and systems teams at D. E. Shaw Research. Moraes has an MASc in electrical engineering from the University of Toronto.']}}, {'name': 'David E. Shaw', 'affiliation': 'D.E. Shaw Research', 'bio': {'p': ['David E. Shaw serves as chief scientist at D. E. Shaw Research, where he works on the development of new algorithms and machine architectures for high-speed biomolecular simulations and on the application of such simulations to basic scientific research and computer-assisted drug design. He is also a senior research fellow at the Center for Computational Biology and Bioinformatics at Columbia University. Shaw has a PhD from Stanford University.']}} %*Overcoming Communication Latency Barriers in Massively Parallel Scientific Computation %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5765918 %f/micro/tqykvd68zi31obnrjwesadimlqh7g9f4.pdf %m0e5fa1402abd9e862d6c2fbe90c24b55 %cmicro %@[{'name': 'Ravi Iyer', 'affiliation': 'Intel Labs', 'bio': {'p': ['Ravi Iyer is a senior principal engineer and director of the SoC Platform Architecture Research Group at Intel Labs. His research focuses on future system-on-chip (SoC) and chip multiprocessor (CMP) architectures, especially small cores, accelerators, cache and memory hierarchies, fabrics, quality of service, emerging applications, and performance evaluation. Iyer has a PhD in computer science from Texas A&M University.']}}, {'name': 'Sadagopan Srinivasan', 'affiliation': 'Intel Labs', 'bio': {'p': ['Sadagopan Srinivasan is an engineer at Intel Labs, where he works on architecture and applications for mobile and heterogeneous systems. His research interests include processor architecture, memory subsystems, and performance modeling and analysis. Srinivasan has a PhD in computer engineering from the University of Maryland, College Park.']}}, {'name': 'Omesh Tickoo', 'affiliation': 'Intel Labs', 'bio': {'p': ['Omesh Tickoo is a research scientist at Intel Labs. His research interests include computer system architecture, multimedia, and networking. Tickoo has a PhD in electrical and computer systems engineering from Rensselaer Polytechnic Institute.']}}, {'name': 'Zhen Fang', 'affiliation': 'Intel Labs', 'bio': {'p': ['Zhen Fang is an engineer at Intel Labs, where he works on architecture and applications for mobile and embedded systems. His research interests include processor architecture, memory subsystems, parallel processing, and performance modeling and analysis. Fang has a PhD in computer science from the University of Utah.']}}, {'name': 'Rameshkumar Illikkal', 'affiliation': 'Intel Labs', 'bio': {'p': ['Ramesh Illikkal is a principal engineer in the Integrated Platform Research Lab at Intel Labs. His research interests include SoCs, CMPs, server architectures, virtualization, and memory hierarchies. Illikkal has an MTech in electronics from Cochin University of Science and Technology in India.']}}, {'name': 'Steven Zhang', 'affiliation': 'Intel Labs', 'bio': {'p': ['Steven Zhang is a senior engineer in the Integrated Platform Research Lab at Intel Labs. His research interests include SoC architecture, reconfigurable computing, and quick prototyping. Zhang has a PhD in communication engineering from Beijing University of Posts and Telecommunications.']}}, {'name': 'Vineet Chadha', 'affiliation': 'Intel Labs', 'bio': {'p': ["Vineet Chadha is a research scientist at Intel Labs. His research interests include computer architecture, virtualization, and distributed computing. Chadha has a PhD in computer and information science and engineering from the University of Florida. He's a member of the IEEE Computer Society and the ACM."]}}, {'name': 'Paul Stillwell', 'affiliation': 'Intel Labs', 'bio': {'p': ['Paul M. Stillwell Jr. is a senior engineer in the Integrated Platform Research Lab at Intel Labs. His research interests include SoCs and deeply embedded architectures. Stillwell has a BS in electrical engineering from North Carolina State University.']}}, {'name': 'Seung Eun Lee', 'affiliation': 'Seoul National University of Science and Technology', 'bio': {'p': ["Seung Eun Lee is an assistant professor in the Department of Electronic and Information Engineering at Seoul National University of Science and Technology. His research interests include computer architecture, multiprocessor SoCs, networks on chips (NoCs), and very large-scale integration (VLSI) design. Lee has a PhD in electrical and computer engineering from the University of California, Irvine. He's a member of IEEE."]}} %*CogniServe: Heterogeneous Server Architecture for Large-Scale Recognition %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5753878 %f/micro/tc3qndymeza6vakoempihwllr0r71sgu.pdf %m3ff6af525ab92d76210ffe5f5c79a29e %cmicro %@[{'name': 'Juan Gonzalez', 'affiliation': 'Barcelona Supercomputing Center', 'bio': {'p': ['Juan Gonzalez is a researcher at the Barcelona Supercomputing Center and a PhD student in the Computer Architecture Department of the Polytechnic University of Catalonia. His research interests include the application of data-mining techniques to the automatic performance analysis of parallel applications. Gonzalez has an MS in computer science from the Polytechnic University of Catalonia.']}}, {'name': 'Judit Gimenez', 'affiliation': 'Barcelona Supercomputing Center', 'bio': {'p': ['Marc Casas is a post-doctoral research scholar at the Lawrence Livermore National Laboratory. His research interests span parallel computing, focusing on faulttolerance and reliability of HPC applications, scalability, and automatic performance analysis. Casas has a PhD in computer architecture from the Polytechnic University of Catalonia.']}}, {'name': 'Marc Casas', 'affiliation': 'Lawrence Livermore National Laboratory', 'bio': {'p': ['Judit Gimenez is a research manager at the Polytechnic University of Catalonia and the Performance Tools Group manager at the Barcelona Supercomputing Center. Her research interests include parallel computing, focusing on developing performance analysis tools. Gimenez has an MS in computer science from the Polytechnic University of Catalonia.']}}, {'name': 'Miquel Moreto', 'affiliation': 'Polytechnic University of Catalonia', 'bio': {'p': ['Miquel Moreto is a lecturer in the Computer Architecture Department at the Polytechnic University of Catalonia. His research interests include modeling parallel computers and resource sharing in multithreaded architectures. Moreto has a PhD in computer architecture from the Polytechnic University of Catalonia.']}}, {'name': 'Alex Ramirez', 'affiliation': 'Polytechnic University of Catalonia', 'bio': {'p': ['Alex Ramirez is an associate professor at the Polytechnic University of Catalonia and a research manager at the Barcelona Super-computing Center. His research interests include heterogeneous multicore architectures, hardware support for programming models, and simulation techniques. Ramirez has a PhD in computer science from the Polytechnic University of Catalonia.']}}, {'name': 'Jesus Labarta', 'affiliation': 'Polytechnic University of Catalonia', 'bio': {'p': ['Jesus Labartais a professor at the Polytechnic University of Catalonia and director of the Computer Science Department of the Barcelona Supercomputer Center. His research interests include high-performance architectures and system software, particularly programming models and performance tools. Labarta has a PhD in telecommunications from the Polytechnic University of Catalonia.']}}, {'name': 'Mateo Valero', 'affiliation': 'Polytechnic University of Catalonia', 'bio': {'p': ["Mateo Valero is a professor at the Polytechnic University of Catalonia and director of the Barcelona Supercomputer Center. His research interests include high-performance architectures. Valero has a PhD in telecommunications from the Polytechnic University of Catalonia. He's a fellow of IEEE and the ACM and a Distinguished Research Fellow at Intel."]}} %*Simulating Whole Supercomputer Applications %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5875957 %f/micro/zaspwub0vpb8kijoqokfx3ht6wm1gv9g.pdf %m3341f023654a5811a9dea10c528c9748 %cmicro %@[{'name': 'Stijn Polfliet', 'affiliation': 'Ghent University', 'bio': {'p': ['Stijn Polfliet is a doctoral student in the Electronics and Information Systems Department at Ghent University. His research interests include computer architecture and systems, with a specific emphasis on managing power consumption in high-end computer systems. Polfliet received his MS in computer science and engineering from Ghent University.']}}, {'name': 'Frederick Ryckbosch', 'affiliation': 'Ghent University', 'bio': {'p': ['Frederick Ryckbosch is a doctoral student in the Electronics and Information Systems Department at Ghent University. His research interests include computer architecture and systems, especially simulation, modeling, and optimization of high-end computer systems. Ryckbosch received his MS in computer science and engineering from Ghent University.']}}, {'name': 'Lieven Eeckhout', 'affiliation': 'Ghent University', 'bio': {'p': ["Lieven Eeckhout is an associate professor in the Electronics and Information Systems Department at Ghent University. His research interests include computer architecture and the hardware/software interface, with a focus on performance analysis, evaluation, and modeling and workload characterization. Eeckhout received his PhD in computer science and engineering from Ghent University. He's a member of IEEE and the ACM."]}} %*Automated Full-System Power Characterization %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5753879 %f/micro/rkyocueyaxopqmsjdv2u9gfh0intjprz.pdf %m1808ccbaee550f14362ab82616065fa2 %cmicro %@[{'name': 'Victor Jimenez', 'affiliation': 'Barcelona Supercomputing Center', 'bio': {'p': ['Víctor Jiménez is a doctoral candidate in the Computer Architecture Department at the Polytechnic University of Catalonia, Spain, and a resident student at the Barcelona Supercomputing Center. His research interests include performance- and power-efficient systems, operating systems, and parallel architectures. Jiménez has an MSc in computer science from the Polytechnic University of Catalonia.']}}, {'name': 'Francisco Cazorla', 'affiliation': 'Barcelona Supercomputing Center', 'bio': {'p': ['Roberto Gioiosa is a senior researcher in the group on operating system/computer architecture interaction at the Barcelona Super-computing Center. His research interests include operating systems, high-performance computing, real-time systems, large parallel clusters, embedded systems, network protocols, processors, and network cards. Gioiosa has a PhD in computer science from the University of Rome Tor Vergata.']}}, {'name': 'Roberto Gioiosa', 'affiliation': 'Spanish National Research Council', 'bio': {'p': ['Francisco J. Cazorla is a researcher in the Spanish National Research Council. He leads the group on operating system/computer architecture interaction at the Barcelona Supercomputing Center. His research interests include multithreaded architectures for both high-performance and real-time systems. Cazorla has a PhD from the Polytechnic University of Catalonia.']}}, {'name': 'Eren Kursun', 'affiliation': 'Polytechnic University of Catalonia', 'bio': {'p': ["Mateo Valero is a professor at the Polytechnic University of Catalonia and director of the Barcelona Supercomputer Center. His research interests include high-performance architectures. Valero has a PhD in telecommunications from the Polytechnic University of Catalonia. He's an IEEE Fellow, an Intel Distinguished Research Fellow, and an ACM Fellow."]}}, {'name': 'Canturk Isci', 'affiliation': 'IBM Thomas J. Watson Research Center', 'bio': {'p': ["Eren Kursun is a research staff member in the Computer Architecture Department at the IBM Thomas J. Watson Research Center. Her research interests include power and temperature management of microprocessor architectures and low-power design. Kursun has a PhD in computer science from the University of California, Los Angeles. She's a member of IEEE and the ACM."]}}, {'name': 'Alper Buyuktosunoglu', 'affiliation': 'IBM Thomas J. Watson Research Center', 'bio': {'p': ['Canturk Isci is a research staff member in the Distributed Systems Department at the IBM Thomas J. Watson Research Center. His research interests include virtualization, data center energy management, and microarchitectural and system-level techniques for workload-adaptive and energy-efficient computing. Isci has a PhD in computer engineering from Princeton University.']}}, {'name': 'Pradip Bose', 'affiliation': 'IBM Thomas J. Watson Research Center', 'bio': {'p': ["Alper Buyuktosunoglu is a research staff member in the Reliability and Power-Aware Microarchitecture Department at the IBM Thomas J. Watson Research Center. His work has included support for IBM p-series and z-series microprocessors in the areas of power-aware computer architectures, dynamic power management, and high-level power modeling. Buyuktosunoglu has a PhD in electrical and computer engineering from the University of Rochester. He's a senior member of IEEE and an editorial board member for IEEE Micro."]}}, {'name': 'Mateo Valero', 'affiliation': 'IBM Thomas J. Watson Research Center', 'bio': {'p': ["Pradip Bose is a research staff member and manager of the Reliability and Power-Aware Microarchitecture Department at the IBM Thomas J. Watson Research Center. His work has included presilicon modeling and definition of IBM Power-series microarchitectures, beginning with the research precursor of the first RS/6000 product. Bose has a PhD in electrical and computer engineering from the University of Illinois at Urbana-Champaign. He's a fellow of IEEE and an advisory board member of IEEE Micro."]}} %*Energy-Aware Accounting and Billing in Large-Scale Computing Facilities %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5753877 %f/micro/hr3iop2i6w5yvtbxdtzm4g7jgfsenjvo.pdf %m9190c3d64dd4bf55814b61914a4b8f98 %cmicro %@[{'name': 'Enrico Bini', 'affiliation': "Scuola Superiore Sant'Anna", 'bio': {'p': ["Enrico Bini is an assistant professor in the Real-Time Systems Laboratory at the Scuola Superiore Sant'Anna of Pisa. His research interests include real-time scheduling, embedded systems design, and optimization methods. Bini has a PhD in computer engineering from Scuola Superiore Sant'Anna. He's a member of the IEEE Computer Society."]}}, {'name': 'Giorgio Buttazzo', 'affiliation': "Scuola Superiore Sant'Anna", 'bio': {'p': ["Giorgio Buttazzo is a full professor in the Department of Computer Engineering at the Scuola Superiore Sant'Anna of Pisa. His research interests include real-time systems, scheduling and resource management algorithms. Buttazzo has a PhD in computer engineering from the Scuola Superiore Sant'Anna. He has coauthored six books on real-time systems, including Soft Real-Time Systems: Predictability vs. Efficiency (Springer, 2010). He's a senior member of IEEE."]}}, {'name': 'Johan Eker', 'affiliation': 'Ericsson Research', 'bio': {'p': ["Johan Eker is a senior specialist at Ericsson Research. He's also the coordinator of the European Seventh Framework Program (FP-7) research project ACTORS. His research interests include embedded software with a focus on real-time systems and program language design. Eker has a PhD in automatic control from Lund University. He's a member of ACM."]}}, {'name': 'Stefan Schorr', 'affiliation': 'Technische Universitat Kaiserslautern', 'bio': {'p': ['Stefan Schorr is a doctoral candidate in realtime systems at Technische Universität Kaiserslautern. His research interests include real-time scheduling theory and multicore real-time systems. Schorr has an MSc in information technology from Technische Universität Kaiserslautern.']}}, {'name': 'Raphael Guerra', 'affiliation': 'Technische Universitat Kaiserslautern', 'bio': {'p': ['Raphael Guerra is a doctoral candidate in real-time systems at Technische Universität Kaiserslautern. His research interests include adaptive and flexible real-time systems. Guerra has an MSc in parallel and distributed computing from the Fluminense Federal University in Brazil.']}}, {'name': 'Gerhard Fohler', 'affiliation': 'Technische Universitat Kaiserslautern', 'bio': {'p': ["Gerhard Fohler is a professor in real-time systems at Technische Universität Kaiserslautern. His research interests include adaptive real-time systems and networks and media processing. He received his PhD in computer science from the Vienna University of Technology. He is an associate editor of the Real-Time Systems Journal and a real-time systems editor of the Journal of System Architectures. He's chairman of the Euromicro Technical Committee on Real-Time Systems and a member of the IEEE Technical Committee on Real-Time Systems. He's a senior member of IEEE."]}}, {'name': 'Karl-Erik Arzen', 'affiliation': 'Lund University', 'bio': {'p': ["Karl-Erik Årzén is a professor in automatic control at Lund University. His research interests include embedded control, control of computing systems, real-time systems, cosimulation tools, and adaptive resource management. Årzén has a PhD in automatic control from Lund University. He's a member of IEEE."]}}, {'name': 'Vanessa Romero', 'affiliation': 'Lund University', 'bio': {'p': ["Vanessa Romero Segovia is a doctoral student in automatic control at Lund University. Her research interests include resource management in real-time systems and control process. Romero got her MS in electrical engineering in the field of automation and control from Technische Universität Kaiserslautern. She's a member of IEEE."]}}, {'name': 'Claudio Scordino', 'affiliation': 'Evidence Srl', 'bio': {'p': ['Claudio Scordino is a software engineer and project manager at Evidence Srl. His current research activities include energy-aware scheduling, real-time operating systems, and embedded devices. Scordino has a PhD in computer science from the University of Pisa.']}} %*Resource Management on Multicore Systems: The ACTORS Approach %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5680892 %f/micro/rhrbou1xclvcw5kd6q7hibsfuzzpmlde.pdf %m18ea4c48b92a07453fadb4022a488a9c %cmicro %@[{'name': 'Wei Huang', 'affiliation': 'IBM Austin Research Laboratory', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/5875951/5875958/5875958-photo-1-small.gif', 'p': ['', 'Wei Huang is a research scientist at the IBM Austin Research Laboratory. His research interests include power-aware processors, systems, and data centers. Huang has a PhD in electrical engineering from the University of Virginia.']}}, {'name': 'Malcolm Allen-Ware', 'affiliation': 'IBM Austin Research Laboratory', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/5875951/5875958/5875958-photo-2-small.gif', 'p': ['', "Malcolm Allen-Ware is a member of the Power-Aware Systems Department at the IBM Austin Research Laboratory and is an IBM Master Inventor. His work includes researching dynamic power management for all classes of IBM servers. Allen-Ware has a master's degree from North Carolina State University."]}}, {'name': 'John B. Carter', 'affiliation': 'IBM Austin Research Laboratory', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/5875951/5875958/5875958-photo-3-small.gif', 'p': ['', 'John B. Carter leads the Power Aware Systems research group at the IBM Austin Research Laboratory. His research interests include reducing data center and server energy consumption. Carter has a PhD in computer science from Rice University.']}}, {'name': 'Mircea R. Stan', 'affiliation': 'University of Virginia', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/5875951/5875958/5875958-photo-4-small.gif', 'p': ['', 'Edmund Cheng is CEO of Gradient Design Automation. His research interests include circuit simulation, energy-efficient circuit design, and thermal simulation. Cheng has a PhD in electrical engineering from the California Institute of Technology.']}}, {'name': 'Kevin Skadron', 'affiliation': 'University of Virginia', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/5875951/5875958/5875958-photo-5-small.gif', 'p': ['', 'Kevin Skadron is a professor in the Department of Computer Science at the University of Virginia. His research interests include computational science and computer architectures for managing power, temperature, and reliability. Skadron has a PhD in computer science from Princeton University.']}}, {'name': 'Edmund Cheng', 'affiliation': 'Gradient Design Automation', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/5875951/5875958/5875958-photo-6-small.gif', 'p': ['', 'Mircea R. Stan is a professor in the Charles L. Brown ECE Department at the University of Virginia in Charlottesville. His research interests include high-performance/low-power VLSI, nanoelectronic circuits, and temperature-aware circuits and architecture. Stan has a PhD from the University of Massachusetts at Amherst.']}} %*Temperature-Aware Architecture: Lessons and Opportunities %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5875958 %f/micro/5jzhmhkcavx3ml2dbgzj0ooxsc4ltvue.pdf %m14cbf907f6afc6b64f7ae081f7a2f932 %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'greenstein@kellogg.northwestern.edu', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/5875951/5875959/5875959-photo-1-small.gif', 'p': ['Shane Greenstein greenstein@kellogg.northwestern.edu']}} %*The Open Internet Order %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5875959 %f/micro/0fxl7i5gwnsg2v9jpqtzfqx18oih6zsb.pdf %mfa9a177a15deb6b523e6f774f03d635b %cmicro %@[{'name': 'Erik R. Altman', 'affiliation': 'ealtman@us.ibm.com', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/5966997/5967001/5967001-photo-1-small.gif', 'p': []}} %*Big Chips and Beyond %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5967001 %f/micro/qhhzefob2cmcvnwuzgp4jrmxe9loi3tv.pdf %mbb079df3fd9069c9af81b3a3bcd9e48a %cmicro %@[{'name': 'Krste Asanović,', 'affiliation': 'University of California, Berkeley', 'bio': {'p': ['Andrew B. Kahng is a professor of CSE and ECE at the University of California at San Diego. His research interests include integrated-circuit physical design and performance analysis, the integrated-circuit design-manufacturing interface, combinatorial algorithms and optimization, and the road-mapping of systems and technology. Kahng holds a PhD in computer science from the University of California at San Diego. He is an IEEE Fellow.']}}, {'name': 'Ralph Wittig', 'affiliation': 'Xilinx', 'bio': {'p': ['Vijayalakshmi Srinivasan is a research staff member at the IBM T.]. Watson Research Center. Her research interests are in computer architecture, especially processor microarchi-tecture, and multicore and multiprocessor memory systems. Srinivasan holds a PhD in electrical engineering and computer science from the University of Michigan. She is a senior member of IEEE.']}} %*Big Chips %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5967002 %f/micro/etlspcbd3iectwrvxzzw2arplbm1yo4u.pdf %mece7c9e49a487cf220a8dd87f8871395 %cmicro %@[{'name': 'Nikos Hardavellas', 'affiliation': 'Northwestern University', 'bio': {'p': ["Nikos Hardavellas is the June and Donald Brewer Assistant Professor of Electrical Engineering and Computer Science at Northwestern University, and the director of the Parallel Architecture Group at Northwestern (PARAG@N). His research interests are in hardware and software design for energy-efficient scalable parallel architectures, memory systems, and on-chip interconnects. Hardavellas has a PhD in computer science from Carnegie Mellon University. He's a member of the ACM and IEEE."]}}, {'name': 'Michael Ferdman', 'affiliation': 'Carnegie Mellon University', 'bio': {'p': ["Michael Ferdman is a PhD candidate in electrical and computer engineering at Carnegie Mellon University. His research interests include computer architecture with an emphasis on proactive memory system design. Ferdman has an MS in electrical and computer engineering from Carnegie Mellon University. He's a student member of the ACM and IEEE."]}}, {'name': 'Babak Falsafi', 'affiliation': 'É,cole Polytechnique Fé,dé,rale de Lausanne', 'bio': {'p': ['Babak Falsafi is a professor of computer and communication sciences at Ecole Polytechnique Fédérale de Lausanne, where he directs the EcoCloud center targeting robust, economic, and environmentally friendly cloud technologies. Falsafi has a PhD in computer science from the University of Wisconsin-Madison. He is a senior member of the ACM and IEEE.']}}, {'name': 'Anastasia Ailamaki', 'affiliation': 'É,cole Polytechnique Fé,dé,rale de Lausanne', 'bio': {'p': ['Anastasia Ailamaki is a professor of computer science at Ecole Polytechnique Federale de Lausanne. Her research interests are in optimizing database workloads for modern hardware and disks and in managing large data sets for scientific applications. Ailamaki has a PhD in computer science from the University of Wisconsin-Madison.', 'Selected CS articles and columns are also available for free at http://ComputingNow.computer.org.']}} %*Toward Dark Silicon in Servers %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5967003 %f/micro/zabya1csk7rzn0juohc2wenrjgppi9x6.pdf %m95d96a5cd3d90fc95ebb3cc7a525e9b7 %cmicro %@[{'name': 'Wei Huang', 'affiliation': 'IBM Research - Austin', 'bio': {'p': ["Wei Huang is a research scientist at IBM Research – Austin. His research interests include power-, thermal- and reliability-aware processors, systems, and data centers. Huang has a PhD in electrical engineering from the University of Virginia. He's a member of IEEE."]}}, {'name': 'Karthick Rajamani', 'affiliation': 'IBM Research - Austin', 'bio': {'p': ["Karthick Rajamani is a research staff member and manager of the Power-Aware Systems Department at IBM Research–Austin. His research interests include dynamic-power management architectures, including the IBM Power6 and Power7 processors and EnergyScale systems, energy-efficient memory subsystems, and energy-aware systems software. Rajamani has a PhD in electrical and computer engineering from Rice University. He's a senior member of IEEE and a member of the ACM."]}}, {'name': 'Mircea R. Stan', 'affiliation': 'University of Virginia', 'bio': {'p': ["Mircea R. Stan is a professor in the Charles L. Brown Department of Electrical and Computer Engineering at the University of Virginia. His research interests include highperformance and low-power VLSI, nanoelectronic circuits, and computer architecture. Stan has a PhD in electrical and computer engineering from the University of Massachusetts Amherst. He's a senior member of IEEE and a member of the ACM."]}}, {'name': 'Kevin Skadron', 'affiliation': 'University of Virginia', 'bio': {'p': ["Kevin Skadron is a professor in the Department of Computer Science at the University of Virginia, and an editorial-board member of IEEE Micro. His research interests include computational science and computer architecture for managing power, temperature, and reliability. Skadron has a PhD in computer science from Princeton University. He's a senior member of IEEE, the IEEE Computer Society, and the IEEE Circuits and Systems Society, and a distinguished scientist in the ACM."]}} %*Scaling with Design Constraints: Predicting the Future of Big Chips %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5887308 %f/micro/o5tqhrcmgkta2vu8bxerzmdqngiw1lhl.pdf %ma25b19752d7e0adfd2dbc08ddb183859 %cmicro %@[{'name': 'Daniel Johnson', 'affiliation': 'University of Illinois at Urbana-Champaign', 'bio': {'p': ["Daniel R. Johnson is a PhD candidate in electrical and computer engineering at the University of Illinois at Urbana-Champaign. His research interests include parallel accelerators and domain-specific architectures. Johnson has an MS in electrical and computer engineering from the University of Illinois at Urbana-Champaign. He's a member of the ACM and IEEE."]}}, {'name': 'Matthew Johnson', 'affiliation': 'University of Illinois at Urbana-Champaign', 'bio': {'p': ["Matthew R. Johnson is a PhD candidate in electrical and computer engineering at the University of Illinois at Urbana-Champaign. His research interests include memory systems, energy-efficient architectures, and hardware/software codesign. Johnson has a BS in electrical and computer engineering and computer science from Duke University. He's a member of the ACM and IEEE."]}}, {'name': 'John Kelm', 'affiliation': 'University of Illinois at Urbana-Champaign', 'bio': {'p': ["John H. Kelm is a software engineer at Intel. His research interests include parallel architectures, memory system design, and cache-coherence protocols. Kelm received his PhD in electrical and computer engineering from the University of Illinois at Urbana-Champaign. He's a member of the ACM and IEEE."]}}, {'name': 'William Tuohy', 'affiliation': 'University of Illinois at Urbana-Champaign', 'bio': {'p': ["William Tuohy is a PhD student in electrical and computer engineering at the University of Illinois at Urbana-Champaign. His research interests include parallel architectures, compilers, and memory systems. Tuohy has a BS in electrical engineering and computer science from the University of California, Berkeley. He's a member of the ACM and IEEE."]}}, {'name': 'Steven Lumetta', 'affiliation': 'University of Illinois at Urbana-Champaign', 'bio': {'p': ["Steven S. Lumetta is an associate professor in the Electrical and Computer Engineering Department at the University of Illinois at Urbana-Champaign. His interests center on high-performance networking and computing, hierarchical systems, and parallel runtime software. Lumetta has a PhD in computer science from the University of California, Berkeley. He's a member of the ACM and IEEE."]}}, {'name': 'Sanjay Patel', 'affiliation': 'University of Illinois at Urbana-Champaign', 'bio': {'p': ["Sanjay J. Patel is an associate professor in the Electrical and Computer Engineering Department and a Sony Faculty Scholar at the University of Illinois at Urbana-Champaign. His research interests include high-throughput chip architectures and visual computing. Patel has a PhD in computer science and engineering from the University of Michigan, Ann Arbor. He's a member of IEEE.", 'Direct questions or comments about this article to Daniel R. Johnson, University of Illinois at Urbana-Champaign, Coordinated Sciences Laboratory, 1306 W. Main St., Urbana, IL 61801, djohns53@illinois.edu.']}} %*Rigel: A 1,024-Core Single-Chip Accelerator Architecture %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5871571 %f/micro/hyxsopk5ezwbgfc2jiuimqtqyg38vpve.pdf %m42c44b8e858a324a99e8d40d88516b24 %cmicro %@[{'name': 'Junli Gu', 'affiliation': 'Tsinghua University', 'bio': {'p': ["Junli Gu is a doctoral student at the Institute of Microelectronics at Tsinghua University. She performed the work described in this article as a visiting scholar at the University of Illinois at Urbana-Champaign. Her research interests include design for multi-and manycore computer architectures and parallel computing. Gu has a BS in communication engineering from Hefei University of Technology. She's a student member of IEEE."]}}, {'name': 'Yihe Sun', 'affiliation': 'Tsinghua University', 'bio': {'p': ["Yihe Sun is a professor in the Department of Microelectronics and Nanoelectronics of Tsinghua University. His research interests include system-on-ship (SoC) testability, design methodology for multimedia VLSI devices, and Web network and data security for VLSI and SoCs based on standard cell technology and digital-signal processing (DSP) cores. Sun has a degree in automatic control from Tsinghua University. He's a member of IEEE."]}}, {'name': 'Steven S. Lumetta', 'affiliation': 'University of Illinois at Urbana-Champaign', 'bio': {'p': ["Steven S. Lumetta is an associate professor of Electrical and Computer Engineering and a research associate professor in the Coordinated Science Laboratory at the University of Illinois at Urbana-Champaign. His research interests include optical networking, highperformance networking and computing, hierarchical systems, and parallel runtime software. Lumetta has a PhD in computer science from the University of California, Berkeley. He's a member of IEEE."]}}, {'name': 'Rakeshh Kumar', 'affiliation': 'University of Illinois at Urbana-Champaign', 'bio': {'p': ["Rakesh Kumar is an assistant professor in the Electrical and Computer Engineering Department at the University of Illinois at Urbana-Champaign. His research interests include robust computer systems, computer architectures, and programming models for emerging workloads. Kumar has a PhD in computer engineering from the University of California, San Diego. He's a member of IEEE.", 'Selected CS articles and columns are also available for free at http://ComputingNow.computer.org']}} %*MOPED: Accelerating Data Communication on Future CMPs %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5887310 %f/micro/5dsyqnolgzo0x4hegjw1mt3pierhm8bq.pdf %m485bfa22896cca89bba158078f298ac2 %cmicro %@[{'name': 'David Papa', 'affiliation': 'Broadway Technology', 'bio': {'p': ['David Papa is a senior developer at Broadway Technology, a small financial software start-up. His research interests include physical design, especially physical synthesis and placement. Papa has a PhD in computer science and engineering from the University of Michigan, Ann Arbor.']}}, {'name': 'Charles Alpert', 'affiliation': 'IBM', 'bio': {'p': ['Natarajan Viswanathan is an advisory engineer at the Systems and Technology Group at IBM. His work focuses on physical synthesis for nanometer-scale integrated circuits. Viswanathan has a PhD in computer engineering from Iowa State University.']}}, {'name': 'Cliff Sze', 'affiliation': 'IBM Austin Research Laboratory', 'bio': {'p': ["Cliff Sze is a research staff member at the IBM Austin Research Laboratory. His research interests include integrated placement, routing, and timing optimization for ASIC and microprocessor designs. Sze has a PhD in computer engineering from Texas A&M University. He's a senior member of IEEE."]}}, {'name': 'Zhuo Li', 'affiliation': 'IBM Austin Research Laboratory', 'bio': {'p': ["Zhuo Li is a research staff member in the IBM Austin Research Laboratory. His research interests include physical synthesis for congestion, area, power, and timing, simulation and modeling, and design and analysis of general large-scale algorithms. Li has a PhD in computer engineering from Texas A&M University. He's a senior member of IEEE."]}}, {'name': 'Natarajan Viswanathan', 'affiliation': 'IBM Austin Research Laboratory', 'bio': {'p': ["Gi-Joon Nam is a research staff member at the IBM Austin Research Laboratory, where he works on the physical design space. His research interests include CAD algorithms, combinatorial optimization, VLSI system design, and computer architecture. Nam has a PhD in computer science and engineering from the University of Michigan, Ann Arbor. He's a senior member of IEEE and the ACM."]}}, {'name': 'Gi-Joon Nam', 'affiliation': 'IBM Austin Research Laboratory', 'bio': {'p': ["Charles Alpert manages the Design Productivity Group at the IBM Austin Research Laboratory. His research interests include architecting design automation tools and methodologies to improve designer productivity and reduce design cost. Alpert has a PhD in computer science from the University of California, Los Angeles. He's an associate editor of IEEE Transactions on Computer-Aided Design and an IEEE Fellow."]}}, {'name': 'Igor Markov', 'affiliation': 'University of Michigan, Ann Arbor', 'bio': {'p': ["Igor L. Markov is an associate professor of electrical engineering and computer science at the University of Michigan, Ann Arbor. His research focuses on computers that make computers. Markov has a PhD in computer science from the University of California, Los Angeles. He coauthored VLSI Physical Design: From Graph Partitioning to Timing Closure (Springer, 2011). He's a senior member of IEEE and the ACM.", 'Direct questions or comments about this article to Gi-Joon Nam, Design Productivity Group (NJDJ), IBM Austin Research Laboratory, 11501 Burnet Rd., MS 904–6G017, Austin, TX 78758, gnam@us.ibm.com.']}} %*Physical Synthesis with Clock-Network Optimization for Large Systems on Chips %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5887309 %f/micro/9okrmdgwft7cvlc4nra85h6ytpvxypu1.pdf %mda613e71993676d3af545f19baa6aeab %cmicro %@[{'name': 'Ayse Coskun', 'affiliation': 'Boston University', 'bio': {'p': ["Ayse K. Coskun is an assistant professor in the Electrical and Computer Engineering Department at Boston University. Her research interests include energy-efficient computing, multicore architectures, 3D stacked architectures, embedded systems, and software. Coskun has a PhD in computer science and engineering from the University of California, San Diego. She's a member of IEEE and the ACM."]}}, {'name': 'David Atienza', 'affiliation': 'Boston University', 'bio': {'p': ['Jie Meng is a PhD student in electrical and computer engineering at Boston University. Her research interests include many-core and 3D stacked architectures, focusing on energy awareness and performance improvement for future systems. Meng has an MS in electrical engineering from McMaster University in Canada.']}}, {'name': 'Mohamed Sabry', 'affiliation': 'Ecole Polytechnique Federale de Lausanne', 'bio': {'p': ["David Atienza is a professor of electrical engineering and the director of the Embedded Systems Laboratory at the Ecole Polytechnique Fédérale de Lausanne, and an adjunct professor in the Computer Architecture Department at the Complutense University of Madrid (UCM). His research interests include system-level design methodologies for high-performance multiprocessor systems on chips (MPSoCs) and embedded systems, including 2D and 3D thermally aware design, wireless sensor networks, hardware and software reconfigurable systems, dynamic-memory optimizations, and network-on-chip design. Atienza has a PhD in computer science and engineering from the Inter-University Microelectronics Center, Belgium, and the UCM. He's an associate editor of IEEE Transactions on CAD, IEEE Embedded Systems Letters, and Integration: The VLSI Journal"]}}, {'name': 'Jie Meng', 'affiliation': 'Ecole Polytechnique Federale de Lausanne', 'bio': {'p': ['Mohamed M. Sabry is a PhD student in the Electrical Engineering Department and a member of the Embedded Systems Laboratory at the Ecole Polytechnique Fédérale de Lausanne. His research interests include system design and resource management methodologies in embedded systems, and MPSoCs, especially temperature and reliability management of 2D and 3D MPSoCs. Sabry has an MS in electrical engineering from AinShams University, Egypt.']}} %*Attaining Single-Chip, High-Performance Computing through 3D Systems with Active Cooling %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5770260 %f/micro/y8z7ujmr2hfobpvw1zdvt5bfcoxeis0j.pdf %mc7b78906ed4abfcde9f013c323e57f3c %cmicro %@[{'name': 'Richard Vuduc', 'affiliation': 'Georgia Institute of Technology', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/5966997/5967004/5967004-photo-1-small.gif', 'p': ['Richard Vuduc is an assistant professor in the School of Computational Science and Engineering at the Georgia Institute of Technology. His research lab, The HPC Garage (http://hpcgarage.org), studies high-performance computing, with an emphasis on parallel algorithms and performance analysis and tuning. Vuduc has a PhD in computer science from the University of California, Berkeley. He is a member of IEEE, the ACM, and SIAM.']}}, {'name': 'Kent Czechowski', 'affiliation': 'Georgia Institute of Technology', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/5966997/5967004/5967004-photo-2-small.gif', 'p': ['Kent Czechowski is a PhD student in the School of Computational Science and Engineering at the Georgia Institute of Technology. His research interests include algorithm-architecture codesign, performance modeling for GPU/many-core architectures, and parallel and distributed algorithms. Czechowski has an MS in computer science from the Georgia Institute of Technology.']}} %*What GPU Computing Means for High-End Systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5967004 %f/micro/thv7nxjvllcams8xgumiask2q0d1dhkg.pdf %m44bb3a8cddaf458f2c2fbb83341baa63 %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'greenstein@kellogg.northwestern.edu', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/5966997/5967005/5967005-photo-1-small.gif', 'p': ['SHANE GREENSTEIN greenstein@kellogg.northwestern.edu']}} %*An Honest Policy Wonk %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5967005 %f/micro/kcdjiplqap0lz4trkudjw1ns6ymzov2c.pdf %ma2784aa18b934ab35522d924a30ec893 %cmicro %@[{'name': 'Erik R. Altman', 'affiliation': 'ealtman@us.ibm.com', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6045679/6045683/6045683-photo-1-small.gif', 'p': ['Erik R. Altman IEEE Micro']}} %*CPUs and GPUs: Who Owns the Future? %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6045683 %f/micro/qehez1bcyztak45u2wnbimsaidxlfhu0.pdf %m6ab76f768f4da02b683503ff604b3689 %cmicro %@[{'name': 'David Brooks', 'affiliation': 'Harvard University', 'bio': {'p': ['David Brooks is a Gordon McKay Professor of Computer Science in the School of Engineering and Applied Sciences at Harvard University. His research interests include technology-aware computer design, with an emphasis on power-efficient computer architectures and system software for high-performance and embedded systems. Brooks has a PhD in electrical engineering from Princeton University.']}} %*CPUs, GPUs, and Hybrid Computing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6045684 %f/micro/dr89uj3pr1ecabzdsywvqna7lnpgsgyh.pdf %mabc57febb1ae8c818ef0e577c884a872 %cmicro %@[{'name': 'Stephen W. Keckler', 'affiliation': 'Nvidia', 'bio': {'p': ["Stephen W. Keckler is the director of architecture research at Nvidia and a professor of computer science and electrical and computer engineering at the University of Texas at Austin. His research interests include parallel-computer architectures, memory systems, and interconnection networks. Keckler has a PhD in computer science from the Massachusetts Institute of Technology. He's a fellow of IEEE and a senior member of the ACM."]}}, {'name': 'William J. Dally', 'affiliation': 'Nvidia', 'bio': {'p': ["William J. Dally is the chief scientist at Nvidia and the Willard R. and Inez Kerr Bell Professor of Engineering at Stanford University. His research interests include parallel-computer architectures, interconnection networks, and high-speed signaling circuits. Dally has a PhD in computer science from the California Institute of Technology. He's a member of the National Academy of Engineering and a fellow of IEEE, the ACM, and the American Academy of Arts and Sciences."]}}, {'name': 'Brucek Khailany', 'affiliation': 'Nvidia', 'bio': {'p': ["Brucek Khailany is a senior research scientist at Nvidia. His research interests include energy-efficient architectures and circuits, cache and register file hierarchies, VLSI design methodology, and computer arithmetic. Khailany has a PhD in electrical engineering from Stanford University. He's a member of IEEE and the ACM."]}}, {'name': 'Michael Garland', 'affiliation': 'Nvidia', 'bio': {'p': ["Michael Garland is the senior manager of programming systems and applications research at Nvidia. His research interests include parallel-programming systems, languages, and algorithms. Garland has a PhD in computer science from Carnegie Mellon University. He's a member of the ACM."]}}, {'name': 'David Glasco', 'affiliation': 'Nvidia', 'bio': {'p': ["David Glasco is a senior research manager at Nvidia. His research interests include highperformance computer systems, interconnection networks, memory system architectures, computer graphics, and cache-coherent protocols. Glasco has a PhD in electrical engineering from Stanford University. He's a member of IEEE.", 'Direct questions and comments about this article to Stephen W. Keckler, Nvidia, 2701 San Tomas Expressway, Santa Clara, CA 95050, skeckler@nvidia.com.']}} %*GPUs and the Future of Parallel Computing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6045685 %f/micro/akp1cwmelspjg5r9f6oagtbvnimucdbv.pdf %m9592362fdfe867f1dc02c2dda492f257 %cmicro %@[{'name': 'David Rohr', 'affiliation': 'Frankfurt Institute for Advanced Studies at the Goethe University Frankfurt', 'bio': {'p': ['David Rohr is a PhD candidate in computer science at the Frankfurt Institute for Advanced Studies at the Goethe University Frankfurt. His research interests include GPU-based real-time event reconstruction for the ALICE experiment at CERN, fast linear algebra calculation, and efficient implementation of erasure codes. Rohr has a Diplom in physics from the University of Heidelberg.']}}, {'name': 'Matthias Bach', 'affiliation': 'Frankfurt Institute for Advanced Studies at the Goethe University Frankfurt', 'bio': {'p': ['Matthias Bach is a PhD candidate in computer science at the Frankfurt Institute for Advanced Studies at the Goethe University Frankfurt. His research interests include efficient lattice quantum chromodynamics calculations on hybrid multi- and many-core systems. Bach has a Diplom in physics from the University of Heidelberg.']}}, {'name': 'Matthias Kretz', 'affiliation': 'Frankfurt Institute for Advanced Studies at the Goethe University Frankfurt', 'bio': {'p': ['Matthias Kretz is a PhD student in computer science at the Frankfurt Institute for Advanced Studies at the Goethe University Frankfurt. His research interests include modern SIMD architectures, mainly developing a library for efficient, intuitive, and portable SIMD programming. Kretz has a Diplom in physics from Heidelberg University.']}}, {'name': 'Volker Lindenstruth', 'affiliation': 'Frankfurt Institute for Advanced Studies at the Goethe University Frankfurt', 'bio': {'p': ['Volker Lindenstruth leads the ALICE High Level Trigger project at CERN and is a Loewe Helmholtz International Center for FAIR (HIC for FAIR) professor at the Frankfurt Institute for Advanced Studies at the Goethe University Frankfurt. His research interests include the development of energy-efficient computer architectures and algorithms. Lindenstruth has a PhD in heavy-ion physics from Goethe University Frankfurt.']}} %*Multi-GPU DGEMM and High Performance Linpack on Highly Energy-Efficient Clusters %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5959146 %f/micro/h3n0dp8mku9tqz1vysclicrgstli7bwo.pdf %m058eba363d0b84bb5f42cac428040a8b %cmicro %@[{'name': 'Siegfried Benkner', 'affiliation': 'University of Vienna', 'bio': {'p': ["Siegfried Benkner is a full professor in the Faculty of Computer Science at the University of Vienna, where he heads the research group for Scientific Computing. His research interests include languages, compilers, and runtime systems for parallel and distributed systems, service-oriented software architectures, and grid and cloud computing. Benkner has a PhD in computer science from the Vienna University of Technology. He's a member of the ACM and IEEE."]}}, {'name': 'Sabri Pllana', 'affiliation': 'University of Vienna', 'bio': {'p': ["Sabri Pllana is a senior research scientist in the research group for Scientific Computing at the University of Vienna. His research interests include performance-oriented software engineering for parallel and distributed systems. Pllana has a PhD in computer science from the Vienna University of Technology. He's a member of IEEE, the HiPEAC network of excellence, and the PlanetHPC network."]}}, {'name': 'Jesper Larsson Traff', 'affiliation': 'University of Vienna', 'bio': {'p': ['Jesper Larsson Träff is a professor in the research group for Scientific Computing at the University of Vienna. His research interests include interfaces, algorithms, and architectures for parallel computing. Larsson Träff has a PhD in computer science and a DSc from the University of Copenhagen.']}}, {'name': 'Philippas Tsigas', 'affiliation': 'Chalmers University of Technology', 'bio': {'p': ['Philippas Tsigas is a professor in the Department of Computing Science at Chalmers University of Technology. His research interests include concurrent data structures for multiprocessor systems, communication, and coordination in parallel systems, fault-tolerant computing, mobile computing, and information visualization. Tsigas has a PhD in computer engineering and informatics from the University of Patras.']}}, {'name': 'Uwe Dolinsky', 'affiliation': 'Codeplay Software', 'bio': {'p': ['Uwe Dolinsky is CTO at Codeplay Software, where he is in charge of researching and developing novel compiler and software optimization technologies (such as Offload C++) for multicore processors. His research interests include programming models and compilation techniques for parallel processing. Dolinsky has a PhD in engineering and computer science from John Moores University Liverpool.']}}, {'name': 'Cedric Augonnet', 'affiliation': 'INRIA Bordeaux', 'bio': {'p': ['Cédric Augonnet is part of the Runtime team at INRIA Bordeaux and a PhD student in computer science at the University of Bordeaux. His research interests include task scheduling and hybrid accelerator-based machines. Augonnet has an MSc in computer science from the University of Bordeaux.']}}, {'name': 'Beverly Bachmayer', 'affiliation': 'Intel GmbH', 'bio': {'p': ["Beverly Bachmayer is a technical consulting engineer in the Software and Solutions Group at Intel GmbH. Her research interests include performance analysis and optimization of software on new computer architectures. Bachmayer has a BS in computer science from the University of Oregon and an MBA from Portland State University. She's a member of IEEE, the ACM, and the European Professional Women's Association."]}}, {'name': 'Christoph Kessler', 'affiliation': 'Linkö,ping University', 'bio': {'p': ["Christoph Kessler is a professor in the Department of Computer and Information Science at Linköping University, where he leads the Programming Environments Laboratory's research group on compiler technology and parallel computing. His research interests include parallel programming, compilers, and software composition. Kessler has a PhD in computer science from Saarbrücken University. He's a member of the ACM and the IEEE Computer Society."]}}, {'name': 'David Moloney', 'affiliation': 'Movidius', 'bio': {'p': ["David Moloney is the cofounder and CTO of Movidius, a fabless semiconductor company focused on the design of software-programmable multimedia accelerator systems on chips. His research interests include computer architecture and digital signal processing. Moloney has a PhD in engineering from Trinity College Dublin. He's a member of IEEE."]}}, {'name': 'Vitaly Osipov', 'affiliation': 'Karlsruhe Institute of Technology', 'bio': {'p': ['Vitaly Osipov is a PhD student in computer science at the Karlsruhe Institute of Technology. His research interests include graph algorithms for modern architectures such as external memory algorithms and parallel algorithms. Osipov has an MSc in mathematics from Ural State University and an MSc in computer science from Saarland University.', 'Selected CS articles and columns are also available for free at http://ComputingNow.computer.org']}} %*PEPPHER: Efficient and Productive Usage of Hybrid Computing Systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5959147 %f/micro/gz3a46n1gsxr0wxttrwflbch82siuqoz.pdf %mf91090646562e95e71dba7ad64d13d4f %cmicro %@[{'name': 'HyoukJoong Lee', 'affiliation': 'Stanford University', 'bio': {'p': ['HyoukJoong Lee is a PhD candidate in electrical engineering at Stanford University. His research interests include parallel computer architecture and general-purpose GPU computing with their programming models. Lee has an MS in electrical engineering from Stanford University.']}}, {'name': 'Kevin Brown', 'affiliation': 'Stanford University', 'bio': {'p': ['Kevin J. Brown is a PhD candidate in electrical engineering at Stanford University. His research interests include parallel computer architecture and heterogeneous runtime systems. Brown has an MS in electrical engineering from Stanford University.']}}, {'name': 'Arvind Sujeeth', 'affiliation': 'Stanford University', 'bio': {'p': ['Arvind K. Sujeeth is a PhD candidate in electrical engineering at Stanford University. His research interests include parallel programming models and domain-specific languages for machine learning. Sujeeth has an MS in electrical engineering from Stanford University.']}}, {'name': 'Hassan Chafi', 'affiliation': 'Stanford University', 'bio': {'p': ['Hassan Chafi is a PhD candidate in electrical engineering at Stanford University. His research interests include parallel programming models, domain-specific languages, and frameworks for simplifying programming heterogeneous systems. Chafi has an MS in electrical engineering from Stanford University.']}}, {'name': 'Tiark Rompf', 'affiliation': 'Stanford University', 'bio': {'p': ["Kunle Olukotun is a professor of electrical engineering and computer science at Stanford University and director of the Stanford Pervasive Parallelism Lab. His research interests include computer architecture and parallel programming environments. Olukotun has a PhD in computer engineering from the University of Michigan. He's a fellow of IEEE and the ACM."]}}, {'name': 'Martin Odersky', 'affiliation': 'Ecole Polytechnique Federale de Lausanne', 'bio': {'p': ['Tiark Rompf is a PhD candidate at Ecole Polytechnique Fédérale de Lausanne. His research interests include programming languages (in particular Scala), parallelism and compilers, with a focus on lowering the cost of very high level programming abstractions. Rompf has an MS in computer science from the University of Lübeck Germany.']}}, {'name': 'Kunle Olukotun', 'affiliation': 'Ecole Polytechnique Federale de Lausanne', 'bio': {'p': ["Martin Odersky is a professor in the school of computer and communication sciences at Ecole Polytechnique Fédérale de Lausanne. His research interests cover fundamental as well as applied aspects of programming languages, including semantics, type systems, programming language design, and compiler construction. Odersky has a PhD in computer science from ETH Zürich. He's a fellow of the ACM.", 'Direct questions and comments about this article to HyoukJoong Lee, Gates Building, Room 454, Stanford, CA 94305, hyouldee@stanford.edu.']}} %*Implementing Domain-Specific Languages for Heterogeneous Parallel Computing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5963629 %f/micro/6yixnlirmjc0fpepu3egbtqd4kwvfabt.pdf %m2b222b3604a63164f72fe747ccaf973f %cmicro %@[{'name': 'Hayden So', 'affiliation': 'University of Hong Kong', 'bio': {'p': ["Hayden K.-H. So is an assistant professor in the Department of Electrical and Electronic Engineering at the University of Hong Kong. His research interests include computer architecture, reconfigurable computing, field-programmable gate arrays, GPUs, and operating-system design. So has a PhD in electrical engineering and computer sciences from the University of California, Berkeley. He's a member of IEEE."]}}, {'name': 'Junying Chen', 'affiliation': 'University of Hong Kong', 'bio': {'p': ["Junying Chen is pursuing a PhD in electrical and electronic engineering at the University of Hong Kong. Her research interests include computer architecture and parallel computing, and their applications in ultrasound imaging systems. Chen has a BEng in electronic and information engineering from Zhejiang University. She's a student member of IEEE."]}}, {'name': 'Billy Yiu', 'affiliation': 'University of Hong Kong', 'bio': {'p': ["Billy Y. S. Yiu is a research associate in the Medical Engineering Program at the University of Hong Kong. His research focuses on medical ultrasound imaging, specifically the design of advanced imaging paradigms and new system hardware. Yiu has an MPhil in electrical and electronic engineering from the University of Hong Kong. He's a member of IEEE."]}}, {'name': 'Alfred Yu', 'affiliation': 'University of Hong Kong', 'bio': {'p': ["Alfred C. H. Yu is a research assistant professor in the Medical Engineering Program at the University of Hong Kong. His research interests include developing new medical ultrasound-imaging methods and systems for clinical applications and studying the fundamentals of various ultrasound-induced wave-matter interactions. Yu has a PhD in electrical engineering from the University of Toronto. He's a member of IEEE."]}} %*Medical Ultrasound Imaging: To GPU or Not to GPU? %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5959145 %f/micro/blqndcv38cehjikmhzydvynwo72xxpti.pdf %mbc642a5e356a6dca5df21cf2264d1852 %cmicro %@[{'name': 'Jeremy Meredith', 'affiliation': 'Oak Ridge National Laboratory', 'bio': {'p': ['Jeremy S. Meredith is a computer scientist in the Future Technologies Group at Oak Ridge National Laboratory. His research interests include emerging computing architectures and large-scale visualization and analysis. Meredith has an MS in computer science from Stanford University.']}}, {'name': 'Philip Roth', 'affiliation': 'Oak Ridge National Laboratory', 'bio': {'p': ['Philip C. Roth is a founding member of the Future Technologies Group at Oak Ridge National Laboratory. His research interests include performance analysis, prediction, and tools, especially scalability, automation, and emerging architectures. Roth has a PhD in computer science from the University of Wisconsin-Madison.']}}, {'name': 'Kyle Spafford', 'affiliation': 'Oak Ridge National Laboratory', 'bio': {'p': ['Kyle L. Spafford is a computer scientist in the Future Technologies Group at Oak Ridge National Laboratory. His research interests include high-performance computing with a focus on emerging architectures. Spafford has an MS in computer science from the Georgia Institute of Technology.']}}, {'name': 'Jeffrey Vetter', 'affiliation': 'Oak Ridge National Laboratory', 'bio': {'p': ['Jeffcey S. Vetter is the founding group leader of the Future Technologies Group at Oak Ridge National Laboratory and a joint professor in the College of Computing at the Georgia Institute of Technology. His research interests include emerging computing architectures and programming environments for high-performance computing. Vetter has a PhD in computer science from the Georgia Institute of Technology.']}} %*Performance Implications of Nonuniform Device Topologies in Scalable Heterogeneous Architectures %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5989784 %f/micro/ckgtwe5uuwxpeqlro7dx6stb9vlnryfa.pdf %mbc0bdac0922ad1302ab7a23471a49478 %cmicro %@[{'name': 'Richard Mateosian', 'affiliation': 'xrm@pacbell.net'} %*Effective Communication [review of ".....Trees, Maps, and Theorems: Effective Commuincation for Rational Minds" (Doumont, J.-L.; 2009)] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6045686 %f/micro/7izbjqnfmghkxp6laxdvy8ifqtducjre.pdf %m790263bbbca8fee8dc8ba89af3da5664 %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'greenstein@kellogg.northwestern.edu', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6045679/6045687/6045687-photo-1-small.gif', 'p': ['SHANE GREENSTEIN greenstein@kellogg.northwestern.edu']}} %*The Wi-Fi Journey %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6045687 %f/micro/msxbdhntkpklqmyxrg6d5ofj1i3hbsg2.pdf %m465d76d66387c177232045f0e4d22691 %cmicro %@[{'name': 'Erik R. Altman', 'affiliation': 'ealtman@us.ibm.com', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6097180/6097184/6097184-photo-1-small.gif', 'p': ['ERIK R. ALTMAN IEEE Micro']}} %*New Blood, Cool Chips, and Heterogeneous Designs %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6097184 %f/micro/amodtjaegihlknyuhsbz78lcqr95xm13.pdf %m0d04fce7f0c2ae6cab9ddc2dcfd7ca86 %cmicro %@[{'name': 'Makoto Ikeda', 'affiliation': 'University of Tokyo', 'bio': {'p': ["Makoto Ikeda is an associate professor in the VLSI Design and Education Center at the University of Tokyo. His research interests include high-performance, low-power, and reliable digital circuit and smart image sensor design. Ikeda has a PhD in electrical engineering from the University of Tokyo. He's a program committee co-chair of the Cool Chips conference series and a program committee member of the International Solid-State Circuits Conference, VLSI Circuits Symposium, Asian Solid-State Circuits Conference, International Symposium on Quality Electronic Design, and International Conference on Field Programmable Technology."]}}, {'name': 'Fumio Arakawa', 'affiliation': 'Renesas Electronics', 'bio': {'p': ["Fumio Arakawa is a chief professional in the System Core Development Division of Renesas Electronics. His research interests include architecture and microarchitecture of low-power and high-performance microprocessors. Arakawa has a PhD in electrical engineering from the University of Tokyo. He's a program committee co-chair of the Cool Chips conference series, a program committee member of the VLSI Circuits Symposium and Asian Solid-State Circuits Conference, and the chairman of Microprocessor Technical Committee and Multi-/Many-core Application Research Committee of Japan Electronics and Information T ech-nology Industries Association. He's a member of IEEE and the Institute of Electronics, Information, and Communication Engineers."]}} %*Cool Chips %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6097185 %f/micro/ihvdgnstye1kb2gh3jlrzfmqmuuaqwcr.pdf %m0db28f3e474e2e54c9de1d492a40d2ad %cmicro %@[{'name': 'Nobuaki Ozaki', 'affiliation': 'Keio University', 'bio': {'p': ["Nobuaki Ozaki is a master's student of computer science at Keio University. His research interests include low-power architectures. Ozaki has a BS in science and engineering from Keio University."]}}, {'name': 'Yoshihiro Yasuda', 'affiliation': 'Keio University', 'bio': {'p': ['Yoshihiro Yasuda works for the Tochigi prefectural office. His research interests include low-power architectures. Yasuda has an MS in computer science from Keio University.']}}, {'name': 'Mai Izawa', 'affiliation': 'Keio University', 'bio': {'p': ['Yoshiki Saito works for Toshiba. His research interests include reconfigurable architectures. Saito has an MS in computer science from Keio University.']}}, {'name': 'Yoshiki Saito', 'affiliation': 'Keio University', 'bio': {'p': ['Daisuke Ikebuchi works for Renesas Electronics. His research interests include energy-aware computing. Ikebuchi has an MS in computer science from Keio University.']}}, {'name': 'Daisuke Ikebuchi', 'affiliation': 'Keio University', 'bio': {'p': ['Masayuki Kimura works for Renesas Electronics. His research interests include reconfigurable computing. Kimura has an MS in computer science from Keio University.']}}, {'name': 'Hideharu Amano', 'affiliation': 'Keio University', 'bio': {'p': ["Hideharu Amano is a professor in the Department of Information and Computer Science at Keio University. His research interests include parallel architectures and reconfigurable computing. Amano has a PhD in electric engineering from Keio University. He's a member of IEEE, the Institute of Electronics, Information, and Communication Engineers (IEICE), and the Information Processing Society of Japan (IPSJ)."]}}, {'name': 'Hiroshi Nakamura', 'affiliation': 'University of Tokyo', 'bio': {'p': ["Hiroshi Nakamura is a professor in the Department of Information Physics and Computing at the University of Tokyo. His research interests include low-power VLSI design, power-aware computing, high-performance computer systems, and dependable computing. Nakamura has a PhD in electrical engineering from the University of Tokyo. He's a member of IEEE, the ACM, and IPSJ."]}}, {'name': 'Kimiyoshi Usami', 'affiliation': 'Shibaura Institute of Technology', 'bio': {'p': ["Kimiyoshi Usami is a professor in the Department of Information Science and Engineering at the Shibaura Institute of Technology. His research interests include energy-aware computing and ultralow-power voltage design. Usami has a PhD in electric engineering from Waseda University. He's a member of IEEE, the ACM, and IEICE."]}}, {'name': 'Mitaro Namiki', 'affiliation': 'Tokyo University of Agriculture and Technology', 'bio': {'p': ["Mitaro Namiki is a professor in the Faculty of Engineering at the Tokyo University of Agriculture and Technology. His research interests include operating systems, programming languages, parallel processing, and computer networks. Namiki has a PhD in computer science from the Tokyo University of Agriculture and Technology. He's a member of the ACM, IEICE, and IPSJ."]}}, {'name': 'Masaaki Kondo', 'affiliation': 'University of Electro-Communications', 'bio': {'p': ["Masaaki Kondo is an associate professor in the Graduate School of Information Systems at the University of Electro-Communications in Tokyo. His research interests include computer architectures, high-performance computing, and dependable computing. Kondo has a PhD in electrical engineering from the University of Tokyo. He's a member of IEEE, the ACM, IEICE, and IPSJ.", 'Direct questions and comments about this article to Nobuaki Ozaki, Faculty of Science and Technology, Keio University, 3–14-1, Hiyoshi, Kohokuku, Yokohama, 223–8522, Japan, ozaki@am.ics.keio.ac.jp.']}} %*Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6060791 %f/micro/6yhqxodtog703bki1fjmbluvxz4dp9vy.pdf %m082c6b0b186dc0a132f877053303e0e6 %cmicro %@[{'name': 'Tomoya Suzuki', 'affiliation': 'Toshiba', 'bio': {'p': ['Tomoya Suzuki is an engineer in the Center for Semiconductor Research & Development at Toshiba. He has an ME in information systems from the Nara Institute of Science and Technology.']}}, {'name': 'Hideki Yamada', 'affiliation': 'Toshiba', 'bio': {'p': ['Hideki Yamada is an engineer in the Center for Semiconductor Research & Development at Toshiba. He has an ME in information and computer sciences from Nagasaki University.']}}, {'name': 'Toshiyuki Yamagishi', 'affiliation': 'Toshiba', 'bio': {'p': ['Toshiyuki Yamagishi is an engineer in the Center for Semiconductor Research & Development at Toshiba. He has an MSc in semiconductor solid-state physics from the University of Tokyo.']}}, {'name': 'Daisuke Takeda', 'affiliation': 'Toshiba', 'bio': {'p': ["Daisuke Takeda is a specialist at Toshiba, where he studies wireless communication. He is also working as Toshiba's representative in the Japan-US New Mexico Project for smart grid. Takeda has a PhD in wireless communication from Keio University."]}}, {'name': 'Koji Horisaki', 'affiliation': 'Toshiba', 'bio': {'p': ['Koji Horisaki is a specialist in the Center for Semiconductor Research & Development at Toshiba. He has an ME in electrical engineering from Keio University.']}}, {'name': 'Tom Vander Aa', 'affiliation': 'Toshiba', 'bio': {'p': ['Toshio Fujisawa is a senior specialist in the Center for Semiconductor Research & Development at Toshiba. He has an MS in electronic engineering from the Tokyo Institute of Technology.']}}, {'name': 'Toshio Fujisawa', 'affiliation': 'Toshiba', 'bio': {'p': ['Yasuo Unekawa is a senior manager of the Wireless & Analog Design Department in the Center for Semiconductor Research & Development at Toshiba. He has a PhD in electronic engineering from the University of Tokyo.']}}, {'name': 'Liesbet Perre', 'affiliation': 'IMEC', 'bio': {'p': ['Tom Vander Aa is a senior researcher in the Wireless Communication group at IMEC. He has a PhD in electrical engineering from the Katholieke Universiteit Leuven.']}}, {'name': 'Yasuo Unekawa', 'affiliation': 'IMEC', 'bio': {'p': ["Liesbet Van der Perre is the program director for the green radio program at IMEC. She's also a professor at the Katholieke Universiteit Leuven. Van der Perre has a PhD in electrical engineering from the Katholieke Universiteit Leuven."]}} %*High-Throughput, Low-Power Software-Defined Radio Using Reconfigurable Processors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6060793 %f/micro/ohl73egdmnkotb1smxcrwpbdfkx92jau.pdf %m019eb226dad38436a4cd7aa405108267 %cmicro %@[{'name': 'Craig Court', 'affiliation': 'Imperial College London', 'bio': {'p': ['Craig A. Court is a PhD student in the Department of Computing at Imperial College London. His research interests include computer architecture, low-power system design, and custom computing using field-programmable gate array technology. Court has an MEng in computer science from the University of Bristol.']}}, {'name': 'Paul Kelly', 'affiliation': 'Imperial College London', 'bio': {'p': ['Paul H.J. Kelly is a professor of software technology in the Department of Computing at Imperial College London, where he heads the Software Performance Optimization Research Group. His research interests include compilers, architectures, domain-specific languages, and end-to-end application optimization, particularly in computational-science applications. Kelly has a PhD in computer science from the University of London.', 'Direct questions and comments about this article to Craig A. Court, Department of Computing, Imperial College London, London, United Kingdom, SW7 2AZ, ccourtt@ic.ac.uk.']}} %*Loop-Directed Mothballing: Power Gating Execution Units Using Runtime Loop Analysis %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6051412 %f/micro/zg4t2dja71ucf05yquprxl3ysocteikn.pdf %m5933216dca3eaf6c16a15fc499a45874 %cmicro %@[{'name': 'Sugako Otani', 'affiliation': 'Renesas Electronics', 'bio': {'p': ['Sugako Otani is a processor architect of M32R and RX and a manager of technical development in the CPU Development Department at Renesas Electronics. Her research interests include networking and microprocessor architectures. Otani has an MS in physics from Waseda University.']}}, {'name': 'Hiroyuki Kondo', 'affiliation': 'Renesas Electronics', 'bio': {'p': ["Hiroyuki Kondo is the director of the CPU Development Department at Renesas Electronics, where he's the chief processor architect of M32R and RX. His research interests include microprocessor architectures and operating systems. Kondo has a BS in physics from Kyoto University."]}}, {'name': 'Itaru Nonomura', 'affiliation': 'Renesas Electronics', 'bio': {'p': ["Itaru Nonomura is a staff engineer at Renesas Electronics, where he's an interconnect designer. His research interests include on-chip and off-chip interconnects. Nonomura has a BS in electrical engineering from Waseda University."]}}, {'name': 'Toshihiro Hanawa', 'affiliation': 'University of Tsukuba', 'bio': {'p': ['Toshihiro Hanawa is an associate professor on the Faculty of Engineering, Information, and Systems at the University of Tsukuba, where he is also a faculty fellow in the Center for Computational Sciences. His research interests include high-performance computing systems. Hanawa has a PhD in engineering from Keio University.']}}, {'name': "Shin'ichi Miura", 'affiliation': 'University of Tsukuba', 'bio': {'p': ["Shin'ichi Miura is a researcher in the Center for Computational Sciences at the University of Tsukuba. His research interests include system software and interconnects for highperformance computing. Miura has a PhD in engineering from the University of Tsukuba."]}}, {'name': 'Taisuke Boku', 'affiliation': 'University of Tsukuba', 'bio': {'p': ['Taisuke Boku is a professor on the Faculty of Engineering, Information, and Systems at the University of Tsukuba, where he is also the deputy director of the Center for Computational Sciences. His research interests include high-performance architecture, large-scale system software, and low-power and high-performance communication. Boku has a PhD in engineering from Keio University.', 'Direct questions and comments about this article to Sugako Otani, System Core Development Division, Renesas Electronics, 4–1 Mizuhara Itami Hyogo, 664–0005, Japan, sugako.otani.uj@renesas.com.']}} %*Peach: A Multicore Communication System on Chip with PCI Express %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6060792 %f/micro/kpcyct6fa3mlq8zopu0oleid4q2gsfun.pdf %m90d1ce154d9865a8ff84b2cf260164eb %cmicro %@[{'name': 'Hiroshi Shimamoto', 'affiliation': 'NHK', 'bio': {'p': ["Hiroshi Shimamoto is a senior research engineer at NHK, the Japan Broadcasting Corporation. His research interests include ultra-high-definition TV camera systems and image sensors. Shimamoto has a PhD in information processing from the Tokyo Institute of Technology, Japan. He's a member of IEEE."]}}, {'name': 'Takayuki Yamashita', 'affiliation': 'NHK', 'bio': {'p': ['Takayuki Yamashita is a senior research engineer at NHK. His research interests include ultra-high-definition TV camera systems. Yamashita has an MS in electronics and information science from the Kyoto Institute of Technology.']}}, {'name': 'Misao Kubota', 'affiliation': 'NHK', 'bio': {'p': ['Misao Kubota is a senior research engineer at NHK. His research interests include high-sensitivity photoconductive targets. Kubota has a BS in electronic engineering from the University of Tokyo.']}}, {'name': 'Hirotaka Maruyama', 'affiliation': 'NHK', 'bio': {'p': ['Hirotaka Maruyama is a chief engineer at NHK. His research interests include solid-state imaging devices and ultra-high-speed charge-coupled device cameras. Maruyama has an MS in electronic engineering from the University of Electro-Communications.', 'Direct questions and comments about this article to Hiroshi Shimamoto, NHK (Japan Broadcasting Corporation), Science and Technology Research Laboratories, 1–10-11, Kinuta, Setagaya-ku, Tokyo 157–8510, Japan, shimamoto.h-iu@nhk.or.jp.']}} %*Advanced Camera Technologies for Broadcasting %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5959148 %f/micro/g94aymfblyvc0jesd8huw6zatkh5iogf.pdf %m5862f2f8c49d0c51e6ced0df33315349 %cmicro %@[{'name': 'Greg Stitt', 'affiliation': 'University of Florida', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6097180/6097186/6097186-photo-1-small.gif', 'p': ['Greg Stitt is an assistant professor in the Electrical and Computer Engineering Department at the University of Florida. His research interests include reconfigurable computing, design automation, and embedded systems. Stitt has a PhD in computer science from the University of California, Riverside.', 'Direct questions or comments about this column to Greg Stitt, gstitt@ece.ufl.edu.']}} %*Are Field-Programmable Gate Arrays Ready for the Mainstream? %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6097186 %f/micro/uxn3ztyopllzcwf8iihm9rgeqbvjgu5v.pdf %m3de75cd80dbdf055f35e02069dd1e2fe %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'greenstein@kellogg.northwestern.edu', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/6097180/6097187/6097187-photo-1-small.gif', 'p': ['SHANE GREENSTEIN greenstein@kellogg.northwestern.edu']}} %*Steve Jobs and the Economics of One Entrepreneur %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6097187 %f/micro/qsumu4bvrhjqgcx39w8fbyik6zmxno2i.pdf %mcda64fbf2d25d2ffe3298b203faea508 %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'greenstein@kellogg.northwestern.edu', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/5430728/5430733/5430733-photo-1-small.gif', 'p': []}} %*The Next Chapter at Google [Micro Economics] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5430733 %f/micro/wjot5eup1u3alar6pmzyymecw0tffncs.pdf %ma27748bcbdc3f6aaeba8104c8bc52715 %cmicro %@[{'name': 'Trevor Mudge', 'affiliation': 'University of Michigan', 'bio': {'p': ['Trevor Mudge is the first Bredt Family Professor of Electrical Engineering and Computer Science at the University of Michigan, Ann Arbor. His research interests include computer architecture, CAD, and compilers. Mudge has a PhD in computer science from the University of Illinois, Urbana-Champaign. He is a member of the ACM, Institution of Engineering and Technology, and British Computer Society, and is a Fellow of the IEEE.']}} %*Guest Editor's Introduction: Top Picks from the Computer Architecture Conferences of 2009 %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5430734 %f/micro/ig0fwzmnzx24rbuaec61oghtherq9j8d.pdf %m7d13b329e8d7ce26ebe6b6f252972e00 %cmicro %@[{'name': 'Andrew Hilton', 'affiliation': 'University of Pennsylvania', 'bio': {'p': ['Andrew Hilton is a PhD candidate in the Department of Computer and Information Science at the University of Pennsylvania. His research interests include computer architecture, microprocessor design, energy-efficient processing, and the interaction of hardware and system software. Hilton has an MS in computer science from the Georgia Institute of Technology. He is a member of the IEEE and ACM.']}}, {'name': 'Santosh Nagarakatte', 'affiliation': 'University of Pennsylvania', 'bio': {'p': ['Santosh Nagarakatte is a PhD candidate in the Department of Computer and Information Science at the University of Pennsylvania. His research interests include computer architecture, hardware, and software support for security and concurrency. Nagarakatte has an MS in computer science from the Indian Institute of Science. He is a member of the IEEE and ACM.']}}, {'name': 'Amir Roth', 'affiliation': 'University of Pennsylvania', 'bio': {'p': ['Amir Roth is an associate professor in the Department of Computer and Information Science at the University of Pennsylvania. His research interests include computer architecture, microprocessor design, performance evaluation, and energy-efficient processing. Roth has a PhD in computer science from the University of Wisconsin-Madison. He is a member of the IEEE and ACM.', 'Direct questions and comments to Amir Roth, Dept. of Computer and Information Science, Univ. of Pennsylvania, 3330 Walnut St., Philadelphia, PA 19104–6389, amir@cis.upenn.edu.']}} %*iCFP: Tolerating All-Level Cache Misses in In-Order Processors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5430735 %f/micro/ux2lod5bwppbjk7jrm8uyiaeftax0le1.pdf %m06625a6c8ab8673bf17135b4cbdf2c45 %cmicro %@[{'name': 'Nikos Hardavellas', 'affiliation': 'Northwestern University', 'bio': {'p': ['Nikos Hardavellas is the June and Donald Brewer Assistant Professor of Electrical Engineering and Computer Science at Northwestern University. His research targets architectures, memory system design, and runtime environments for parallel systems. Hardavellas has a PhD in computer science from Carnegie Mellon University. He is a member of the ACM and the IEEE.']}}, {'name': 'Michael Ferdman', 'affiliation': 'Carnegie Mellon University', 'bio': {'p': ['Michael Ferdman is a PhD candidate in electrical and computer engineering at Carnegie Mellon University. His research interests include computer architecture, with an emphasis on proactive memory system design. Ferdman has an MS in electrical and computer engineering from Carnegie Mellon University. He is a student member of the ACM and the IEEE.']}}, {'name': 'Babak Falsafi', 'affiliation': 'É,cole Polytechnique Fé,dé,rale de Lausanne', 'bio': {'p': ['Babak Falsafi is a professor of computer and communication sciences at Ecole Polytechnique Fédérale de Lausanne, where he directs the Parallel Systems Architecture Lab. His research targets architectural support for parallel programming, resilient systems, memory systems, and computer system performance modeling and evaluation. Falsafi has a PhD in computer science from the University of Wisconsin-Madison. He is a senior member of the ACM and the IEEE.']}}, {'name': 'Anastasia Ailamaki', 'affiliation': 'É,cole Polytechnique Fé,dé,rale de Lausanne', 'bio': {'p': ['Anastasia Ailamaki is a professor of computer science at the Ecole Polytechnique Fédérale de Lausanne. Her research interests include optimizing database workloads for modern hardware and disks and managing large data sets for scientific applications. Ailamaki has a PhD in computer science from the University of Wisconsin-Madison.']}} %*Near-Optimal Cache Block Placement with Reactive Nonuniform Cache Architectures %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5430736 %f/micro/m6vwuwngefga9xbk1tirqce8ylfj57dq.pdf %m820aec9e3a048c408f512235c96fb0d9 %cmicro %@[{'name': 'John H. Kelm', 'affiliation': 'University of Illinois at Urbana-Champaign', 'bio': {'p': ['John H. Kelm is a PhD candidate at the University of Illinois at Urbana-Champaign. His research interests include parallel archi-tectures, memory system design, and cache coherence protocols. Kelm has an MS in computer engineering from the University of Illinois. He is a member of the ACM and IEEE.']}}, {'name': 'Daniel R. Johnson', 'affiliation': 'University of Illinois at Urbana-Champaign', 'bio': {'p': ['Daniel R. Johnson is a PhD candidate at the University of Illinois at Urbana-Champaign. His research interests include parallel accelerators and domain-specific architectures. Johnson has a BS in electrical engineering from the University of Texas at Austin. He is a member of the ACM and IEEE.']}}, {'name': 'Steven S. Lumetta', 'affiliation': 'University of Illinois at Urbana-Champaign', 'bio': {'p': ['Matthew I. Frank is a software engineer in the Performance, Analysis, and Threading Lab at Intel. His technical interests include programming tools for parallel programming. Frank has a PhD in computer science from the Massachusetts Institute of Technology.']}}, {'name': 'Sanjay J. Patel', 'affiliation': 'University of Illinois at Urbana-Champaign', 'bio': {'p': ['Steven S. Lurnetta is an associate professor of Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign. His interests include high-performance networking and computing, hierarchical systems, and parallel runtime software. Lumetta has a PhD in computer science from the University of California, Berkeley. He is a member of the ACM and IEEE.']}}, {'name': 'Matthew I. Frank', 'affiliation': 'Intel', 'bio': {'p': ['Sanjay J. Patel is an associate professor of Electrical and Computer Engineering and Sony Faculty Scholar at the University of Illinois at Urbana-Champaign. His interests are in high-throughput chip architectures and visual computing. Patel has a PhD in computer science and engineering from the University of Michigan, Ann Arbor. He is a member of the IEEE.']}} %*A Task-Centric Memory Model for Scalable Accelerator Architectures %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5430737 %f/micro/u6cavfpynz5zmlgq3qbsrcwnehbxdhjj.pdf %m5011d538936d64b8b281626056bb0a7b %cmicro %@[{'name': 'Joseph Devietti', 'affiliation': 'University of Washington', 'bio': {'p': ['Joseph Devietti is a PhD candidate in the Computer Science and Engineering Department at the University of Washington. His research interests include parallel-programming models and the intersection of architecture and programming languages. Devietti has an MS in computer science and engineering from the University of Washington. He is a member of the ACM.']}}, {'name': 'Brandon Lucia', 'affiliation': 'University of Washington', 'bio': {'p': ['Brandon Lucia is a PhD candidate in the Computer Science and Engineering Department at the University of Washington. His research interests include hardware support for dynamic analysis of concurrent programs, with a focus on debugging and increasing software reliability. Lucia has an MS in computer science and engineering from the University of Washington. He is a member of the ACM.']}}, {'name': 'Luis Ceze', 'affiliation': 'University of Washington', 'bio': {'p': ['Luis Ceze is an assistant professor in the Computer Science and Engineering Department at the University of Washington. His research interests include computer architecture, programming languages, and compilers and operating systems to improve programmability and reliability of multiprocessors. He is a cofounder of PetraVM, a start-up company formed around the DMP technology. Ceze has a PhD in computer science from the University of Illinois at Urbana-Champaign. He is a member of the ACM and the IEEE.']}}, {'name': 'Mark Oskin', 'affiliation': 'University of Washington', 'bio': {'p': ['Mark Oskin is an associate professor in the Computer Science and Engineering Department at the University of Washington. He is currently on leave at PetraVM, a start-up commercializing many of the ideas behind DMP. His research interests include parallel computing, communication networks, and silicon manufacturing. Oskin has a PhD in computer science from the University of California at Davis.']}} %*DMP: Deterministic Shared-Memory Multiprocessing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5430738 %f/micro/f1mdcaiwnspxjs0rbca6wktvxzql27ki.pdf %mb9527337e789393d6932f86ff4f12770 %cmicro %@[{'name': 'Thomas F. Wenisch', 'affiliation': 'University of Michigan', 'bio': {'p': ['Thomas F. Wenisch is an assistant professor of electrical engineering and computer science at the University of Michigan. His research interests include computer architecture, server and data center energy efficiency, multiprocessor systems, and performance evaluation methodology. Wenisch has a PhD in electrical and computer engineering from Carnegie Mellon University. He is a member of the IEEE and ACM.']}}, {'name': 'Michael Ferdman', 'affiliation': 'Carnegie Mellon University', 'bio': {'p': ['Michael Ferdman is a PhD candidate in electrical and computer engineering at Carnegie Mellon University, currently studying at Ecole Polytechnique Fédérale de Lausanne. His research interests include computer architecture with an emphasis on proactive memory system design. Ferdman has an MS in electrical and computer engineering from Carnegie Mellon University. He is a student member of the IEEE and ACM.']}}, {'name': 'Anastasia Ailamaki', 'affiliation': 'É,cole Polytechnique Fé,dé,rale de Lausanne', 'bio': {'p': ['Anastasia Ailamaki is a professor of computer science at École Polytechnique Federale de Lausanne. Her research interests include the broad area of database systems and applications, with emphasis on database system behavior on modern processor hardware and disks. Ailamaki has a PhD in computer science from the University of Wisconsin-Madison. She is a member of the IEEE and ACM.']}}, {'name': 'Babak Falsafi', 'affiliation': 'É,cole Polytechnique Fé,dé,rale de Lausanne', 'bio': {'p': ['Babak Falsafi is a professor of computer science at Ecole Polytechnique Fédérale de Lausanne, where he directs the Parallel Systems Architecture Lab. His research interests include architectural support for parallel programming, resilient systems, architectures to break the memory wall, and computer system performance evaluation. Falsafi has a PhD in computer science from the University of Wisconsin. He is a senior member of the IEEE and the ACM.']}}, {'name': 'Andreas Moshovos', 'affiliation': 'University of Toronto', 'bio': {'p': ['Andreas Moshovos is an associate professor of electrical and computer engineering at the University of Toronto. His research interests include microarchitectural optimizations for high-performance processors and systems. Moshovos has a PhD in computer science from the University of Wisconsin-Madison. He is a member of IEEE and the ACM.']}} %*Making Address-Correlated Prefetching Practical %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5430739 %f/micro/n8f1fjru6gdhgtanietxzbepkhu3q4wz.pdf %m9992919bf0228ad5a5c681b9d9c195c6 %cmicro %@[{'name': 'M. Aater Suleman', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ["M. Aater Suleman is a PhD candidate of electrical and computer engineering at the University of Texas at Austin. His research interests include chip multiprocessor architectures and parallel programming. Suleman has a master's degree in electrical and computer engineering from the University of Texas at Austin. He is a member of the IEEE, ACM, and HKN."]}}, {'name': 'Onur Mutlu', 'affiliation': 'Carnegie Mellon University', 'bio': {'p': ['Onur Mutlu is an assistant professor of electrical and computer engineering at Carnegie Mellon University. His research interests include computer architecture and systems. Mutlu has a PhD in electrical and computer engineering from the University of Texas at Austin. He is a member of the IEEE and ACM.']}}, {'name': 'Moinuddin K. Qureshi', 'affiliation': 'IBM Research', 'bio': {'p': ['Moinuddin Qureshi is a research staff member at IBM Research. His research interest includes computer architecture, scalable memory system design, resilient computing, and analytical modeling of computer systems. Qureshi has a PhD in electrical and computer engineering from the University of Texas at Austin. He is a member of the IEEE.']}}, {'name': 'Yale N. Patt', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ['Yale N. Patt is the Ernest Cockrell, Jr., Centennial Chair in Engineering at the University of Texas at Austin. His research interests include harnessing the expected fruits of future process technology into more effective microarchitectures for future micro-processors. Patt has a PhD in electrical engineering from Stanford University. He is a Fellow of both the IEEE and ACM.']}} %*Accelerating Critical Section Execution with Asymmetric Multicore Architectures %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5430740 %f/micro/ykfzrsqfktbd9wer7jcpi50p6obnm1m8.pdf %m1c363a9ea546a4d2816aeaaf2f851ddd %cmicro %@[{'name': 'Stijn Eyerman', 'affiliation': 'Ghent University', 'bio': {'p': ['Stijn Eyerman is a postdoctoral researcher in the Electronics and Information Systems Department at Ghent University, Belgium. He is supported through a postdoctoral fellowship by the Research Foundation, Flanders (FWO). His research interests include computer architecture, in particular performance analysis and modeling. Eyerman has a PhD in computer science and engineering from Ghent University.']}}, {'name': 'Lieven Eeckhout', 'affiliation': 'Ghent University', 'bio': {'p': ['Lieven Eeckhout is an associate professor in the Electronics and Information Systems Department at Ghent University, Belgium. His research interests include computer architecture, with a focus on performance analysis, evaluation and modeling, and workload characterization. Eeckhout has a PhD in computer science and engineering from Ghent University. He is a member of the IEEE and ACM.']}} %*Per-Thread Cycle Accounting %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5430741 %f/micro/3w1idtpjltb5ymkfgev8wv9uugmz4xep.pdf %mc457b5bfd9f5dfb88b6eb8034f0ca9af %cmicro %@[{'name': 'Mark Woh', 'affiliation': 'University of Michigan, Ann Arbor', 'bio': {'p': ['Mark Woh is a PhD candidate in electrical engineering at the University of Michigan, Ann Arbor. His research interests include low-power microarchitecture, wireless communications, and signal processing language and compiler design. Woh has a BS in electrical engineering and computer engineering from the University of Michigan, Ann Arbor.']}}, {'name': 'Sangwon Seo', 'affiliation': 'University of Michigan, Ann Arbor', 'bio': {'p': ['Sangwon Seo is a PhD candidate in electrical engineering and computer science at the University of Michigan, Ann Arbor. His research interests include low-power microarchitecture and wireless signal processing. Seo has a BS in electrical engineering from Seoul National University.']}}, {'name': 'Scott Mahlke', 'affiliation': 'University of Michigan, Ann Arbor', 'bio': {'p': ['Scott Mahlke is an associate professor in the Electrical Engineering and Computer Science Department at the University of Michigan, Ann Arbor, where he leads the Compilers Creating Custom Processors group. His research interests include compilers for multicore processors, application-specific processors for mobile computing, and reliable system design. Mahlke has a PhD in electrical engineering from the University of Illinois, Urbana-Champaign.']}}, {'name': 'Trevor Mudge', 'affiliation': 'University of Michigan, Ann Arbor', 'bio': {'p': ['Trevor Mudge is the first Bredt Family Professor of Electrical Engineering and Computer Science at the University of Michigan, Ann Arbor. His research interests include computer architecture, CAD, and compilers. Mudge has a PhD in computer science from the University of Illinois, Urbana-Champaign. He is a member of the ACM, Institution of Engineering and Technology, and British Computer Society, and is a Fellow of the IEEE.']}}, {'name': 'Chaitali Chakrabarti', 'affiliation': 'Arizona State University', 'bio': {'p': ['Chaitali Chakrabarti is a professor of electrical engineering at Arizona State University. Her research interests are in the areas of VLSI architectures and algorithms for signal processing and communications, and low-power system design. Chakrabarti has a PhD in electrical engineering from the University of Maryland, College Park.']}}, {'name': 'Krisztian Flautner', 'affiliation': 'ARM, Ltd.', 'bio': {'p': ['Kriszti án Flautner is vice president of research and development at ARM, Ltd. His research interests include high-performance, low-energy processing platforms that support advanced software environments. Flautner has a PhD in electrical engineering and computer science from the University of Michigan, Ann Arbor. He is a member of the ACM and IEEE.']}} %*AnySP: Anytime Anywhere Anyway Signal Processing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5430742 %f/micro/y72adb0deoz93s8h41whum5vnf6cqbvk.pdf %m2281ff347e69ca389aed738e9bbf1248 %cmicro %@[{'name': 'Mohit Tiwari', 'affiliation': 'University of California, Santa Barbara', 'bio': {'p': ['Mohit Tiwari is pursuing a PhD in the Department of Computer Science at the University of California, Santa Barbara. His research interests include computer architecture and program analysis, especially for security and debugging. He has a BTech in computer science from the Indian Institute of Technology, Guwahati.']}}, {'name': 'Xun Li', 'affiliation': 'University of California, Santa Barbara', 'bio': {'p': ['Xun Li is pursuing a PhD in the Department of Computer Science at the University of California, Santa Barbara. His research interests include computer architecture, computer security, and compilers. He has a BSc in software engineering, jointly from Fudan University (China) and University College Dublin.']}}, {'name': 'Hassan M.G. Wassel', 'affiliation': 'University of California, Santa Barbara', 'bio': {'p': ['Hassan M.G. Wassel is pursuing a PhD in the Department of Computer Science at the University of California, Santa Barbara. His research focuses on computer architecture and its interaction with software and novel hardware technologies. He has an MSc in computer science and automatic control from Alexandria University in Egypt. He is a student member of the IEEE.']}}, {'name': 'Bita Mazloom', 'affiliation': 'University of California, Santa Barbara', 'bio': {'p': ['Bita Mazloom is pursuing a PhD in computer science from the University of California, Santa Barbara. Her research interests include dataflow analysis, information-flow modeling, reverse engineering of software, visualization of systems, and pedagogical techniques in computer science. She has a BS in computer science from the University of California, Santa Barbara.']}}, {'name': 'Shashidhar Mysore', 'affiliation': 'University of California, Santa Barbara', 'bio': {'p': ['Shashidhar Mysore is a product specialist at Eucalyptus Systems. He completed the work described in this article while pursuing his PhD at the University of California, Santa Barbara. His technical interests include developing technological expertise and strategies for innovation based on cutting-edge research and extensive market analysis in cloud computing, and understanding complex computer systems. He has a PhD in computer science from the University of California, Santa Barbara. He is a member of the IEEE.']}}, {'name': 'Frederic T. Chong', 'affiliation': 'University of California, Santa Barbara', 'bio': {'p': ['Frederic T. Chong is the director of computer engineering and a professor of computer science at the University of California, Santa Barbara. He also directs the Greenscale Center for Energy-Efficient Computing. His research interests include emerging technologies for computing, multicore and embedded architectures, computer security, and sustainable computing. He has a PhD in electrical engineering and computer science from the Massachusetts Institute of Technology.']}}, {'name': 'Timothy Sherwood', 'affiliation': 'University of California, Santa Barbara', 'bio': {'p': ['Timothy Sherwood is an associate professor of computer science and electrical engineering at the University of California, Santa Barbara. His research interests include software profiling and debugging peripherals, novel uses of 3D integration, whiteboard-based sketch computing, MEMS (microelectromechanical systems) control architectures, and secure hardware-software systems. He has a PhD in computer science and engineering from the University of California, San Diego.']}} %*Gate-Level Information-Flow Tracking for Secure Architectures %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5430743 %f/micro/67m8ac1ym3p4kdjnxexrthwtypfeuisl.pdf %mcbd6bbee191481e220f5cd030e8b3ab5 %cmicro %@[{'name': 'Vijay Janapa Reddi', 'affiliation': 'Harvard University', 'bio': {'p': ['Vijay Janapa Reddi is a PhD candidate in the computer science department at Harvard University. His research interests are in the area of computer systems. He is specifically interested in applying his background in virtual machines, runtime compiler systems, and architecture to address processor power and reliability challenges via hardware-software codesign. Janapa Reddi has an MS in computer engineering from the University of Colorado, Boulder.']}}, {'name': 'Meeta Gupta', 'affiliation': 'Harvard University', 'bio': {'p': ['Meeta S. Gupta is a research staff member in the reliability and power-aware microarchi-tecture group at IBM TJ Watson, Yorktown Heights. Her interests include power-aware, reliable microarchitecture design, and highperformance computing. Gupta has a PhD in electrical engineering from Harvard University.']}}, {'name': 'Glenn Holloway', 'affiliation': 'Harvard University', 'bio': {'p': ['Glenn Holloway is a staff member in the Electrical and Computer Science Department at Harvard University. His technical interests are code optimization, computer architecture, and circuit design. Holloway has an MS in physics from Harvard University.']}}, {'name': 'Michael D. Smith', 'affiliation': 'Harvard University', 'bio': {'p': ['Michael D. Smith is a John H. Finley, Jr., Professor of Engineering and Applied Sciences and the Dean of the Faculty of Arts and Sciences at Harvard University. His research interests include dynamic optimization, machine-specific and profile-driven compilation, high-performance computer architecture, and practical applications of security. Smith has a PhD in electrical engineering from Stanford University.']}}, {'name': 'Gu-Yeon Wei', 'affiliation': 'Harvard University', 'bio': {'p': ['Gu-Yeon Wei is a Gordon McKay Professor of Electrical Engineering in the School of Engineering and Applied Sciences at Harvard University. His research interests span several areas: high-speed, low-power link design, mixed-signal circuits for communications, power regulation circuitry and management, codesign of circuits and architecture for highperformance and embedded processors to address process-voltage-temperature variability and power consumption that plague nanoscale CMOS technologies, and developing an electronic brain and nervous system for the Harvard RoboBees project. Wei has a PhD in electrical engineering from Stanford University.']}}, {'name': 'David Brooks', 'affiliation': 'Harvard University', 'bio': {'p': ['David Brooks is a professor of computer science at Harvard University. His research interests include architectural and software approaches to address power, thermal, and reliability issues for embedded and highperformance computing systems. Brooks has a PhD in electrical engineering from Princeton University.']}} %*Predicting Voltage Droops Using Recurring Program and Microarchitectural Event Activity %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5430744 %f/micro/ezicj52ggw14blh8ojysfr69kmpwdc7a.pdf %m5fccfe1371d50a54632befd3dffa7442 %cmicro %@[{'name': 'Constantin Pistol', 'affiliation': 'Duke University', 'bio': {'p': ['Constantin Pistol is working with industry. His research interests include computer architecture and molecular-scale computation. Pistol has a PhD in computer science from Duke University.']}}, {'name': 'Wutichai Chongchitmate', 'affiliation': 'Duke University', 'bio': {'p': ['Wutichai Chongchitmate is working on a BS degree in computer science and mathematics at Duke University.']}}, {'name': 'Christopher Dwyer', 'affiliation': 'Duke University', 'bio': {'p': ['Christopher Dwyer is an assistant professor of computer science and of electrical and computer engineering at Duke University. His research interests include self-assembly, DNA, and the development of circuit technologies for molecular-scale fabrication processes. Dwyer has a PhD in computer science from the University of North Carolina at Chapel Hill. He is a senior member of the IEEE and a member of the ACM.']}}, {'name': 'Alvin R. Lebeck', 'affiliation': 'Duke University', 'bio': {'p': ['Alvin R. Lebeck is a professor of computer science and of electrical and computer engineering at Duke University. His interests include architectures for emerging nanotechnologies, multicore processors, memory systems, and energy-efficient computing. Lebeck has a PhD in computer science from the University of Wisconsin―Madison. He is a senior member of the IEEE and a member of the ACM.']}} %*Architectural Implications of Nanoscale-Integrated Sensing and Computing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5430745 %f/micro/vedhdp3nkvgz72li5ocqboi6uwbafq80.pdf %m2a158121b821c3306096da280b82c81b %cmicro %@[{'name': 'Adrian M. Caulfield', 'affiliation': 'University of California, San Diego', 'bio': {'p': ["Adrian M. Caulfield is a doctoral student in computer engineering at the Nonvolatile Systems Laboratory at the University of California, San Diego. He's interested in all aspects of computer architecture, but focuses mainly on the integration of nonvolatile memory technologies into system architectures to enhance the performance and energy efficiency of computer systems. Caulfield received a BS in computer science from the University of Washington."]}}, {'name': 'Laura M. Grupp', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Laura M. Grupp is a third-year doctoral student in the department of Computer Science and Engineering at the University of California, San Diego. Her current research focuses on the intricacies of flash translation layers, the development of models for new types of nonvolatile memory, and the characterization of flash memory. Grupp received a BS in electrical engineering from the University of Washington.']}}, {'name': 'Steven Swanson', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Steven Swanson is an assistant professor in the Computer Science and Engineering Department at the University of California, San Diego, and leads the Nonvolatile Systems Laboratory. His research interests include architectural, systems, and security issues surrounding nonvolatile, solid-state memories as well as massively heterogeneous multiprocessor architectures. Swanson has a PhD in computer science from the University of Washington. He is a member of the ACM.']}} %*Gordon: An Improved Architecture for Data-Intensive Applications %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5430746 %f/micro/jn6s4tegpxmzj3ar0it5koc1mavlqubn.pdf %m8bf94a7c8f6f341587b57118de57efe5 %cmicro %@[{'name': 'Benjamin C. Lee', 'affiliation': 'Stanford University', 'bio': {'p': ['Benjamin C. Lee is a Computing Innovation Fellow in electrical engineering and a member of the VLSI Research Group at Stanford University. His research focuses on scalable technologies, power-efficient computer architectures, and high-performance applications. Lee has a PhD in computer science from Harvard University.']}}, {'name': 'Ping Zhou', 'affiliation': 'University of Pittsburgh', 'bio': {'p': ['Ping Zhou is pursuing his PhD in electrical and computer engineering at the University of Pittsburgh. His research interests include new memory technologies, 3D architecture, and chip multiprocessors. Zhou has an MS in computer science from Shanghai Jiao Tong University in China.']}}, {'name': 'Jun Yang', 'affiliation': 'University of Pittsburgh', 'bio': {'p': ['Jun Yang is an associate professor in the Electrical and Computer Engineering Department at the University of Pittsburgh. Her research interests include computer architecture, microarchitecture, energy efficiency, and memory hierarchy. Yang has a PhD in computer science from the University of Arizona.']}}, {'name': 'Youtao Zhang', 'affiliation': 'University of Pittsburgh', 'bio': {'p': ['Youtao Zhang is an assistant professor of computer science at the University of Pittsburgh. His research interests include computer architecture, compilers, and system security. Zhang has a PhD in computer science from the University of Arizona.']}}, {'name': 'Bo Zhao', 'affiliation': 'University of Pittsburgh', 'bio': {'p': ['Bo Zhao is pursuing a PhD in electrical and computer engineering at the University of Pittsburgh. His research interests include VLSI circuits and microarchitectures, memory systems, and modern processor architectures. Zhao has a BS in electrical engineering from Beihang University, Beijing.']}}, {'name': 'Engin Ipek', 'affiliation': 'University of Rochester', 'bio': {'p': ['Engin Ipek is an assistant professor of computer science and of electrical and computer engineering at the University of Rochester. His research focuses on computer architecture, especially multicore architectures, hardware-software interaction, and high-performance memory systems. Ipek has a PhD in electrical and computer engineering from Cornell University.']}}, {'name': 'Onur Mutlu', 'affiliation': 'Carnegie Mellon University', 'bio': {'p': ['Onur Mutlu is an assistant professor of electrical and computer engineering at Carnegie Mellon University. His research focuses on computer architecture and systems. Mutlu has a PhD in electrical and computer engineering from the University of Texas at Austin.']}}, {'name': 'Doug Burger', 'affiliation': 'Microsoft Research', 'bio': {'p': ['Doug Burger is a principal researcher at Microsoft Research, where he manages the Computer Architecture Group. His research focuses on computer architecture, memory systems, and mobile computing. Burger has a PhD in computer science from the University of Wisconsin, Madison. He is a Distinguished Scientist of the ACM and a Fellow of the IEEE.']}} %*Phase-Change Technology and the Future of Main Memory %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5430747 %f/micro/ddwtw7pe6sn9ujhob5uniqkgticzsao4.pdf %mdd405711fbff39f4db15536b25b46743 %cmicro %@[{'name': 'Richard Mateosian', 'affiliation': 'xrm@pacbell.net', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/5430728/5430748/5430748-photo-1-small.gif', 'p': []}} %*Technical Writing [review of Managing Writers: A Real World Guide to Managing Technical Documentation (Hamilton, R.; 2009)] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5430748 %f/micro/9oqyhj1rwdegtco7wacx4s6um2qitzpy.pdf %mcb59c4f623122251f127d1927d8b94dd %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'greenstein@kellogg.northwestern.edu', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/5446241/5446245/5446245-photo-1-small.gif', 'p': []}} %*Bleeding-Edge Mass Market Standards [Micro Economics] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5446245 %f/micro/yehp3gnwe6wqyozvlbbv7rcik0rm14du.pdf %m24e665aeb2eea74985cbdf5eeb9345d3 %cmicro %@[{'name': 'Krste Asanović,', 'affiliation': 'University of California, Berkeley', 'bio': {'p': ['Krste Asanović is an associate professor in the electrical engineering and computer science department at the University of California, Berkeley. His research interests include computer architecture, VLSI design, parallel programming and operating system design. Asanovic has a PhD in computer science from the University of California, Berkeley.']}}, {'name': 'Ralph Wittig', 'affiliation': 'Xilinx', 'bio': {'p': ['Ralph Wittig is the director of computing platforms at Xilinx. His interests include computer architecture, multicore processor systems, hybrid computing platforms, and heterogeneous platform programming models. Wittig has an MASc in computer engineering from the University of Toronto.', 'Direct questions and comments about this article to the authors at program2009@hotchips.org.']}} %*Guest Editors' Introduction: Hot Chips 21 %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5446246 %f/micro/3ecbzzpk7rgynca04dv9u8k5ivijdfhy.pdf %m7b9094fb11c804c53d1c292ebbc25d50 %cmicro %@[{'name': 'Ron Kalla', 'affiliation': 'IBM', 'bio': {'p': ['Ron Kalla is the chief engineer of the Power7 processor in the Systems and Technology Group at IBM. His technical interests are in the area of postsilicon hardware bring-up and verification. He has a BS in electrical engineering from the University of Minnesota.']}}, {'name': 'Balaram Sinharoy', 'affiliation': 'IBM', 'bio': {'p': ['Balaram Sinharoy is the chief core architect of the Power7 processor in the Systems and Technology Group at IBM. His research focuses on computer architecture. He has a PhD in computer science from Rensselaer Polytechnic Institute. He is an IBM Distinguished Engineer, an IBM Master Inventor, and a Fellow of IEEE.']}}, {'name': 'William J. Starke', 'affiliation': 'IBM', 'bio': {'p': ["William J. Starke chief symmetric-multiprocessing architect in the Systems and Technology Group at IBM. His technical interests include the Power7 processor's cache hierarchy, coherence protocol, SMP (symmetric multiprocessing) interconnect, memory, and I/O subsystems. He has a BS in computer science from Michigan Technological University."]}}, {'name': 'Michael Floyd', 'affiliation': 'IBM', 'bio': {'p': ['Michael Floyd is the architect and lead for the Power7 EnergyScale design in the Systems and Technology Group at IBM. His technical interests include hardware bring-up, test, debug, and RAS (reliability, availability, and serviceability) design for IBM server chips, as well as the design of adaptive power/performance computing into microprocessors. He has an MS in electrical engineering from Stanford University. He is an IBM Master Inventor.']}} %*Power7: IBM's Next-Generation Server Processor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5446247 %f/micro/zxagiykqahxn3f2ckjzy1viutleslnrg.pdf %m08d9fc79a9413e0177f6a9b781b6c9d3 %cmicro %@[{'name': 'Pat Conway', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ['Pat Conway is a principal member of the technical staff at AMD. His technical interests include server design and accelerated computing. Conway has a masters in electrical engineering from University College Cork, Ireland, and an MBA from Golden Gate University. He is a member of the IEEE.']}}, {'name': 'Nathan Kalyanasundharam', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ["Nathan Kalyanasundharam is a principal member of AMD's technical staff. His technical interests include the design of the load/store unit, cache controller, and north-bridge. Kalyanasundharam has an MS in electrical engineering from Texas A&M University."]}}, {'name': 'Gregg Donley', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ["Gregg Donley is a senior member of AMD's technical staff. His technical interests include third-level cache and system architecture. Donley has an MS in computer engineering from the University of Michigan."]}}, {'name': 'Kevin Lepak', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ["Kevin Lepak is a principal member of AMD's technical staff. His technical interests include various aspects of next-generation server platforms and processor development. Lepak has a PhD in electrical and computer engineering from the University of Wisconsin."]}}, {'name': 'Bill Hughes', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ['Bill Hughes is a senior fellow at AMD, where he leads the Northbridge and HyperTransport Microarchitecture team. He has a PhD electrical and electronic engineering from Leeds University, England.']}} %*Cache Hierarchy and Memory Subsystem of the AMD Opteron Processor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5446248 %f/micro/kduwyj6nwmfj2kprbgepod9nibal0zqy.pdf %m54a62f521630b17388ae99d48a9f2539 %cmicro %@[{'name': 'Takumi Maruyama', 'affiliation': 'Fujitsu', 'bio': {'p': ['Takumi Maruyama is a deputy general manager in the Next Generation Technical Computing Unit at Fujitsu. His technical interests include microprocessor architecture and VLSI design. Maruyama has a BE in mathematical engineering and instrumentation physics from the University of Tokyo.']}}, {'name': 'Toshio Yoshida', 'affiliation': 'Fujitsu', 'bio': {'p': ['Toshio Yoshida is an engineer in the Next Generation Technical Computing unit at Fujitsu. His technical interests include microprocessor architecture. Yoshida has an MS in physics from the Faculty of Science and Graduate School of Science at the University of Tokyo.']}}, {'name': 'Ryuji Kan', 'affiliation': 'Fujitsu', 'bio': {'p': ['Ryuji Kan is an engineer in the Next Generation Technical Computing unit at Fujitsu. He has been involved in the development of the execution units of the Sparc64 V, VI, VII, and VIIIfx processors. Kan has an ME in informatics from Kyoto University.']}}, {'name': 'Iwao Yamazaki', 'affiliation': 'Fujitsu', 'bio': {'p': ['Iwao Yamazaki is an engineer in the Next Generation Technical Computing unit at Fujitsu. His technical interests include cache designs for server processors. Yamazaki has a BS in physics from Kyoto University.']}}, {'name': 'Shuji Yamamura', 'affiliation': 'Fujitsu', 'bio': {'p': ['Shuji Yamamura is an engineer in the Next Generation Technical Computing unit at Fujitsu. His technical interests are in highperformance processor architectures. Yamamura has a PhD in electronics and information science from the Kyoto Institute of Technology. He is a member of the IEEE Computer Society.']}}, {'name': 'Noriyuki Takahashi', 'affiliation': 'Fujitsu', 'bio': {'p': ['Noriyuki Takahashi is an engineer in the Next Generation Technical Computing unit at Fujitsu. His technical interests include memory controller design. Takahashi has an ME in electrical engineering from Ehime University.']}}, {'name': 'Mikio Hondou', 'affiliation': 'Fujitsu', 'bio': {'p': ['Mikio Hondou is an engineer in the Next Generation Technical Computing unit at Fujitsu. His technical interests include microprocessor architecture and performance analysis. Hondou has an MS in physics from Keio University.']}}, {'name': 'Hiroshi Okano', 'affiliation': 'Fujitsu Laboratories', 'bio': {'p': ['Hiroshi Okano is a senior researcher in the Platform Technologies Laboratories at Fujitsu Laboratories. His technical interest is in low-power techniques for large-scale integration from system level to circuit level design. Okano has an ME in electrical engineering from Hiroshima University.']}} %*Sparc64 VIIIfx: A New-Generation Octocore Processor for Petascale Computing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5446249 %f/micro/7tovhojiy0ukque4wqztxgljairz2eyg.pdf %m78eae73d9fc8913c6c81a1a08698615b %cmicro %@[{'name': 'Bryan Catanzaro', 'affiliation': 'University of California, Berkeley', 'bio': {'p': ['Bryan Catanzaro is a PhD candidate in the in the electrical engineering and computer science department at the University of California, Berkeley. His research interests center on programming models for manycore computers, with an applications-driven emphasis. Catanzaro has an MS in electrical engineering from Brigham Young University. He is a member of IEEE.']}}, {'name': 'Armando Fox', 'affiliation': 'University of California, Berkeley', 'bio': {'p': ['Armando Fox is an adjunct associate professor in the electrical engineering and computer science at the University of California, Berkeley, and active in the Parallel Computing Laboratory and the Reliable Adaptive Distributed Systems laboratory (RAD Lab). His research interests include cloud computing, programming languages and frameworks, and applied machine learning. Fox has a PhD in computer science from the University of California, Berkeley. He is a senior member of the ACM.']}}, {'name': 'Kurt Keutzer', 'affiliation': 'University of California, Berkeley', 'bio': {'p': ['Kurt Keutzer is a professor of electrical engineering and computer science at the University of California, Berkeley, and the principal investigator in the Parallel Computing Laboratory. His research interests include patterns and frameworks for efficient parallel programming. Keutzer has a PhD in computer science from Indiana University. He is a fellow of IEEE.']}}, {'name': 'David Patterson', 'affiliation': 'University of California, Berkeley', 'bio': {'p': ['David Patterson is the director of the Parallel Computing Laboratory, director of the Reliable Adaptive Distributed Systems Laboratory, and Pardee Professor of Computer Science at the University of California, Berkeley. His research interests include hardware and software issues in many-core systems and cloud computing. Patterson has a PhD in computer science from the University of California, Los Angeles. He is a fellow of IEEE and the ACM.']}}, {'name': 'Bor-Yiing Su', 'affiliation': 'University of California, Berkeley', 'bio': {'p': ['Bor-Yiing Su is a PhD candidate in the electrical engineering and computer science at the University of California, Berkeley. His research interests focus on developing programming frameworks for computer vision applications on many-core platforms. Su has a BS in electrical engineering from National Taiwan University.']}}, {'name': 'Marc Snir', 'affiliation': 'University of Illinois at Urbana-Champaign', 'bio': {'p': ['Marc Snir is the Richard Feiman and Saburo Muroga Professor of Computer Science at the University of Illinois, Urbana-Champaign, codirector of UPCRC-Illinois, and chief software architect for the Petascale Blue Waters system. His research interests include high-performance computing, parallel programming models and programming environments, and computing education. Snir has a PhD in mathematics from the Hebrew University of Jerusalem. He is a fellow of IEEE, the ACM, and the AAAS.']}}, {'name': 'Kunle Olukotun', 'affiliation': 'Stanford University', 'bio': {'p': ['Kunle Olukotun is a professor of electrical engineering and computer science at Stanford University and director of the Stanford Pervasive Parallelism Lab. His research interests include computer architecture and parallel programming environments. Olukotun has a PhD in computer engineering from the University of Michigan. He is a fellow of IEEE and the ACM.']}}, {'name': 'Pat Hanrahan', 'affiliation': 'Stanford University', 'bio': {'p': ['Pat Hanrahan is the Canon Professor of Computer Science and Electrical Engineering at Stanford University. His research interests include programming environments for parallel computing, graphics systems and architectures, and visualization. Hanrahan has a PhD in biophysics from the University of Wisconsin.']}}, {'name': 'Hassan Chafi', 'affiliation': 'Stanford University', 'bio': {'p': ['Hassan Chafi is a PhD candidate in electrical engineering at Stanford University. His research interests include transactional memory and parallel programming models. Hassan has an MS in electrical engineering from Stanford University.']}} %*Ubiquitous Parallel Computing from Berkeley, Illinois, and Stanford %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5446250 %f/micro/nk9ycibth5u4paigrwqsl6q70mfkjz3d.pdf %m9e3f1e0ad5be4522d369e47d58a82828 %cmicro %@[{'name': 'John Nickolls', 'affiliation': 'NVIDIA', 'bio': {'p': ['John Nickolls is the director of architecture at NVIDIA for GHPU computing. His technical interests include developing parallel processing products, languages, and architectures. Nickolls has a PhD in electrical engineering from Stanford University.']}}, {'name': 'William J. Dally', 'affiliation': 'NVIDIA', 'bio': {'p': ["William J. Dally is the chief scientist and senior vice president of research at NVIDIA and the Willard R. and Inez Kerr Bell Professor of Engineering at Stanford University. His technical interests include parallel computer architecture, parallel programming systems, and interconnection networks. He's a member of the National Academy of Engineering and a fellow of IEEE, ACM, and the American Academy of Arts and Sciences. Dally has a PhD in computer science from the California Institute of Technology."]}} %*The GPU Computing Era %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5446251 %f/micro/n0jp7pj4ub9es8dhwzyi2gvbxvo35rag.pdf %mf6e5248914a7f181e1a22cab2e747925 %cmicro %@[{'name': 'Tony M. Brewer', 'affiliation': 'Convey Computer', 'bio': {'p': ['Tony M. Brewer is the chief technology officer and cofounder of Convey Computer. His passion is architecting high-performance systems and algorithms that can be applied to solving real-world problems. Brewer has an MS in electrical engineering from Purdue University.']}} %*Instruction Set Innovations for the Convey HC-1 Computer %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5446252 %f/micro/y3tkaxbwl0bhzosg2jvuufqvf9odnqpm.pdf %mab970643e6ba796e168a02e62f21b3b7 %cmicro %@[{'name': 'Sassan Tabatabaei', 'affiliation': 'SiTime Corporation', 'bio': {'p': ['Sassan Tabatabaei is the director of strategic applications at SiTime Corporation. His technical interests include signal integrity, timing, jitter, and clocking analysis, instrumentation, test, and design. Tabatabaei has a PhD in electrical engineering from the University of British Columbia.']}}, {'name': 'Aaron Partridge', 'affiliation': 'SiTime Corporation', 'bio': {'p': ['Aaron Partridge is chief science officer of SiTime. His technical expertise includes microelectromechanical systems, sensors, resonators, analog circuits, and precision timing. Partridge has a PhD in electrical engineering from Stanford University.']}} %*Silicon MEMS Oscillators for High-Speed Digital Systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5446253 %f/micro/b8zc79dvma5trgvp3sy6umxnq4f2lwjz.pdf %m57f534107eaf7ef1cd5edda3f8d47997 %cmicro %@[{'name': 'Richard Mateosian', 'affiliation': 'xrm@pacbell.net', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/5446241/5446254/5446254-photo-1-small.gif', 'p': []}} %*Designing for Discovery [review of "Search Patterns" Design for Discovery" (Morville, P. and Callender, J.; 2010)] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5446254 %f/micro/um13qco0n8pudkirv59mhqpxaz7znadt.pdf %m4b60e7acc0adc58927566fd6ab435e38 %cmicro %@[{'name': 'David H. Albonesi', 'affiliation': 'albonesi@csl.cornell.edu', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/5506926/5506932/5506932-photo-1-small.gif', 'p': []}} %*Future Directions in Computer Architecture Research %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5506932 %f/micro/nvnhdzjvsugzutok9xapr4kq6o5lrbxi.pdf %m8bf3776a42d6065f718fa30803595171 %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'greenstein@kellogg.northwestern.edu', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/5506926/5506933/5506933-photo-1-small.gif', 'p': []}} %*Standardization and Coordination %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5506933 %f/micro/rgn9cklkh0chofxgiqabzwrlmpnqmjue.pdf %m5efb88f05d664939d3d71469654dec82 %cmicro %@[{'name': 'James C. Hoe', 'affiliation': 'Carnegie Mellon University', 'bio': {'p': ['Doug Burger is director of client and cloud applications research at Microsoft Research, where he also manages the computer architecture research group. His research interests include computer architecture, new computing technologies, mobile user interfaces, cloud applications, and, of course, computer system simulation. Burger has a PhD in computer science from the University of Wisconsin. He is an IEEE Fellow, an ACM Distinguished Scientist, and chair of ACM SIGARCH.']}}, {'name': 'Doug Burger', 'affiliation': 'Microsoft Research', 'bio': {'p': ['Joel Emer is an Intel Fellow and director of microarchitecture research at Intel, where he leads the VSSAD group. He also teaches part-time at the Massachusetts Institute of Technology. His research interests include performance modeling frameworks, reconfigurable logic computing, parallel and multithreaded processors, cache organization, processor pipeline organization and processor reliability. Emer has a PhD in electrical engineering from the University of Illinois. He is an ACM Fellow and an IEEE Fellow.']}}, {'name': 'Joel Emer', 'affiliation': 'Intel', 'bio': {'p': ['James C. Hoe is a professor of electrical and computer engineering at Carnegie Mellon University. His research interests include computer architecture and high-level hardware description and synthesis. He has a PhD in electrical engineering and computer science from the Massachusetts Institute of Technology. He is a senior member of IEEE and a member of the ACM. For more information, please visit http://www.ece.cmu.edu/~jhoe.']}}, {'name': 'Derek Chiou', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ['Derek Chiou is an assistant professor in the Electrical and Computer Engineering Department at the University of Texas at Austin. His research interests include computer system simulation, computer architecture, parallel computer architecture, and Internet router architecture. Chiou has a PhD in electrical engineering and computer science from the Massachusetts Institute of Technology. He is a senior member of IEEE and a member of the ACM.']}}, {'name': 'Resit Sendag', 'affiliation': 'University of Rhode Island', 'bio': {'p': ['Resit Sendag is an associate professor in the Department of Electrical, Computer, and Biomedical Engineering at the University of Rhode Island, Kingston. His research interests include high-performance computer architecture, memory systems performance issues, and parallel computing. Sendag has a PhD in electrical and computer engineering from the University of Minnesota, Minneapolis. He is a member of IEEE and the IEEE Computer Society.']}}, {'name': 'Joshua Yi', 'affiliation': 'University of Texas School of Law', 'bio': {'p': ['Joshua J. Yi is a first year JD student at the University of Texas School of Law. His research interests include high-performance computer architecture, performance methodology, and deep submicron effects. Yi has a PhD in electrical engineering from the University of Minnesota, Minneapolis. He is a member of IEEE and the IEEE Computer Society.']}} %*The Future of Architectural Simulation %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5506934 %f/micro/7ysxt69hkbcy80wa3bwdereiklzotlpu.pdf %mbc1a73f10b4a4ab02e17fb54a72df066 %cmicro %@[{'name': 'Arvind ', 'affiliation': 'Massachusetts Institute of Technology', 'bio': {'p': ['Arvind is the Johnson Professor of Computer Science and Engineering at the Massachusetts Institute of Technology. His current research focus is on enabling rapid development of embedded systems. He is coauthor of Implicit Parallel Programming in pH. Arvind has a PhD in computer science from the University of Minnesota. He is a Fellow of both IEEE and ACM, and a member of the National Academy of Engineering.']}}, {'name': 'David August', 'affiliation': 'Princeton University', 'bio': {'p': ['David I. August is an associate professor in the Department of Computer Science at Princeton University, where he directs the Liberty Research Group, which aims to solve the multicore problem. August has a PhD in electrical engineering from the University of Illinois at Urbana-Champaign. He is a member of IEEE and ACM.']}}, {'name': 'Keshav Pingali', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ['Keshav Pingali is a professor in the Department of Computer Science at the University of Texas at Austin, where he holds the W.A.“Tex” Moncrief Chair of Grid and Distributed Computing in the Institute for Computational Engineering and Science. His research interests include programming languages, compilers, and high-performance computing. Pingali has an ScD in electrical engineering from the Massachusetts Institute of Technology. He is a Fellow of IEEE and of the American Association for the Advancement of Science (AAS).']}}, {'name': 'Derek Chiou', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ['Resit Sendag is an associate professor in the Department of Electrical, Computer, and Biomedical Engineering at the University of Rhode Island, Kingston. His research interests include high-performance computer architecture, memory systems performance issues, and parallel computing. Sendag has a PhD in electrical and computer engineering from the University of Minnesota, Minneapolis. He is a member of IEEE and the IEEE Computer Society.']}}, {'name': 'Resit Sendag', 'affiliation': 'University of Rhode Island', 'bio': {'p': ['Derek Chiou is an assistant professor in the Electrical and Computer Engineering Department at the University of Texas at Austin. His research interests include computer system simulation, computer architecture, parallel computer architecture, and Internet router architecture. Chiou has a PhD in electrical engineering and computer science from the Massachusetts Institute of Technology. He is a senior member of IEEE and a member of ACM']}}, {'name': 'Joshua J. Yi', 'affiliation': 'University of Texas School of Law', 'bio': {'p': ['Joshua J. Vi is a first year JD student at the University of Texas School of Law. His research interests include high-performance computer architecture, performance methodology, and deep submicron effects. Yi has a PhD in electrical engineering from the University of Minnesota, Minneapolis. He is a member of IEEE and the IEEE Computer Society.']}} %*Programming Multicores: Do Applications Programmers Need to Write Explicitly Parallel Programs? %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5506935 %f/micro/28keostmvjty5xvhd09w1uh6odgiupig.pdf %m9e9fe971062ad511e0e2b518f02c49fa %cmicro %@[{'name': 'Elliott Cooper-Balis', 'affiliation': 'University Of Maryland', 'bio': {'p': ['Elliott Cooper-Balis is pursuing a PhD in computer engineering at the University of Maryland, College Park. His research interests include next-generation memory systems, with a focus on architectural simulation. He has an MS in computer engineering from the University of Maryland, College Park.']}}, {'name': 'Bruce Jacob', 'affiliation': 'U. of Maryland', 'bio': {'p': ['Bruce Jacob is a professor at the University of Maryland, College Park. His research interests include memory-system design, DRAM architectures, virtual-memory systems, and microarchitectural support for real-time embedded systems. He has a PhD in computer science and engineering from the University of Michigan, Ann Arbor. He is a member of the IEEE Computer Society, IEEE, and the ACM.']}} %*Fine-Grained Activation for Power Reduction in DRAM %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5453331 %f/micro/twlrhzn4dr9x5uvgnk7aq1xkjmfp36hi.pdf %mb7c7812206a2ab19f179640f47eaabeb %cmicro %@[{'name': 'Hyesook Lim', 'affiliation': 'Ewha Womans University, Seoul', 'bio': {'p': ['Hyesook Lim is an associate professor in the Department of Electronics Engineering at Ewha Womans University, Seoul, Korea. Her research interests include router design issues such as IP address lookup, packet classification, and deep packet inspection. Lim has a PhD in electrical and computer engineering from the University of Texas at Austin. She is a member of IEEE.']}}, {'name': 'So Yeon Kim', 'affiliation': 'Ewha Womans University, Seoul', 'bio': {'p': ['So Yeon Kim is a research engineer at Samsung Electronics. Her research interests include fast IP address lookup and packet classification algorithms. Kim has an MS from the Department of Electronics Engineering at Ewha Womans University, Seoul, Korea.', 'Direct questions and comments about this article to Hyesook Lim, Ewha Womans University, Seoul 120–750, Korea, hlim@ewha.ac.kr.']}} %*Tuple Pruning Using Bloom Filters for Packet Classification %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5467010 %f/micro/vgokx3d0h7jfniutch9upqwdwclipxm2.pdf %m923cf3147be1dd9fc1bc2dc173d71934 %cmicro %@[{'name': 'Gabriel H. Loh', 'affiliation': 'Georgia Institute of Technology', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/5506926/5506936/5506936-photo-1-small.gif', 'p': ['Gabriel Loh Gabriel Loh is an assistant professor in the College of Computing at the Georgia Institute of Technology. His research interests include computer architecture, processor microarchitecture, emerging technologies and 3D die stacking. Loh has a PhD in computer science from Yale University. He is a senior member of IEEE and the ACM.']}}, {'name': 'Yuan Xie', 'affiliation': 'Pennsylvania State University', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/5506926/5506936/5506936-photo-2-small.gif', 'p': ['Yuan Xie is an associate professor in the Computer Science and Engineering Department at Pennsylvania State University. His research interests include computer architecture, electronic design automation, VLSI design, and embedded system design. Xie has a PhD in electrical engineering from Princeton University. He is a member of IEEE and the ACM.']}} %*3D Stacked Microprocessor: Are We There Yet? %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5506936 %f/micro/hg5wv2ehq3qxjm6m9yks1lbwxjevbuoa.pdf %mcdb6bb4cc250d91a22494d3fa0983798 %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'greenstein@kellogg.northwestern.edu', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/5550987/5550993/5550993-photo-1-small.gif', 'p': ['']}} %*Digitization and Value Creation %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5550993 %f/micro/l3wij7h8vnxkevplhmqgougabnca14yq.pdf %mbc91ddc0daa335f385e5032587a5ccf2 %cmicro %@[{'name': 'Luiz Andre Barroso', 'affiliation': 'Google', 'bio': {'p': ['Luiz Andre Barroso is distinguished engineer at Google. His research interests include hardware and software design for datacenter-scale systems and energy-efficient computing. Barroso has a PhD in computer engineering from the University of Southern California.']}}, {'name': 'Parthasarathy Ranganathan', 'affiliation': 'HP Labs', 'bio': {'p': ['Parthasarathy Ranganathan is a distinguished technologist at HP Labs. His research interests include system architecture and energy-efficient computing. Ranganathan has a PhD in electrical and computer engineering from Rice University. He is a senior member of IEEE and ACM.', 'Direct questions and comments about this article to Luiz Barroso, luiz@google.com, or Parthasarathy Ranganathan, Partha.ranganathan@hp.com.']}} %*Guest Editors' Introduction: Datacenter-Scale Computing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5550994 %f/micro/dblxhmmkqpngorp57l4tawigc2qhubor.pdf %m6c5343b15f693a3e89bd4245056c715a %cmicro %@[{'name': 'Christos Kozyrakis', 'affiliation': 'Stanford University', 'bio': {'p': ['Christos Kozyrakis is an associate professor of electrical engineering and computer science and the Willard R. and Inez Kerr Bell faculty scholar at Stanford University. His current research focuses on energy-efficient data centers, architecture and runtime environments for many-core chips, hardware and software techniques for transactional memory, and security systems. Kozyrakis has a PhD in computer science from the University of California, Berkeley. He is a senior member of IEEE and ACM.']}}, {'name': 'Aman Kansal', 'affiliation': 'Microsoft', 'bio': {'p': ['Aman Kansal is a researcher in systems and networking at Microsoft Research. His research interests include energy-proportional computing, wireless and mobile systems, and sensor-actuator networks. Kansal has a PhD in electrical engineering from the University of California, Los Angeles. He is a member of IEEE and ACM.', 'Direct questions and comments about this article to Aman Kansal, 1 Microsoft Way, Redmond, WA 98052, Kansal@microsoft.com.']}}, {'name': 'Sriram Sankar', 'affiliation': 'Microsoft', 'bio': {'p': ["Sriram Sankar is a hardware engineer in Microsoft's Online Services Division. In addition to designing server architectures for large-scale data centers, his research interests include workload characterization, energy-efficient data centers, and emerging storage architectures. Sankar has a master's degree in computer science from the University of Virginia, Charlottesville. He is a member of ACM."]}}, {'name': 'Kushagra Vaid', 'affiliation': 'Microsoft', 'bio': {'p': ["Kushagra Vaid is a principal architect in Microsoft's Online Services Division and leads the Hardware Engineering Team for Microsoft's Datacenter Infrastructure. His current interests are in researching innovations across the entire platform stack for deploying large-scale distributed server farms, and low-power energy-efficient microprocessor designs. Vaid has an MS from the State University of New York, Binghamton. He is a member of IEEE and ACM."]}} %*Server Engineering Insights for Large-Scale Online Services %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5550995 %f/micro/0mkijnxravu2c7ucvys8hoqe4pnbtzrs.pdf %m01778b01b17e26845762025fe216825a %cmicro %@[{'name': 'Trevor Mudge', 'affiliation': 'Dept. of Electr. Eng. &, Comput. Sci., Univ. of Michigan, Ann Arbor, MI, USA', 'bio': {'p': ['Trevor Mudge is the Bredt Family Professor of Engineering in the Department of Electrical Engineering and Computer Science at the University of Michigan, Ann Arbor. His research interests include computer architecture, power aware computing, low-power DSP architectures, robust computing, and prototyping. Mudge has a PhD in computer science from the University of Illinois, Urbana-Champaign. He is a member of the ACM, Institution of Engineering and Technology, and British Computer Society, and is a Fellow of IEEE.']}}, {'name': 'Urs Hö,lzle', 'affiliation': 'Google, CA, USA', 'bio': {'p': ['Urs Hölzle is senior vice president of operations and Google Fellow at Google. His research interests include cluster com-puting, data centers, networking, and energy efficiency. Holzle has a PhD in computer science from Stanford University. He is a Fellow of ACM.']}} %*Challenges and Opportunities for Extremely Energy-Efficient Processors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5550996 %f/micro/wum4vsxmvlh7gajcp6aerpzozfdnq3gh.pdf %m7e269df8f3a5aa6033bd430ecd7a6ceb %cmicro %@[{'name': 'Jose E. Moreira', 'affiliation': 'IBM Thomas J. Watson Research Center', 'bio': {'p': ['José E. Moreira is a research staff member at the IBM Thomas J. Watson Research Center. Moreira has a PhD in electrical engineering from the University of Illinois at Urbana-Champaign. His research interests include system software for highperformance computing, microarchitecture of server processors, and cloud computing. He is a member of IEEE and an ACM Distinguished Scientist.']}}, {'name': 'John Karidis', 'affiliation': 'IBM Thomas J. Watson Research Center', 'bio': {'p': ['John P. Karidis is a distinguished engineer at the IBM Thomas J. Watson Research Center. His research interests include high-speed robotics, mobile computing devices, high-performance cooling systems, phasechange memory, server memory architectures, and cloud computing. Karidis has a PhD in mechanical engineering from the Pennsylvania State University. He is a member of the American Society of Mechanical Engineers.']}} %*The Case for Full-Throttle Computing: An Alternative Datacenter Design Strategy %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5550997 %f/micro/lgi0rpm3ce2fxxiy5ecusb8oz4lk9v7r.pdf %mee7336ccf4a667ae2ca85bdeb6afb214 %cmicro %@[{'name': 'Amin Vahdat', 'affiliation': 'University of California, San Diego', 'bio': {'p': ["Amin Vahdat is a professor and holds the Science Applications International Corporation chair in the Department of Computer Science and Engineering at the University of California, San Diego. He's also director of UC San Diego's Center for Networked Systems. His research interests include distributed systems, networks, and operating systems. Vahdat has a PhD in computer science from University of California, Berkeley."]}}, {'name': 'Mohammad Al-Fares', 'affiliation': 'University of California, San Diego', 'bio': {'p': ["Mohammad AI-Fares is a PhD candidate in computer science at the University of California, San Diego, working in the Systems and Networking group. His research interests include building large datacenter network architectures, especially focusing on topology, routing, and forwarding efficiency. AL-Fares has an MS in computer science from UC San Diego. He's a member of ACM and Usenix."]}}, {'name': 'Nathan Farrington', 'affiliation': 'University of California, San Diego', 'bio': {'p': ["Nathan Farrington is a PhD candidate in computer science and engineering at the University of California, San Diego. His research interests include improving datacenter networks' cost, performance, power efficiency, scalability, and manageability. Farrington has an MS in computer science from UC San Diego. He's a member of IEEE and ACM."]}}, {'name': 'Radhika Niranjan Mysore', 'affiliation': 'University of California, San Diego', 'bio': {'p': ["Radhika Niranjan Mysore is a PhD candidate in computer science at the University of California, San Diego. Her research interests include datacenter networks' scalability, storage, and protocol design and correctness proofs. Mysore has an MS in electrical and computer engineering from Georgia Institute of Technology. She's a member of ACM and Usenix."]}}, {'name': 'George Porter', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['George Porter is a postdoctoral researcher in the Center for Networked Systems at the University of California, San Diego. His research interests include improving the scale, efficiency, and reliability of large-scale distributed systems, with a current focus on the data center. Porter has a PhD in computer science from the University of California, Berkeley.']}}, {'name': 'Sivasankar Radhakrishnan', 'affiliation': 'University of California, San Diego', 'bio': {'p': ["Sivasankar Radhakrishnan is a graduate student in computer science at the University of California, San Diego. His research interests include designing large-scale datacenter networks that deliver the high performance and efficiency required for planetary scale services. Radhakrishnan has a BTech in computer science and engineering from Indian Institute of Technology, Madras. He's a member of ACM and Usenix."]}} %*Scale-Out Networking in the Data Center %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5550998 %f/micro/xro9j2nqolm0brqfctwyaduwpiz4kgtu.pdf %m43858ccb003d1dc5fa23c8eaa1128ccd %cmicro %@[{'name': 'Sven-Arne Reinemo', 'affiliation': 'Simula Research Laboratory', 'bio': {'p': ['Sven-Arne Reinemo is a postdoctoral researcher at Simula Research Laboratory. His current research interests are routing, fault tolerance, and quality of service in interconnection networks. Reinemo has a PhD in computer science from the University of Oslo. He is a member of IEEE.']}}, {'name': 'Tor Skeie', 'affiliation': 'Simula Research Laboratory', 'bio': {'p': ['Tor Skeie is a professor at the Simula Research Laboratory and the University of Oslo. His research interests include scalability, effective routing, fault tolerance, and quality of service in switched network topologies. Other research interests include the road to deterministic Ethernet end-to-end and how precise time synchronization can be achieved across switched Ethernet. Skeie has a PhD in computer science from the University of Oslo.']}}, {'name': 'Manoj K. Wadekar', 'affiliation': 'QLogic', 'bio': {'p': ["Manoj K. Wadekar is a Fellow and senior director of technology at QLogic Corporation. His research interests include standardizing enhancements to Ethernet for the data center in the IEEE and in cross-industry initiatives. Wadekar has a master's degree in electrical engineering from the Indian Institute of Technology. He is a member of IEEE and a voting member of the IEEE 802.1 working group."]}} %*Ethernet for High-Performance Data centers: On the New IEEE Datacenter Bridging Standards %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5550999 %f/micro/ah1qd2h5mss3ptzvitfcgjbd89rkzaoo.pdf %m209976acddadab0fa8ba6c4bf9575f71 %cmicro %@[{'name': 'David G. Andersen', 'affiliation': 'Carnegie Mellon University', 'bio': {'p': ['David G. Andersen is an assistant professor at Carnegie Mellon University. His research interests include distributed systems, energy efficient computing, and networks. Andersen has a PhD in computer science and electrical Engineering from the Massachusetts Institute of Technology. He is a member of IEEE, ACM, and Usenix.']}}, {'name': 'Steven Swanson', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Steven Swanson is an assistant professor in the Department of Computer Science and Engineering at the University of California, San Diego. His research focuses on high-performance, solid-state storage systems, low-power architectures, and memory system optimizations for multiprocessors. Swanson has a PhD in computer science from the University of Washington. He is a member of ACM.']}} %*Rethinking Flash in the Data Center %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5551000 %f/micro/pwu2b09km7og41edgxbu5fflvns6jstx.pdf %mbfc4df43bda70ab758b3a170dc3ed549 %cmicro %@[{'name': 'Peng Wang', 'affiliation': 'Institute of Computing Technology, Chinese Academy of Sciences', 'bio': {'p': ['Peng Wang is a PhD student at the Institute of Computing Technology, Chinese Academy of Sciences, where his research focuses on programming models for massive data processing. Wang has an MS in computer science from the Ocean University of China.']}}, {'name': 'Dan Meng', 'affiliation': 'Institute of Computing Technology, Chinese Academy of Sciences', 'bio': {'p': ['Dan Meng is a professor of computer science at the Institute of Computing Technology, Chinese Academy of Sciences. His research interests include data-intensive computing and virtualization. Meng has a PhD in computer science from the Harbin Institute of Technology.']}}, {'name': 'Jizhong Han', 'affiliation': 'Institute of Computing Technology, Chinese Academy of Sciences', 'bio': {'p': ['Jizhong Han is an associate professor of computer science at the Institute of Computing Technology, Chinese Academy of Sciences. His research interests include parallel processing and storage system. Han has a PhD in computer science from the Institute of Computing Technology.']}}, {'name': 'Jianfeng Zhan', 'affiliation': 'Institute of Computing Technology, Chinese Academy of Sciences', 'bio': {'p': ['Jianfeng Zhan is an associate researcher at the Institute of Computing Technology, Chinese Academy of Sciences. His research interests include system software for highperformance computing and energy-efficient computing systems. Zhan has a PhD in computer science from the Institute of Software, Chinese Academy of Sciences.']}}, {'name': 'Bibo Tu', 'affiliation': 'Institute of Computing Technology, Chinese Academy of Sciences', 'bio': {'p': ['Bibo Tu is an assistant researcher at the Institute of Computing Technology, Chinese Academy of Sciences. His research interests include multicore computing and data-intensive computing. Tu has a PhD in computer science from the Institute of Computing Technology.']}}, {'name': 'Xiaofeng Shi', 'affiliation': 'Tencent Corporation', 'bio': {'p': ['Xiaofeng Shi is a senior software engineer at Tencent Corporation, where he leads the team working on distributed computing platforms. His research interests include data-intensive computing and distributed file systems. Shi has an MS in computer science from Xian Jiaotong University.']}}, {'name': 'Le Wan', 'affiliation': 'Tencent Corporation', 'bio': {'p': ['Le Wan is a software engineer at Tencent Corporation, where he leads the development of clickstream applications. His research interests include data-intensive computing and data management. Wan has an MS in computer science from Jilin University.']}} %*Transformer: A New Paradigm for Building Data-Parallel Programming Models %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5551001 %f/micro/1pp7yiczugz3nxx8dgwm4jtlc9vhtqri.pdf %m8333e541e447b025f86f9bfb9dfd7715 %cmicro %@[{'name': 'Gang Ren', 'affiliation': 'Google', 'bio': {'p': ["Gang Ren is a senior software engineer at Google, where he's working on datacenter application performance analysis and optimization. His research interests include application performance tuning in data centers and building tools for datacenter-scale performance analysis and optimization. Ren has a PhD in computer science from the University of Illinois at Urbana-Champaign."]}}, {'name': 'Eric Tune', 'affiliation': 'Google', 'bio': {'p': ["Eric Tune is a senior software engineer at Google, where he's working on a system that allocates computational resources and provides isolation between jobs that share machines. Tune has a PhD in computer engineering from the University of California, San Diego."]}}, {'name': 'Tipp Moseley', 'affiliation': 'Google', 'bio': {'p': ["Tipp Moseley is a software engineer at Google, where he's working on datacenter-scale performance analysis. His research interests include program analysis, profiling, and optimization. Moseley has a PhD in computer science from the University of Colorado, Boulder. He is a member of ACM."]}}, {'name': 'Yixin Shi', 'affiliation': 'Google', 'bio': {'p': ["Yixin Shi is a software engineer at Google, where he's working on performance analysis tools and large-volume imagery data processing. His research interests include architectural support for securing program execution, cache design for wide-issue processors, computer architecture simulators, and large-scale data processing. Shi has a PhD in computer engineering from the University of Illinois at Chicago. He is a member of ACM."]}}, {'name': 'Silvius Rus', 'affiliation': 'Google', 'bio': {'p': ["Silvius Rus is a senior software engineer at Google, where he's working on datacenter application performance optimization through compiler and library transformations based on memory allocation and reference analysis. Rus has a PhD in computer science from Texas A&M University. He is a member of ACM."]}}, {'name': 'Robert Hundt', 'affiliation': 'Google', 'bio': {'p': ["Robert Hundt is a tech lead at Google, where he's working on compiler optimization and datacenter performance. Hundt has a Diplom Univ. in computer science from the Technical University in Munich. He is a member of IEEE and SIGPLAN."]}} %*Google-Wide Profiling: A Continuous Profiling Infrastructure for Data Centers %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5551002 %f/micro/macpkkddvulns6iv487prqyrtjzo5gbx.pdf %m8a0ba93e54623c3ceb59a6f715785080 %cmicro %@[{'name': 'Benton H. Calhoun', 'affiliation': 'University of Virginia', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/5550987/5551003/5551003-photo-1-small.gif', 'p': ['Benton H. Calhoun is an assistant professor in the Charles L. Brown Department of Electrical and Computer Engineering at the University of Virginia. His research interests include low-power digital circuit design, subthreshold digital circuits, SRAM design for end-of-the-roadmap silicon, variation-tolerant circuit design methodologies, and low-energy electronics for medical applications. Calhoun has a PhD in electrical engineering from the Massachusetts Institute of Technology. He is a member of IEEE.']}}, {'name': 'David Brooks', 'affiliation': 'Harvard University', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/5550987/5551003/5551003-photo-2-small.gif', 'p': ['David Brooks is a Gordon McKay Professor of Computer Science in the School of Engineering and Applied Sciences at Harvard University. His research interests include power-efficient computer system design, variation-tolerant computer architectures, and embedded system design. Brooks has a PhD in electrical engineering from Princeton University. He is a member of IEEE and ACM.', 'Direct questions or comments about this article to Benton Calhoun, 351 McCormick Road, PO Box 400743, Charlottesville, VA 22904–4743, bcalhoun@virginia.edu.']}} %*Can Subthreshold and Near-Threshold Circuits Go Mainstream? %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5551003 %f/micro/5z1oaj0lhqicu3xpv6rkrwmkqpeuwnta.pdf %m516c24ae2f691abe60dcd9fcc8ab9be7 %cmicro %@[{'name': 'Richard Mateosian', 'affiliation': 'xrm@pacbell.net'} %*Miscellany [Book reviews] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5551004 %f/micro/6zm3bkcktlfprhg7gielq2dftimna8va.pdf %mc8db209665bacb7d063410de7b347c1c %cmicro %@[{'name': 'Mateo Valero', 'affiliation': 'Barcelona Supercomputing Center', 'bio': {'p': ['Mateo Valero is a professor in the Computer Architecture Department at the Universitat Politècnica de Catalunya (UPC) and the director of the Barcelona Supercomputing Center, the National Center of Supercomputing in Spain. His research interests focuses on high-performance architectures. Valero has a PhD in telecommunications from UPC. He is a Fellow of IEEE and the ACM and an Intel Distinguished Research Fellow.']}}, {'name': 'Nacho Navarro', 'affiliation': 'Universitat Politè,cnica de Catalunya', 'bio': {'p': ['Nacho Navarro is an associate professor of computer engineering at the Universitat Politècnica de Catalunya (UPC) and a senior researcher at the Barcelona Supercomputing Center. His research interests include heterogeneous accelerators (FPGAs and GPUs), runtime support for parallelism and operating systems for multicores Navarro has a PhD in computer science from UPC. He a member of IEEE, the IEEE Computer Society, and the ACM.', 'Direct questions and comments about this article to Mateo Valero or Nacho Navarro, Computer Architecture Dept., Universitat Politècnica de Catalunya, Jordi Girona 3, 08034 Barcelona, Spain, {mateo, nacho}@ac.upc.edu.']}} %*Multicore: The View from Europe %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5640602 %f/micro/8nypmezfrh5pujdkdtyqo3vfmauglbce.pdf %mb379a44883a4de2f34c28d50ea64e911 %cmicro %@[{'name': 'Veerle Desmet', 'affiliation': 'Ghent University', 'bio': {'p': ['Veerle Desmet is a scientific advisor at the Flemish Institute for the Promotion of Scientific-Technological Research in the Industry (IWT). Her research interests include computer architecture, design-space exploration, multicore systems, reliability, and speculation techniques such as branch prediction, value prediction, and return address prediction. Desmet has a PhD in computer science engineering from Ghent University.']}}, {'name': 'Sylvain Girbal', 'affiliation': 'Thales Reseacrh adn Technologies', 'bio': {'p': ['Sylvain Girbal is a research engineer at Thales TRT, France. His research interests include computer architecture simulation methodology, design-space exploration methodology, and compiler techniques. Girbal has a PhD from the University of Paris-Sud.']}}, {'name': 'Alex Ramirez', 'affiliation': 'Universitat Politecnica de Catalunya Barcelona Supercomputing Center', 'bio': {'p': ['Alex Ramirez is an associate professor in the Computer Architecture Department at the Universitat Politecnica de Catalunya, Spain, and leader of the computer architecture group at the Barcelona Supercomputing Center. His research interests include heterogeneous multicore architectures, application specific accelerators, and architecture support for parallel programming models. Ramirez has a PhD in computer science from the Universitat Politecnica de Catalunya.']}}, {'name': 'Olivier Temam', 'affiliation': 'Universitat Politecnica de Catalunya Barcelona Supercomputing Center', 'bio': {'p': ['Augusto J. Vega is an engineer at the IBM Thomas J. Watson Research Center, an external collaborator at the Barcelona Super-computing Center, and a PhD student in the Computer Architecture Department at the Universitat Politecnica de Catalunya, Spain. His research interests include performance and power modeling, simulation techniques, and architecture design of multicore processors. Vega has an MSc in computer architecture, networks, and systems from the Universitat Polirecnica de Catalunya.']}}, {'name': 'Augusto Vega', 'affiliation': 'Inria Saclay', 'bio': {'p': ['Olivier Temam is a senior research fellow at Inria Saclay in Paris, where he heads the Alchemy Group, and a professor at Ecole Polytechnique, His research interests include microarchitecture, simulation, compilation, programming models, and alternative computing systems. Temam has a PhD in computer science from the University of Rennes.', 'Direct questions or comments about this article to Olivier Temam, Inria Saclay, Batiment N, Parc Club Universite, rue Jean Rostand, 91893 Orsay Cedex, France, olivier.temam@inria.fr.']}} %*ArchExplorer for Automatic Design Space Exploration %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5567089 %f/micro/z1qseubmnyaafwzkidnhlpcx2prg3umg.pdf %m8c23e6c5eeacf789ea6561e192b25c97 %cmicro %@[{'name': 'Alex Ramirez', 'affiliation': 'Barcelona Supercomputing Center', 'bio': {'p': ['Alex Ramirez is an associate professor in the Computer Architecture Department at the Universitat Polirecnica de Catalunya (UPC), Barcelona, Spain, and leader of the Computer Architecture group at the Barcelona Super-computing Center. His research interests include heterogeneous multicore architectures and application-specific accelerators. Ramirez has a PhD in computer science from UPC.']}}, {'name': 'Felipe Cabarcas', 'affiliation': 'Barcelona Supercomputing Center', 'bio': {'p': ["Felipe Cabarcas is a professor of electrical engineering at the Universidad de Antioquia, Medellin, Colombia, a PhD candidate in computer architecture at the Universitat Politecnica de Catalunya, and a research assistant at the Barcelona Supercomputing Center. His research interests include highperformance and multicore architectures. Cabarcas has a master's degree in electrical engineering from the University of Delaware."]}}, {'name': 'Ben Juurlink', 'affiliation': 'Technische Universitat Berlin', 'bio': {'p': ['Ben Juurlink is a professor of embedded systems architectures in the Faculty of Electrical Engineering and Computer Science of the Technische Universitat Berlin. His research interests include multi-and manycore processors and memory systems. Juurlink has a PhD in computer science from Leiden University. He is a senior member of IEEE, a member of the ACM, and a member of the HiPEAC Network of Excellence.']}}, {'name': 'Mauricio Alvarez Mesa', 'affiliation': 'Universitat Politecnica de Catalunya', 'bio': {'p': ['Mauricio Alvarez is a PhD student in the Computer Architecture Department at the Universitat Politecnica de Catalunya, where he is a member of the High Performance Computing Group. His research interests include highperformance architectures for multimedia applications and streaming architectures. Alvarez has a BSc in electronic engineering from the University of Antioquia, Colombia.']}}, {'name': 'Friman Sanchez', 'affiliation': 'Universitat Politecnica de Catalunya', 'bio': {'p': ['Arnaldo Azevedo is a doctoral candidate in the Computer Engineering Laboratory of the Faculty of Electrical Engineering, Mathematics and Computer Science of Delft University of Technology, the Netherlands. His research interests include multimedia accelerators architectures for multicore processors. Azevedo has an MSc in computer science from the Universidade Federal do Rio Grande do SuI, Brazil.']}}, {'name': 'Arnaldo Azevedo', 'affiliation': 'Delft University of Technology', 'bio': {'p': ['Cor H. Meenderinck is a postdoctoral researcher in the Computer Engineering Laboratory of the Faculty of Electrical Engineering, Mathematics, and Computer Science at Delft University of Technology, the Netherlands. His research interests include multicore architecture and runtime systems. Meenderinck has a PhD in computer engineering from Delft University of Technology.']}}, {'name': 'Cor Meenderinck', 'affiliation': 'Delft University of Technology', 'bio': {'p': ['Cätälin Ciobanu is a PhD student in the Computer Engineering Laboratory of the Faculty of Electrical Engineering, Mathematics and Computer Science of Delft University of Technology, the Netherlands. His research interests include computer architecture and parallel processing. Ciobanu has an MSc in computer engineering from Delft University of Technology.']}}, {'name': 'Catalin Ciobanu', 'affiliation': 'Delft University of Technology', 'bio': {'p': ['Sebastian Isaza is a PhD student in computer engineering at Delft University of Technology, the Netherlands, and is on the faculty at the University of Antioquia, Colombia. His research interests include multicore architectures and accelerators for bioinformatics workloads. Isaza has an MSc in embedded systems design from the University of Lugano, Switzerland.']}}, {'name': 'Sebastian Isaza', 'affiliation': 'Delft University of Technology', 'bio': {'p': ['Friman Sanchez is a PhD student in the Computer Architecture Department at the Universitat Politecnica de Catalunya. His research interests include performance characterization of bioinformatics applications and parallel programming. Sanchez has a BSc in electronic engineering from the University of Antioquia, Colombia.']}}, {'name': 'Gerogi Gaydadjiev', 'affiliation': 'Delft University of Technology', 'bio': {'p': ['Georgi Gaydadjiev is a faculty member in the Computer Engineering Laboratory, Microelectronics and Computer Engineering Department of Delft University of Technology, the Netherlands. His research interests include embedded systems design and advanced computer architectures. Gaydadjiev has a PhD in computer engineering from Delft University of Technology, the Netherlands. He is a member of the IEEE Computer Society and the ACM. Direct questions and comments about this article to Alex Ramirez, Campus Nord UPC, C6-E205, Jordi Girona, 1–3, 08034 Barcelona, Spain, alex.ramirez@bsc.es.']}} %*The SARC Architecture %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5567090 %f/micro/crzmxgr65bn2aysbkjvu8t1fz9gyhoie.pdf %m1513484776b27e7799c24aab43de9db5 %cmicro %@[{'name': 'Manolis G H Katevenis', 'affiliation': 'FORTH-ICS, Heraklion, Greece', 'bio': {'p': ['Manolis G.H. Katevenis is a professor in the Computer Science Department at the University of Crete. He is also the head of the Computer Architecture and VLSI Systems Laboratory and deputy director in the Institute of Computer Science at the Foundation for Research and Technology-Hellas (FORTH-ICS), Heraklion, Crete. His research interests include embedded and scalable multiprocessor architecture, interprocessor communication mechanisms, interconnection network architecture, packet switch architecture and VLSI systems. Katevenis has a PhD from the University of California, Berkeley. He is a member of the steering committee of the HiPEAC European Network of Excellence.']}}, {'name': 'V Papaefstathiou', 'affiliation': 'FORTH-ICS, Heraklion, Greece', 'bio': {'p': ['Vassilis Papaefstathiou is a PhD candidate in the Computer Science Department at the University of Crete and a research assistant in the Institute of Computer Science at the Foundation for Research and Technology-Hellas (FORTH-ICS). His research interests include parallel and high-performance archi-tectures, packet-switch architectures, network processing hardware, and embedded systems. Papaefstathiou has an MS in computer science from the University of Crete. He is a member of the HiPEAC European Network of Excellence.']}}, {'name': 'S Kavadias', 'affiliation': 'FORTH-ICS, Heraklion, Greece', 'bio': {'p': ['Stamatis Kavadias is a PhD candidate in the Computer Science Department at the University of Crete and a research assistant in the Institute of Computer Science at the Foundation for Research and Technology-Hellas (FORTH-ICS). His research interests include multicore architectures, scheduling and processor microarchitecture. Kavadias has an MS in electronic and computer engineering from the Electronic and Computer Engineering Department at the Technical University of Crete. He is a member of the HiPEAC European Network of Excellence.']}}, {'name': 'D Pnevmatikatos', 'affiliation': 'FORTH-ICS, Heraklion, Greece', 'bio': {'p': ['Dionisios Pnevmatikatos is a professor in the Electronic and Computer Engineering Department at the Technical University of Crete and director of the Microprocessor and Hardware Lab. He is also an associate researcher in the Institute of Computer Science at the Foundation for Research and Technology-Hellas (FORTH-ICS). His research interests include computer architecture, reconfigurable computing and digital systems design. Pnevmatikatos has a PhD in computer science from the University of Wisconsin-Madison. He is a member of IEEE and the HiPEAC European Network of Excellence.']}}, {'name': 'Dimitrios S Nikolopoulos', 'affiliation': 'FORTH-ICS, Heraklion, Greece', 'bio': {'p': ['Dimitrios S. Nikolopoulos is an associate professor of computer science at the University of Crete and affiliated faculty of the Institute of Computer Science at the Foundation for Research and Technology-Hellas (FORTH-ICS). His research interests include the hardware-software interface of parallel computer architectures, parallel pro-gramming, and system software. Nikolopou-los has a PhD in computer engineering from the University of Patras. He is a member of the ACM, IEEE, and the HiPEAC European Network of Excellence.', 'Direct questions and comments about this article to Vassilis Papaefstathiou, Inst. of Computer Science, Foundation for Research and Technology-Hellas, 100 N. Plastira St., Vassilika Vouton, GR-70013, Heraklion, Crete, Greece, papaef@ics.forth.gr.']}}, {'name': 'Federico Silla', 'affiliation': 'Univ. Politec. de Valencia, Valencia, Spain', 'bio': {'p': ['Federico Silla is an associate professor in the Department of Computer Engineering at the Technical University of Valencia, Spain. His research interests include high-performance interconnects for on-chip and off-chip net-works. Silla has a PhD in computer engineering from the Technical University of Valencia. He is a member of the Advanced Technology Group of the HyperTransport Consortium and the HiPEAC European Network of Excellence.']}} %*Explicit Communication and Synchronization in SARC %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5567092 %f/micro/j8ny9g2lqalfvmozkiop0jdvsxkzhiqg.pdf %md85a08542a3fa2c40a4040716beecacb %cmicro %@[{'name': 'SARC European Project ', 'affiliation': 'Barcelona Supercomputing Center', 'bio': {'p': ["Roger Ferrer is a researcher at the Barcelona Supercomputing Center. His research interests include language and compiler support for parallel programming models. Ferrer has a master's degree in computer architecture and network systems from the Universitat Politècnica de Catalunya."]}} %*Parallel Programming Models for Heterogeneous Multicore Architectures %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5640603 %f/micro/rflown3bg0arjtkucxmnb87eievp1tud.pdf %m0c4ae7f2858cd4e5a462dee3a256a635 %cmicro %@[{'name': 'Stefanos Kaxiras', 'affiliation': 'Uppsala University, Sweden', 'bio': {'p': ['Stefanos Kaxiras is a professor in the Information Technology Department at U ppsala University, Sweden. His research interests include power-efficient processor/memory design and modeling of power consumption and performance in multicore architectures. Kaxiras has a PhD in computer science from the University of Wisconsin.']}}, {'name': 'Georgios Keramidas', 'affiliation': 'Industrial Systems Institute, Greece', 'bio': {'p': ['Georgios Keramidas is a postdoctoral fellow at the Industrial Systems Institute, Greece, and a visiting assistant professor at the University of Patras, Greece. His research interests include computer architecture, in particular, the design of the memory subsystem of single core and multicore systems. Keramidas has a PhD in electrical and computer engineering from the University of Patras.', 'Direct questions and comments about this article to Georgios Keramidas, lSI, Patras Science Park S.A., Stadiou str., Platani, Patras GR-26504, Greece, keramidas@ece.upatras.gr.']}} %*SARC Coherence: Scaling Directory Cache Coherence in Performance and Power %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5582068 %f/micro/nuokgsh82hijfex3epswit0tmzcdubkl.pdf %m9652f7beb6583e091259ee1f24939b59 %cmicro %@[{'name': 'Theo Ungerer', 'affiliation': 'University of Augsburg, Augsburg', 'bio': {'p': ['Theo Ungerer is chair of systems and networking in the Computer Science Department at the University of Augsburg, Germany, and the coordinator of the European Commission project MERASA. He has a doctoral degree in mathematics and a habilitation degree in computer science from the University of Augsburg.']}}, {'name': 'Francisco Cazorla', 'affiliation': 'Barcelona SuperComputing Center , barcelona', 'bio': {'p': ['Francisco J. Cazorla leads the group on interaction between computer architecture and operating systems (CAOS) at the Barcelona Supercomputing Center. He has a doctoral degree in computer architecture from the Universitat Politecnica de Catalunya. He led the architecture work package of Merasa.']}}, {'name': 'Pascal Sainrat', 'affiliation': 'Université, Paul Sabatier, Toulouse', 'bio': {'p': ['Pascal Sainrat is a professor at the Universite Paul Sabatier de Toulouse and head of the Traces team at the Institut de Recherche en Informatique de Toulouse. He has doctoral degrees in computer science from the University of Toulouse.']}}, {'name': 'Guillem Bernat', 'affiliation': 'Rapita Systems L.t.d, York', 'bio': {'p': ['Guillem Bernat is the founder and CEO of Rapita Systems, a spin-off company from the University of York, transferring measurement-based worst-case execution time analysis technology into commercial practice. He has a doctoral degree in computer science from the Universitat de les Illes Balears.']}}, {'name': 'Zlatko Petrov', 'affiliation': 'Honeywell International s.r.o., Brno', 'bio': {'p': ['Zlatko Petrov is a technical leader of the Platform system group at Honeywell Advanced Technology Europe. He has master of science degrees in automation and control systems from the Technical University of Varna, Bulgaria, and in embedded systems design from the University of Lugano, Switzerland.']}}, {'name': 'Christine Rochange', 'affiliation': 'Université, Paul Sabatier, Toulouse', 'bio': {'p': ['Hugues Cassé is an associate professor at Université Paul Sabatier de Toulouse and member of the Traces team of Institut de Recherche en Informatique de Toulouse. He has a doctoral degree in computer science from the University of Toulouse.']}}, {'name': 'Eduardo Quinones', 'affiliation': 'Barcelona Supercomputing Center, barcelona', 'bio': {'p': ['Christine Rochange is an associate professor at Université Paul Sabatier de Toulouse and member of the Traces team of Institut de Recherche en Informatique de Toulouse. She has a doctoral degree in computer science from the University of Toulouse.']}}, {'name': 'Mike Gerdes', 'affiliation': 'University of Augsburg, Augsburg', 'bio': {'p': ['Eduardo Quiñones is a senior researcher at the Barcelona Supercomputing Center. He has a doctoral degree in computer architecture from the Universitat Politècnica de Catalunya.']}}, {'name': 'Marco Paolieri', 'affiliation': 'Barcelona Supercomputing Center, Barcelona', 'bio': {'p': ['Sascha Uhrig is a senior researcher at University of Augsburg, Germany, at the chair of systems and networking. He has a doctoral degree in computer science from the University of Augsburg.']}}, {'name': 'Julian Wolf', 'affiliation': 'University of Augsburg, Augsburg', 'bio': {'p': ['Mike Gerdes is a researcher and PhD student at University of Augsburg, Germany, at the chair of systems and networking. He has a diploma in applied computer science from the University of Augsburg.']}}, {'name': 'Hugues Casse', 'affiliation': 'Universite´, Paul Sabatier de Toulouse', 'bio': {'p': ['Irakli Guliashvili is a researcher at the University of Augsburg, Germany, at the chair of systems and networking. He has a diploma in applied computer science from the University of Augsburg.']}}, {'name': 'Sascha Uhrig', 'affiliation': 'University of Augsburg', 'bio': {'p': ['Michael Houston is a senior software engineer at Rapita Systems. He has an ME in computer systems and software engineering from the University of York.']}}, {'name': 'Irakli Guliashvili', 'affiliation': 'University of Augsburg', 'bio': {'p': ['Florian Kluge is a senior researcher in the Computer Science Department at the University of Augsburg, Germany. He has a doctoral degree in computer science from the University of Augsburg.']}}, {'name': 'Michael Houston', 'affiliation': 'Rapita Systems', 'bio': {'p': ['Stefan Metzlaff is a researcher and PhD student at the University of Augsburg, Germany, at the chair of systems and networking. He has a diploma in computer science from the University of Magdeburg.']}}, {'name': 'Floria Kluge', 'affiliation': 'University of Augsburg', 'bio': {'p': ['Jörg Mische is a researcher and PhD student at the University of Augsburg, Germany, at the chair of systems and networking. He has a diploma in computer science from the University of Augsburg.']}}, {'name': 'Stefan Metzlaff', 'affiliation': 'University of Augsburg', 'bio': {'p': ['Marco Paolieri is a PhD student in the Computer Architecture Department at the Barcelona Supercomputing Center. He has a master of science degree in embedded systems design at the Advanced Learning and Research Institute, the University of Lugano, Switzerland.']}}, {'name': 'Jorg Mische', 'affiliation': 'University of Augsburg', 'bio': {'p': ['Julian Wolf is a researcher and PhD student at the University of Augsburg, Germany, at the chair of systems and networking. He has a diploma in applied computer science from the University of Augsburg.', 'Direct questions and comments to Theo Ungerer, University of Augsburg, Universi-tätsstr. 6a, 86159 Augsburg, Germany, ungerer@informatik.uni-augsburg.de.']}} %*Merasa: Multicore Execution of Hard Real-Time Applications Supporting Analyzability %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5567091 %f/micro/nw0zfth91dao2ha8ftb6gynuxogk5dvj.pdf %m3abf71ee9661c1b8314fc195979ca2b2 %cmicro %@[{'name': 'Yehuda Afek', 'affiliation': 'Tel Aviv University', 'bio': {'p': ['Pascal Felber is a professor of computer science at the University of Neuchâtel Switzerland. He has a PhD in computer science from Ecole Polytechnique Fédérale de Lausanne, Switzerland. He is a member of IEEE, the ACM, Usenix, and EuroSys.']}}, {'name': 'Ulrich Drepper', 'affiliation': 'Red Hat', 'bio': {'p': ['Etienne Rivière is a researcher at the University of Neuchâtel Switzerland. He has a PhD in computer science from the University of Rennes 1, France. He is a member of IEEE, the ACM, Usenix, and EuroSys.']}}, {'name': 'Pascal Felber', 'affiliation': 'University of Neuchatel', 'bio': {'p': ['Walther Maldonado Moreira is a PhD student at the University of Neuchâtel, Switzerland. He has an engineering degree in computer science from Ecole des Mines de Nantes, France. He is a member of IEEE.']}}, {'name': 'Christof Fetzer', 'affiliation': 'Technische Universitat Dresden', 'bio': {'p': ['Derin Harmanci is a PhD student at the University of Neuchâtel, Switzerland. He has a MSc in computer science from Ecole Polytechnique Fédérale de Lausanne, Switzerland. He is a member of IEEE and the ACM.']}}, {'name': 'Vincent Gramoli', 'affiliation': 'University of Neuchâ,tel', 'bio': {'p': ['Patrick Marlier is a PhD student at the University of Neuchâtel Switzerland. He has an engineering degree in computer science from the Universite de Technologie de Compiègne, France.']}}, {'name': 'Michael Hohmuth', 'affiliation': 'Advancd Micro Devices', 'bio': {'p': ["Stephan Diestelhorst is a software engineer 2 at AMD's Operating System Research Center, Germany. He has a MSc in computer science from Technische Universi-tat Dresden, Germany."]}}, {'name': 'Etienne Riviere', 'affiliation': 'University of Neuchatel', 'bio': {'p': ["Michael Hohmuth is a member of the technical staff at AMD's Operating System Research Center, Germany. He has a Dr.-lng in Computer Science from the Technische Universität Dresden, Germany. He is a member of the ACM."]}}, {'name': 'Per Stenstrom', 'affiliation': 'Chalmers University of Technology', 'bio': {'p': ["Martin Pohlack is a senior software engineer at AMD's Operating System Research Center, Germany. He has a DrIng in computer science from the Technische Universität Dresden, Germany. He is a member of EuroSys."]}}, {'name': 'Osman Unsal', 'affiliation': 'Barcelona Supercomputing Center', 'bio': {'p': ['Adrian Cristal is a researcher and comanager of computer architecture for parallel paradigms at the Barcelona Supercomputing Center and the Artificial Intelligence Research Institute, Spanish National Research Council. He has a PhD in computer science from the Universitat Politècnica de Catalunya.']}}, {'name': 'Walther Maldonado Moreira', 'affiliation': 'University of Neuchatel', 'bio': {'p': ['Ibrahim Hur is a senior researcher at the Barcelona Supercomputing Center, Spain. He has a PhD in computer science from the University of Texas at Austin. He is a member of IEEE and the ACM.']}}, {'name': 'Derin Harmanci', 'affiliation': 'University of Neuchatel', 'bio': {'p': ['Osman S. Unsal is a group manager at the Barcelona Supercomputing Center, Spain. He has a PhD in electrical and computer engineering from University of Massachusetts, Amherst.']}}, {'name': 'Patrick Marlier', 'affiliation': 'University of Neuchatel', 'bio': {'p': ['Per Stenström is a professor at Chalmers University of Technology, Sweden. He has a PhD in computer engineering from Lund University, Sweden. He is a Fellow of IEEE and the ACM and a member of Royal Swedish Academy of Engineering Sciences.']}}, {'name': 'Stephan Diestelhorst', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ['Aleksandar Dragojevic is a PhD student in computer science at Ecole Polytechnique Fédérale de Lausanne, Switzerland. He is a graduate engineer in electrical and computer engineering from University of Novi Sad, Serbia.']}}, {'name': 'Martin Pohlack', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ['Rachid Guerraoui is a professor at Ecole Polytechnique Fédérale de Lausanne, Switzerland. He has a PhD in computer science from the University of Orsay, France. He is a member of IEEE and the ACM.']}}, {'name': 'Adrian Cristal', 'affiliation': 'Barcelona Supercomputing Center', 'bio': {'p': ['Michal Kapalka was a PhD student in computer science at Ecole Polytechnique Fédérale de Lausanne, Switzerland. He has a PhD in computer science from Ecole Polytechnique Fédérale de Lausanne, Switzerland.']}}, {'name': 'Ibrahim Hur', 'affiliation': 'Barcelona Supercomputing Center', 'bio': {'p': ['Vincent Gramoli is a researcher at Ecole Polytechnique Fédérale de Lausanne and the University of Ncuchatel, Switzerland. He has a PhD in computer science from the University of Rennes 1, France.']}}, {'name': 'Aleksandar Dragojevic', 'affiliation': 'Ecole Polytechnique Federale de Lausanne', 'bio': {'p': ['Ulrich Drepper is a consulting engineer at Red Hat. He has a MSc in computer science from Universität Karlsruhe, Germany. He is a member of IEEE.']}}, {'name': 'Rachid Guerraoui', 'affiliation': 'Ecole Polytechnique Federale de Lausanne', 'bio': {'p': ['Sasša Tomic is a PhD student in computer architecture at the Universitat Politècnica de Catalunya, Spain. He has a MSc in computer science from the School of Electrical Engineering (ETF) in Belgrade, Serbia. He is a member of IEEE and the ACM.']}}, {'name': 'Michal Kapalka', 'affiliation': 'Ecole Polytechnique Federale de Lausanne', 'bio': {'p': ['Yehuda Afek is a professor at Tel Aviv University. He has a PhD in computer science from the University of California, Los Angeles.']}}, {'name': 'Sasa Tomic', 'affiliation': 'Universitat Politecnica de Catalunya', 'bio': {'p': ['Guy Korland is a PhD student at Tel Aviv University. He has a MSc in computer science from the Technion, Israel institute of Technology.']}}, {'name': 'Guy Korland', 'affiliation': 'Tel Aviv University', 'bio': {'p': ['Nir Shavit is a professor at Tel Aviv University. He has a PhD in computer science from the Technion, Haifa. He is a member of the ACM.']}}, {'name': 'Nir Shavit', 'affiliation': 'Tel Aviv University', 'bio': {'p': ['Christof Fetzer is a professor at the Technische Universität Dresden, Germany. He has a PhD in computer science from the University of California, San Diego. He is a member of the ACM.']}}, {'name': 'Martin Nowack', 'affiliation': 'Technische Universitat Dresden', 'bio': {'p': ['Martin Nowack is a PhD student at the Technische Universität Dresden, Germany. He has a MSc in computer science from the Technische Universität Dresden.']}}, {'name': 'Torvald Riegel', 'affiliation': 'Technische Universitat Dresden', 'bio': {'p': ['Torvald Riegel is a PhD student in computer science at the Technische Universitat Dresden, Germany. He has a MSc in computer science from the Technische Universität Dresden.']}} %*The Velox Transactional Memory Stack %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5567088 %f/micro/9iitu8qdowmf5jkccfhysbvzd6x2pugx.pdf %m3e10998687df1cd17a732fa36c2bf8be %cmicro %@[{'name': 'Koen Bertels', 'affiliation': 'Delft University of Technology', 'bio': {'p': ['Koen Bertels is an associate professor in the Computer Engineering Lab, at Delft University of Technology. His research interests include electronic system-level design, reconfigurable computing, and multicore computing. Bertels has a PhD in computer information systems from the University of Antwerp. He is a member of IEEE and the IEEE Computer Society.']}}, {'name': 'Vlad-Mihai Sima', 'affiliation': 'Delft University of Technology', 'bio': {'p': ['Vlad-Mihai Sima is pursuing a PhD in computer engineering at Delft University of Technology. His research interests include compilers, reconfigurable computing, and heterogeneous embedded systems. Sima has an MSc in computer science and engineering from Universitatea Politehnica in Bucharest, Romania.']}}, {'name': 'Yana Yankova', 'affiliation': 'Delft University of Technology', 'bio': {'p': ['Yana Yankova is pursuing a PhD in computer engineering at Delft University of Technology. Her research interests include compilation systems, automated hardware generation, reconfigurable computing, and embedded systems. Yankova has an MSc in computer systems from the Technical University of Sofia in Bulgaria.']}}, {'name': 'Georgi Kuzmanov', 'affiliation': 'Delft University of Technology', 'bio': {'p': ['Georgi Kuzmanov is an assistant professor in the Computer Engineering Lab at Delft University of Technology. His research interests include reconfigurable computing, media processing, computer architecture and organi-zation, and embedded sy stems. Kuzmanov has a PhD in computer engineering from Delft University of Technology. He is a member of IEEE and the IEEE Computer Society.']}}, {'name': 'Wayne Luk', 'affiliation': 'Imperial College London', 'bio': {'p': ['Wayne Luk is a professor of computer engineering at Imperial College London. His research focuses on theory and practice of customizing hardware and software for specific application domains, such as multi-media, financial modeling, and medical computing. Luk has a DPhil in engineering and computing science from the University of Oxford. He is an IEEE Fellow.']}}, {'name': 'Gabriel Coutinho', 'affiliation': 'Imperial College London', 'bio': {'p': ['Gabriel Coutinho is a research associate in the Custom Computing Research Group of the Computing Department at Imperial College London. His research interests include hardware compilation, source-level transformations, high-performance computing, and embedded systems. Coutinho has a PhD in computer science from Imperial College London.']}}, {'name': 'Fabrizio Ferrandi', 'affiliation': 'Politecnico di Milano', 'bio': {'p': ['Fabrizio Ferrandi is an associate professor in the Department of Electronics and Information at Politecnico di Milano. His research interests include synthesis, verification simu-lation, and testing of digital circuits and sy stems. Ferrandi has a PhD in information and automation engineering from Politecnico di Milano. He is a member of IEEE and the IEEE Computer Society.']}}, {'name': 'Christian Pilato', 'affiliation': 'Politecnico di Milano', 'bio': {'p': ['Christian Pilato is pursuing a PhD in information technology at Politecnico di Milano. His research interests include high-level synthesis, evolutionary algorithms for design space exploration and multiobjective optimization, and multiprocessor design. Pilato has an MSc in computing systems engineering from Politecnico di Milano.']}}, {'name': 'Marco Lattuada', 'affiliation': 'Politecnico di Milano', 'bio': {'p': ['Marco Lattuada is pursuing a PhD in information technology at Politecnico di Mila-no. His research interests include automatic parallelization of sequential specification, high-level synthesis, and integer linear programming. Lattuada has an MSc in computing systems engineering from Politecnico di Milano.']}}, {'name': 'Donatella Sciuto', 'affiliation': 'Politecnico di Milano', 'bio': {'p': ['Donatella Sciuto is a full professor in the Department of Electronics and Information at Politecnico di Milano. Her research interests include embedded systems and multicore systems, including reconfigurable and adaptive systems. Sciuto has a PhD in electrical and computer engineering from the University of Colorado, Boulder. She is a member of IEEE.']}}, {'name': 'Andrea Michelotti', 'affiliation': 'Atmel Roma', 'bio': {'p': ['Andrea Michelotti is a hardware-software codesign manager at Atmel Roma. His technical interests include DSP (digital-signal processor) hardware and software design, embedded operating systems, system integration, and test vector generation. Michelotti has an MSc in physics from the Sapienza University of Rome.', 'Direct questions and comments about this article to Koen Bertels, Computer Engineering Lab, Faculty of Electrical Engineering, Mathematics, and Computer Science, Delft Univ. of Technology, Mekelweg 4, 2628 CD Delft, the Netherlands,. k.l.m.bertels@tudelft.nl', 'Selected CS articles and columns are also Cn available for free at http://ComputingNow.computer.org.']}} %*HArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5640604 %f/micro/ma8yoveoaukzw6cw4sfbxn9hpergdvrl.pdf %m2fd0a622ccc6bb76aa2a27c711cb469c %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'greenstein@kellogg.northwestern.edu'} %*Gatekeeping Economics %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5640606 %f/micro/hjfzaldeektubtdwix7joz258y1rvvow.pdf %mc7d3d89ca93c053934a372696011f5ed %cmicro %@[{'name': 'David H. Albonesi', 'affiliation': 'albonesi@csl.cornell.edu', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/5675636/5675642/5675642-photo-1-small.gif', 'p': ['David H. Albonesi']}} %*Moving Forward %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5675642 %f/micro/owrlmnycacsj8ixq2he6bpvdxyps70q3.pdf %m392bb8e97fadeeda1afa8ddfb8c1e633 %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'greenstein@kellogg.northwestern.edu'} %*Building Broadband Ahead of Digital Demand %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5675643 %f/micro/nu2xskab7xiqhvoe5s6urclzgdabytcd.pdf %mfe4202970789ee03dd4c57e168d74450 %cmicro %@[{'name': 'Ofer Shacham', 'affiliation': 'Stanford, Stanford', 'bio': {'p': ['Ofer Shacham is pursuing a PhD in electrical engineering at Stanford University. His research interests include highperformance and parallel computer architectures, and VLSI design and verification techniques. Shacham has an MS in electrical engineering from Stanford University.']}}, {'name': 'Omid Azizi', 'affiliation': 'Stanford, Stanford', 'bio': {'p': ['Omid Azizi is a member of the Chip Generator Group at Stanford University. He is also an engineer at Hicamp Systems in Menlo Park, California. He is also His research interests include systems design and optimization, with an emphasis on energy efficiency. Azizi has a PhD in electrical engineering from Stanford University. He is a member of IEEE.']}}, {'name': 'Megan Wachs', 'affiliation': 'Stanford, Stanford', 'bio': {'p': ['Megan Wachs is pursuing a PhD in electrical engineering at Stanford University. Her research interests include the development of hardware design and verification techniques. Wachs has an MS in electrical engineering from Stanford University.']}}, {'name': 'Stephen Richardson', 'affiliation': 'Stanford, Stanford', 'bio': {'p': ['Wajahat Qadeer is pursuing a PhD in electrical engineering at Stanford University. His research interests include design of highly efficient parallel computer systems for emerging applications. Wajahat has an MS in electrical engineering from Stanford University. He is a member of IEEE.']}}, {'name': 'Mark Horowitz', 'affiliation': 'Stanford, Stanford', 'bio': {'p': ['Zain Asgar is pursuing his PhD in electrical engineering at Stanford University.k He is also an engineer at NVIDIA. His research interests include multiprocessors and the design of next-generation graphics proces-sors. Asgar has an MS in electrical engineering from Stanford University.']}} %*Rethinking Digital Design: Why Design Must Change %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5567087 %f/micro/oclukhwi90wg2lfsmzn1bqr3xtjcudjp.pdf %m90b7f99cc1283edfcf888c4cc11a7a47 %cmicro %@[{'name': 'Christopher Hughes', 'affiliation': 'Intel, Santa Clara', 'bio': {'p': ['Christopher J. Hughes is a staff researcher at Intel Labs in Santa Clara, California. His research interests include parallel computer architecture and emerging workloads, in particular, memory systems for processors with many cores and wide single instruction, multiple data execution. Hughes has a PhD in computer science from the University of Illinois at Urbana-Champaign. He is a member of IEEE.']}}, {'name': 'Changkyu Kim', 'affiliation': 'Intel, Santa Clara', 'bio': {'p': ['Changkyu Kim is a research scientist at Intel Labs in Santa Clara, California. His research interests include high-performance micro-processors, memory systems, parallel processor architectures, and throughput computing. Kim has a PhD in computer science from the University of Texas at Austin. He is a member of IEEE.']}}, {'name': 'Yen-Kuang Chen', 'affiliation': 'Intel Corporation , Santa Clara', 'bio': {'p': ['Yen-Kuang Chen is a principal research scientist at Intel Labs in Santa Clara, California. His research interests include developing innovative multimedia applications, studying the performance bottlenecks in current computer platforms, and designing next-generation processor/platforms with multiple cores. Chen has a PhD in electrical engineering from Princeton University. He is a senior member of IEEE.']}} %*Performance and Energy Implications of Many-Core Caches for Throughput Computing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5601683 %f/micro/l7drok2tldf4ynj1vhzcm9qcyoseines.pdf %mbffd103e0ce7b2e45c3f1c17601a8891 %cmicro %@[{'name': 'Amin Ansari', 'affiliation': 'University of Michigan, Ann Arbor', 'bio': {'p': ["Amin Ansari is a PhD candidate in the electrical engineering and computer science department at the University of Michigan, Ann Arbor. His research interests include designing architectural and microarchitectur-al techniques for enhancing reliability of high-performance microprocessors in deep submicron technologies. Ansari has an MSE in computer science and engineering from the University of Michigan. He's a student member of IEEE and the ACM."]}}, {'name': 'Shuguang Feng', 'affiliation': 'University of Michigan, Ann Arbor', 'bio': {'p': ['Shuguang Feng is a PhD candidate in the electrical engineering and computer science department at the University of Michigan, Ann Arbor. His research interests include fault-tolerant, reconfigurable computer architectures and techniques for exploiting the interaction between software and hardware to enhance system reliability. Feng has an MSE in computer engineering from the University of Michigan, Ann Arbor.']}}, {'name': 'Shantanu Gupta', 'affiliation': 'University of Michigan, Ann Arbor', 'bio': {'p': ['Shantanu Gupta is a PhD candidate in the electrical engineering and computer science department at the University of Michigan, Ann Arbor. His research interests include compilers and architectures, with a focus on fault tolerance, power efficiency, and single-thread performance. Gupta has an MSE in computer engineering from the University of Michigan.']}}, {'name': 'Scott Mahlke', 'affiliation': 'University of Michigan, Ann Arbor', 'bio': {'p': ['Scott Mahlke is an associate professor in the electrical engineering and computer science department at the University of Michigan, Ann Arbor, where he leads the Compilers Creating Custom Processors research group. His research interests include compilers for multicore processors, application-specific processors for mobile computing, and reliable system design. Mahlke has a PhD in electrical engineering from the University of Illinois at Urbana-Champaign.', 'Direct questions and comments to Amin Ansari, 4861 CSE Bldg., Univ. of Michigan, 2260 Hayward St., Ann Arbor, MI 48109, ansary@umich.edu.']}} %*Putting Faulty Cores to Work %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5654490 %f/micro/n7hm9jb1xzqfyavtihpb03zcflu65a8y.pdf %m438d698a858c509715ee5933a1d674da %cmicro %@[{'name': 'Frederick Ryckbosch', 'affiliation': 'Ghent University, Gent', 'bio': {'p': ['Frederick Ryckbosch is a PhD student in the Electronics and Information Systems Department at Ghent University, Belgium. His research interests include computer architecture in general, and simulation of large-scale computer systems in particular. Ryckbosch has an MS in computer science and engineering from Ghent University.']}}, {'name': 'Stijn Polfliet', 'affiliation': 'Ghent University, Gent', 'bio': {'p': ['Stijn Polfliet is a PhD student in the Electronics and Information Systems Department at Ghent University, Belgium. His research interests include computer architecture in general, and simulation of large-scale computer systems in particular. Polfliet has an MS in computer science and engineering from Ghent University.']}}, {'name': 'Lieven Eeckhout', 'affiliation': 'Ghent University, Gent', 'bio': {'p': ['Lieven Eeckhout is an associate professor in the Electronics and Information Systems Department at Ghent University, Belgium. His research interests include computer architecture and the hardware/software inter-face, with a focus on performance analysis, evaluation and modeling, and workload characterization. Eeckhout has a PhD in computer science and engineering from Ghent University. He is a member of IEEE and the ACM.', 'Direct questions and comments about this article to Lieven Eeckhout, ELIS— University, Sint-Pietersnieuwstraat 41, B-9000 Gent, Belgium, leeckhou@elis.ugent.be.']}} %*Fast, Accurate, and Validated Full-System Software Simulation of x86 Hardware %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5654488 %f/micro/pmd4nyi6tahd3mzb09fkj2tlfrsahjlg.pdf %m1bbdd665a24409f0ddfcc2dfdf91127c %cmicro %@[{'name': 'Luk Van Ertvelde', 'affiliation': 'Ghent University, Ghent', 'bio': {'p': ['Luk Van Ertvelde is a PhD student in the Electronics and Information Systems Department at Ghent University, Belgium. His research interests include computer architecture in general, and workload characterization in particular. Van Ertvelde has an MS in computer science from Ghent University.']}}, {'name': 'Lieven Eeckhout', 'affiliation': 'Ghent University, Gent', 'bio': {'p': ['Lieven Eeckhout is an associate professor in the Electronics and Information Systems Department at Ghent University, Belgium. His research interests include computer architecture and the hardware/software interface in general, with a focus on performance analysis, evaluation and modeling, and workload characterization. Eeckhout has a PhD in computer science and engineering from Ghent University. He is a member of IEEE and the ACM.', 'Direct questions and comments about this article to Lieven Eeckhout, ELIS-Ghent University, Sint-Pietersnieuwstraat 41, B-9000 Gent, Belgium, leeckhou@eliseugent.be.']}} %*Workload Reduction and Generation Techniques %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5654489 %f/micro/lhsqxrm8oet2kqdjgbfgdnt03xhl4uzr.pdf %md799a9665e702313248a6f99c5164f0d %cmicro %@[{'name': 'Roberto Airoldi', 'affiliation': 'Tampere University of Technology, Tampere', 'bio': {'p': ['Roberto Airoldi is a PhD student in computer systems and a researcher at Tampere University of Technology. His research interests include multiprocessor systems on chip, software-defined radios, cognitive radios, and wireless communications. Airoldi has an MSc in microelectronics from the University of Bologna.']}}, {'name': 'Omer Anjum', 'affiliation': 'Tampere University of Technology, Tampere', 'bio': {'p': ["Omer Anjum is a PhD student at Tampere University of Technology, Finland. His research interests include computer architecture, digital signal processing, and digital transmission. Anjum has a master's degree in information technology from Tampere University of Technology."]}}, {'name': 'Fabio Garzia', 'affiliation': 'Tampere University of Technology, Tampere', 'bio': {'p': ['Fabio Garzia is a research fellow at Tampere University of Technology. His research interests include system-on-chip design, reconfigurable architectures, and platforms for 3D graphics, multimedia and SDR applications. Garzia has a doctor of science in technology from the Tampere University of Technology.']}}, {'name': 'Alexander Wyglinski', 'affiliation': 'Worcester Polytechnic Institute', 'bio': {'p': ['Jari Nurmi is a professor of computer systems at Tampere University of Technol-ogy. His current research interests include system-on-chip integration, on-chip commu-nication, embedded and application-specific processor architectures, and circuit implementations of digital communication, positioning and DSP systems. Nurmi has a PhD in computer systems from Tampere University of Technology. He is a senior member of the IEEE Circuits and Systems Society, Computer Society, Signal Processing Society, Solid-State Circuits Society, and Communications Society.']}}, {'name': 'Jari Nurmi', 'affiliation': 'Tampere University of Technology, Tampere', 'bio': {'p': ['Alexander M. Wyglinski is an assistant professor of electrical and computer engineering at Worcester Polytechnic Insti-tute, director of the WPI Limerick Project Center, and director of the Wireless Innovation Laboratory. His research interests include wireless communications, wireless networks, cognitive radios, software-defined radios, transceiver optimization algorithms, dynamic spectrum access networks, spectrum sensing techniques, machine learning techniques for communication systems, and signal processing techniques for digital communications. Wyglinski has a PhD in electrical engineering from McGill University. He is a member of IEEE, the IEEE Communications Society, IEEE Signal Processing Society, IEEE Vehicular Technology Society, IEEE Women in Engineering, and Sigma Xi.']}} %*Energy-Efficient Fast Fourier Transforms for Cognitive Radio Systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5601684 %f/micro/oh8wwlupy0xmbgfqskofge67bxhnznlk.pdf %m2bc327569e0ed64c19ddf47f76ecac3c %cmicro %@[{'name': 'Richard Mateosian', 'affiliation': 'xrm@pacbell.net'} %*Being Geek %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5675645 %f/micro/ybvskpffwradehpisluox8arbojmxv30.pdf %me304993555b6a5055b5b96d176aecae4 %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'greenstein@kellogg.northwestern.edu', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/4796159/4796163/4796163-photo-1-small.gif', 'p': []}} %*Symptoms of Healthy Innovativeness %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4796163 %f/micro/y0k3bsq4uithbmel2qxrlfm18androyn.pdf %mf340d81dc1aaccedcb8a07487c3485dd %cmicro %@[{'name': 'Joel Emer', 'affiliation': 'Intel', 'bio': {'p': ['Joel Emer is an Intel Fellow and director of microarchitecture research at Intel. His current research interests include memory hierarchy design, processor reliability, FPGA-based computation, and performance modeling. Emer has a PhD in electrical engineering from the University of Illinois at Urbana-Champaign. He is a Fellow of both the ACM and the IEEE.']}}, {'name': 'Dean Tullsen', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Dean Tullsen is a professor in the Computer Science and Engineering Department at the University of California, San Diego. His research is on the architecture of highperformance processors, including multicore and multithreaded processors. Tullsen has a PhD in computer science and engineering from the University of Washington. He is a Fellow of the IEEE and a member of the ACM.']}} %*Top Picks from the 2008 Computer Architecture Conferences %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4796164 %f/micro/te3fcmuprm8n1obpx5hywcd9fhvbd2al.pdf %mc1559a80406a1117dd88af26f551598e %cmicro %@[{'name': 'Larry Seiler', 'affiliation': 'Intel Corporation', 'bio': {'p': ["Larry Seiler is a senior principal engineer with Intel's Visual Computing Group, working on graphics APIs and algorithms for Larrabee. He has a PhD in computer science from MIT."]}}, {'name': 'Doug Carmean', 'affiliation': 'Intel Corporation', 'bio': {'p': ["Doug Carmean is an Intel fellow and Larrabee chief architect in the Visual Computing Group of Intel's Digital Enterprise Group. He has a bachelor's degree in electrical engineering from Oregon State University."]}}, {'name': 'Eric Sprangle', 'affiliation': 'Intel Corporation', 'bio': {'p': ["Eric Sprangle is a principal engineer with Intel's Visual Computing Group and a lead architect on the Larrabee project. He has an MS in computer architecture from the University of Michigan."]}}, {'name': 'Tom Forsyth', 'affiliation': 'Intel Corporation', 'bio': {'p': ['Tom Forsyth is a software and hardware architect working on the Larrabee project at Intel. He has an MA in computer science from Cambridge University.']}}, {'name': 'Pradeep Dubey', 'affiliation': 'Intel Corporation', 'bio': {'p': ['Michael Abrash is a programmer at RAD Games Tools. He has an MS in energy management and policy from the University of Pennsylvania.']}}, {'name': 'Stephen Junkins', 'affiliation': 'Intel Corporation', 'bio': {'p': ['Pradeep Dubey is a senior principal engineer in the Microprocessor Technology Lab at Intel working on emerging applications for Larrabee. He has a PhD in electrical engineering from Purdue University. He is a Fellow of the IEEE.']}}, {'name': 'Adam Lake', 'affiliation': 'Intel Corporation', 'bio': {'p': ["Stephen Junkins is a principal engineer in Intel's Software Services Group. He has an MS in computer science from Clemson University."]}}, {'name': 'Robert Cavin', 'affiliation': 'Intel Corporation', 'bio': {'p': ["Adam Lake is a senior software architect with Intel's Advanced Visual Computing group. He has an MS in computer science from the University of North Carolina, Chapel Hill."]}}, {'name': 'Roger Espasa', 'affiliation': 'Intel Corporation', 'bio': {'p': ['Jeremy Sugerman is a PhD candidate in computer science at Stanford University and a principal engineer at VMware. He has an MS in computer science with a systems concentration from Stanford University.']}}, {'name': 'Ed Grochowski', 'affiliation': 'Intel Corporation', 'bio': {'p': ['Robert Cavin is a senior architect on the Larrabee Project at Intel and a primary contributor to the ISA, execution engine design and implementation, and performance projections. He has an MS in computer engineering and electrical engineering from the University of Florida.']}}, {'name': 'Toni Juan', 'affiliation': 'Intel Corporation', 'bio': {'p': ["Roger Espasa is a principal engineer with Intel's Visual Computing Group. He has a PhD in computer architecture from the Universitat Politècnica de Catalunya."]}}, {'name': 'Michael Abrash', 'affiliation': 'RAD Game Tools', 'bio': {'p': ['Ed Grochowski is a senior principal engineer at Intel, working on the architecture of the Larrabee core. He has an MS in electrical engineering from the University of California, Berkeley.']}}, {'name': 'Jeremy Sugerman', 'affiliation': 'Stanford University', 'bio': {'p': ["Toni Juan is a principal engineer at Intel and the architect of Larrabee's on-die interconnect, tag-directory, and the memory controller. He has a PhD in computer engineering from the Universitat Politècnica de Catalunya."]}}, {'name': 'Pat Hanrahan', 'affiliation': 'Stanford University', 'bio': {'p': ['Pat Hanrahan is the CANON Professor of Computer Science and Electrical Engineering at Stanford. He has a PhD in biophysics from the University of Wisconsin.', 'Direct questions and comments about this article to Pradeep Dubey, Intel Corp., 3600 Juliette Lane, Santa Clara, CA 95054, Pradeep. Dubey@intel.com.', 'For more information on this or any other computing topic, please visit our Digital Library at http://computer.org/csdl.']}} %*Larrabee: A Many-Core x86 Architecture for Visual Computing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4796165 %f/micro/pflyoo9shnmrtl7is2kghyrbtxvqg0xe.pdf %m18ba07d6ee217978e2ab05860d130605 %cmicro %@[{'name': 'Onur Mutlu', 'affiliation': 'Carnegie Mellon University', 'bio': {'p': ['Onur Mutlu is an assistant professor of electrical and computer engineering at Carnegie Mellon University. His research interests include computer architecture and systems research. Mutlu has a PhD in electrical and computer engineering from the University of Texas, Austin.']}}, {'name': 'Thomas Moscibroda', 'affiliation': 'Microsoft Research', 'bio': {'p': ['Thomas Moscibroda is a researcher at Microsoft Research in Redmond. His research focuses on distributed computing, networking, and algorithmic aspects of computer architecture. Moscibroda has a PhD in computer science from ETH Zurich.', 'Direct questions and comments about this article to Onur Mutlu, Carnegie Mellon University, ECE Dept., 5000 Forbes Ave., Pittsburgh, PA 15213, onur@cmu.edu.', 'For more information on this or any other computing topic, please visit our Digital Library at http://computer.org/csdl.']}} %*Parallelism-Aware Batch Scheduling: Enabling High-Performance and Fair Shared Memory Controllers %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4796166 %f/micro/n2kqgutvp49qijr0ywgbxcfhzellcoid.pdf %m7638972136ce08bbea09db81768196e1 %cmicro %@[{'name': 'John Kim', 'affiliation': 'Northwestern University', 'bio': {'p': ["John Kim is a research assistant professor at Northwestern University. His research interests include computer architecture and interconnection networks. Kim has a PhD in electrical engineering from Stanford University. He's a member of the IEEE and the ACM."]}}, {'name': 'William Dally', 'affiliation': 'Stanford University', 'bio': {'p': ["William Dally is the Willard R. and Inez Kerr Bell Professor of Engineering and the chair of the Department of Computer Science at Stanford University. He's also cofounder, chair, and chief scientist of Stream Processors. His research interests include computer architecture, network ar-chitecture, and programming systems. Dally has a PhD in computer science from the California Institute of Technology. He's a Fellow of the IEEE, the ACM, and the American Academy of Arts and Sciences."]}}, {'name': 'Steve Scott', 'affiliation': 'Cray', 'bio': {'p': ["Steve Scott is the chief technology officer at Cray. His research interests include processor and system architecture and interconnection networks. Scott has a PhD in computer architecture from the University of Wisconsin. He's a member of the IEEE and ACM."]}}, {'name': 'Dennis Abts', 'affiliation': 'Google', 'bio': {'p': ["Dennis Abts is a member of the technical staff at Google, where he's a technical lead for a next-generation large-scale network. His research interests include parallel computer architecture, interconnection networks, memory system design, robust system design, and fault tolerance. Abts has a PhD in computer science from the University of Minnesota. He's a member of the IEEE, ACM, and IEEE Computer Society.", 'Direct questions and comments about this article to John Kim at Northwestern Univ., 2145 Sheridan Rd., Evanston, IL 60208, jjk12@northwestern.edu.', 'For more information on this or any other computing topic, please visit our Digital Library at http://computer.org/csdl.']}} %*Cost-Efficient Dragonfly Topology for Large-Scale Systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4796167 %f/micro/wjjizzqf2kmayioydsnw7xlpq6ph34c9.pdf %m2da869a251f236c77bc0b3558e1f571e %cmicro %@[{'name': 'Kevin Lim', 'affiliation': 'University of Michigan', 'bio': {'p': ['Kevin Lim is a PhD candidate in the Computer Science and Engineering Department at the University of Michigan. His research interests include data-center-level architectures, memory systems, and simulators. Lim has an MSE in computer science and engineering from the University of Michigan.']}}, {'name': 'Parthasarathy Ranganathan', 'affiliation': 'Hewlett-Packard Labs', 'bio': {'p': ['Parthasarathy Ranganathan is a distinguished technologist at Hewlett-Packard Labs. His research interests include systems architecture and power efficiency. Ranganathan has a PhD in electrical and computer engineering from Rice University. He is a senior member of the IEEE and ACM.']}}, {'name': 'Jichuan Chang', 'affiliation': 'Hewlett-Packard Labs', 'bio': {'p': ['Jichuan Chang is researcher at Hewlett Packard Labs. His research interests include computer systems architecture and memory systems. Chang has a PhD in computer science from the University of Wisconsin Madison. He is a member of the ACM.']}}, {'name': 'Chandrakant Patel', 'affiliation': 'Hewlett-Packard Labs', 'bio': {'p': ['Chandrakant Patel is a Hewlett-Packard Fellow and director of the Sustainable Information Technology Laboratory at Hewlett-Packard Labs. His research interests include creating an IT ecosystem to enable net-positive impact on the environment. Patel has an MS in mechanical engineering from San Jose State University and is a licensed professional mechanical engineer in California. He is an IEEE Fellow.']}}, {'name': 'Trevor Mudge', 'affiliation': 'University of Michigan', 'bio': {'p': ['Trevor Mudge is the first Bredt Family Professor of Computer Science and Engineering at the University of Michigan. His research interests include computer architecture, VLSI, and compilers. Mudge has a PhD in computer science from the University of Illinois, Urbana-Champaign. He is a member of the ACM, the Institution of Engineering and Technology, and the British Computer Society, and is a Fellow of the IEEE.']}}, {'name': 'Steven K. Reinhardt', 'affiliation': 'University of Michigan', 'bio': {'p': ["Steven K. Reinhardt is a Fellow in AMD's Research and Advanced Development Labs and an adjunct associate professor at the University of Michigan. His research interests include computer system architecture. Reinhardt has a PhD in computer sciences from the University of Wisconsin-Madison. He is a member of the IEEE and ACM."]}} %*Server Designs for Warehouse-Computing Environments %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4796168 %f/micro/yxnvsuvkqon3qb82fapmdi7ll6ahc0x4.pdf %m5c66be7cb705643dd86b5700cf28c966 %cmicro %@[{'name': 'Sudhanva Gurumurthi', 'affiliation': 'University of Virginia', 'bio': {'p': ['Sudhanva Gurumurthi is an assistant professor in the Computer Science Department at the University of Virginia. His research interests include energy-efficient data center architectures and silicon reliability. Guru-murthi has a PhD in computer science and engineering from Penn State University. He is a member of the ACM and the IEEE.']}}, {'name': 'Sriram Sankar', 'affiliation': 'Microsoft', 'bio': {'p': ['Sriram Sankar is a member of the Hardware Performance and Standards team at Microsoft. His research interests include computer architecture and storage systems. Sankar has an MS in computer science from the University of Virginia. He is a member of the ACM.']}}, {'name': 'Mircea R. Stan', 'affiliation': 'University of Virginia', 'bio': {'p': ['Mircea R. Stan is a professor in the Charles L. Brown Department of Electrical and Computer Engineering at the University of Virginia. His research interests include high-performance and low-power VLSI, temperature-aware circuits and architecture, and embedded systems. Stan has a PhD in electrical and computer engineering from the University of Massachusetts at Amherst. He is a member of the ACM and the Institution of Engineering and Technology and a senior member of the IEEE.', 'Direct questions and comments about this article to Sudhanva Gurumurthi, Dept. of Computer Science, Univ. of Virginia, Charlottesville, VA 22904, gurumurthi@cs.virginia.edu.', 'For more information on this or any other computing topic, please visit our Digital Library at http://computer.org/csdl.']}} %*Using Intradisk Parallelism to Build Energy-Efficient Storage Systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4796169 %f/micro/qsczoihnecgm80rkho7wptmvad9gxfb5.pdf %mfabac77a42e76136db5bc12ac59cce49 %cmicro %@[{'name': 'Shimin Chen', 'affiliation': 'Intel Research Pittsburgh', 'bio': {'p': ['Shimin Chen is a research scientist at Intel Research Pittsburgh. His research interests include database systems, computer architecture, operating systems and distributed systems, with special emphasis on exploiting modern hardware features for software correctness, performance, and power efficiency. Chen hasa PhD in computer science from Carnegie Mellon University.']}}, {'name': 'Michael Kozuch', 'affiliation': 'Intel Research Pittsburgh', 'bio': {'p': ['Michael Kozuch is a principal researcher with Intel. His interests include processor microarchitecture and cluster architecture, he is particularly interested in the interaction of virtualization with these two topics. Kozuch has a PhD in electrical engineering from Princeton University.']}}, {'name': 'Phillip B. Gibbons', 'affiliation': 'Intel Research Pittsburgh', 'bio': {'p': ['Theodoros Strigkos is a PhD student in electrical and computer engineering at Carnegie Mellon University. His research interests include microarchitecture and multiprocessor architecture. Strigkos has an MS in electrical and computer engineering from Carnegie Mellon University. He is a student member of the ACM.']}}, {'name': 'Michael Ryan', 'affiliation': 'Intel Research Pittsburgh', 'bio': {'p': ['Babak Falsafi is a professor in the School of Computer and Communication Sciences and directs the Parallel Systems Architecture Laboratory at Ecole Polytechnique Federale de Lausanne. His research targets architectural support for parallel programming, resilient systems, architectures to break the memory wall, and analytic and simulation tools for computer system performance evaluation. Falsafi has a PhD in computer science from University of Wisconsin at Madison. He is a senior member of the IEEE and the ACM.']}}, {'name': 'Theodoros Strigkos', 'affiliation': 'Carnegie Mellon University', 'bio': {'p': ['Phillip B. Gibbons is a principal research scientist at Intel Research Pittsburgh. His research interests include parallel and distributed computing, databases, and sensor networks. Gibbons has a PhD in computer science from the University of California at Berkeley. He is a Fellow of the ACM.']}}, {'name': 'Todd C. Mowry', 'affiliation': 'Carnegie Mellon University', 'bio': {'p': ['Todd C. Mowry is a professor in the Computer Science Department at Carnegie Mellon University. He currently co-leads the Claytronics project and the Log-Based Architectures project. His research interests span a broad set of systems areas, as well as database performance and modular robotics. Mowry has a PhD in electrical engineering from Stanford University.']}}, {'name': 'Olatunji Ruwase', 'affiliation': 'Carnegie Mellon University', 'bio': {'p': ['Vijaya Ramachandran is a professor of computer science at the University of Texas at Austin. Her research interests are in algorithm design and analysis, graph theory, data structures, and algorithms for multicore computing. Ramachandran has a PhD in electrical engineering and computer science from Princeton University. She serves on the Editorial Boards of Journal of the ACM, SIAM Journal on Computing, and ACM Transactions on Algorithms.']}}, {'name': 'Evangelos Vlachos', 'affiliation': 'Carnegie Mellon University', 'bio': {'p': ['Olatunji Ruwase is a computer science PhD student at Carnegie Mellon University. His research interests are in compilers and computer architecture. Ruwase has an MSc in computer science from Stanford University.']}}, {'name': 'Babak Falsafi', 'affiliation': 'École Polytechnique Fédérale de Lausanne', 'bio': {'p': ['Michael Ryan is a research engineer at Intel Research Pittsburgh. His interests include systems-level development, emulation, rapid application development, and cloud computing. Ryan has a BS in computer science from Carnegie Mellon University.']}}, {'name': 'Vijaya Ramachandran', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ['Evangelos Vlachos is a PhD student in electrical and computer engineering at Carnegie Mellon University. His research interests include computer architecture. Vlachos has an MSc in computer science from the University of Crete, Greece. He is a student member of the ACM.', 'Direct questions and comments about this article to Shimin Chen, Intel Research Pitts-burgh, 4720 Forbes Ave., Ste. 410, Pittsburgh, PA 15213, shimin.chen@intel.com.', 'For more information on this or any other computing topic, please visit our Digital Library at http://computer.org/csdl.']}} %*Flexible Hardware Acceleration for Instruction-Grain Lifeguards %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4796170 %f/micro/vamfs2qiyh4y9ozqrx8ce1t5jxgt7r6u.pdf %m13a2da48935e66120357ac91cf0f55f3 %cmicro %@[{'name': 'Brandon Lucia', 'affiliation': 'University of Washington', 'bio': {'p': ['Brandon Lucia is a graduate student in computer science at the University of Washington. His research interests include hardware support for dynamic analysis of concurrent software, with a focus on debugging and increasing software reliability. Lucia has a BS in computer science from Tufts University. He is a member of the ACM.']}}, {'name': 'Joseph Devietti', 'affiliation': 'University of Washington', 'bio': {'p': ['Joseph Devietti is a graduate student in computer science at the University of Washington. His research interests include parallel-programming models, and the intersection of architecture and programming languages. Devietti has a BS in engineering and computer science from the University of Pennsylvania. He is a member of the ACM.']}}, {'name': 'Luis Ceze', 'affiliation': 'University of Washington', 'bio': {'p': ['Karin Strauss is a researcher at the AMD Research and Advanced Development Labs and an affiliate assistant professor in the Department of Computer Science and Engineering at the University of Washington. Her research interests encompass multiprocessor systems and enabling technologies for multiprocessor adoption, including hardware support for debugging. She has a PhD in computer science from the University of Illinois at Urbana-Champaign. She is a member of the ACM and the IEEE.']}}, {'name': 'Karin Strauss', 'affiliation': 'AMD and University of Washington', 'bio': {'p': ['Luis Ceze is an assistant professor in the Department of Computer Science and Engineering at the University of Washington. His research interests include computer architecture and systems to improve the programmability of multiprocessor systems. He has a PhD in computer science from the University of Illinois at Urbana-Champaign. He is a member of the ACM and the IEEE.', 'Direct questions and comments about this article to Brandon Lucia, Dept. of Computer Science and Engineering, Univ. of Washington, PO Box 352350, Seattle, WA 98195, blucia0a@cs.washington.edu.', 'For more information on this or any other computing topic, please visit our Digital Library at http://computer.org/csdl.']}} %*Atom-Aid: Detecting and Surviving Atomicity Violations %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4796171 %f/micro/xlyjwaxf37bkgfeezq91usaq6mpwlktv.pdf %m12740a659e77f4e7c476747ef8cb617a %cmicro %@[{'name': 'James Tuck', 'affiliation': 'North Carolina State University', 'bio': {'p': ['James Tuck is an assistant professor of electrical and computer engineering at North Carolina State University. His research interests include the interaction between compilers and architectures to create software with better performance, power, and reliability. Tuck has a PhD in computer science from the University of Illinois, Urbana-Champaign. He is a member of the IEEE and ACM.']}}, {'name': 'Wonsun Ahn', 'affiliation': 'University of Illinois, Urbana-Champaign', 'bio': {'p': ['Wonsun Ahn is a doctoral candidate in the Department of Computer Science at the University of Illinois, Urbana Champaign. His research interests include compiler-hardware hybrid optimization and hardware support for ease of parallel programming. Ahn has a BS in computer science and engineering from Seoul National University.']}}, {'name': 'Josep Torrellas', 'affiliation': 'University of Illinois, Urbana-Champaign', 'bio': {'p': ['Luis Ceze is an assistant professor at the University of Washington. His research focuses on computer architecture and systems to improve the programmability of multiprocessor systems. Ceze has a PhD in computer science from the University of Illinois, Urbana-Champaign.', 'Josep Torrellas is a professor of computer science and Willett Faculty Scholar at the University of Illinois, Urbana-Champaign. His research interests include multiprocessor computer architecture and hardware and software reliability. Torrellas has a PhD in electrical engineering from Stanford University. He is an IEEE Fellow and a member of the ACM.', 'Direct questions and comments about this article to James Tuck, Center for Efficient, Secure, and Reliable Computing, North Carolina State Univ., Campus Box 7256, Raleigh, NC 27695–7256, jtuck@ncsu.edu.', 'For more information on this or any other computing topic, please visit our Digital Library at http://computer.org/csdl.']}}, {'name': 'Luis Ceze', 'affiliation': 'University of Washington'} %*SoftSig: Software-Exposed Hardware Signatures for Code Analysis and Optimization %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4796172 %f/micro/4jm7iuowgxaxg8lnymdowpauvsjrpynt.pdf %m74f8ce537ea8d6543b5bae2f00b42520 %cmicro %@[{'name': 'Chris Wilkerson', 'affiliation': 'Intel', 'bio': {'p': ['Chris Wilkerson is a research scientist in the Oregon Microarchitecture Lab at Intel. His research interests include low-power design including microarchitectural mechanisms to enable low-voltage operation for microprocessors Wilkerson has a combined BS and MS in electrical and computer engineering from Carnegie Mellon University.']}}, {'name': 'Hongliang Gao', 'affiliation': 'Intel', 'bio': {'p': ['Hongliang Gao is a computer architect in the Digital Enterprise Group at Intel in Oregon. His research interests include control-flow speculation, fault tolerance, and power efficiency in processor designs. Gao has a PhD in computer science from the University of Central Florida.']}}, {'name': 'Alaa R. Alameldeen', 'affiliation': 'Intel', 'bio': {'p': ['Alaa R. Alameldeen is a research scientist in the Oregon Microarchitecture Lab at Intel. His research interests include memory and cache design for multiprocessors and power-efficient processor design. Alameldeen has a PhD in computer science from the University of Wisconsin-Madison.', 'Zeshan Chishti is a research scientist in the Oregon Microarchitecture Lab at Intel. His research interests include energy-efficient microprocessor and memory design and cache hierarchies for chip multiprocessors. Chishti has a PhD in computer engineering from Purdue University.']}}, {'name': 'Zeshan Chishti', 'affiliation': 'Intel', 'bio': {'p': ['Muhammad Khellah is a research scientist in the Circuits Research Lab at Intel in Oregon. He works on embedded memories and interconnect circuits. Khellah has a PhD in electrical and computer engineering from the University of Waterloo.']}}, {'name': 'Muhammad Khellah', 'affiliation': 'Intel', 'bio': {'p': ['Shih-Lien Lu is a principal engineer and currently leads the Oregon Microarchitecture Lab at Intel. His research interests include resilient design and low power architecture. Lu has a PhD in computer science and engineering from the University of California, Los Angeles.', 'Direct questions and comments about this article to Alaa R. Alameldeen, 2111 NE 25th Ave., Mailstop JF2–04, Hillsboro, OR 97124, alaa.r.alameldeen@intel.com.', 'For more information on this or any other computing topic, please visit our Digital Library at http://computer.org/csdl.']}}, {'name': 'Shih-Lien Lu', 'affiliation': 'Intel'} %*Trading Off Cache Capacity for Low-Voltage Operation %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4796173 %f/micro/rpewjbkucevw0tivormudx1lcmla4i82.pdf %md7d434611688fd04f20124b7146f79bd %cmicro %@[{'name': 'René,e St. Amant', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ['Renée St. Amant is a PhD student in the Department of Computer Sciences at the University of Texas at Austin. Her research interests include low-power microarchitectures and new computing technologies. St. Amant has a BS in electrical and computer engineering from the University of Texas at Austin.']}}, {'name': 'Daniel A. Jimé,nez', 'affiliation': 'University of Texas at San Antonio', 'bio': {'p': ['Daniel Angel Jiménez is an associate professor in the Department of Computer Science at the University of Texas at San Antonio. His research interests include microarchitecture and low-level compiler optimizations. Jiménez has a PhD in computer sciences from the University of Texas at Austin. He is a member of the ACM.']}}, {'name': 'Doug Burger', 'affiliation': 'Microsoft Research', 'bio': {'p': ['Doug Burger is a principal researcher at Microsoft Research. His research interests include power-efficient, high-performance architectures, and approximate, general purpose mixed-signal design. Burger has a PhD in computer sciences from the University of Wisconsin-Madison. He is a senior member of the IEEE and a distinguished scientist of the ACM.', 'Direct questions and comments about this article to Renée St. Amant, Univ. of Texas at Austin, Dept. of Computer Sciences, 1 University Station C0500, Taylor Hall 2.12, Austin, TX 78712–0233, stamantt@cs. utexas.edu.', 'For more information on this or any other computing topic, please visit our Digital Library at http://computer.org/csdl.']}} %*Mixed-Signal Approximate Computation: A Neural Predictor Case Study %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4796174 %f/micro/za2tedqvdxcsjnnqeblmw7xfkjp4owyi.pdf %mb705ca417503914fec69c5bcc3853e6c %cmicro %@[{'name': 'Eren Kursun', 'affiliation': 'IBM Thomas J. Watson Research Center', 'bio': {'p': ['Eren Kursun is a research staff member in the Computer Architecture Department at the IBM T.J. Watson Research Center. Her research interests include power and temperature management of microprocessor architectures and low-power design. Kursun has a PhD in computer science from the University of California, Los Angeles. She is a member of the IEEE and ACM.']}}, {'name': 'Chen-Yong Cher', 'affiliation': 'IBM Thomas J. Watson Research Center', 'bio': {'p': ['Chen-Yong Cher is a research staff member in the Computer Architecture Department at the IBM T.J. Watson Research Center. His research interests include low-power and high-performance computing through microprocessor and software designs. Cher has a PhD in electrical and computer engineering from Purdue University.', 'Direct questions and comments about this article to Eren Kursun at IBM Research, 1101 Kitchawan Rd., Yorktown Heights, NY 10598, ekursun@us.ibm.com.', 'For more information on this or any other computing topic, please visit our Digital Library at http://computer.org/csdl.']}} %*Temperature Variation Characterization and Thermal Management of Multicore Architectures %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4796175 %f/micro/jevuraxjfbk5xzgkvsf2eylpddmn0o1r.pdf %m634459fc253014e404640e9d774083b0 %cmicro %@[{'name': 'Xiaoyao Liang', 'affiliation': 'Harvard University', 'bio': {'p': ['Xiaoyao Liang is pursuing a PhD in electrical engineering at Harvard University. His research interests include computer architecture and VLSI design, focusing on joint circuit and architecture solutions to combat process variability. Liang has an MS in electrical engineering from Stony Brook University.']}}, {'name': 'Gu-Yeon Wei', 'affiliation': 'Harvard University', 'bio': {'p': ['Gu-Yeon Wei is an associate professor of electrical engineering at Harvard University. His research interests include mixed-signal VLSI design for wireline data communication, energy-efficient computing devices for sensor networks, and collaborative software, architecture, and circuit techniques to combat variability in nanoscale technologies. Wei has a PhD in electrical engineering from Stanford University.']}}, {'name': 'David Brooks', 'affiliation': 'Harvard University', 'bio': {'p': ['David Brooks is an associate professor of computer science at Harvard University. His research interests include architectural and software approaches to address power, thermal, and reliability issues for embedded and high-performance computing systems. Brooks has a PhD in electrical engineering from Princeton University.', 'Direct questions and comments about this article to David Brooks, School of Engineering and Applied Sciences, Harvard Univ., Cambridge, MA 02138, dbrooks@eecs.harvard.edu.', 'For more information on this or any other computing topic, please visit our Digital Library at http://computer.org/csdl.']}} %*Revival: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4796176 %f/micro/wofsvhmq6j524ncs37ibbd08aquo19la.pdf %mf3094841ae191ca1f84696cfc2b139ea %cmicro %@[{'name': 'Richard H. Stern', 'affiliation': 'rstern@khhte.com', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/4796159/4796177/4796177-photo-1-small.gif', 'p': []}} %*One of the Last Updates on Rambus Standardization Skullduggery %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4796177 %f/micro/muh3goisiqncpfd1zewva0tjrmu7zb4c.pdf %m3ccf3451fd57e85ab429be3ef4384a30 %cmicro %@[{'name': 'Richard Mateosian', 'affiliation': 'xrm@pacbell.net'} %*System Green [review of Hot, Flat, and Crowded: Why We Need a Green Revolution and How It Can Renew America (Friedman, T.L.; 2008); 2008] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4796178 %f/micro/spftt8qju6zqmmyavyfn1dbhhgiua7ve.pdf %m96427f8646045e967489468f389a83c1 %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'greenstein@kellogg.northwestern.edu', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/4812126/4812130/4812130-photo-1-small.gif', 'p': ['SHANE GREENSTEIN']}} %*Building Broadband as Economic Stimulus %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4812130 %f/micro/w03g7ynbzzd48t6sfudobkophfeejmcv.pdf %m34f992433de2691b4d3c5a8232a4243e %cmicro %@[{'name': 'Christos Kozyrakis', 'affiliation': 'Stanford University', 'bio': {'p': ['Christos Kozyrakis is an assistant professor of electrical engineering and computer science at Stanford University. He works on architectures, runtime environments, and programming models for parallel computer systems. His current research focuses on transactional memory, architectural support for security, and power-management techniques. Kozyrakis has a PhD in computer science from the University of California at Berkeley. He is a senior member of the IEEE and the ACM.']}}, {'name': 'Jan-Willem van de Waerdt', 'affiliation': 'NXP Semiconductors', 'bio': {'p': ['Jan-Willem van de Waerdt is chief architect at NXP Semiconductors, where he works on next-generation video processing subsystems for consumer chips. He is the architect of several TriMedia media processors and several types of video processing blocks. He enjoys working in the cross-functional domain of hardware design, compiler/scheduler design, and application-domain-specific optimizations. Van de Waerdt has a PhD in electrical engineering from Delft University of Technology, the Netherlands. He holds 16 patents.', 'Direct questions and comments about this special issue to Christos Kozyrakis, christos@ee.stanford.edu, or Jan-Willem van de Waerdt, Jan-Willem.van_de_Waerdt@nxp.com.']}} %*Hot Chips Turns 20 [Guest editors' introduction] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4812131 %f/micro/pedvn3wg1swns7e4uqpuqkfrlxayhmyd.pdf %m75cd957b75cb3a865db84e5422acb80f %cmicro %@[{'name': 'Shailender Chaudhry', 'affiliation': 'Sun Microsystems', 'bio': {'p': ['Shailender Chaudhry is a distinguished engineer at Sun Microsystems, where he is chief architect of the Rock processor. His research interests include processor architecture, transactional memory, algorithms, and protocols. Chaudhry has an MS in computer engineering from Syracuse University.']}}, {'name': 'Robert Cypher', 'affiliation': 'Sun Microsystems', 'bio': {'p': ['Robert Cypher is a distinguished engineer and a chief system architect at Sun Micro-systems. His research interests include parallel computer architecture, processor architecture, transactional memory, and parallel programming. He has a PhD in computer science from the University of Washington.']}}, {'name': 'Magnus Ekman', 'affiliation': 'Sun Microsystems', 'bio': {'p': ['Magnus Ekman is a staff engineer at Sun Microsystems, where he is a performance architect. His research interests include processor architecture and memory system design. Ekman has a PhD in computer engineering from Chalmers University of Technology. He also has an MS in financial economics from Gothenburg University.']}}, {'name': 'Martin Karlsson', 'affiliation': 'Sun Microsystems', 'bio': {'p': ["Martin Karlsson is a staff engineer at Sun Microsystems, where he is a core architect working closely with the design team on Rock's microarchitecture. His research interests include transactional memory, instruction scheduling, and checkpoint-based architectures. He has a PhD in computer science from Uppsala University."]}}, {'name': 'Anders Landin', 'affiliation': 'Sun Microsystems', 'bio': {'p': ['Anders Landin is a distinguished engineer and a chief system architect at Sun Micro-systems. His research interests include multiprocessor system architecture, processor architecture, and application and system performance modeling. He has an MS in computer science and engineering from Lund University, Sweden.']}}, {'name': 'Sherman Yip', 'affiliation': 'Sun Microsystems', 'bio': {'p': ["Sherman Yip is a staff engineer at Sun Microsystems, where he is a core architect working closely with the design team on Rock's microarchitecture. His research interests include evaluating new processor features and efficient implementation of architectures that use deep speculation. Yip has a BS in computer science from the University of California at Davis."]}}, {'name': 'Hå,kan Zeffer', 'affiliation': 'Sun Microsystems', 'bio': {'p': ['Håkan Zeffer is a staff engineer at Sun Microsystems, where he is a system and performance architect. His research interests include parallel computer architecture, coherence, memory consistency, and system software. He has a PhD in computer science from Uppsala University.']}}, {'name': 'Marc Tremblay', 'affiliation': 'Sun Microsystems', 'bio': {'p': ["Marc Tremblay is a Sun Fellow, senior vice president, and chief technology officer for Sun's Microelectronics Group. In this role, Tremblay sets future directions for Sun's processor and system roadmap. His mission has been to move the entire Sparc processor product line to the throughput computing paradigm, incorporating techniques he has helped develop over the years-including multicores, multithreading, speculative multi-threading, scout threading, and transactional memory."]}} %*Rock: A High-Performance Sparc CMT Processor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4812132 %f/micro/c4ka2kfgrstwurqphwt1zyz08d9ixboy.pdf %m6d94076afdca01070cd62107e49c5b6d %cmicro %@[{'name': 'Weiwu Hu', 'affiliation': 'Institute of Computing Technology, Chinese Academy of Sciences', 'bio': {'p': ['Weiwu Hu is a professor of computer science at the Institute of Computing Technology, Chinese Academy of Sciences. His research interests include high-performance computer architecture, parallel processing, and VLSI design. Hu has a PhD in computer science from the Institute of Computing Technology.']}}, {'name': 'Jian Wang', 'affiliation': 'Institute of Computing Technology, Chinese Academy of Sciences', 'bio': {'p': ['Jian Wang is an associate professor of computer science at the Institute of Computing Technology, Chinese Academy of Sciences. His research interests include highperformance computer architecture and operating systems. Wang has an MS in computer science from the Institute of Computing Technology.']}}, {'name': 'Xiang Gao', 'affiliation': 'Institute of Computing Technology, Chinese Academy of Sciences', 'bio': {'p': ['Xiang Gao is an assistant professor of computer science at the Institute of Computing Technology, Chinese Academy of Sciences. His research interests include highperformance computer architecture, parallel processing, and operating systems. Gao has a PhD in computer science from the University of Science and Technology of China.']}}, {'name': 'Yunji Chen', 'affiliation': 'Institute of Computing Technology, Chinese Academy of Sciences', 'bio': {'p': ['Yunji Chen is an assistant professor of computer science at the Institute of Computing Technology, Chinese Academy of Sciences. His research interests include hardware verification and high-performance computer architecture. Chen has a PhD in computer science from the Institute of Computing Technology.']}}, {'name': 'Qi Liu', 'affiliation': 'Institute of Computing Technology, Chinese Academy of Sciences', 'bio': {'p': ['Qi Liu is a PhD candidate in computer science at the Institute of Computing Technology, Chinese Academy of Sciences. His research interests include computer architecture, virtualization, and binary translation. Liu has a BS in computer science from the University of Electronic Science and Technology of China.']}}, {'name': 'Guojie Li', 'affiliation': 'Institute of Computing Technology, Chinese Academy of Sciences', 'bio': {'p': ['Guojie Li is the director of the Institute of Computing Technology, Chinese Academy of Sciences, and an academician at the Chinese Academy of Engineering. His research interests include high-performance computer architecture, parallel algorithms, and artificial intelligence. Li received his PhD in computer science from Purdue University.']}} %*Godson-3: A Scalable Multicore RISC Processor with x86 Emulation %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4812133 %f/micro/7lvm0trpelpzi9kxd8u6efnb2tgjv53b.pdf %m70a93d9b51ca63796ac645e1e2e30df3 %cmicro %@[{'name': 'Richard Selvaggi', 'affiliation': 'Broadcom', 'bio': {'p': ['Richard Selvaggi is an associate technical director at Broadcom, working in the digital television group. His research interests include multiprocessor architecture and programming models, ISA design, configurable processors, platform-based design, and system modeling. Selvaggi has an MS in electrical and computer engineering from Carnegie Mellon University. He is a member of the IEEE and the IEEE Computer Society.']}}, {'name': 'Larry Pearlstein', 'affiliation': 'Broadcom', 'bio': {'p': ['Larry Pearlstein is a technical director of video algorithm development at Broadcom. His research interests include scalable video computing architectures and the development of practical algorithms for intelligent video processing. Pearlstein has a PhD in electrical engineering from Princeton University.']}} %*Broadcom mediaDSP: A Platform for Building Programmable Multicore Video Processors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4812134 %f/micro/wnsvhfsfgme7hcivmj1dylttuiq4ar2n.pdf %m6861bdd618d079b1c50510fe53ecaea0 %cmicro %@[{'name': 'Dan Mansur', 'affiliation': 'Altera', 'bio': {'p': ["Dan Mansur is director of Altera's Technology Office and contributor to field-programmable gate array research and product definition. His research interests include microprocessors, programmable logic and heterogeneous processing systems. Dan has a BSEE from the University of California, San Diego and a MBA from Santa Clara University."]}} %*A New 40-nm FPGA and ASIC Common Platform %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4812135 %f/micro/rhku5hlq8t2d34mivbnli9qu6npdfaba.pdf %m9f0ead25902044795374e89840835952 %cmicro %@[{'name': 'Lloyd Watts', 'affiliation': 'Audience', 'bio': {'p': ['Lloyd Watts is the founder, chair, and chief technology officer of Audience. His research interests include auditory signal processing and signal processor architecture. Watts has a PhD in electrical engineering from the California Institute of Technology. He is a member of the IEEE.']}}, {'name': 'Dana Massie', 'affiliation': 'Audience', 'bio': {'p': ['Dana Massie is the director of DSP architecture at Audience. His research interests include VLSI architectures and DSP algorithm development and implementation. Massie previously was director of the Creative Technology Advanced Technology Center, where he led the development of the EMU10K1, a multimedia coprocessor for PCs that accelerated environmental audio extensions.']}}, {'name': 'Allen Sansano', 'affiliation': 'Audience', 'bio': {'p': ['Allen Sansano is the director of VLSI engineering at Audience. His research interests include low-power VLSI design and system-on-chip architectures. Sansano has an MS in electrical engineering from the University of Washington.']}}, {'name': 'Jim Huey', 'affiliation': 'Audience', 'bio': {'p': ['Jim Huey is the vice president of VLSI engineering at Audience. His research interests include microprocessor architecture/design, Bayesian inference, and decision theory. Huey has a BS in electrical engineering and computer science from Duke University.']}} %*Voice Processors Based on the Human Hearing System %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4812136 %f/micro/jwpxvweqlqunt2korcd4fcxpegfzoyir.pdf %m31b1f73c795ba7f37e270a53480e52fb %cmicro %@[{'name': 'Richard Stern', 'affiliation': 'rstern@khhte.com'} %*IEEE-USA Tells Congress that Patent Reform Is Essential to Economic Recovery %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4812137 %f/micro/0vc87kqf6em4dbutakjrhnlapeymhgoz.pdf %m2a61f27de35714df77c2da7b69f6ea14 %cmicro %@[{'name': 'Richard Mateosian', 'affiliation': 'xrm@pacbell.net'} %*No More Wishful Thinking %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4812138 %f/micro/oeczvixudqh7mks4mzj5bk32gidaf0jw.pdf %m088fdedcde3355b0a77e7896231aab9b %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'greenstein@kellogg.northwestern.edu', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/5076428/5076433/5076433-photo-1-small.gif', 'p': []}} %*The Revolution in Spectrum Allocation %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5076433 %f/micro/zdkuqy5znbgef12hwoaptg0vnb6m9rpt.pdf %m32a0f1277e6b6740aed8c6c64cec77ee %cmicro %@[{'name': 'Markus Levy', 'affiliation': 'Embedded Microprocessor Benchmark Consortium and Multicore Association', 'bio': {'p': ['Markus Levy is president of the Embedded Microprocessor Benchmark Consortium and the Multicore Association, and chair of Multicore Expo. His research interests include embeddded processor performance and energy analysis and standards to support multicore system development. Levy has a BS in electrical engineering from San Francisco State University. He is the coauthor of Designing with Flash Memory (Annabooks, 1993) and has several patents related to flash memory architecture.']}}, {'name': 'Thomas M. Conte', 'affiliation': 'Georgia Institute of Technology', 'bio': {'p': ['Thomas M. Conte is a professor in the College of Computing at Georgia Institute of Technology. His research is in the areas of manycore/multicore architectures, microprocessor architectures, compiler code generation, architectural performance evaluation, and embedded computer systems. Conte has a PhD in electrical engineering from the University of Illinois at Urbana, Champaign. He is an associate editor of ACM Transactions on Embedded Computer Systems, ACM Transactions on Architecture and Compiler Optimization, Computer, and IEEE Micro.']}} %*Embedded Multicore Processors and Systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5076434 %f/micro/y0veluarwqtnxgifax8q9p4dkvw6zkzs.pdf %m34c4df8fb347c8da705def5575618954 %cmicro %@[{'name': 'Thomas B. Berg', 'affiliation': 'MIPS Technologies', 'bio': {'p': ['Thomas B. Berg is a staff engineer at MIPS Technologies, where he is a lead hardware developer of multicore and I/O-coherence technology. His interests include cache hierarchy, coherent multiprocessing computer systems, and I/O subsystem architecture. Berg received an MS in electrical engineering from Purdue University.']}} %*Maintaining I/O Data Coherence in Embedded Multicore Systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5076435 %f/micro/bp6otukcurpzbhgvwex72l85jjnq9av4.pdf %m1f4c2e29ee4d61c0dfb7e821b41ccf9e %cmicro %@[{'name': 'Jiang Xu', 'affiliation': 'Hong Kong University of Science and Technology', 'bio': {'p': ['Jiang Xu is an assistant professor in the Department of Electronic and Computer Engineering at Hong Kong University of Science and Technology. His research areas include systems on chip, networks on chip, multiprocessor systems, low-power VLSI design, nanoelectronic design, hardware/software codesign, and embedded systems. He has a PhD in electrical engineering from Princeton University.']}}, {'name': 'Wayne Wolf', 'affiliation': 'Georgia Institute of Technology', 'bio': {'p': ['Wayne Wolf is the Farmer Distinguished Chair and Georgia Research Alliance Eminent Scholar at the Georgia Institute of Technology. His research interests included embedded computing, embedded video and computer vision, and VLSI systems. Wolf has a PhD in electrical engineering from Stanford University. He is a Fellow of the IEEE and the ACM.']}}, {'name': 'Wei Zhang', 'affiliation': 'Princeton University', 'bio': {'p': ['Wei Zhang is a PhD candidate in the Electrical Engineering Department at Princeton University. Her research interests include embedded systems, nanotechnology-based VLSI design, low-power reconfigurable systems, nanoeletronic design automation, and bio-inspired electronic systems. She has an MS in electrical engineering from Harbin Institute of Technology, China.', 'Direct questions and comments about this article to Jiang Xu, Dept. of Electronic and Computer Engineering, Hong Kong Univ. of Science and Technology, Clear Water Bay, NT, Hong Kong, jiang.xu@ust.hk']}} %*Double-Data-Rate, Wave-Pipelined Interconnect for Asynchronous NoCs %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5076436 %f/micro/htqwpsvqbn89bared7u3dygfv02yixwh.pdf %m145f3a91765c1749539c06d613f44757 %cmicro %@[{'name': 'Jean-Yves Mignolet', 'affiliation': 'IMEC Belgium', 'bio': {'p': ['Jean-Yves Mignolet is an activity leader at IMEC Belgium. His research interests include design-time tools for multiprocessor systems-on-chip, digital design, reconfigurable hardware, processor and multiprocessor architecture, and modeling. He has an MSc in electrical engineering from the Université Catholique de Louvain, Louvain-La-Neuve, Belgium.']}}, {'name': 'Rogier Baert', 'affiliation': 'IMEC Belgium', 'bio': {'p': ['Rogier Baert is a researcher in the Digital Components group at IMEC Belgium. His research interests include all aspects of MPSoC design, in particular application mapping methods and runtime resource management techniques. Baert has an MSc in electrical engineering from the Eindhoven University of Technology, the Netherlands.']}}, {'name': 'Thomas J. Ashby', 'affiliation': 'IMEC Belgium', 'bio': {'p': ["Thomas Ashby is a senior research engineer in IMEC's Digital Components group. His research interests include embedded systems design and design automation for advanced industrial applications. Ashby has a PhD in computer science from the University of Edinburgh, UK."]}}, {'name': 'Prabhat Avasare', 'affiliation': 'IMEC Belgium', 'bio': {'p': ['Prabhat Avasare is a researcher at IMEC Belgium in the area of system-level design technologies. His main research interests include developing design technologies for heterogeneous multiprocessor system-on-chip platforms. Avasare has a BTech in electrical engineering from the Indian Institute of Technology.']}}, {'name': 'Hye-On Jang', 'affiliation': 'Samsung', 'bio': {'p': ["Hye-On Jang is a senior engineer on the SoC Platform Development Team at Samsung Electronics, where she's working on highperformance processor development and verification. Her research interests include parallel programming, multicore systems, and system verification methodologies. Jang has a BSc in electrical engineering from the University of Rochester in New York."]}}, {'name': 'Jae Cheol Son', 'affiliation': 'Samsung', 'bio': {'p': ['Jae Cheol Son is a vice president on the SoC Platform Development Team at Samsung Electronics, where he leads high-performance processor development. His research interests include high-performance microprocessor and VLSI design, multimedia processing, and statistical signal processing. Son has a PhD in electrical engineering from the Korea Advanced Institute of Science and Technology, Korea. He is a senior member of the IEEE.']}} %*MPA: Parallelizing an Application onto a Multicore Platform Made Easy %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5076437 %f/micro/gndtkrolyve8gus2faxvomi5bcqbjwhz.pdf %m2d8e4225adaff09a9d21aea42563d27a %cmicro %@[{'name': 'Jim Holt', 'affiliation': 'Freescale Semiconductor', 'bio': {'p': ['Jim Holt manages the Multicore Design Evaluation team in the Networking Systems Division at Freescale Semiconductor. His research interests include multicore-programming models and software architecture. He has a PhD in computer engineering from the University of Texas at Austin. He is a senior member of the IEEE.']}}, {'name': 'Anant Agarwal', 'affiliation': 'Massachusetts Institute of Technology', 'bio': {'p': ['Anant Agarwal is a professor in the Department of Electrical Engineering and Computer Science at the Massachusetts Institute of Technology, where he is also an associate director of the Computer Science and Artificial Intelligence Laboratory. In addition, he is a cofounder and CTO of Tilera. His research interests include computer architecture, VLSI, and software systems. He has a PhD in electrical engineering from Stanford University. He is an ACM Fellow and a member of IEEE.']}}, {'name': 'Sven Brehmer', 'affiliation': 'PolyCore Software', 'bio': {'p': ['Sven Brehmer is president and CEO of PolyCore Software, a company providing multicore software solutions. He has many different technical interests, including embedded systems software, multiprocessing, and alternative energy, especially multicore. He has an MS in electrical engineering from the Royal Institute of Technology, Sweden. He is the founding member of the Multicore Association and the MCAPI working group chair. He is a member of the Multicore Association.']}}, {'name': 'Max Domeika', 'affiliation': 'Intel', 'bio': {'p': ["Max Domeika is an embedded-tools consultant in the Developer Products Division at Intel, where he builds software products targeting the Embedded Intel Architecture. His technical interests include software development practices for multicore processors. He has a master's degree in computer science from Clemson University and a master's degree in management in science and technology from the Oregon Graduate Institute. He co-chairs the Multicore Programming Practices working group within the Multicore Association. He is the author of Software Development for Embedded Multicore Systems."]}}, {'name': 'Patrick Griffin', 'affiliation': 'Tilera', 'bio': {'p': ['Patrick Griffin is a senior design engineer on the software team at Tilera. His research interests include parallel-programming models and high-speed I/O for embedded applications. He has a MEng in electrical engineering and computer science from the Massachusetts Institute of Technology.']}}, {'name': 'Frank Schirrmeister', 'affiliation': 'Synopsys', 'bio': {'p': ['Frank Schirrmeister is director of Product Management in the Solutions Group at Synopsys. His research interests include electronic system-level design and verification, particularly presilicon virtual platforms for software development, architecture exploration, and verification. Schirrmeister has an MS in electrical engineering from the Technical University of Berlin with a focus on microelectronics and computer science. He is a member of the IEEE and the Association of German Engineers (VDI).']}} %*Software Standards for the Multicore Era %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5076438 %f/micro/ms5qyfojumz6ybvstuw1gpjpxti9vxra.pdf %m099ef4e9ef815a09668a38d06a10e765 %cmicro %@[{'name': 'Feng Wang', 'affiliation': 'Hong Kong University of Science and Technology', 'bio': {'p': ['Feng Wang is a financial quantitative analyst in a Chinese investment bank. His academic research interests are generally in computer networks. In particular, he is focusing on the design and analysis of high performance switches and routers. Wang has a PhD in computer science from the Hong Kong University of Science and Technology.']}}, {'name': 'Mounir Hamdi', 'affiliation': 'Hong Kong University of Science and Technology', 'bio': {'p': ['Mounir Hamdi is a full professor and head of the Department of Computer Science and Engineering at the Hong Kong University of Science and Technology. He is also director of the Master of Science program in Information Technology and director of the Computer Engineering and Networking Lab. His main research area of interest is high-speed wired and wireless networking. Hamdi has a PhD in electrical engineering from the University of Pittsburgh.']}} %*Memory Subsystems in High-End Routers %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5076439 %f/micro/cfmdcn0ihbngditjap78w1hkawju9rxy.pdf %m2555b5a529445cfdd0f0f16f73d6ba14 %cmicro %@[{'name': 'Richard Mateosian', 'affiliation': 'xrm@pacbell.net'} %*Software Architects [review of 97 Things Every Software Architect Should Know: Collective Wisdom from the Experts (Monson-Haefel, R., Ed.; 2009)] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5076440 %f/micro/fxtotzm83eqwsacgbd5rghl7jnvshofu.pdf %mc619c72bb5641788eabc407d78413d2d %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'greenstein@kellogg.northwestern.edu', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/5209924/5209928/5209928-photo-1-small.gif', 'p': ['Shane Greenstein greenstein@kellogg.northwestern.edu']}} %*Micro Economics: Soccer Mom Messaging Is the Poetry of Our Age %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5209928 %f/micro/rga1diuf0prezbgiosjhx69kcmy7wynm.pdf %m942a290b6bddf2960eb4e4ed7464b870 %cmicro %@[{'name': 'Keren Bergman', 'affiliation': 'Columbia University', 'bio': {'p': ['Keren Bergman is a professor of electrical engineering at Columbia University, where she also directs the Lightwave Research Laboratory. She leads multiple research programs on optical interconnection networks for advanced computing systems, terascale optical routers, wavelength-striped optical packet-switched networks, and chip multiprocessor nanophotonic networks on chip. Bergman has a PhD in electrical engineering from the Massachusetts Institute of Technology. She is a Fellow of the IEEE and the Optical Society of America, and currently serves as the co-editor in chief of the recently launched IEEE/OSA Journal of Optical Communications and Networking.']}}, {'name': 'Ron Brightwell', 'affiliation': 'Sandia National Laboratories', 'bio': {'p': ['Ron Brightwell is manager of the Scalable System Software Department at Sandia National Laboratories in Albuquerque, New Mexico. His research interests include highperformance scalable communication interfaces and protocols for system-area networks and lightweight operating systems for massively parallel computing systems. Brightwell has an MS in computer science from Mississippi State University. He is a senior member of the IEEE and the ACM.']}}, {'name': 'Fabrizio Petrini', 'affiliation': 'IBM TJ Watson Research Laboratory', 'bio': {'p': ['Fabrizio Petrini is a senior researcher of the Multicore Computing Department of the IBM TJ Watson Research Laboratory. His research interests include various aspects of high-performance interconnects, multicore processors and supercomputers, parallel architectures, operating systems, and parallel programming languages. Petrini has a PhD in computer science from the University of Pisa. He is associate editor of IEEE Transactions on Parallel and Distributed Processing.']}} %*Guest Editors' Introduction: Hot Interconnects %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5209930 %f/micro/yycp72vfr3fmv0xahoguijxmdpw91inj.pdf %mfd043ea110af351c62957c2f76456a67 %cmicro %@[{'name': 'Christopher Batten', 'affiliation': 'Massachusetts Institute of Technology', 'bio': {'p': ['Christopher Batten is a PhD candidate in the Electrical Engineering and Computer Science Department at the Massachusetts Institute of Technology. His research interests include energy-efficient parallel computer systems and architectures for emerging technologies. Batten has an MPhil in engineering from the University of Cambridge.']}}, {'name': 'Ajay Joshi', 'affiliation': 'Massachusetts Institute of Technology', 'bio': {'p': ["Ajay Joshi is a postdoctoral associate in MIT's Research Laboratory of Electronics. His research interests include interconnect modeling, network-on-chip design, high-speed low-power digital design, and physical design. Joshi has a PhD in electrical engineering from the Georgia Institute of Technology."]}}, {'name': 'Jason Orcutt', 'affiliation': 'Massachusetts Institute of Technology', 'bio': {'p': ["Jason Orcutt is a PhD candidate in MIT's Electrical Engineering and Computer Science Department. His research interests include device and process design for CMOS photonic integration. Orcutt has an MS in electrical engineering from MIT."]}}, {'name': 'Anatol Khilo', 'affiliation': 'Massachusetts Institute of Technology', 'bio': {'p': ["Anatol Khilo is a PhD candidate in MIT's Electrical Engineering and Computer Science Department. His research interests include the design of nanophotonic devices and photonic analog-to-digital conversion. Khilo has an MS in electrical engineering from MIT."]}}, {'name': 'Benjamin Moss', 'affiliation': 'Massachusetts Institute of Technology', 'bio': {'p': ["Benjamin Moss is an MS candidate in MIT's Electrical Engineering and Computer Science Department. His research interests include circuit design and modeling for integrated photonic CMOS systems. Moss has a BS in electrical engineering, computer science, and computer engineering from the Missouri University of Science and Technology."]}}, {'name': 'Charles W. Holzwarth', 'affiliation': 'Massachusetts Institute of Technology', 'bio': {'p': ["Charles W. Holzwarth is a PhD candidate in MIT's Material Science and Engineering Department. His research interests include the development of nanofabrication techniques for integrated electronic-photonic systems. Holzwarth has a BS in material science and engineering from the University of Illinois at Urbana-Champaign."]}}, {'name': 'Miloš, A. Popovic', 'affiliation': 'Massachusetts Institute of Technology', 'bio': {'p': ["Milo Å¡ A. Popović is a postdoctoral associate in MIT's Research Laboratory of Electronics. His research interests include the design and fundamental limitations of nanophotonic devices, energy-efficient electronic-photonic circuits, and nano-optomechanical photonics based on light forces. Popović has a PhD in electrical engineering from MIT."]}}, {'name': 'Hanqing Li', 'affiliation': 'Massachusetts Institute of Technology', 'bio': {'p': ["Hanging Li is a research scientist with MIT's Microsystems Technology Laboratories. His research interests include MEMS fabrication technologies, photonics, energy harvesting, and micro sensors and actuators. Li has a PhD in physics from the University of Nebraska-Lincoln."]}}, {'name': 'Henry I. Smith', 'affiliation': 'Massachusetts Institute of Technology', 'bio': {'p': ["Henry I. Smith is a professor in MIT's Electrical Engineering and Computer Science Department and is president of LumArray, a spin-off from MIT developing a maskless photolithography system. He supervises research in nanofabrication technology and applications thereof in electronics, photonics, and materials science. Smith has a PhD from Boston College."]}}, {'name': 'Judy L. Hoyt', 'affiliation': 'Massachusetts Institute of Technology', 'bio': {'p': ["Judy L. Hoyt is a professor in MIT's Electrical Engineering and Computer Science Department and associate director of MIT's Microsystems Technology Laboratories. Her research interests include fabrication and device physics of silicon-based heterostructures and nanostructures, such as high mobility Si and Ge-channel MOSFETs, nanowire FETs, novel transistor structures, and photodetectors for electronic/photonic integrated circuits. Hoyt has a PhD in applied physics from Stanford University."]}}, {'name': 'Franz X. Kartner', 'affiliation': 'Massachusetts Institute of Technology', 'bio': {'p': ["Franz X. Kärtner is a professor in MIT's Electrical Engineering and Computer Science Department. His research interests include classical and quantum noise in electronic and optical devices as well as femtosecond lasers and their applications in frequency metrology. Kärtner has a PhD in electrical engineering from Technische Universitat München, Germany."]}}, {'name': 'Rajeev J. Ram', 'affiliation': 'Massachusetts Institute of Technology', 'bio': {'p': ["Rajeev J. Ram is a professor in MIT's Electrical Engineering and Computer Science Department, director of the MIT Center for Integrated Photonic Systems, and associate director of the Research Laboratory of Electronics. His research interests include optoelectronic devices for applications in communications, biological sensing, and energy production. Ram has a PhD in electrical engineering from the University of California, Santa Barbara."]}}, {'name': 'Vladimir Stojanovic', 'affiliation': 'Massachusetts Institute of Technology', 'bio': {'p': ["Vladimir Stojanović is an assistant professor in MIT's Electrical Engineering and Computer Science Department. His research interests include high-speed electrical and optical links and networks, communications and signal-processing architectures, and high-speed digital and mixed-signal IC design. Stojanović has a PhD in electrical engineering from Stanford University."]}}, {'name': 'Krste Asanovic', 'affiliation': 'University of California, Berkeley', 'bio': {'p': ['Krste Asanović is an associate professor in the Electrical Engineering and Computer Science Department at the University of California, Berkeley. His research interests include computer architecture, VLSI design, and parallel programming. Asanović has a PhD in computer science from the University of California, Berkeley.']}} %*Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5209931 %f/micro/xhpyw16xufpbdcvzh3f0sc4n9iykadtm.pdf %m0e2dfe1c6ea0bc1f110f8fe69be0c2ad %cmicro %@[{'name': 'Nikos Chrysos', 'affiliation': 'Foundation for Research and Technology—,Hellas', 'bio': {'p': ['Nikos Chrysos is a postdoctoral fellow with IBM Research in Zurich. His current research interests include algorithms and hardware for multiprocessor interconnection networks and optical networks. Chrysos has a PhD in computer science from the University of Crete.']}}, {'name': 'Giorgos Dimitrakopoulos', 'affiliation': 'Foundation for Research and Technology—,Hellas', 'bio': {'p': ['Giorgos Dimitrakopoulos is a postdoctoral fellow at the Institute of Computer Science of the Foundation for Research and Technology—Hellas (FORTH) and a visiting assistant professor at the University of Crete. His research interests include VLSI design, computer architecture, and energy optimization of digital systems. Dimitrakopoulos has a PhD in computer engineering from the University of Patras.']}} %*Practical High-Throughput Crossbar Scheduling %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5209932 %f/micro/udcihgzv6g7np2iqmkahort45lmjyqex.pdf %mc270cc304e3035afe41937de1cd8bbd9 %cmicro %@[{'name': 'John Feehrer', 'affiliation': 'Sun Microsystems', 'bio': {'p': ["John Feehrer is the CoHub architecture lead in Sun Microsystems' Microelectronics Group in Burlington, Massachusetts. His research interests include computer architecture and I/O interconnection networks. Feehrer has a PhD from the University of Colorado, Boulder. He is a member of the IEEE."]}}, {'name': 'Paul Rotker', 'affiliation': 'Sun Microsystems', 'bio': {'p': ["Paul Rotker is the ASIC integration and physical design lead in Sun Microsystems' Microelectronics Group in Burlington, Massachusetts. His research interests include microprocessor design, physical design, and SerDes design. Rotker has a BSEE from Northeastern University."]}}, {'name': 'Milton Shih', 'affiliation': 'Sun Microsystems', 'bio': {'p': ["Milton Shih is the CoHub functional design lead in Sun Microsystems' Microelectronics Group in Burlington, Massachusetts. His research interests include multithreaded and parallel computing. Shih has an MS in computer science from the University of Michigan. He is a member of the IEEE."]}}, {'name': 'Paul Gingras', 'affiliation': 'Sun Microsystems', 'bio': {'p': ["Paul Gingras is the CoHub ASIC and system verification lead in Sun Microsystems' Microelectronics Group in Burlington, Massachusetts. His research interests include ASIC and system verification methodologies. Gingras has an MBA from Marist College and a BSEE from Northeastern University."]}}, {'name': 'Peter Yakutis', 'affiliation': 'Sun Microsystems', 'bio': {'p': ["Peter Yakutis is the performance analysis and simulation lead in Sun Microsystems' Microelectronics Group in Burlington, Massachusetts. His research interests include simulation and I/O subsystem architecture and performance. Yakutis has an MS in computer science from the University of Southern Maine. He is a member of the IEEE."]}}, {'name': 'Stephen Phillips', 'affiliation': 'Sun Microsystems', 'bio': {'p': ["Stephen Phillips is lead microprocessor architect, Distinguished Engineer and director of the Chip Multithreading (CMT) Architecture Group in Sun Microsystems' Microelectronics Group in Santa Clara, California. His research interests include threading models, cache coherence, interconnects, and system-on-chip architecture. Phillips has an MSEE from Rutgers University. He is a member of the IEEE."]}}, {'name': 'John Heath', 'affiliation': 'University of Southern Maine', 'bio': {'p': ['John Heath was with Sun Microsystems from 2000 until 2006. At present, he is a senior research fellow of RCG, a research group at the University of Southern Maine, an adjunct full professor of computer science, and a member of the graduate faculty of the University of Maine, Orono. His research activities focus on performance analysis and modeling of computer systems. Heath has a PhD in computer and information science from the University of Minnesota, Minneapolis. He is a member of the IEEE.']}} %*Coherency Hub Design for Multisocket Sun Servers with CoolThreads Technology %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5209933 %f/micro/tgma5o1j3fk0uqsvkcyzgdexu7xbqrhz.pdf %mad82e74bcd1a86d5e92836d0c3852d7b %cmicro %@[{'name': 'Tushar Krishna', 'affiliation': 'Princeton University', 'bio': {'p': ["Tushar Krishna is a PhD candidate in the Department of Electrical Engineering at Princeton University. His research interests include networks on chip and parallel computer architectures. Krishna has a bachelor's degree in electrical engineering from lIT Delhi, India. He is a student member of the IEEE and ACM SIGARCH."]}}, {'name': 'Amit Kumar', 'affiliation': 'Princeton University', 'bio': {'p': ["Amit Kumar is a research scientist in Intel's Microarchitecture Research Lab in Santa Clara, California, and a PhD candidate in the Department of Electrical Engineering at Princeton University. His research interests include on-chip networks, computer architecture, and power- and thermal-aware system design. Kumar has an MA in electrical engineering from Princeton University. He is a member of the IEEE and ACM."]}}, {'name': 'Li-Shiuan Peh', 'affiliation': 'Princeton University', 'bio': {'p': ['Li-Shiuan Peh is an associate professor of electrical engineering at Princeton University. Her research focuses on low-power interconnection networks, on-chip networks, and parallel computer architectures. Peh has a PhD in computer science from Stanford University.']}}, {'name': 'Jacob Postman', 'affiliation': 'Oregon State University', 'bio': {'p': ['Jacob Postman is a PhD student in electrical and computer engineering at Oregon State University, Corvallis. His research interests include low-power, high-performance circuits, microarchitectures, and networks on chip. Postman has a BS in electrical and computer engineering from Oregon State University, Corvallis.']}}, {'name': 'Patrick Chiang', 'affiliation': 'Oregon State University', 'bio': {'p': ['Patrick Chiang is an assistant professor of electrical and computer engineering at Oregon State University. His interests are in the design of low-power, process-calibrating, mixed-signal circuits in deep submicron CMOS. Chiang has a PhD in electrical engineering from Stanford University.']}}, {'name': 'Mattan Erez', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ['Mattan Erez is an assistant professor of electrical and computer engineering at the University of Texas at Austin. His research interests include computer architecture and programming models. Erez has a PhD in electrical engineering from Stanford University.']}} %*Express Virtual Channels with Capacitively Driven Global Links %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5209934 %f/micro/zpdkl1qerfxjribovy9uga5nxfsz3bqa.pdf %m41efab0f56b4d900e3eeaa09450ae90c %cmicro %@[{'name': 'Michael R.T. Tan', 'affiliation': 'Hewlett-Packard', 'bio': {'p': ['Michael R.T. Tan is a distinguished technologist at Hewlett-Packard Laboratories. His research interests include surface acoustic wave (SAW), RF, and mm-wave devices and high-speed vertical-cavity surface-emitting lasers (VCSELs) for data communications and laser printing applications. Tan has a PhD in electrical engineering from Stanford University. He is a member of the IEEE.']}}, {'name': 'Paul Rosenberg', 'affiliation': 'Hewlett-Packard', 'bio': {'p': ['Paul Rosenberg is an optoelectronic engineer at Hewlett-Packard Laboratories. His research interests include advanced optomechanical packaging and thermal design for low cost optical transceivers. Rosenberg has an MS in materials science and engineering from Stanford University.']}}, {'name': 'Jong-Souk Yeo', 'affiliation': 'Hewlett-Packard', 'bio': {'p': ['Jong-Souk Yeo is a research scientist at Hewlett-Packard. His research interests include laser micromachining, nanoscale devices, integrated photonics, flexible electronics, and displays. Yeo has a PhD in materials science and engineering from Stanford University.']}}, {'name': 'Moray McLaren', 'affiliation': 'Hewlett-Packard', 'bio': {'p': ['Moray McLaren is a distinguished technologist in the Exascale Computing Laboratory of Hewlett-Packard Laboratories. His research interests include the impact of nano-photonics on future computer architectures with a focus on high-speed networking and memory architectures. McLaren has an honors degree in microelectronics from the University of Edinburgh.']}}, {'name': 'Sagi Mathai', 'affiliation': 'Hewlett-Packard', 'bio': {'p': ['Sagi Mathai is a researcher in the Information and Quantum Systems Lab at Hewlett-Packard Laboratories. His research interests include parallel optical interconnects and nanowire optoelectronics. Mathai has a PhD in electrical engineering from UCLA. He is a member of the IEEE Photonics Society and the Optical Society of America (OSA).']}}, {'name': 'Terry Morris', 'affiliation': 'Hewlett-Packard', 'bio': {'p': ['Terry Morris is an HP Fellow at Enterprise Storage and Servers. His research interests include high-speed interconnections for computer systems ranging from GaAs supercomputers to blades.']}}, {'name': 'Huei Pei Kuo', 'affiliation': 'Hewlett-Packard', 'bio': {'p': ['Huei Pei Kuo is a master scientist in the Information and Quantum Systems Lab at Hewlett-Packard Laboratories. His research interests include off-chip optical interconnect technology. Kuo has a PhD in applied and engineering physics from Cornell University.']}}, {'name': 'Joseph Straznicky', 'affiliation': 'Hewlett-Packard', 'bio': {'p': ['Joseph Straznicky is a researcher in the Information and Quantum Systems Lab at Hewlett-Packard Laboratories. His research interests include molecular electronics and optical communication. Straznicky has a Dipl.-Ing. in electrical engineering from Technical University Brno, Czechoslovakia. He is a member of the IEEE.']}}, {'name': 'Norman P. Jouppi', 'affiliation': 'Hewlett-Packard', 'bio': {'p': ["Norman P. Jouppi is an HP Fellow and director of HP's Exascale Computing Laboratory. His research interests include computer memory systems, including stream prefetch buffers, victim caching, and development of the CACTI tool. Jouppi has a PhD in electrical engineering from Stanford University. He is a Fellow of the ACM and the IEEE."]}}, {'name': 'Shih-Yuan Wang', 'affiliation': 'Hewlett-Packard', 'bio': {'p': ['Shih-Yuan Wang is a distinguished technologist at Hewlett-Packard Laboratories. His research interests include VCSELs, photodetectors, modulators, GaN LED, nanophotonics/ electronics, and nanowire devices. Wang has a PhD in electrical engineering and computer sciences from the University of California, Berkeley. He is a Fellow of the IEEE and the Optical Society of America.']}} %*A High-Speed Optical Multidrop Bus for Computer Interconnections %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5209935 %f/micro/91wrkblgwasqdvtvtjqmab50yipgmx7c.pdf %m77655a8b6c1a2c913f00f9eb9fe52316 %cmicro %@[{'name': 'Michele Petracca', 'affiliation': 'Columbia University', 'bio': {'p': ['Michele Petracca is a postdoctoral researcher in the Computer Science Department at Columbia University. His research interests include optical communication and networks, system and RTL design for network devices, and networks -on -chip design. Petracca has a PhD in electrical engineering from Politecnico di Torino, Italy. He is member of the IEEE.']}}, {'name': 'Benjamin G. Lee', 'affiliation': 'Columbia University', 'bio': {'p': ['Benjamin G. Lee is a postdoctoral researcher at the IBM T.J. Watson Research Center, Yorktown Heights, New York. His research interests include silicon photonic devices, integrated optical switches and networks for high -performance computing systems, and all -optical processing systems. Lee has a PhD in electrical engineering from Columbia University. He is a member of the IEEE Photonics Society and the Optical Society of America.']}}, {'name': 'Keren Bergman', 'affiliation': 'Columbia University', 'bio': {'p': ['Keren Bergman is a professor in the Department of Electrical Engineering at Columbia University, where she directs the Lightwave Research Laboratory. Her research interests include optical interconnection networks for advanced computing systems, photonic packet switching, and nanophotonic networks -on -chip. Bergman has a PhD in electrical engineering from the Massachusetts Institute of Technology. She is the coeditor in chief of the newly launched IEEE/ OSA Journal of Optical Communications and Networking and is a Fellow of the IEEE and of the Optical Society of America.']}}, {'name': 'Luca P. Carloni', 'affiliation': 'Columbia University', 'bio': {'p': ['Luca P. Carloni is an associate professor in the Department of Computer Science at Columbia University. His research interests include design tools and methodologies for integrated circuits and systems, distributed embedded systems design, and the design of high -performance computers. He has a PhD in electrical engineering and computer sciences from the University of California, Berkeley. He is a member of the IEEE and the ACM.']}} %*Photonic NoCs: System-Level Design Exploration %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5209936 %f/micro/y5f0fjgpqtash8eiqolgmi1uhwyb7ub2.pdf %m8834cad5f5754929bb52a4292b6413ec %cmicro %@[{'name': 'Richard H. Stern', 'affiliation': 'rstern@khhte.com', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/5209924/5209937/5209937-photo-1-small.gif', 'p': ['Richard H. Stern rstern@khhte.com']}} %*Micro Law: An End to the Rambus Skullduggery Saga %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5209937 %f/micro/nix760jtk9luciar54hkuz8rzvq3eymv.pdf %m564e003ca14ff79c65374d33ff119c30 %cmicro %@[{'name': 'Richard Mateosian', 'affiliation': 'xrm@pacbell.net'} %*Micro Review: Twitter %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5209938 %f/micro/dlbwoa4msidgvlgnkzvwtyzxxyqr2afp.pdf %m294962282734689dc6df82c8c17a918c %cmicro %@[{'name': 'David H. Albonesi', 'affiliation': 'albonesi@csl.cornell.edu', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/5325146/5325150/5325150-photo-1-small.gif', 'p': ['Dave Albonesi Editor in Chief IEEE Micro']}} %*From the Editor in Chief: Welcome A-Board %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5325150 %f/micro/jpeloz5bvkt3qogauhdbgwpqln6f1yra.pdf %m75b4aa9598417c83311db529f425d32a %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'greenstein@kellogg.northwestern.edu', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/5325146/5325151/5325151-photo-1-small.gif', 'p': ['SHANE GREENSTEIN']}} %*Micro Economics: Does Google Have Too Much Money? %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5325151 %f/micro/sth679q2tvoiejbcrpmvmsy5d8nidezy.pdf %m2500f39dcfd961985702e355d2a24fd7 %cmicro %@[{'name': 'Jose F. Martinez', 'affiliation': 'Cornell University', 'bio': {'p': ['José F. Martínez is an associate professor of electrical and computer engineering at Cornell University. His research interests include reconfigurable and self-optimizing architectures. Martínez has a PhD in computer science from the University of Illinois, Urbana-Champaign. He is a member of the ACM and the IEEE.']}}, {'name': 'Engin Ipek', 'affiliation': 'University of Rochester', 'bio': {'p': ['Engin İpek is an assistant professor of computer science and electrical and computer engineering at the University of Rochester. His research interests include self-optimizing architectures and low-power memory subsystems. İpek has a PhD in electrical and computer engineering from Cornell University. He is a member of the ACM and the IEEE.']}} %*Dynamic Multicore Resource Management: A Machine Learning Approach %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5325152 %f/micro/rphgjld2bxzmwofyq4wsnbuotghmazat.pdf %m0c8e60248210b4e2857425a95c160868 %cmicro %@[{'name': 'Jason A. Poovey', 'affiliation': 'Georgia Institute of Technology', 'bio': {'p': ["Jason A. Poovey is a PhD student in the College of Computing at the Georgia Institute of Technology. His research interests include performance modeling, workload characterization, and manycore/ multi-core technology. Poovey has a master's degree in computer engineering from North Carolina State University."]}}, {'name': 'Thomas M. Conte', 'affiliation': 'Georgia Institute of Technology', 'bio': {'p': ['Markus Levy is the president and founder of the Embedded Microprocessor Benchmark Consortium (EEMBC), and founder of the Multicore Association. His research interests include microprocessor technology, processor benchmarking, and multicore programming. He received several patents while at Intel for his ideas related to flash memory architecture and usage as a disk drive alternative. Levy has a BS in electrical engineering from San Francisco State University.']}}, {'name': 'Markus Levy', 'affiliation': 'EDN Embedded Microprocessor Benchmark Consortium', 'bio': {'p': ['Shay Gal-On is the director of software engineering at the Embedded Microprocessor Benchmark Consortium and leader of the EEMBC Technology Center. His interests include performance analysis, software security, and compilers. Gal-On received his degree from the Technion in Israel, following which he worked on compilers and performance tools for Intel, Improv Systems, PMC, and now EEMBC. Contact Gal-On atshay@eembc.org.']}}, {'name': 'Shay Gal-On', 'affiliation': 'EDN Embedded Microprocessor Benchmark Consortium', 'bio': {'p': ['Thomas M. Conte is a professor in the College of Computing at the Georgia Institute of Technology. His research is in the areas of manycore/ multicore architectures, microprocessor architectures, compiler code generation, architectural performance evaluation, and embedded computer systems. Conte has a PhD in electrical engineering from the University of Illinois at Urbana Champaign. He is associate editor of ACM Transactions on Embedded Computer Systems, ACM Transactions on Architecture and Compiler Optimization, Computer, and IEEE Micro.']}} %*A Benchmark Characterization of the EEMBC Benchmark Suite %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5325153 %f/micro/ys6bfianegjx2uych8efqmaowxd5ptug.pdf %m5e7857af0539f05ef8de1b409a161d00 %cmicro %@[{'name': 'Tran Nguyen Bao Anh', 'affiliation': 'Singapore Engineering Center', 'bio': {'p': ['Tran Nguyen Bao Anh is a senior embedded engineer at STS Wireless Sound Solutions Singapore. His research interests include embedded and real-time system development. Anh has an MSc in embedded systems from Nanyang Technological University.']}}, {'name': 'Su-Lim Tan', 'affiliation': 'Nanyang Technological University', 'bio': {'p': ['Su-Lim Tan is an assistant professor in the School of Computer Engineering at Nanyang Technological University, Singapore. His research interests include embedded network sensing and smart sensors. Tan has a PhD in engineering from the University of Warwick.']}} %*Real-Time Operating Systems for Small Microcontrollers %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5325154 %f/micro/o4iezcdpwrkynf52ouwxltsnata360j1.pdf %md06af8285c9eec597ee8b2d81619d117 %cmicro %@[{'name': 'Hsiang-Ning Liu', 'affiliation': 'National Central University, Taiwan', 'bio': {'p': ['Hsiang-Ning Liu is a soldier in the Taiwan air force. His research interests include network-on-a-chip design and memory testing. Liu has an MS from the Department of Electrical Engineering at National Central University.']}}, {'name': 'Yu-Jen Huang', 'affiliation': 'National Central University, Taiwan', 'bio': {'p': ['Yu-Jen Huang is a doctoral student in the Department of Electrical Engineering at National Central University. Her research interests include VLSI design, memory testing, and fault-tolerant VLSI design. Huang has a BS from the Department of Electrical Engineering, National Central University.']}}, {'name': 'Jin-Fu Li', 'affiliation': 'National Central University, Taiwan', 'bio': {'p': ['Jin-Fu Li is a full professor in the Department of Electrical Engineering at National Central University. His research interests include advanced very large scale integration (VLSI)/SOC design and test, memory testing and repair, reliable VLSI circuits and systems, and 3D IC architecture design and test. Li has a PhD from the Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan.']}} %*Memory Built-in Self Test in Multicore Chips with Mesh-Based Networks %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5325155 %f/micro/hdyzcp7dlnovljqr1m58bgff6xn3pez0.pdf %m8f16e8f1d520ab3566b12298722c4326 %cmicro %@[{'name': 'Ying-Dar Lin', 'affiliation': 'National Chiao Tung University', 'bio': {'p': ['Ying-Dar Lin is a professor in the Department of Computer and Information Science at National Chiao Tung University, Hsinchu, Taiwan. His research interests include design, analysis, implementation, and benchmarking of network protocols and algorithms, wirespeed switching and routing, quality of service, deep packet inspection, network processors and systems on chip, and embedded hardware-software codesign. Lin has a PhD in computer science from the University of California, Los Angeles.']}}, {'name': 'Po-Ching Lin', 'affiliation': 'National Chung Cheng University', 'bio': {'p': ['Po-Ching Lin is an assistant professor in the Department of Computer and Information Science at the National Chung Cheng University, Chiayi, Taiwan. His research interests include network security, content networking, and algorithm designing. Lin has a PhD in computer science from National Chiao Tung University, Hsinchu, Taiwan.']}}, {'name': 'Yuan-Cheng Lai', 'affiliation': 'National Taiwan University of Science and Technology', 'bio': {'p': ['Yuan-Cheng Lai is a professor in the Department of Information Management at the National Taiwan University of Science and Technology, Taipei, Taiwan. His research interests include high-speed networking, wireless networks, network performance evaluation, and Internet applications. Lai has a PhD in computer and information science from National Chiao Tung University, Hsinchu, Taiwan.']}}, {'name': 'Tai-Ying Liu', 'affiliation': 'Avermedia', 'bio': {'p': ['Tai-Ying Lin is an engineer at Avermedia, Taipei, Taiwan. His research interests include embedded hardware-software codesign and content networking. Liu has an MS in computer science in National Chiao Tung University.']}} %*Hardware-Software Codesign for High-Speed Signature-based Virus Scanning %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5325156 %f/micro/ua5gumyidjv0kxcqfscqx6ytlbkznbvh.pdf %mcd24ac1b6855f906bcfd13249527f263 %cmicro %@[{'name': 'Richard Mateosian', 'affiliation': 'xrm@pacbell.net'} %*Micro Review: Life and Work %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5325157 %f/micro/afosilnusxqhat17wbr3ingwv6pyjkfd.pdf %mb2d23ff2cb8cc3488a169fed56516d7a %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'Kellogg Graduate School of Management', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/4460501/4460506/4460506-photo-1-small.gif', 'p': ['']}} %*The Long Arc Behind Bill Gates' Wealth %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4460506 %f/micro/dzxqyjcp0mqvbacwslbhge3gopwf4r8r.pdf %md0d09e63452c7889cbde66ef07a3b02e %cmicro %@[{'name': 'Sarita Adve', 'affiliation': 'University of Illinois, Urbana-Champaign', 'bio': {'p': ['Sarita V. Adve is a professor in the Department of Computer Science at the University of Illinois at Urbana-Champaign. Her research interests are in computer architecture and systems, with a current focus on reliability and multicore programming. She has a PhD in computer science from the University of Wisconsin-Madison.']}}, {'name': 'David Brooks', 'affiliation': 'Harvard', 'bio': {'p': ['David Brooks is an associate professor of computer science at Harvard University. His research interests include architectural and software approaches to address power, thermal, and reliability issues for embedded and high-performance computing systems. Brooks has a PhD in electrical engineering from Princeton University.']}}, {'name': 'Craig Zilles', 'affiliation': 'University of Illinois, Urbana-Champaign', 'bio': {'p': ['Craig Zilles is an assistant professor in computer science at the University of Illinois at Urbana-Champaign. His research interests include interaction between compilers and computer architecture, especially in the context of managed and dynamic languages. Zilles has a PhD in computer science from the University of Wisconsin-Madison. He is a member of IEEE and the ACM.', 'Direct questions and comments about this special issue to the guest editors: Sarita Adve, sadve@cs.uiuc.edu, David Brooks, dbrooks@eecs.harvard.edu, Craig Zilles, zilles@cs.uiuc.edu.', 'For more information on this or any other computing topic, please visit our Digital Library at http://computer.org/csdl.']}} %*Guest Editors' Introduction: Top Picks from the Computer Architecture Conferences of 2007 %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4460507 %f/micro/xh3oguqap0frhzownl6mvr4stwubdy8y.pdf %m6b0ed6f788e1411bd3b25982aef0361f %cmicro %@[{'name': 'Matthew J. Bridges', 'affiliation': 'Princeton University', 'bio': {'p': ['Matthew J. Bridges is pursuing a PhD in the Department of Computer Science at Princeton University. His research interests include compilers, compiler architecture, and programming languages, with an emphasis on parallelism extraction. Bridges has a HBS in computer and information science from the University of Delaware and an MA in computer science from Princeton University. He is a student member of the ACM.']}}, {'name': 'Neil Vachharajani', 'affiliation': 'Princeton University', 'bio': {'p': ['Neil Vachharajani is pursuing a PhD in the Department of Computer Science at Princeton University. His research interests include compilers, compiler architecture, and programming languages. Vachharajani has a BSE in electrical engineering and an MA in computer science from Princeton Uni-versity. He is a student member of the ACM and a National Science Foundation Graduate Fellow.']}}, {'name': 'Yun Zhang', 'affiliation': 'Princeton University', 'bio': {'p': ['Yun Zhang is pursuing a PhD in the Department of Computer Science at Princeton University. Her research interests include computer architecture, compiler optimization, distributed systems, and machine learning. Yun has a BS from Peking University and an MS from the University of Toronto, both in computer science. She is a student member of the ACM.']}}, {'name': 'Thomas Jablin', 'affiliation': 'Princeton University', 'bio': {'p': ['Thomas Jablin is pursuing a PhD in the Department of Computer Science at Princeton University. His research interests include compilers and just-in-time profiling and optimization, with an emphasis on parallelism extraction. Thomas has a BA in computer science from Amherst College. He is a student member of the ACM.']}}, {'name': 'David I. August', 'affiliation': 'Princeton University', 'bio': {'p': ['David I. August is an associate professor in the Department of Computer Science at Princeton University, where he directs the Liberty Research Group (http://liberty. princeton.edu), which is studying next-generation architectures, code analyses, and code transformations to enhance perfor-mance, reliability, and security. August earned his PhD in electrical engineering from the University of Illinois at Urbana-Champaign, where he worked as a member of the IMPACT research compiler group.']}} %*Revisiting the Sequential Programming Model for the Multicore Era %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4460508 %f/micro/uek037hhj2io49bgzti6m85nqqloswwe.pdf %mc8287e0f6e888e96d3167a25670412fc %cmicro %@[{'name': 'Naveen Neelakantam', 'affiliation': 'University of Illinois at Urbana-Champaign', 'bio': {'p': ['Naveen Neelakantam is a PhD student in computer science at the University of Illinois at Urbana-Champaign and is an Intel Foundation PhD Fellowship recipient. His research interests include microprocessor architecture and optimizing compilers. Neelakantam has an MS in electrical engineering from the University of Illinois at Urbana-Champaign. He is a student member of the ACM.']}}, {'name': 'Ravi Rajwar', 'affiliation': 'Intel', 'bio': {'p': ['Ravi Rajwar is an architect in the Digital Enterprise Group at Intel. His research interests include the theoretical and practical aspects of computer architecture. Rajwar has a PhD in computer science from the University of Wisconsin-Madison.']}}, {'name': 'Suresh Srinivas', 'affiliation': 'Intel', 'bio': {'p': ['Suresh Srinivas is a principal engineer in the Software and Solutions Group within Intel, where he currently focuses on new technology development using open-source technologies. Srinivas has a PhD in computer science from Indiana University.']}}, {'name': 'Uma Srinivasan', 'affiliation': 'Intel', 'bio': {'p': ['Uma Srinivasan is a senior staff software engineer in the Software and Solutions Group and is the technical lead for the Java on Itanium Just-in-Time Compiler project in the Java/XML Engineering Lab at Intel. Srinivasan has an MS in computer science from the University of Wisconsin-Madison.']}}, {'name': 'Craig Zilles', 'affiliation': 'University of Illinois at Urbana-Champaign', 'bio': {'p': ['Craig Zilles is an assistant professor in computer science at the University of Illinois at Urbana-Champaign. His research interests include interaction between compilers and computer architecture, especially in the context of managed and dynamic languages. Zilles has a PhD in computer science from the University of Wisconsin-Madison. He is a member of IEEE and the ACM.']}} %*Hardware Atomicity: An Effective Abstraction for Reliable Software Speculation %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4460509 %f/micro/ctjlbdrrpvy9yzfszk8abliu0spum2oh.pdf %me1e4e27fbeb2b15b1f2309e11755c0bc %cmicro %@[{'name': 'Jayaram Bobba', 'affiliation': 'University of Wisconsin¿Madison', 'bio': {'p': ['Jayaram Bobba is a graduate student at the University of Wisconsin-Madison. His research interests include parallel programming models, software-hardware interface, and parallel system design. He has an MS in computer science from the University of Wisconsin—Madison. He is a member of the ACM.']}}, {'name': 'Kevin E. Moore', 'affiliation': 'Sun Microsystems', 'bio': {'p': ['Kevin Moore is a researcher at Sun Microsystems Labs. His interests include transactional memory and multiprocessor memory systems. Moore has a PhD in computer science from the University of Wisconsin-Madison. He is a member of the ACM.']}}, {'name': 'Haris Volos', 'affiliation': 'University of Wisconsin¿Madison', 'bio': {'p': ['Haris Volos is a graduate student in computer science at the University of Wisconsin—Madison. His research focuses on parallel programming models, operating systems, and the interaction of architecture and systems. Volos has an MS in computer science from the University of Wisconsin-Madison.']}}, {'name': 'Luke Yen', 'affiliation': 'University of Wisconsin¿Madison', 'bio': {'p': ['Luke Yen is a graduate student at the University of Wisconsin—Madison. His research interests include multiprocessor system design, models for parallel programming, and hardware support for future parallel programming paradigms. He has an MS in computer science from the University of Wisconsin—Madison. He is a member of the IEEE Computer Society and the ACM.']}}, {'name': 'Mark D. Hill', 'affiliation': 'University of Wisconsin¿Madison', 'bio': {'p': ['Mark D. Hill is a professor in both the Computer Sciences Department and the Electrical and Computer Engineering Department at the University of Wisconsin-Madison. His research interests include parallel computer system design, memory system design, and computer simulation. He earned a PhD in computer science from the University of California, Berkeley. He is an ACM Fellow and an IEEE Fellow.']}}, {'name': 'Michael M. Swift', 'affiliation': 'University of Wisconsin¿Madison', 'bio': {'p': ['Michael M. Swift is an assistant professor in the Computer Sciences Department at the University of Wisconsin-Madison. His research interests include operating system reliability, the interaction of architecture and operating systems, and device driver architecture. He has a PhD in computer science from University of Washington. He is a member of the ACM.']}}, {'name': 'David A. Wood', 'affiliation': 'University of Wisconsin¿Madison', 'bio': {'p': ['David A. Wood is a professor in the Computer Sciences Department and the Electrical and Computer Engineering Department at the University of Wisconsin-Madison. His research interests include techniques for improving availability, designability, programmability, and performance of commercial multiprocessor servers. Wood has a PhD in computer sciences from the University of California, Berkeley. He is a Fellow of the ACM and the IEEE, and a member of the IEEE Computer Society.']}} %*Performance Pathologies in Hardware Transactional Memory %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4460510 %f/micro/uacm69dp8hasvvkwof15yiwbziqk7gnd.pdf %m7936f5f38a4fd738e2f01cdab31aff79 %cmicro %@[{'name': 'Hany E. Ramadan', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ['Hany E. Ramadan is a PhD student at the University of Texas at Austin. His research interests include parallelism in large software systems, architectural support to enable greater concurrency in software, and transaction models. Ramadan has an MS in computer science from the Univer-si ty of Minnesota.']}}, {'name': 'Christopher J. Rossbach', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ['Christopher J. Rossbach is a PhD student at the University of Texas at Austin. His research focuses on transactional memory, architecture, and parallel programming. Rossbach has a BS in computer systems engineering from Stanford University.']}}, {'name': 'Donald E. Porter', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ['Donald E. Porter is a PhD student in computer science at the University of Texas at Austin. His research interests include concurrent systems and operating system support for transactions. Porter has a BA in computer science and mathematics from Hendrix College.']}}, {'name': 'Owen S. Hofmann', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ['Owen S. Hofmann is a PhD student in computer science at the University of Texas at Austin. His research interests include hardware and operating system support for parallel programming. Hofmann has a BA in computer science from Amherst College.']}}, {'name': 'Aditya Bhandari', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ['Aditya Bhandari is a graduate student in computer science at the University of Texas at Austin. His research interests include transactional memory in operating systems and virtualization. Bhandari has a BE in computer engineering from the University of Pune.']}}, {'name': 'Emmett Witchel', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ['Emmett Witchel is an assistant professor of computer science at the University of Texas at Austin. His research interests include computer architecture and its relationship to the operating system and compiler. Witchel has a PhD in electrical engineering and computer science from the Massachusetts Institute of Technology.', 'Direct questions or comments to Hany Ramadan, Department of Computer Sci-ences, University of Texas at Austin, 1 University Station C0500 Austin, TX 78712, ramadan@cs.utexas.edu.']}} %*MetaTM/TxLinux: Transactional Memory for an Operating System %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4460511 %f/micro/e2muvfkyxwhsnr40rpq9sv3c7kqzt8cz.pdf %me3bbc920e88a66b64f58e571ee544d9d %cmicro %@[{'name': 'Albert Meixner', 'affiliation': 'Duke University', 'bio': {'p': ['Albert Meixner is a PhD student in the Department of Computer Science at Duke University. His research interests focus on architectures and compilers for fault-tolerant computing. He has an MS in applied computer science from Paris Lodron Universitat, Salzburg, Austria.']}}, {'name': 'Michael E. Bauer', 'affiliation': 'Duke University', 'bio': {'p': ['Michael E. Bauer is a BSE student in the Department of Electrical and Computer Engineering at Duke University. His research interests focus on computer architecture and applied mathematics.']}}, {'name': 'Daniel J. Sorin', 'affiliation': 'Duke University', 'bio': {'p': ['Daniel J. Sorin is an assistant professor of electrical and computer engineering and of computer science at Duke University. His research interests focus primarily on dependable computer architecture. He has a PhD in electrical and computer engineering from the University of Wisconsin-Madison.']}} %*Argus: Low-Cost, Comprehensive Error Detection in Simple Cores %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4460512 %f/micro/zepjtgbgohbpjq6xyf1rd20kscywm5m4.pdf %mae35c4e164a47eea49144d80abb14437 %cmicro %@[{'name': 'Xiaoyao Liang', 'affiliation': 'Harvard University', 'bio': {'p': ['Xiaoyao Liang is pursuing a PhD in electrical engineering at Harvard University. His research interests include computer architecture and VLSI design, currently focusing on joint circuit and architecture solutions to combat process variability. Liang has an MS from Stony Brook University and a BS from Fudan University, China, both in electrical engineering.']}}, {'name': 'Ramon Canal', 'affiliation': 'Universitat Politècnica de Catalunya', 'bio': {'p': ['Ramon Canal is an associate professor in the Computer Architecture Department of the Universitat Politècnica de Catalunya (UPC), Spain. His research interests include power-and thermal-aware architectures, chip multiprocessors, and reliability. Canal has BS, MS, and PhD degrees in computer engineering from UPC. He was a Fulbright scholar at Harvard University.']}}, {'name': 'Gu-Yeon Wei', 'affiliation': 'Harvard University', 'bio': {'p': ['Gu-Yeon Wei is an associate professor of electrical engineering at Harvard University. His research interests include mixed-signal VLSI design for wire-line data communication, energy-efficient computing devices for sensor networks, and collaborative software, architecture, and circuit techniques to combat variability in nanoscale technologies. Wei has BS, MS, and PhD degrees in electrical engineering from Stanford University.']}}, {'name': 'David Brooks', 'affiliation': 'Harvard University', 'bio': {'p': ['David Brooks is an associate professor of computer science at Harvard University. His research interests include architectural and software approaches to address power, thermal, and reliability issues for embedded and high-performance computing systems. Brooks has a PhD in electrical engineering from Princeton University.', 'Direct questions and comments about this article to David Brooks, School of Engineering and Applied Sciences, Harvard University, 33 Oxford St., Cambridge, MA 02138, dbrooks@eecs.harvard.edu.']}} %*Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4460513 %f/micro/bkqx8t3rv7zaniw1mheruxt0zjps52cc.pdf %md867c213b36516bcb382ec738030b26c %cmicro %@[{'name': 'Naveen Muralimanohar', 'affiliation': 'University of Utah', 'bio': {'p': ['Naveen Muralimanohar is pursuing a PhD in computer science at the University of Utah. His research focuses on interconnect design for future communication-bound processors and large cache hierarchies. Muralimanohar has a BS in electrical and electronics engineering from the University of Madras, India.']}}, {'name': 'Rajeev Balasubramonian', 'affiliation': 'University of Utah', 'bio': {'p': ['Rajeev Balasubramonian is an assistant professor in the School of Computing at the University of Utah. His research interests include the design of high-performance microprocessors that can efficiently tolerate long on-chip wire delays, high power densities, and frequent errors. Balasubramonian has a PhD in computer science from the University of Rochester. He is a member of the IEEE.']}}, {'name': 'Norman P. Jouppi', 'affiliation': 'Hewlett-Packard Laboratories', 'bio': {'p': ["Norm Jouppi is a fellow and director of HP's Advanced Architecture Lab. His research interests include computer memory systems, networking for cluster computing, blade system architectures, graphics accelerators, and video, audio, and physical telepresence. Jouppi has a PhD in electrical engineering from Stanford University. He is a Fellow of the IEEE and ACM.", 'Direct questions and comments about this article to Rajeev Balasubramonian, 50 S. Central Campus Dr., Rm. 3190, Salt Lake City, Utah 84112, rajeev@cs.utah.edu.']}} %*Architecting Efficient Interconnects for Large Caches with CACTI 6.0 %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4460514 %f/micro/hvzkvwsitnb8rdpyxgo0ojj4xgqlfdkl.pdf %me86d9e9f4faf814d201aef7e39517cb3 %cmicro %@[{'name': 'Amit Kumar', 'affiliation': 'Princeton University', 'bio': {'p': ['Amit Kumar is a PhD student in the Department of Electrical Engineering at Princeton University. His research interests include interconnection networks, computer architecture, and power- and thermal-aware system design. He has an MA in electrical engineering from Princeton University. He was awarded the Intel Foundation PhD Fellowship in 2006 and is a student member of the IEEE and ACM.']}}, {'name': 'Li-Shiuan Peh', 'affiliation': 'Princeton University', 'bio': {'p': ['Li-Shiuan Peh is an assistant professor of electrical engineering at Princeton University. Her research focuses on low-power interconnection networks, on-chip networks, and parallel computer architectures. She has a PhD in computer science from Stanford University. She was awarded the Anita Borg Early Career Award in 2007, Sloan Research Fellowship in 2006 and the NSF CAREER award in 2003.']}}, {'name': 'Partha Kundu', 'affiliation': 'Microprocessor Technology Labs, Intel', 'bio': {'p': ["Partha Kundu is a researcher within Intel's Microprocessor Technology Labs in Santa Clara, California. His research interests include on-chip networks, memory system design, transactional memory, and performance simulation. He has an MS from the State University of New York, Stony Brook."]}}, {'name': 'Niraj K. Jha', 'affiliation': 'Princeton University', 'bio': {'p': ['Niraj K. Jha is a professor in the Department of Electrical Engineering at Princeton University. His interests are in nanotechnology, CAD, computer architecture, security, and testing. He has a PhD in electrical engineering from the University of Illinois at Urbana-Champaign. He is a Fellow of both the IEEE and the ACM.']}} %*Toward Ideal On-Chip Communication Using Express Virtual Channels %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4460515 %f/micro/mojcmlv3r0pgs7ab6vejwzzka9qind4i.pdf %m4bd118ae66519b700f07591dac5768cc %cmicro %@[{'name': 'Moinuddin K. Qureshi', 'affiliation': 'IBM Research', 'bio': {'p': ['Moinuddin K. Qureshi is a research scientist at IBM Research. His research interests include computer architecture, especially the design of high-performance and scalable memory systems. Qureshi has a PhD in electrical and computer engineering from the University of Texas at Austin. He was a recipient of the IBM PhD fellowship for academic years 2003 through 2006. He is a member of the IEEE and the ACM.']}}, {'name': 'Aamer Jaleel', 'affiliation': 'Intel', 'bio': {'p': ['Aamer Jaleel is a hardware engineer at Intel, working in the VSSAD group. His research interests include cache/memory system design, parallel architectures, computer architecture, microarchitecture, performance modeling, and workload characterization. Jaleel has a PhD in electrical engineering from the University of Maryland, College Park. He is a member of the IEEE.']}}, {'name': 'Yale N. Patt', 'affiliation': 'The University of Texas at Austin', 'bio': {'p': ['Yale N. Patt is the Ernest Cockrell, Jr., Centennial Chair in Engineering at the University of Texas at Austin. His research interests include harnessing the expected benefits of future process technology to create more effective microarchitectures for future microprocessors. He is coauthor of Introduction to Computing Systems: From Bits and Gates to C and Beyond (McGraw-Hill, 2nd edition, 2004). His honors include the 1996 IEEE/ACM Eckert-Mauchly Award and the 2000 ACM Karl V. Karlstrom Award. He is a Fellow of both the IEEE and the ACM.']}}, {'name': 'Simon C. Steely Jr.', 'affiliation': 'Intel', 'bio': {'p': ['Simon C. Steely Jr. is a senior principal engineer at Intel, working in the VSSAD group. His technical interests include cache/ memory hierarchies, cache coherency, and computer architecture. Steely has a BE (computer science option) from the University of New Mexico. He is a member of the IEEE and the ACM.']}}, {'name': 'Joel Emer', 'affiliation': 'Intel', 'bio': {'p': ['Joel Emer is an Intel Fellow and director of microarchitecture research at Intel, where he leads the VSSAD group. Recently, he has also been teaching part-time at MIT. His research interests include performance-modeling frameworks, parallel and multithreaded processors, cache organization, processor pipeline organization, and processor reliability. Emer has a PhD in electrical engineering from the University of Illinois. He is an ACM Fellow and an IEEE Fellow.']}} %*Set-Dueling-Controlled Adaptive Insertion for High-Performance Caching %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4460516 %f/micro/agoj1vpks3zcqrnxrvdltfmbkaifjw70.pdf %md67a39d88290f466194f853801c2b70b %cmicro %@[{'name': 'Michael R. Marty', 'affiliation': 'University of Wisconsin¿Madison', 'bio': {'p': ['Michael R. Marty is a software engineer at Google. His research focuses on the memory systems of multicore processors. He obtained his PhD in computer sciences from the University of Wisconsin-Madison.']}}, {'name': 'Mark D. Hill', 'affiliation': 'University of Wisconsin¿Madison', 'bio': {'p': ['Mark D. Hill is a professor in the Computer Sciences and the Electrical and Computer Engineering Departments at the University of Wisconsin—Madison. His research interests include parallel computer system design, memory system design, and computer simulation. He earned a PhD in computer science from the University of California, Berkeley. He is an IEEE Fellow and an ACM Fellow.']}} %*Virtual Hierarchies %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4460517 %f/micro/tukwsxieexcbqmk5prz4mjzorvtulgwh.pdf %m9cefe660401f2eb37696febcfa61abfc %cmicro %@[{'name': 'Philip Emma', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/4460501/4460518/4460518-photo-1-small.gif', 'p': ['']}} %*A Collaborative IP-Development Session %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4460518 %f/micro/zcluxe8no0twmfq6bspe27rmkxabj14g.pdf %m767a94335ff5629b6121718ec29cf545 %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'Kellogg Graduate School of Management', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/4523348/4523352/4523352-photo-1-small.gif', 'p': []}} %*The Long Arc Behind Bill Gates' Wealth, Part 2 %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4523352 %f/micro/guzj7dmpyih4v6hxoylacnqu2ede8lcr.pdf %maa3e43d4765271be1e680ae5f501daa0 %cmicro %@[{'name': 'Raj Amirtharajah', 'affiliation': 'University of California, Davis', 'bio': {'p': ['Rajeevan Amirtharajah is an assistant professor in the Electrical and Computer Engineering Department at the University of California, Davis. His research interests include low-power VLSI design for sensor applications, powering systems from ambient energy sources, and high-performance circuit and interconnect design. Amirthar-ajah has an SB, an MEng, and a PhD-all in electrical engineering-from the Massachusetts Institute of Technology. He received the National Science Foundation Career award in 2006 and is a member of the IEEE, the AAAS, and Sigma Xi.']}}, {'name': 'John Mashey', 'affiliation': 'Techviser', 'bio': {'p': ['John Mashey is a consultant for venture capitalists and technology companies, and he gives public talks on software engineering, RISC design, performance benchmarking, supercomputing, and Silicon Valley entrepreneurialism. Mashey was one of the founders of the SPEC benchmarking group, was an ACM National Lecturer for four years, and is one of the long-time organizers of Hot Chips. He holds a PhD in computer science from Pennsylvania State University.']}} %*Guest Editors' Introduction: Hot Chips 19 %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4523354 %f/micro/hzw5gipmz6ojkvsqum4bcqxy7jkldbcu.pdf %m2c7f37be3ce79ca180475f27d1bbc3e0 %cmicro %@[{'name': 'Jonathan Owen', 'affiliation': 'AMD', 'bio': {'p': ['Jonathan Owen is a principal member of technical staff at AMD, working in north-bridge architecture and design for mobile CPUs. He has been a contributor to both the HyperTransport I/O Link and PCI Express Base specifications. Owen has an MEng in electrical engineering from Cornell University.']}}, {'name': 'Maurice Steinman', 'affiliation': 'AMD', 'bio': {'p': ['Maurice Steinman is an AMD Fellow, working in northbridge architecture and design for mobile CPUs. He has been working in the computer industry for more than 20 years since graduating from Rensselaer Polytechnic Institute with a BS in computer and systems engineering in 1986.']}} %*Northbridge Architecture of AMD's Griffin Microprocessor Family %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4523355 %f/micro/ecxvt7fs2kyld4mwoanthw3pvq61p590.pdf %m7b9c7de40bcfd5b3adb9190e198a4e06 %cmicro %@[{'name': 'Charles F. Webb', 'affiliation': 'IBM', 'bio': {'p': ["Charles F. Webb is an IBM Fellow in IBM's Systems and Technology Group in Poughkeepsie, New York, working on processor and system design for future IBM System z servers. He was the overall technical leader for the z10 processor, and his technical interests include various aspects of mainframe processor design, including performance analysis, microarchitecture, instruction set architecture, and system design. He has a BS and an MEng in computer and systems engineering from Rensselaer Polytechnic Institute. He is a member of the IEEE Computer Society."]}} %*IBM z10: The Next-Generation Mainframe Microprocessor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4523356 %f/micro/0slkwikbtuqgsaviphhn3ujrwyo2tvec.pdf %m0a3d07f668250e1382f6d6c8561f0474 %cmicro %@[{'name': 'Kevin Reick', 'affiliation': 'IBM Systems & Technology Group', 'bio': {'p': ['Kevin Reick is a senior technical staff member at the IBM Systems & Technology Group and is currently the Power7 RAS architect. His work specializes in all aspects of system RAS, system debug design, and virtual bringup. He received his MS in computer engineering from Syracuse University.']}}, {'name': 'Pia N. Sanda', 'affiliation': 'IBM Systems & Technology Group', 'bio': {'p': ['Pia N. Sanda is a senior technical staff member with the IBM Systems & Technology Group in the Poughkeepsie-based Technology Development Team and is a member of the IBM Academy of Technology. Her current work focuses on soft error reliability to ensure the dependability of server systems. She received a PhD in physics from Cornell University. She is a senior member of the IEEE.']}}, {'name': 'Scott Swaney', 'affiliation': 'IBM Systems & Technology Group', 'bio': {'p': ['Scott Swaney is a senior technical staff member with the IBM Systems & Technology Group. He has extensive experience with RAS design at the system and processor microarchitectural levels. He received a BS in electrical engineering from Pennsylvania State University.']}}, {'name': 'Jeffrey W. Kellington', 'affiliation': 'IBM Systems & Technology Group', 'bio': {'p': ['Jeffrey W. Kellington is a staff functional verification engineer for the System P Development Group in the IBM Systems & Technology Group. His work includes running Linux and assembly-based functional exercisers and benchmark programs on development hardware and verification models. He received his BS in computer engineering from the University of Illinois.']}}, {'name': 'Michael Mack', 'affiliation': 'IBM Systems & Technology Group', 'bio': {'p': ['Michael J. Mack is a senior engineering manager in processor development for the IBM Systems and Technology Group. His work includes hardware-based processor recovery, SoC design, designer-based verification techniques, and engineering management. He received a BS in computer engineering from Syracuse University.']}}, {'name': 'Michael Floyd', 'affiliation': 'IBM Systems & Technology Group', 'bio': {'p': ['Michael S. Floyd is a senior engineer with the IBM Server & Technology Group. He specializes in RAS, test, debug, and power-efficient design of server microprocessors and systems. He received a MS in electrical engineering from Stanford University.']}}, {'name': 'Daniel Henderson', 'affiliation': 'IBM Systems & Technology Group', 'bio': {'p': ['Daniel Henderson is a senior technical staff member leading Power Systems availability RAS design. His research interests include Power system hardware design, RAS architecture, test, and fault analysis. He received his BS in electrical engineering from New Mexico State University.']}} %*Fault-Tolerant Design of the IBM Power6 Microprocessor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4523357 %f/micro/f4xmyifxgqbgrqlrnsjw5kppe91k3ehz.pdf %mb446a7cb6e3e289ff4b01e67f78b2cee %cmicro %@[{'name': 'Erik Lindholm', 'affiliation': 'NVIDIA', 'bio': {'p': ['Erik Lindholm is a distinguished engineer at NVIDIA, working in the architecture group. His research interests include graphics processor design and parallel graphics architectures. Lindholm has an MS in electrical engineering from the University of British Columbia.']}}, {'name': 'John Nickolls', 'affiliation': 'NVIDIA', 'bio': {'p': ['John Nickolls is director of GPU computing architecture at NVIDIA. His interests include parallel processing systems, languages, and architectures. Nickolls has a BS in electrical engineering and computer science from the University of Illinois and MS and PhD degrees in electrical engineering from Stanford University.']}}, {'name': 'Stuart Oberman', 'affiliation': 'NVIDIA', 'bio': {'p': ['Stuart Oberman is a design manager in the GPU hardware group at NVIDIA. His research interests include computer arithmetic, processor design, and parallel architectures. Oberman has a BS in electrical engineering from the University of Iowa and MS and PhD degrees in electrical engineering from Stanford University. He is a senior member of the IEEE.']}}, {'name': 'John Montrym', 'affiliation': 'NVIDIA', 'bio': {'p': ['John Montrym is a chief architect at NVIDIA, where he has worked in the development of several GPU product families. His research interests include graphics processor design, parallel graphics architectures, and hardware-software interfaces. Montrym has a BS in electrical engineering from the Massachusetts Institute of Technology.']}} %*NVIDIA Tesla: A Unified Graphics and Computing Architecture %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4523358 %f/micro/z6wifbmheckmgly8njtu5pexuypgtnlh.pdf %m5ca61f8951e15eba730552250be45c8f %cmicro %@[{'name': 'Jeffrey M. Gilbert', 'affiliation': 'SiBEAM', 'bio': {'p': ['Jeffrey M. Gilbert is the chief technical officer at SiBEAM. His research interests include wireless communication and video, image, and audio compression and enhancement. Gilbert has a PhD in electrical engineering from the University of California, Berkeley, an MPhil from Cambridge University, and a BA from Harvard College.']}}, {'name': 'Chinh H. Doan', 'affiliation': 'SiBEAM', 'bio': {'p': ['Chinh H. Doan is the vice president of RF and analog design and a cofounder at SiBEAM. His research interests include the design of 60-GHz circuits and systems for wireless transceivers using CMOS technology. Doan has an MS in electrical engineering from the University of California, Berkeley, and a BS from the California Institute of Technology.']}}, {'name': 'Sohrab Emami', 'affiliation': 'SiBEAM', 'bio': {'p': ['Sohrab Emami is the chief architect and a cofounder of SiBEAM. His research interests include the design and modeling of 60-GHz CMOS transceiver circuits. Emami has an MS in physical electronics from the Tokyo Institute of Technology.']}}, {'name': 'C. Bernard Shung', 'affiliation': 'SiBEAM', 'bio': {'p': ['C. Bernard Shung is the vice president of IC engineering and a cofounder at SiBEAM. His research interests include wireless communication, digital signal processing, and VLSI architecture. Shung has a PhD and MS in electrical engineering and computer science from the University of California, Berkeley, and a BS from National Taiwan University.']}} %*A 4-Gbps Uncompressed Wireless HD A/V Transceiver Chipset %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4523359 %f/micro/xmvbmisdnlbq7i5oat9eekaurkhwonzs.pdf %m2a090044766a2c5e6f9ce4378dd9f4ea %cmicro %@[{'name': 'Richard Stern', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/4523348/4523361/4523361-photo-1-small.gif', 'p': []}} %*FTC Sues N-Data for Violating Standards Commitment to IEEE %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4523361 %f/micro/lght1jxidnlzifmadscworuy0pkewgan.pdf %m1b83b9ef7220f8578fbfd4f0072ba0cd %cmicro %@[{'name': 'Richard Mateosian'} %*The Paradigms, They Are A-Changin' %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4523362 %f/micro/m7mrfo0cwbxe6pzsghwf1libku8zg2y9.pdf %mf1582a1f2de0882b58a06f165427f597 %cmicro %@[{'name': 'Sangyeun Cho', 'affiliation': 'University of Pittsburgh', 'bio': {'p': ['Sangyeun Cho is an assistant professor in the Computer Science Department at the University of Pittsburgh. His primary research interests are in computer architecture, system software design, and their synergy. His current projects investigate various ways to improve performance, reliability, and power/energy of next-generation many-core processors. He was a processor architect and designer at Samsung Semiconductor and participated in the commercially successful CalmRISC project. He has a BS in computer engineering from Seoul National University, and an MS and PhD from the University of Minnesota, Minneapolis. He is a member of the ACM and the IEEE.']}}, {'name': 'Tao Li', 'affiliation': 'University of Florida', 'bio': {'p': ['Tao Li is an assistant professor in the Department of Electrical and Computer Engineering at the University of Florida. His research interests include computer architecture, dependable computing systems, and the impacts of emerging techniques and applications on computer designs and operating systems. Li received 2006 and 2007 IBM Faculty Awards. He has a PhD in computer engineering from the University of Texas at Austin.']}}, {'name': 'Onur Mutlu', 'affiliation': 'Microsoft Research', 'bio': {'p': ['Onur Mutlu is a researcher at Microsoft Research. His research interests include computer architecture, especially the interaction and cooperation between program-mers, languages, operating systems, compilers, and architectures. Mutlu has BS degrees in computer engineering and psychology from the University of Michigan, Ann Arbor, and MS and PhD degrees in electrical and computer engineering from the University of Texas at Austin. He was a recipient of the Intel PhD fellowship and the University of Texas George H. Mitchell Award for Excellence in Graduate Research. He is a member of the IEEE and the ACM.', 'Direct questions and comments about this special issue to Sangyeun Cho, 5407 Sennott Square, Pittsburgh, PA 15260, cho@cs.pitt.edu.']}} %*Guest Editors' Introduction: Interaction of Many-Core Computer Architecture and Operating Systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4550855 %f/micro/kfoobwpvjns5btqp0as92ic7we4tykzd.pdf %mb4c5ef7523ee871352f61e15f003fdc0 %cmicro %@[{'name': 'Kyle J. Nesbit', 'affiliation': 'University of Wisconsin-Madison', 'bio': {'p': ['Kyle J. Nesbit is a PhD candidate in the Department of Electrical and Computer Engineering at the University of Wiscon-sin-Madison. His research interests include computer architecture and virtual machines, particularly multicore architectures and resource management for emerging plat-forms. Nesbit received his BS in computer engineering from the University of Wiscon-sin-Madison.']}}, {'name': 'Miquel Moreto', 'affiliation': 'Polytechnic University of Catalonia', 'bio': {'p': ['James E. Smith is a professor emeritus in the Department of Electrical and Computer Engineering at the University of Wiscon-sin-Madison and a member of the technical staff at Google. His current research interests include high-performance and power-efficient processor implementations, processor performance modeling, and virtual machines. Smith has a PhD in computer science from the University of Illinois.', "Direct questions and comments about this article to Kyle J. Nesbit, Univ. of Wisconsin-Madison, 2420 Engineering Hall, 1415 Engineering Dr., Madison, WI 53706–1691, kjnesbitis'wisc.edu.", 'For more information on this or any other computing topic, please visit our Digital Library at http://computer.org/csdl.']}}, {'name': 'Francisco J. Cazorla', 'affiliation': 'Barcelona Supercomputing Center', 'bio': {'p': ['Miquel Moreto is a PhD candidate in the Computer Architecture Department at the Polytechnic University of Catalonia, Spain. His research interests include modeling parallel computers and resource sharing in multithreaded architectures. Moreto received his MS in both mathematics and electrical engineering from the Polytechnic University of Catalonia.']}}, {'name': 'Alex Ramirez', 'affiliation': 'Barcelona Supercomputing Center and Polytechnic University of Catalonia', 'bio': {'p': ['Francisco J. Cazorla is the leader of the Operating System/Computer Architecture Interface group at the Barcelona Super-computing Center. His research focuses on multithreaded architectures for both highperformance and real-time computing sys-tems. Cazorla received his PhD in Computer Architecture from the Polytechnic University of Catalonia.']}}, {'name': 'Mateo Valero', 'affiliation': 'Barcelona Supercomputing Center and Polytechnic University of Catalonia', 'bio': {'p': ['Alex Ramirez is an associate professor at the Polytechnic University of Catalonia and research manager at the Barcelona Super-computing Center. Research interests include heterogeneous multicore architectures, hardware support for programming models, and simulation techniques. He received his PhD in computer science from the Polytechnic University of Catalonia.']}}, {'name': 'James E. Smith', 'affiliation': 'University of Wisconsin-Madison', 'bio': {'p': ['Mateo Valero is a professor at the Polytechnic University of Catalonia and director of the Barcelona Supercomputer Center. His research interests include high-perfor-mance architectures. Valero has a PhD in telecommunications from the Polytechnic University of Catalonia. He is a recipient of the Eckert-Mauchly Award and a founding member of the Royal Spanish Academy of Engineering. He is an IEEE Fellow, an Intel Distinguished Research Fellow, and an ACM Fellow.']}} %*Multicore Resource Management %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4550856 %f/micro/qebw2tqhjgytpdrgwfic04ndb8ph9ck7.pdf %m3dfc7a6ef9ba3b20132221dcad7dc1c2 %cmicro %@[{'name': 'Fred A. Bower', 'affiliation': 'IBM and Duke University', 'bio': {'p': ['Fred A. Bower is a senior engineer in the Systems and Technology Group at IBM, and is pursuing his PhD in computer science at Duke University. His research interests focus on processor microarchitecture and the exposed interface to system software. He has a BS in mechanical engineering and computer science from Oregon State University and an MS in computer science and engineering from the Oregon Graduate Institute.']}}, {'name': 'Daniel J. Sorin', 'affiliation': 'Duke University', 'bio': {'p': ['Daniel J. Sorin is an assistant professor of electrical and computer engineering and of computer science at Duke University. His research interests are centered on computer architecture, with a focus on dependability and verification. He has a BSE in electrical engineering from Duke University, and an MS and a PhD in electrical and computer engineering from the University of Wiscon-SIn.']}}, {'name': 'Landon P. Cox', 'affiliation': 'Duke University', 'bio': {'p': ['Landon P. Cox is an assistant professor in the Computer Science Department at Duke University. His research interests include distributed systems and operating systems. He has a BS in computer science from Duke University, and an MS and a PhD in computer science and engineering from the University of Michigan.']}} %*The Impact of Dynamically Heterogeneous Multicore Processors on Thread Scheduling %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4550857 %f/micro/0bzqw4vt9iq73dx6yrbsokghj5ijfowa.pdf %m594de127472e79bbcf7652943436adac %cmicro %@[{'name': 'Jeffrey C. Mogul', 'affiliation': 'HP Labs', 'bio': {'p': ['Jeffrey C. Mogul is a Fellow at HP Laboratories. His research interests include operating systems and computer networks. Mogul has a PhD in computer science from Stanford University. He is a Fellow of the ACM.']}}, {'name': 'Jayaram Mudigonda', 'affiliation': 'HP Labs', 'bio': {'p': ['Jayaram Mudigonda is a research scientist at HP Laboratories. His research interests include networking, operating systems, and architecture. Mudigonda has a PhD in computer sciences from the University of Texas at Austin.']}}, {'name': 'Nathan Binkert', 'affiliation': 'HP Labs', 'bio': {'p': ['Nathan Binkert is a research scientist at HP Laboratories. His research interests lie at the intersection of computer architecture, operating systems, and networking. Binkert has a BSE in electrical engineering, and an MS and a PhD in computer science, all from the University of Michigan.']}}, {'name': 'Parthasarathy Ranganathan', 'affiliation': 'HP Labs', 'bio': {'p': ['Parthasarathy Ranganathan is a principal research scientist at HP Laboratories. His research interests include low-power design, system architecture, and parallel computing. Ranganathan has a PhD in electrical and computer engineering from Rice University.']}}, {'name': 'Vanish Talwar', 'affiliation': 'HP Labs', 'bio': {'p': ['Vanish Talwar is a research scientist at HP Laboratories. His research interests include distributed systems, operating systems, and computer networks, with a focus on management technologies. Talwar has a PhD in computer science from the University of Illinois at Urbana Champaign.', 'Direct questions and comments about this article to Jeffrey Mogul, 1501 Page Mill Road, MS 1177, Palo Alto, CA 94304, jeff.mogul@hp.com.']}} %*Using Asymmetric Single-ISA CMPs to Save Energy on Operating Systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4550858 %f/micro/nndgvzcj6ae2z9bitj43tbwegysxqu8x.pdf %ma231881dff85ea4d80091afb5fbe28f0 %cmicro %@[{'name': 'Stijn Eyerman', 'affiliation': 'Ghent University', 'bio': {'p': ['Stijn Eyerman is a PhD student in the Electronics and Information Systems Department at Ghent University, Belgium. His research interests include computer architecture in general and performance analysis and modeling in particular. Eyer-man has an MS in computer science and engineering from Ghent University.']}}, {'name': 'Lieven Eeckhout', 'affiliation': 'Ghent University', 'bio': {'p': ['Lieven Eeckhout is an assistant professor in the Electronics andInformation Systems Department at Ghent University, Belgium. His research interests include computer architecture, virtual machines, performance analysis and modeling, and workload char-acterization. Eeckhout has a PhD in computer science and engineering from Ghent University. He is a member of the IEEE and the ACM.', 'Direct questions and comments about this article to Lieven Eeckhout, ELIS Dept., Ghent University, Sint-Pieternieuwstraat 41, B-9000 Ghent, Belgium, leeckhou@elis.UGent.be.', 'For more information on this or any other computing topic, please visit our Digital Library at http://computer.org/csdl.']}} %*System-Level Performance Metrics for Multiprogram Workloads %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4550859 %f/micro/wg7ayihcu0gs4eslyf6dmjimofdkb5av.pdf %m4a75b15a0f990a3f9023a50287daf3b1 %cmicro %@[{'name': 'Rob Knauerhase', 'affiliation': 'Intel', 'bio': {'p': ['Rob Knauerhase is a staff research scientist at Intel Labs. His research interests include system software, machine virtualization, mobile computing and communications, and information privacy in the digital world. Knauerhase has an MS in computer science from the University of Illinois at Urbana-Champaign. He is a senior member of the IEEE.']}}, {'name': 'Paul Brett', 'affiliation': 'Intel', 'bio': {'p': ['Paul Brett is a senior software engineer at Intel Labs. His professional interests include virtualization, distributed systems, and system software. Brett has a first-class honours degree in systems engineering from the Open University, UK.']}}, {'name': 'Barbara Hohlt', 'affiliation': 'Intel', 'bio': {'p': ['Barbara Hohlt is a research scientist at Intel Labs. Her research interests include operating systems, distributed systems, and networks. Hohlt has a PhD in computer science from the University of California at Berkeley.']}}, {'name': 'Tong Li', 'affiliation': 'Intel', 'bio': {'p': ['Tong Li is a senior software engineer at Intel Labs. His research interests include processor micro architecture and operating systems. Li has a PhD in computer science from Duke University.']}}, {'name': 'Scott Hahn', 'affiliation': 'Intel', 'bio': {'p': ['Scott Hahn is a principal engineer at Intel Labs, where he leads the Operating System Research Group. His professional interests include operating systems, data networking, supercomputer networks, and network management. Hahn has an MS in computer science from Union College.', 'Direct questions and comments about this article to Rob Knauerhase, Intel Labs, Intel Corp., 2111 NE 25th Ave., Mailstop]F2–55, Hillsboro, OR 97124–5961, knauer@ichips.intel.com.', 'For more information on this or any other computing topic, please visit our Digital Library at http://computer.org/csdl.']}} %*Using OS Observations to Improve Performance in Multicore Systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4550860 %f/micro/ppry9yqhdckhifjkmnxu0oc52i8avo6v.pdf %mdcc08e6c8e2364a2207d062314277f01 %cmicro %@[{'name': 'Richard Stern'} %*AAI Asks FTC to Investigate RAND Issues Concerning Digital TV Standard %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4550862 %f/micro/5xhsbzofvwvir4yt6acrcoe71faiyump.pdf %m12b93abc780d40a060fa5dc0e1094e3a %cmicro %@[{'name': 'Shane Greenstein', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/4626808/4626813/4626813-photo-1-small.gif', 'p': ['Shane Greenstein greenstein@kellogg.northwestern.edu']}} %*Voting and Economic Asymmetry %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4626813 %f/micro/10v6ixyuevzhzqepcmgsuknpxwoadqa9.pdf %mddfcc11405e9c81488a30f8e981449b1 %cmicro %@[{'name': 'Sanjay Patel', 'affiliation': 'University of Illinois at Urbana-Champaign', 'bio': {'p': ['Sanjay J. Patel is an associate professor of electrical and computer engineering and Willett Faculty Scholar at the University of Illinois at Urbana-Champaign. His research interests include high-performance and massively parallel chip architectures, parallel programming models, and visual computing applications. He has considerable commercial chip design experience, working and consulting for a number of companies, including Digital Equipment Corporation and Intel. From 2005 to 2008, he was the CTO and Chief Architect of AGEIA Technologies, a fabless semiconductor industry that developed chips for accelerating physical simulation for video games. Patel earned his BS, MS, and PhD in computer science and engineering from the University of Michigan, Ann Arbor. He is a member of the IEEE.']}}, {'name': 'Wen-mei W. Hwu', 'affiliation': 'University of Illinois at Urbana-Champaign', 'bio': {'p': ['Wen-mei W. Hwu is Sanders-AMD Endowed Chair Professor in the Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign. He also directs the IMPACT research group (Illinois Microarchitecture Project utilizing Advanced Compiler Technology, www.crhc.uiuc.edu/Impact) and is hardware lead of the NSF Petascale Computer Project awarded to the University of Illinois and IBM in 2007. His research interests are in architecture, implementation, and programming tools for parallel computer systems-in particular, novel computer architectures and the compiler techniques they require. For his contributions in research and teaching, he received the Eta Kappa Nu Holmes MacDonald Outstanding Teaching Award, the ACM SigArch Maurice Wilkes Award, the ACM Grace Murray Hopper Award, the Tau Beta Pi Daniel C. Drucker Eminent Faculty Award, and the ACM/IEEE ISCA Most Influential Paper Award. Hwu has a PhD in computer science from the University of California, Berkeley. He is a fellow of both the IEEE and the ACM.']}} %*Accelerator Architectures %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4626814 %f/micro/pgnqmbm7xyewvuzdklo8nfw2aejvcpib.pdf %m98c30a2651f9e26a5bf6d8146bd73e6f %cmicro %@[{'name': 'Michael Garland', 'affiliation': 'NVIDIA', 'bio': {'p': ['Michael Garland is a research scientist at NVIDIA. His research interests include computer graphics and visualization, geometric algorithms, and parallel algorithms and programming models. Garland received his PhD in computer science from Carnegie Mellon University.']}}, {'name': 'Scott Le Grand', 'affiliation': 'NVIDIA', 'bio': {'p': ['Scott Le Grand is a senior engineer on the CUDA software team at NVIDIA. Le Grand received a BS in biology from Siena College and a PhD in biochemistry from Pennsylvania State University.']}}, {'name': 'John Nickolls', 'affiliation': 'NVIDIA', 'bio': {'p': ['John Nickolls is director of architecture at NVIDIA for GPU computing. His interests include parallel processing systems, languag-es, and architectures. Nickolls received his PhD in electrical engineering from Stanford University.']}}, {'name': 'Joshua Anderson', 'affiliation': 'Iowa State University and Ames Laboratory', 'bio': {'p': ['Joshua Anderson is a graduate student in the Department of Physics and Astronomy at Iowa State University and the Ames Laboratory. His PhD work focuses on the design and implementation of a general-purpose molecular dynamics simulation code on the GPU and the theoretical design of new polymeric materials by computational methods. Anderson received his BS in physics and computer science from Michigan Tech.']}}, {'name': 'Jim Hardwick', 'affiliation': 'TechniScan Medical Systems', 'bio': {'p': ['Jim Hardwick is the senior software engineer at TechniScan Medical Systems in Salt Lake City, Utah. His expertise is in medical device development, including software and hardware development and human-computer interaction. Hardwick received his BS in computer science from Westminster College.']}}, {'name': 'Scott Morton', 'affiliation': 'Hess', 'bio': {'p': ['Scott Morton leads a geophysical technology group at Hess Corporation. His research interests include geophysical technologies with a focus on seismic imaging. Morton received his PhD in astrophysics from the University of Illinois at Urbana-Champaign.']}}, {'name': 'Everett Phillips', 'affiliation': 'University of California, Davis', 'bio': {'p': ['Everett Phillips is a graduate student at the University of California, Davis, working in mechanical and aeronautical engineering and electrical and computer engineering. His research interests include computational fluid dynamics, parallel computing, and graphics hardware. Phillips received his BS in mechanical engineering from the University of California, Davis.']}}, {'name': 'Yao Zhang', 'affiliation': 'University of California, Davis', 'bio': {'p': ['Yao Zhang is a PhD student in the Department of Electrical and Computer Engineering at University of California, Davis. Zhang received his BS in electrical engineering from the Beijing Institute of Technology. His research interests are in the area of GPU computing, especially in solving linear algebra and fluid problems on GPUs.']}}, {'name': 'Vasily Volkov', 'affiliation': 'University of California, Berkeley', 'bio': {'p': ['Vasily Volkov is a PhD student in the Department of Electrical Engineering and Computer Science at the University of California, Berkeley. His reserach interests include high-performance computing and numerical linear algebra. Volkov received his MS from the Moscow Institute of Physics and Technology and MEng from the Nanyang Technological University.']}} %*Parallel Computing Experiences with CUDA %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4626815 %f/micro/bilumg4c2a6eo5h3kz19gslrcebutxmv.pdf %mf0149fbad555515dfe6d52fd9ea21f67 %cmicro %@[{'name': 'Dong Hyuk Woo', 'affiliation': 'Georgia Institute of Technology', 'bio': {'p': ['Dong Hyuk Woo is a PhD student in the School of Electrical and Computer Engineering at Georgia Institute of Technology. His research interests include energy-efficient many-core architecture and resource-sharing problems of multicore processors. Woo received his MS in electrical and computer engineering from the Georgia Institute of Technology.']}}, {'name': 'Hsien-Hsin S. Lee', 'affiliation': 'Georgia Institute of Technology', 'bio': {'p': ['Hsien-Hsin S. Lee is an associate professor of the School of Electrical and Computer Engineering at the Georgia Institute of Technology. His research interests include computer architecture, cyber security, and 3D integration. Lee received his PhD in computer science and engineering from the University of Michigan at Ann Arbor. He has received the US Department of Energy and the National Science Foundation Career awards.']}}, {'name': 'Joshua B. Fryman', 'affiliation': 'Intel', 'bio': {'p': ["Joshua B. Fryman is a senior research scientist with Intel's Microprocessor Technology Lab. His interests include computer architecture, interconnection networks, parallel programming, and the performance bottlenecks of many-core systems. Fryman received his PhD in computer science from the Georgia Institute of Technology."]}}, {'name': 'Allan D. Knies', 'affiliation': 'Intel', 'bio': {'p': ["Allan D. Knies is a principal engineer and associate director of Intel's Berkeley Research Lab. His interests include computer architecture, performance analysis, and parallelism. Knies received his PhD in computer engineering from Purdue University."]}}, {'name': 'Marsha Eng', 'affiliation': 'Intel', 'bio': {'p': ['Marsha Eng is a marketing engineer at Intel Corporation. Her interests include computer architecture design, performance analysis, and benchmarking. Eng received her MBA from Santa Clara University and MS in computer science from the University of California at San Diego.']}} %*POD: A 3D-Integrated Broad-Purpose Acceleration Layer %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4626816 %f/micro/dtrrxb9ipvkejmd8vg3bf0caoileq4cl.pdf %m642a6b4623b6a73d312f898fb0cdd5ad %cmicro %@[{'name': 'Bruno Bougard', 'affiliation': 'IMEC', 'bio': {'p': ["Bruno Bougard is a senior researcher at IMEC, Belgium's Interuniversity MicroElectronic Centre, which performs research and development, ahead of industrial needs by three to 10 years, in microelectronics, nanotechnology, enabling design methods, and technologies for information and communications technology systems. His research interests focus on energy-efficient circuits and systems for broadband wireless communication, specifically energy-aware software-defined and cognitive radio. He has an MSc in electrical engineering from the Polytechnic University of Mons, Belgium, and a PhD in electrical engineering from Katholieke Universiteit Leuven, Belglum."]}}, {'name': 'Bjorn De Sutter', 'affiliation': 'Ghent University', 'bio': {'p': ['Bjorn De Sutter led the architecture and compilation team at IMEC until early 2008, where he completed the work described in this article. He now holds a research position at Ghent University. His compiler research has focused on whole program optimization, program compaction, binary rewriting, and code generation techniques for reconfigurable architectures. He has an MSc and a PhD in computer science from Ghent University, Belgium.']}}, {'name': 'Diederik Verkest', 'affiliation': 'IMEC', 'bio': {'p': ["Diederik Verkest is a member of IMEC's VLSI Design Methodology Group and is currently in charge of IMEC's research on design technology for nomadic embedded systems. He is also a professor at Vrije Universiteit Brussel and at Katholieke Universiteit Leuven. He has an MSc degree and a PhD in applied sciences from Katholieke Universiteit Leuven."]}}, {'name': 'Liesbet Van der Perre', 'affiliation': 'IMEC', 'bio': {'p': ['Liesbet Van der Perre is the scientific director of the IMEC Wireless Research Group, comprising teams of researchers in the fields of digital baseband solutions, RF front ends, cross-layer optimization, mixed signal design technologies, and ultralow power radios. She has an MSc and a PhD in electrical engineering from Katholieke Universiteit Leuven.']}}, {'name': 'Rudy Lauwereins', 'affiliation': 'IMEC', 'bio': {'p': ['Rudy Lauwereins is vice president of IMEC, where he leads the Nomadic Embedded Systems Division. He is also a professor at Katholieke Universiteit Leuyen. His current research interests include many system-level aspects of digital design technology. These range from multicore software mapping, over the exploitation of 3D stacking technology, to system-level solutions to process variability. He has an MEng and a PhD in electrical engineering from Katholieke Universiteit Leuven.']}} %*A Coarse-Grained Array Accelerator for Software-Defined Radio Baseband Processing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4626817 %f/micro/wgack4fricavl6ymxel5trh0uy1fsp2d.pdf %mc7af0dc0106098bbd345890fda91f55b %cmicro %@[{'name': 'Mei Wen', 'affiliation': 'National University of Defense Technology, China', 'bio': {'p': ['Mei Wen is an associate professor in the National Laboratory for Parallel and Distributed Processing at the National University of Defense Technology, China. Her research interests include computer architecture and parallel processing. Wen has a BS, an MS, and a PhD in computer science and technology from the National University of Defense Technology.']}}, {'name': 'Nan Wu', 'affiliation': 'National University of Defense Technology, China', 'bio': {'p': ['Nan Wu is a PhD candidate in the Computer School at the National University of Defense Technology. His research interests include computer architecture and parallel processing. Wu has a BS and an MS in computer science and technology from the National University of Defense Technology.']}}, {'name': 'Chunyuan Zhang', 'affiliation': 'National University of Defense Technology, China', 'bio': {'p': ['Chunyuan Zhang is a professor of computer science and technology at the National University of Defense Technology, where his group developed the MASA stream system and took part in the development of the FT64. Zhang has a BS, an MS, and a PhD in computer science and technology from the National University of Defense Technology.']}}, {'name': 'Qianming Yang', 'affiliation': 'National University of Defense Technology, China', 'bio': {'p': ["Qianming Yang is a master's student in computer science and technology at the National University of Defense Technology. His research interests include VLSI circuit techniques and systems architecture. Yang has a BS in computer science and technology from the National University of Defense Technology."]}}, {'name': 'Jun Ren', 'affiliation': 'National University of Defense Technology, China', 'bio': {'p': ['Jun Ren is a PhD candidate in the Computer School at the National University of Defense Technology. His research interests include parallel processing and computation-intensive applications. Ren has a BS from Dongbei University and an MS from the National University of Defense Technology.']}}, {'name': 'Yi He', 'affiliation': 'National University of Defense Technology, China', 'bio': {'p': ['Yi He is a PhD candidate in the Computer School at the National University of Defense Technology. His research interests include computer architecture and circuit design. He has a BS from Wuhan University and an MS from the National University of Defense Technology.']}}, {'name': 'Wei Wu', 'affiliation': 'National University of Defense Technology, China', 'bio': {'p': ["Wei Wu is a master's student in computer science and technology at the National University of Defense Technology. His research interests include software support for parallel computer systems and media processing. Wu has a BS in computer science and technology from the National University of Defense Technology."]}}, {'name': 'Jun Chai', 'affiliation': 'National University of Defense Technology, China', 'bio': {'p': ["Jun Chai is a master's student in computer science and technology at the National University of Defense Technology. His research interests include circuit design and computation-intensive applications. Chai has a BS in computer science and technology from National University of Defense Technology."]}}, {'name': 'Maolin Guan', 'affiliation': 'National University of Defense Technology, China', 'bio': {'p': ['Maolin Guan is a PhD candidate in computer science and technology at the National University of Defense Technology. His research interests include compilers for high-performance processors. Guan has a BS and an MS in computer science and technology from the National University of Defense Technology.']}}, {'name': 'Changqing Xun', 'affiliation': 'National University of Defense Technology, China', 'bio': {'p': ["Changqing Xun is a master's student in computer science and technology at the National University of Defense Technology. His research interests include software support for parallel computer systems and computation-intensive applications. Xun has a BS in computer science and technology from the National University of Defense Technology."]}} %*On-Chip Memory System Optimization Design for the FT64 Scientific Stream Accelerator %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4626818 %f/micro/tilf5sexbvu2jkardy4iv6jyncb0r7hp.pdf %m0152ce7c471bbd93c9147bc317058ece %cmicro %@[{'name': 'Zhanpeng Jin', 'affiliation': 'University of Pittsburgh', 'bio': {'p': ['Zhanpeng Jin is a PhD student of electrical and computer engineering at the University of Pittsburgh. His research interests include computer architecture, biomedical and bioimplantable computing systems, ultra low-power, energy-efficient processors, VLSI and ASIC system design, and mathematical modeling. He has a BS and an MS in computer science from the Northwestern Polytechnical University in China. He is a student member of IEEE and the IEEE Computer Society.']}}, {'name': 'Allen C. Cheng', 'affiliation': 'University of Pittsburgh', 'bio': {'p': ['Allen C. Cheng is an assistant professor in the departments of Electrical and Computer Engineering, Computer Science, Neurological Surgery, and Neural Engineering in the McGowan Institute for Regenerative Medicine at the University of Pittsburgh, where he also serves as director of the Advanced Computing Technology Laboratory (ACT). His research interests include the interdisciplinary confluence of computer engineering, computer science, electrical engineering, neural engineering, biomedical engineering, and medicine. He has a BS in computer engineering from North Carolina State University, and an MS and a PhD in computer science and engineering from the University of Michigan, Ann Arbor. He is a member of the IEEE, the ACM, and the American Association for the Advancement of Science (AAAS).']}} %*ImplantBench: Characterizing and Projecting Representative Benchmarks for Emerging Bioimplantable Computing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4626819 %f/micro/5lnbh7opy9wrk6kt408velqrfchszmmu.pdf %mdd6a8a5d8bf351dd6215d177f758622e %cmicro %@[{'name': 'Richard Stern', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/4626808/4626820/4626820-photo-1-small.gif', 'p': ['']}} %*What Kinds of Computer-Software-Related Advances (if Any) Are Eligible for Patents? Part I %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4626820 %f/micro/ahm7sleqxzye0mu6jck4ynovjv5cokug.pdf %m59cea7a44b20eefa11c81218b9d397d1 %cmicro %@[{'name': 'David H. Albonesi', 'affiliation': 'albonesi@csl.cornell.edu', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/4659262/4659268/4659268-photo-1-small.gif', 'p': []}} %*Changes Ahead %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4659268 %f/micro/khpzu3ymeoj9pvs2yzngtl8fae4q1sbf.pdf %md875cb0bb88c48bd988c4f5cffcee268 %cmicro %@[{'name': 'Shane Greenstein', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/4659262/4659270/4659270-photo-1-small.gif', 'p': []}} %*Slouching Toward a Dystopian Internet %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4659270 %f/micro/x4ykorn6pn5kedsyuojiq3c9ftb2hawu.pdf %me9503e454d647924056ff492fd268f90 %cmicro %@[{'name': 'Eric Li', 'affiliation': 'Intel', 'bio': {'p': ['Eric Li is a senior researcher in the Corporate Technology Group at Intel. His research interests include innovative multimedia technology, performance analysis in current architectures, and designing next-generation architectures and platforms. He received an MS in electrical engineering from Tsinghua University, China.']}}, {'name': 'Wenlong Li', 'affiliation': 'Intel', 'bio': {'p': ['Wenlong Li is a researcher in the Corporate Technology Group at Intel. His research interests include energy-efficient cache and memory subsystem design for multicore processors, workload parallelization and characterization, and performance analysis. Wenlong received his PhD in computer science and technology from Tsinghua University.']}}, {'name': 'Xiaofeng Tong', 'affiliation': 'Intel', 'bio': {'p': ['Xiaofeng Tong is a researcher in the Corporate Technology Group at Intel. His research interests include media mining, computer vision, and parallel computing. He has been involved in projects on sports-video analysis, object detection and tracking, and semantic event surveillance. Tong received his PhD in computer science and technology computer science from the Institute of Automation, Chinese Academy of Sciences.']}}, {'name': 'Jianguo Li', 'affiliation': 'Intel', 'bio': {'p': ['Jianguo Li is a researcher in the Corporate Technology Group at Intel. His research interests include immersive visual computing, multimedia mining, and parallel algorithm design and analysis. Li received his PhD in electrical engineering from Tsinghua University.']}}, {'name': 'Yurong Chen', 'affiliation': 'Intel', 'bio': {'p': ['Yurong Chen is a senior researcher in the Corporate Technology Group at Intel. His research interests include emerging application prototyping, parallel processing, scalable workloads, benchmarking, and performance evaluation. Chen received his PhD in computational mathematics from the Tsinghua University, China.']}}, {'name': 'Tao Wang', 'affiliation': 'Intel', 'bio': {'p': ['Tao Wang is a researcher in the Corporate Technology Group at Intel. His research interests include multimedia mining, computer vision, pattern recognition, and computer graphics. Wang received his PhD in computer science from Tsinghua University.']}}, {'name': 'Patricia P. Wang', 'affiliation': 'Intel', 'bio': {'p': ['Patricia P. Wang is a researcher in the Corporate Technology Group at Intel. Her interests focus on exploring emerging applications and performing workload analysis. Wang received her PhD in computer science from Tsinghua University, China.']}}, {'name': 'Wei Hu', 'affiliation': 'Intel', 'bio': {'p': ['Wei Hu is a senior researcher in the Corporate Technology Group at Intel. His research interests include advanced media mining, computer vision, machine learning, and 3D object modeling. Hu received his PhD in computer science from the Institute of Computing Technology, Chinese Academy of Sciences.']}}, {'name': 'Yangzhou Du', 'affiliation': 'Intel', 'bio': {'p': ['Yangzhou Du is a researcher in the Corporate Technology Group at Intel. His research interests include pattern recognition, computer vision, and graphics as well as optimization and parallelization of multimedia application in multicore processors. Du received his PhD in computer science from Tsinghua University, Beijing.']}}, {'name': 'Yimin Zhang', 'affiliation': 'Intel', 'bio': {'p': ['Yimin Zhang is a research manager and senior researcher in the Corporate Technology Group at Intel. His research interests include developing advanced technology in the field of visual computing, media search and mining, and studying the performance implications for next-generation microprocessors and platforms. Zhang received his PhD in computer science from Shanghai Jiaotong University.']}}, {'name': 'Yen-Kuang Chen', 'affiliation': 'Intel', 'bio': {'p': ['Yen-Kuang Chen is a principal engineer in the Corporate Technology Group at Intel. His research interests include developing innovative multimedia applications, studying the performance bottleneck in current architectures, and designing next-generation microprocessors and platforms. Chen received his PhD in electrical engineering from Princeton University. He is a senior member of IEEE.']}} %*Accelerating Video-Mining Applications Using Many Small, General-Purpose Cores %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4659271 %f/micro/h2uscykqf09h7dakjxgwqmd3pg8zrnw1.pdf %mc1f4705f68b4316c9efdc141efc7ad45 %cmicro %@[{'name': 'Avinash Karanth Kodi', 'affiliation': 'Ohio University', 'bio': {'p': ['Avinash Karanth Kodi is an assistant professor of electrical engineering and computer science at Ohio University. His research interests include computer architecture, optical interconnects, chip multi-processors, and networks on chip. Kodi received his PhD in electrical and computer engineering from the University of Arizona, Tucson. He is a member of IEEE.']}}, {'name': 'Ahmed Louri', 'affiliation': 'University of Arizona', 'bio': {'p': ['Ahmed Louri is a professor of electrical and computer engineering at the University of Arizona and the director of the High-Performance Computing Architectures and Technologies (HPCA T) Laboratory. His research interests include computer architecture, parallel processing, optical interconnection networks, and networks on chip. Louri received his PhD in computer engineering from the University of Southern California. He is a senior member of IEEE and a member of the Optical Society of America.']}} %*Optisim: A System Simulation Methodology for Optically Interconnected HPC Systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4659272 %f/micro/aehhrnwffognts8dj9kbpx1edqxkzjcp.pdf %m89a40e6cacb13cf3472c4a79177c1e47 %cmicro %@[{'name': 'S.R. Chowdhury', 'affiliation': 'Jadavpur Univ., Kolkata', 'bio': {'p': ["Shubhajit Roy Chowdhury is a PhD student in the IC Design and Fabrication Center, Department of Electronics and Telecommunication, at Jadavpur University, Kolkata, India. His research interests include architectural design of ICs, FPGA-based smart embedded systems for medical diagnosis, and ASIC design of intelligent signal-processing circuits. Roy Chowdhury has an ME in software engineering from Jadavpur University. He's a member of VLSI Society of India, the Indian Statistical Institute, and the Indian Microelectronics Society."]}}, {'name': 'H. Saha', 'affiliation': 'Jadavpur Univ., Kolkata', 'bio': {'p': ["Hiranmay Saha is a professor and the coordinator of the IC Design and Fabrication Center in the Department of Electronics and Telecommunication Engineering at Jadavpur University. His research interests include microelectromechanical systems (MEMS)-based gas sensors, biosensors, complementary metal-oxide semiconductor MEMS integration, analog VLSI design, VLSI-based intelligent signal processing, embedded systems, and silicon solar cells. Saha has a PhD in solar cells and systems from Jadavpur University. He's a Fellow of the Institution of Electronics and Telecommunication Engineers, the West Bengal Academy of Science and Technology, and the Solar Energy Society of India."]}} %*A High-Performance FPGA-Based Fuzzy Processor Architecture for Medical Diagnosis %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4659274 %f/micro/reacrvwt8szpckgjbfozy9hu3b1akiq6.pdf %mf09fb122687ae6617870ac216c42e553 %cmicro %@[{'name': 'Junji Sakai', 'affiliation': 'NEC Corporation', 'bio': {'p': ['Junji Sakai is a principal researcher at the System IP Core Research Laboratories, NEC Corporation. He has been involved in the R & D of embedded multicore software for more than 10 years. He received an MS in information science from Kyoto University. He is an affiliate member of the IEEE Computer Society.']}}, {'name': 'Inoue Hiroaki', 'affiliation': 'NEC Corporation', 'bio': {'p': ["Inoue Hiroaki is an assistant manager at the System IP Core Research Laboratories, NEC Corporation. His research interests include hardware and software codesign for multiprocessor systems. He received a master's degree in engineering from Keio University. He is a member of the IEEE and ACM."]}}, {'name': 'Sunao Torii', 'affiliation': 'NEC Corporation', 'bio': {'p': ['Sunao Torii is a principal researcher at the System IP Core Research Laboratories, NEC Corporation. His research interests include multicore and low-power processor architecture and systems. He received an MS in computer sciences from Keio University.']}}, {'name': 'Masato Edahiro', 'affiliation': 'NEC Corporation', 'bio': {'p': ['Masato Edahiro is a research fellow at NEC Corporation and a visiting professor in the Department of Computer Science at the University of Tokyo. His research interests include graph/network algorithms, combinatorial optimization, and parallel algorithms for many cores. Masato received a PhD from Princeton University. He is a member of the IEEE, the Institute of Electronics, Information, and Communication Engineers, and the Information Processing Society of Japan.']}} %*Multitasking Parallel Method for High-End Embedded Appliances %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4659276 %f/micro/heyuvh3ssr9cfqmcixgfy06oaaj4nno7.pdf %m11760c3cea0c7690f4088fecab49fedc %cmicro %@[{'name': 'Richard Stern'} %*What Kinds of Computer-Software-Related Advances (if Any) Are Eligible for Patents? Part II: The "Useful Arts" Requirement %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4659278 %f/micro/nvpcdzof6f2cjwtyqstzubuvj8bexhqr.pdf %m2735306b36f3c170e6719bd860a5fd5f %cmicro %@[{'name': 'Richard Mateosian', 'affiliation': 'xrm@pacbell.net', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/4659262/4659279/4659279-photo-1-small.gif', 'p': ['Effective Java, second edition, Joshua Block (Addison-Wesley, 2008, 368 pp. US$49.99, ISBN 978–0-321–35668-0)', 'For more information on this or any other computing topic, please visit our Digital Library at http://computer.org/csdl.']}} %*Software Development Patterns [Micro Review] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4659279 %f/micro/76exuvastazpuycqiyq2bfsbck0fwojr.pdf %medfac074e40c38203206abed4e35de7f %cmicro %@[{'name': 'Shane Greenstein', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/4731164/4731168/4731168-photo-1-small.gif', 'p': ['SHANE GREENSTEIN']}} %*Chicken Little Predictions %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4731168 %f/micro/3zrbsapceuozxjm9fj6emkw4d7ko5gut.pdf %m15d7dc26047db7719b422bb2a221371d %cmicro %@[{'name': 'Philip G. Emma', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ["Philip G. Emma joined the IBM T.J. Watson Research Center in 1983. He has worked in the areas of microarchitecture, architecture, systems design, circuit design, electronic packaging, materials, interconnection technology, and optics. He is currently the manager of the Systems Technology and Microarchitecture group, which does advanced concept work in architecture and microarchitecture for IBM's p-series and z-series processors, as well as for processors for mobile applications and games. He also works on exploring and leveraging new physical technologies within the context of systems design. He holds over 100 patents and was named an IBM Master Inventor. Emma received his BS, MS, and PhD in electrical engineering from the University of Illinois. He is a member of the IBM Academy of Technology, and is a Fellow of the IEEE.", 'For more information on this or any other computing topic, please visit our Digital Library at http://computer.org/csdl.']}} %*Existential Architectures: The Metaphysics of Computer Design %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4731170 %f/micro/tvzq8caanuwieodjyuby2pgsk3cxbllf.pdf %m30fdeac8ff33fde275ee87ec70629bc2 %cmicro %@[{'name': 'Constantin Pistol', 'affiliation': 'Duke University', 'bio': {'p': ['Constantin Pistol is a doctoral student in computer science at Duke University. His research interests include architectures and digital-circuit design for molecular-scale computing systems. He has a BS in computer science from University of Craiova, Romania, and an MS in computer science from Duke University.']}}, {'name': 'Chris Dwyer', 'affiliation': 'Duke University', 'bio': {'p': ['Chris Dwyer is currently an assistant professor of electrical and computer engineering and of computer science at Duke University. His research interests include self-assembly, DNA, and the development of circuit technologies for molecular-scale fabrication processes. He has a BS in computer engineering from Pennsylvania Sate University, University Park, and an M\nS and a PhD in computer science from the University of North Carolina at Chapel Hill.']}}, {'name': 'Alvin R. Lebeck', 'affiliation': 'Duke University', 'bio': {'p': ['Alvin R. Lebeck is a professor of computer science and of electrical and computer engineering at Duke University. His research interests include architectures for emerging nanotechnologies and memory systems. He has a PhD in computer science from the University of Wisconsin–Madison. He is a senior member of the IEEE and a member of the ACM.']}} %*Nanoscale Optical Computing Using Resonance Energy Transfer Logic %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4731171 %f/micro/kwsz2boxjka9q0ndviow81lv3xc65ur7.pdf %mdb7a5f010407294abe11f1ce1f8109ed %cmicro %@[{'name': 'Zhanpeng Jin', 'affiliation': 'University of Pittsburgh', 'bio': {'p': ['Zhanpeng Jin is a PhD student in the Department of Electrical and Computer Engineering at the University of Pittsburgh. His research interests include computer architecture, biomedical and bioimplantable computing systems, ultralow-power energy-efficient processors, VLSI and ASIC system design, and mathematical modeling. Jin received his MS in computer science from the Northwestern Polytechnical University in China. He is a student member of the IEEE and the IEEE Computer Society.']}}, {'name': 'Allen C. Cheng', 'affiliation': 'University of Pittsburgh', 'bio': {'p': ['Allen C. Cheng is an assistant professor in the Department of Electrical and Computer Engineering, the Department of Computer Science, and the Department of Neurological Surgery at the University of Pittsburgh. He also serves as the director of the Advanced Computing Technology (ACT) Laboratory at University of Pittsburgh. His research interests are at the interdisciplinary confluence of computer engineering, computer science, electrical engineering, neural engineering, biomedical engineering, and medicine. Cheng received his PhD in computer science and engineering from the University of Michigan at Ann Arbor. He is a member of the IEEE, the ACM, and AAAS.', 'Direct questions and comments about this article to Zhanpeng Jin at the Dept. of Electrical and Computer Eng., Univ. of Pittsburgh, Pittsburgh, PA 16261, zhj6@pitt.edu.']}} %*Evolutionary Benchmark Subsetting %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4731172 %f/micro/p9164adnn5ytqxsiokycpmgcibvwgrea.pdf %ma1e8dab25442a920c6e6ae05c525ec0f %cmicro %@[{'name': 'Jaume Abella', 'affiliation': 'Intel Barcelona Research Center', 'bio': {'p': ['Jaume Abella is a senior researcher at the Intel Barcelona Research Center. His main research interests are hardware reliability and low-power designs. He received a PhD in computer science from the Universitat Politècnica de Catalunya, Barcelona, Spain.']}}, {'name': 'Xavier Vera', 'affiliation': 'Intel Barcelona Research Center', 'bio': {'p': ['Xavier Vera is a senior researcher at the Intel Barcelona Research Center. His research interests include reliable and variation-aware microarchitectures, and the design and analysis of high-performance and low-power computer architectures. He received an MS in computer science from the Universitat Politècnica de Catalunya and a PhD in computer science from Malardalens Högskola at Västerås.']}}, {'name': 'Osman S. Unsal', 'affiliation': 'Intel Barcelona Research Center', 'bio': {'p': ['Osman S. Unsal is a group manager at the Barcelona Supercomputing Center. His research interests include computer architecture, parallel processing, and reliability. He received a PhD in electrical and computer engineering from the University of Massachusetts, Amherst.']}}, {'name': 'Oguz Ergin', 'affiliation': 'Intel Barcelona Research Center', 'bio': {'p': ['Oguz Ergin is an assistant professor in the Department of Computer Engineering of TOBB University of Economics and Tech-nology, Ankara, Turkey. He was a senior research scientist at Intel Barcelona Research Center before he joined his current university. His research interests include computer architecture and VLSI design. He received a PhD in computer science from the State University of New York at Binghamton.']}}, {'name': 'Antonio Gonzá,lez', 'affiliation': 'Intel Barcelona Research Center and Universitat Politècnica de Catalunya', 'bio': {'p': ['Antonio Gonzalez is a professor in the Computer Architecture Department at the Universitat Politècnica de Catalunya. He is the founding director of the Intel Barcelona Research Center, which focuses on new microarchitecture paradigms and code-generation techniques for future microprocessors. He received a PhD in computer architecture from the Universitat Politecnica de Catalunya.']}}, {'name': 'James W. Tschanz', 'affiliation': 'Circuit Research Labs, Intel Corporation', 'bio': {'p': ["James W. Tschanz is a researcher at Intel's Circuit Research Lab. His research interests include low-power and variation-tolerant circuits. He received an MS in electrical engineering from the University of Illinois at Urbana-Champaign. Direct questions and comments about this article to Jaume Abella, Intel Barcelona Research Center, Intel Labs-UPC, Jordi Girona, 29, 3rd floor, 08034 Barcelona, Spain, jaume.abella@intel.com."]}} %*Refueling: Preventing Wire Degradation due to Electromigration %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4731173 %f/micro/zjofng3mtm5rrqj7pd92cukbwi01aciv.pdf %mad8c9032e6fc77300b488620cce970db %cmicro %@[{'name': 'Philip G. Emma', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ['The biography of Philip G. Emma appears on p. 6 of this issue.']}}, {'name': 'William R. Reohr', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ['William R. Reohr is a research staff member at the IBM T.J. Watson Research Center. His research interests include the design of high-performance processors (primarily their cache memories) and embedded DRAM for silicon-on-insulator technology. Reohr has an MS in electrical engineering from Columbia University.']}}, {'name': 'Mesut Meterelliyoz', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ['Mesut Meterelliyoz is pursuing a PhD in electrical engineering at Purdue University. He is also an intern at the IBM T.J. Watson Research Center, where he focuses on embedded-DRAM technology. His research interests include process-variation-aware design, high-density and high-speed memory design, and burn-in test. Meterelliyoz has an MS in electrical engineering from Purdue University.', 'Direct questions and comments about this article to Philip G. Emma, 25–242B, IBM T.J. Watson Research Center, PO Box 218, Yorktown Heights, NY 10598, pemma@us.ibm.com.']}} %*Rethinking Refresh: Increasing Availability and Reducing Power in DRAM for Cache Applications %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4731174 %f/micro/kyxecqb58vmqbl703dncmoehgr4pzyuw.pdf %m31e34e7606c042f3ca3151882ca3fca6 %cmicro %@[{'name': 'Richard Stern', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/4731164/4731175/4731175-photo-1-small.gif', 'p': []}} %*An Update on "Exhaustion"—Supreme Court Decides Quanta Case %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4731175 %f/micro/uc74nd9yiwhmgp8db2taxmaffkzkorhj.pdf %mb75d55470b6646b2bac7d9d0266c1af9 %cmicro %@[{'name': 'Richard Stern'} %*Micro News %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4731176 %f/micro/kjyh4lvu0uplgtnf6riwdoxdznkoctqp.pdf %m349fdf5232ceedc915e8af4c9d4a78b6 %cmicro %@[{'name': 'David H. Albonesi', 'affiliation': 'Cornell University'} %*Standing on Solid Ground %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4205117 %f/micro/fyzcpgorx2mrk5vliijfbaadwwhxmseu.pdf %ma082e8718b5ea8ca27a2ba0c807bec83 %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'Kellogg Graduate School of Management', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/4205111/4205118/4205118-photo-1-small.gif', 'p': []}} %*The High Cost of a Cheap Lesson %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4205118 %f/micro/dchbcmszveg1k2e3twsyflp0odokrx8a.pdf %m93587e637270699e85c71505baf96900 %cmicro %@[{'name': 'Ronny Ronen', 'affiliation': 'Intel Corporation, Haifa', 'bio': {'p': ["Ronny Ronen is an Intel Senior Principal Engineer and director of Intel's Microprocessor Research Lab in Haifa, Israel, focusing on microarchitecture research. Ronen has been with Intel for more than 25 years. He was heavily involved in the definition stages of the Intel Pentium M processor and its successors, earlier he led compiler and performance simulation activities in the Software Department of Intel Israel. Ronen received his MSc degree from the Technion, Israel Institute of Technology. He is a senior member of the IEEE."]}}, {'name': 'Antonio Gonzalez', 'affiliation': 'Intel Corporation and UPC, Barcelona', 'bio': {'p': ['Antonio González is the founding director of the Intel-UPC Barcelona Research Center and a professor of computer architecture at Universitat Politècnica de Catalunya. His research focuses on computer architecture, with particular emphasis on processor microarchitecture and code generation techniques. González is an associate editor of IEEE Transactions on Computers, IEEE Transactions on Parallel and Distributed Systems, ACM Transactions on Architecture and Code Optimization, and Journal of Embedded Computing.', 'Direct questions and comments about this issue to Ronny Ronen, Intel Israel, P.O. Box 1659, Haifa, 31015, Israel, ronny. ronen@intel.com, or to Antonio González, Intel Labs—UPC, c/ Jordi Girona 29, Edifici Nexuss II, 3a. planta, 08034 Barce-lona, Spain, antonio.gonzalez@intel.com.', 'For more information on this or any other computing topic, please visit our Digital Library at http://computer.org/publications/dlib.']}} %*Guest Editors' Introduction: Micro's Top Picks from the Microarchitecture Conferences %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4205119 %f/micro/ho8qsably1ycgtxtfczq46a57uw2rjk3.pdf %ma0976ab8b6f4be7b91d5a07d7c23d8a2 %cmicro %@[{'name': 'Smruti Sarangi', 'affiliation': 'University of Illinois, Urbana-Champaign', 'bio': {'p': ['Smruti Sarangi is a PhD student in computer science at the University of Illinois, Urbana-Champaign. His research interests include processor reliability, schemes to mitigate the effects of process variation, and power management schemes. Sarangi has a BTech in computer science and engineering from the Indian Institute of Technology, Kharagpur, and an MS in computer science from the University of Illinois. He is a student member of the IEEE.']}}, {'name': 'Satish Narayanasamy', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Satish Narayanasamy is a PhD candidate in the Computer Science Department at the University of California, San Diego. His research interests include computer architecture support for system software and programming languages, programmer productivity tools, and fault tolerance. Narayanasamy has an MS from the University of California, San Diego, and a BE from Anna University, College of Engineering, Guindy, Chennai, India, both in computer science. He is a member of the ACM and the IEEE.']}}, {'name': 'Bruce Carneal', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Bruce Carneal is a PhD student in the Computer Science Department at the University of California, San Diego. His research interests include computer architecture and machine learning. He received a BS in computer science from Brigham Young University.']}}, {'name': 'Abhishek Tiwari', 'affiliation': 'University of Illinois, Urbana-Champaign', 'bio': {'p': ['Abhishek Tiwari is a PhD student in computer science at the University of Illinois, Urbana-Champaign. His research focuses on processor reliability and power management for deep submicron technologies. Tiwari has a BTech in computer science and engineering from the Indian Institute of Technology, Kanpur, and an MS in computer science from the University of Illinois. He is a student member of the IEEE.']}}, {'name': 'Brad Calder', 'affiliation': 'University of California, San Diego, and Microsoft', 'bio': {'p': ['Brad Calder is a professor of computer science and engineering at the University of California, San Diego. He has cofounded three startups (TracePoint, Entropia, and BitRaker), and is now an architect at Microsoft. He is co-editor-in-chief of ACM Transactions on Computer Architecture and Code Optimization. His research interests span distributed computing, architecture, compilers, and systems. Calder received his PhD in computer science from the University of Colorado, Boulder. He is an IEEE senior member and a member of the ACM.']}}, {'name': 'Josep Torrellas', 'affiliation': 'University of Illinois, Urbana-Champaign', 'bio': {'p': ['Josep Torrellas is a professor of computer science and Willett Faculty Scholar at the University of Illinois, Urbana-Champaign. He is also chair of the IEEE Technical Committee on Computer Architecture (TCCA). His research interests include multiprocessor computer architecture, thread-level speculation, low-power design, and hardware and software reliability. Torrellas has a PhD in electrical engineering from Stanford University. He is an IEEE Fellow and a member of the ACM.', 'Direct questions and comments about this article to Brad Calder, University of California, San Diego, Dept. of Computer Science and Engineering, 9500 Gilman Dr., La Jolla, CA 92093–0404 (calder@cs.ucsd.edu), and to Josep Torrellas, Dept. of Computer Science, University of Illinois, 201 North Goodwin Ave., Urbana, IL, 61801 (torrellas@cs.uiuc.edu).']}} %*Patching Processor Design Errors with Programmable Hardware %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4205120 %f/micro/phh0anezoixndvbsjliky836qgucdlws.pdf %mcd937cf6ae5b2d423734c0d52467931d %cmicro %@[{'name': 'Shan Lu', 'affiliation': 'University of Illinois at Urbana-Champaign', 'bio': {'p': ['Shan Lu is a PhD candidate in the Department of Computer Science of the University of Illinois at Urbana-Champaign. Her research interests include system and architecture support for software reliability. Lu has a BS in computer science from the University of Science and Technology of China. She is a student member of the ACM.']}}, {'name': 'Joseph Tucek', 'affiliation': 'University of Illinois at Urbana-Champaign', 'bio': {'p': ['Joseph Tucek is a PhD candidate in the Department of Computer Science of the University of Illinois at Urbana-Champaign. His research interests include systems and architecture support for reliability and debugging. Tucek has BS degrees in computer science and computer engineering from Washington University in St. Louis. He is a student member of both the ACM and Usenix.']}}, {'name': 'Feng Qin', 'affiliation': 'University of Illinois at Urbana-Champaign', 'bio': {'p': ['Feng Qin is an assistant professor at Ohio State University. His research interests include operating systems, software dependability, security, and computer architecture. Qin has a PhD in computer science from the University of Illinois at Urbana-Champaign. He is a member of the ACM.']}}, {'name': 'Yuanyuan Zhou', 'affiliation': 'University of Illinois at Urbana-Champaign', 'bio': {'p': ['Yuanyuan Zhou is an associate professor in the Department of Computer Science of the University of Illinois at Urbana-Champaign. Her research interests include software reliability, operating systems, computer architecture, and storage systems. Zhou obtained her PhD and MA in computer science from Princeton University. She is a member of the ACM and the IEEE Computer Society.', 'Direct questions and comments about this article to Shan Lu, 201 N. Goodwin Ave., Thomas M. Siebel Center for Computer Science, Department of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL 61801–2302, shanlu@uiuc.edu.', 'For further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/publications/dlib.']}} %*AVIO: Detecting Atomicity Violations via Access-Interleaving Invariants %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4205121 %f/micro/iuypczboqd379f4us82lgjbryfhkqv0e.pdf %m3f2a06ed0bafc789cfe6d7d4be7ebe19 %cmicro %@[{'name': 'George A. Reis', 'affiliation': 'Princeton University', 'bio': {'p': ['George A. Reis is a fourth-year PhD student in the Department of Electrical Engineering at Princeton University. His research interests include computer reliability and configurable techniques to mitigate processor faults using combinations of software and hardware implementations. Reis has a BSE and an MA in electrical engineering from Princeton University. He is a student member of the ACM.']}}, {'name': 'Jonathan Chang', 'affiliation': 'Princeton University', 'bio': {'p': ['Jonathan Chang is a fourth-year PhD student in the Department of Electrical Engineering at Princeton University. His research interests include natural language processing and machine learning, as well as computer architecture and fault tolerance. Chang has a BS in electrical and computer engineering from the California Institute of Technology and an MA in electrical engineering from Princeton University. He is a student member of the ACM.']}}, {'name': 'David I. August', 'affiliation': 'Princeton University', 'bio': {'p': ['David I. August is an associate professor in the Department of Computer Science at Princeton University, where he directs the Liberty Research Group. The Liberty Research Group is studying next-generation architectures, code analyses, and code transformations to enhance performance, reliability, and security. August has a PhD in electrical engineering from the University of Illinois at Urbana-Champaign. He is a member of the IEEE and ACM.', 'Direct questions about this article to David August, Department of Computer Science, Princeton University, 35 Olden St., Princeton, NJ 08540, august@princeton.edu.', 'For more information on this or any other computing topic, please visit our Digital Library at http://computer.org/publications/dlib.']}} %*Automatic Instruction-Level Software-Only Recovery %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4205122 %f/micro/o9pp2y0bal7drqt1qkghcoxcizlfnjwr.pdf %m3c50d801bc418ab1ac1a823935c4b7f4 %cmicro %@[{'name': 'Min Xu', 'affiliation': 'VMware', 'bio': {'p': ['Min Xu is a member of the technical staff at VMware. His interests include hardware and software techniques in deterministic replay. Xu has a PhD in electrical engineering from the University of Wisconsin-Madison. He is a member of the ACM and IEEE.']}}, {'name': 'Rastislav Bodik', 'affiliation': 'University of California, Berkeley', 'bio': {'p': ['Rastislav Bodík is an assistant professor in the Computer Sciences Division at the University of California, Berkeley. His research interests include static and dynamic program analysis, software tools, and compilation. He has a PhD in computer science from the University of Pittsburgh.']}}, {'name': 'Mark D. Hill', 'affiliation': 'University of Wisconsin at Madison', 'bio': {'p': ['Mark D. Hill is a professor in both the Computer Sciences and Electrical and Computer Engineering Departments at the University of Wisconsin—Madison. His research interests include parallel computer system design, memory system design, and computer simulation. He has a PhD in computer science from the University of California, Berkeley, and is a fellow of the IEEE and ACM.', 'Direct questions and comments about this article to Mark D. Hill, Computer Sciences Dept., University of Wisconsin-Madison, 1210 West Dayton St., Madison, WI 53706–1685, markhill@cs.wisc.edu.', 'For more information on this or any other computing topic, please visit our Digital Library at http://computer.org/publications/dlib.']}} %*A Hardware Memory Race Recorder for Deterministic Replay %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4205123 %f/micro/1lakuwxz4fifjk3ynju5dvqeqmxtmyc7.pdf %m78d1b1aea9fd58bab1a1911a22f6b51c %cmicro %@[{'name': 'Austen McDonald', 'affiliation': 'Stanford University', 'bio': {'p': ['Austen McDonald is a PhD candidate in computer science at Stanford University. His research interests are transactional memory and parallel architectures. McDonald has a BS in computer science from the Georgia Institute of Technology.']}}, {'name': 'Brian D. Carlstrom', 'affiliation': 'Stanford University', 'bio': {'p': ['Brian D. Carlstrom is a PhD candidate in computer science at Stanford University. His research interests include transactional programming models as well as other aspects of modern programming language design and implementation. Carlstrom has an SB and MEng in electrical engineering and computer science from the Massachusetts Institute of Technology. He is a member of the ACM.']}}, {'name': 'JaeWoong Chung', 'affiliation': 'Stanford University', 'bio': {'p': ['JaeWoong Chung is a PhD candidate in electrical engineering at Stanford University. His research interests include transactional memory virtualization and operating system support for transactional programming. Chung has a BSEE and an MSEE from Korean Advanced Institute of Science and Technology.']}}, {'name': 'Chi Cao Minh', 'affiliation': 'Stanford University', 'bio': {'p': ['Chi Cao Minh is a PhD candidate in electrical engineering at Stanford University. His research interests include computer architecture and parallel programming environments. Cao Minh received an MSEE from Stanford University and a BSEE from the University of Texas at Austin.']}}, {'name': 'Hassan Chafi', 'affiliation': 'Stanford University', 'bio': {'p': ['Hassan Chafi is a PhD candidate in electrical engineering at Stanford University. His research interests include transactional memory and parallel architectures. He has a BSEE from the University of Maryland, College Park.']}}, {'name': 'Christos Kozyrakis', 'affiliation': 'Stanford University', 'bio': {'p': ['Christos Kozyrakis is an assistant professor of electrical engineering and computer science at Stanford. His research focuses on architectural support for parallel programming, security, and power management. Kozyrakis has a PhD in computer science from the University of California, Berkeley.']}}, {'name': 'Kunle Olukotun', 'affiliation': 'Stanford University', 'bio': {'p': ['Kunle Olukotun is an associate professor of electrical engineering and computer science at Stanford University. His research interests include computer architecture, parallel programming environments, and formal hardware verification. Olukotun has a PhD in computer science and engineering from the University of Michigan. He is a fellow of the ACM.', 'Direct questions or comments to Austen McDonald, Stanford University, Computer System Laboratory, 353 Serra Mall, Stanford, CA 94305–9040, austenmc@stanford.edu.', 'For more information on this or any other computing topic, please visit our Digital Library at http://computer.org/publications/dlib.']}} %*Transactional Memory: The Hardware-Software Interface %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4205125 %f/micro/zt90tor8ryn64eyokex1jda2jmfxbuv3.pdf %m9079ff33ac5ef82105b87a68baf6b0ff %cmicro %@[{'name': 'Shashidhar Mysore', 'affiliation': 'University of California, Santa Barbara', 'bio': {'p': ['Shashidhar Mysore is a PhD candidate in the Department of Computer Science at University of California, Santa Barbara (UCSB). He previously worked as a research assistant at the Indian Institute of Science, Bangalore. His research interests are in computer architecture, specifically in the design of algorithms and hardware accelerators to aid runtime program and system analysis. His work on Range Adaptive Profiling received the Best Paper Award at the Code Generation and Optimization Conference in 2006. Mysore received his BTech from the BMS College of Engineering, Bangalore. He is a student member of the IEEE.']}}, {'name': 'Banit Agrawal', 'affiliation': 'University of California, Santa Barbara', 'bio': {'p': ["Banit Agrawal is a PhD student in the Department of Computer Science at UCSB. His research interests include network and security processors, three-dimensional ICs, memory design and modeling, and power-aware architectures. He has a master's degree in computer science from University of California, Riverside, and a BTech(H) from the Indian Institute of Technology, Kha-ragpur. He is a member of the IEEE."]}}, {'name': 'Navin Srivastava', 'affiliation': 'University of California, Santa Barbara', 'bio': {'p': ['Navin Srivastava is a PhD candidate at UCSB studying nanometer-scale VLSI interconnect issues. Previously, he spent three years working in the electronic design automation industry. Srivastava received a BTech with honors from the Indian Institute of Technology, Kharagpur, India, and an MS in electrical and computer engineering from University of California, Santa Barbara. He was a corecipient of the Outstanding Graduate Student Paper Award at the VLSI Multilevel Interconnect Conference, 2005. He is a student member of the IEEE.']}}, {'name': 'Sheng-Chih Lin', 'affiliation': 'University of California, Santa Barbara', 'bio': {'p': ['Sheng-Chih Lin is a PhD candidate in the Department of Electrical and Computer Engineering at UCSB. His research interests include electrothermal modeling and anal-ysis, variation-aware circuit design optimi-zation, and thermal management for na-noscale CMOS and high-performance ICs. He received a BS in electrical engineering from National Taiwan University, Taiwan, and is a student member of the IEEE.']}}, {'name': 'Kaustav Banerjee', 'affiliation': 'University of California, Santa Barbara', 'bio': {'p': ["Kaustav Banerjee is an associate professor of electrical and computer engineering at UCSB. Before joining the UCSB faculty in 2002, he was a research associate at Stanford University's Center for Integrated Systems. His present research focuses on nanometer-scale issues in high-performance and low-power VLSI, and on circuits and systems issues in emerging nanoelectronics. Banerjee has a PhD in electrical engineering and computer sciences from University of California, Berkeley. He is a senior member of the IEEE."]}}, {'name': 'Timothy Sherwood', 'affiliation': 'University of California, Santa Barbara', 'bio': {'p': ['Timothy Sherwood is an assistant professor in the Department of Computer Science at UCSB. His research interests are in computer architecture, specifically in the development of novel high-throughput methods by which systems can be monitored and analyzed. For example, his program phase analysis tool, SimPoint, is used by industry partners and many academics to guide the design of their largest microprocessors. Sherwood received his BS from University of California, Davis, and his MS and PhD from University of California, San Diego. He is a member of the IEEE.', 'Direct questions and comments about this article to Shashidhar Mysore, Univ. of California, Santa Barbara, Computer Science Dept., Engineering I, Room 2104, Santa Barbara, CA 93106–5110, shashimc@ cs.ucsb.edu.', 'For further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/publications/dlib.']}} %*3D Integration for Introspection %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4205126 %f/micro/fvc05mpirazmgodh4lwhtcal38knjnje.pdf %m2343e53a8cd8f0b0b9c9f12de681dee5 %cmicro %@[{'name': 'Stijn Eyerman', 'affiliation': 'Ghent University', 'bio': {'p': ['Stijn Eyerman is a PhD student in the Electronics and Information Systems Department at Ghent University, Belgium. His research interests include computer architecture in general and performance analysis and modeling in particular. Eyer- man has an MS in computer science and engineering from Ghent University.']}}, {'name': 'Lieven Eeckhout', 'affiliation': 'Ghent University', 'bio': {'p': ['Lieven Eeckhout is an assistant professor in the Electronics and Information Systems Department at Ghent University, Belgium. His research interests include computer architecture, performance analysis and modeling, and workload characterization. Eeckhout has a PhD in computer science and engineering from Ghent University. He is a member of the IEEE.']}}, {'name': 'Tejas Karkhanis', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ['Tejas Karkhanis is a microprocessor design engineer in the Boston Design Center of Advanced Micro Devices. His research interests include high-performance and low-power microprocessor design. Karkhanis has BS, MS, and PhD degrees in electrical engineering from the University of Wisconsin-Madison.']}}, {'name': 'James E. Smith', 'affiliation': 'University of Wisconsin-Madison', 'bio': {'p': ['James E. Smith is a professor in the Department of Electrical and Computer Engineering at the University of Wisconsin-Madison. His research interests include high-performance and power-efficient processor implementations, processor performance modeling, and virtual machines. Smith has a PhD in computer science from the University of Illinois. He is a member of the IEEE and the ACM.', 'Direct questions and comments about this article to Lieven Eeckhout, ELIS-Ghent University, Sint-Pietersnieuwstraat 41, B-9000 Gent, Belgium, leeckhou@elis. UGent.be.', 'For further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/publications/dlib.']}} %*A Top-Down Approach to Architecting CPI Component Performance Counters %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4205127 %f/micro/wvwuq1pkcrlbvoahi06dnca5pdkoglxj.pdf %m70c41fb02ef61323eaa03b1d998ffc89 %cmicro %@[{'name': 'Hyesoon Kim', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ['Hyesoon Kim is a PhD candidate in the Electrical and Computer Engineering Department of the University of Texas at Austin. Her research interests include highperformance energy-efficient computer architectures and programmer-compiler-architecture interaction. Kim has a BS in mechanical engineering from Korea Advanced Institute of Science and Technology, an MS in mechanical engineering from Seoul National University, and an MS in computer engineering from the University of Texas at Austin. She is a student member of the IEEE and the ACM.']}}, {'name': 'Jose A. Joao', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ['Jose A. Joao is a PhD student in the Electrical and Computer Engineering Department of the University of Texas at Austin. His research interests include highperformance microarchitectures and compiler-architecture interaction. Joao has an MS in computer engineering from the University of Texas at Austin and a BS in electronics engineering from Universidad Nacional de la Patagonia San Juan Bosco, Argentina, where he is an assistant professor (on leave). He was a recipient of the Microelectronics and Computer Development Fellowship from the University of Texas at Austin during 2003–2005. He is a student member of the IEEE and the ACM.']}}, {'name': 'Onur Mutlu', 'affiliation': 'Microsoft Research', 'bio': {'p': ['Onur Mutlu is a researcher at Microsoft Research. His research interests include computer architecture, especially the interactions between software and microarchitecture. Mutlu has BS degrees in computer engineering and psychology from the University of Michigan, Ann Arbor, and PhD and MS degrees in electrical and computer engineering from the University of Texas at Austin. He was a recipient of the Intel PhD fellowship in 2004 and the University of Texas George H. Mitchell Award for Excellence in Graduate Research in 2005. He is a member of the IEEE and the ACM.']}}, {'name': 'Yale N. Patt', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ['Yale N. Patt is the Ernest Cockrell, Jr., Centennial Chair in Engineering at the University of Texas at Austin. His research interests include harnessing the expected benefits of future process technology to create more effective microarchitectures for future microprocessors. He is coauthor of Introduction to Computing Systems: From Bits and Gates to C and Beyond (McGraw-Hill, 2nd edition, 2004). His honors include the 1996 IEEE/ACM Eckert-Mauchly Award and the 2000 ACM Karl V. Karlstrom Award. He is a fellow of both the IEEE and the ACM.', 'Direct questions and comments about this article to Hyesoon Kim, Dept. of Electrical and Computer Engineering, University of Texas, 1 University Station C0803, Austin, TX 78712, hyesoon@ece. utexas.edu.', 'For further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/publications/dlib.']}} %*Diverge-Merge Processor: Generalized and Energy-Efficient Dynamic Predication %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4205128 %f/micro/ig52e8ic91omszbpvtnl3wconkspa0qa.pdf %mb04ac3d9270a0a34a17235183199682e %cmicro %@[{'name': 'Tingting Sha', 'affiliation': 'University of Pennsylvania', 'bio': {'p': ["Tingting Sha is a PhD candidate in the Department of Computer and Information Science at the University of Pennsylvania. Her research interests include complexity-effective microarchitectures. Sha has a master's degree in computer science from the University of Pennsylvania. She is a student member of the ACM."]}}, {'name': 'Milo M.K. Martin', 'affiliation': 'University of Pennsylvania', 'bio': {'p': ['Milo M.K. Martin is an assistant professor in the Department of Computer and Information Science at the University of Pennsylvania. His research interests include scalable microarchitectures, multiprocessor computer architectures, memory systems, and verification. Martin has a PhD in computer science from the University of Wisconsin-Madison. He is a member of the ACM and the IEEE.']}}, {'name': 'Amir Roth', 'affiliation': 'University of Pennsylvania', 'bio': {'p': ['Amir Roth is an assistant professor in the Department of Computer and Information Science at the University of Pennsylvania. His research interests include computer architecture and microarchitecture. Roth has a PhD in computer science from the University of Wisconsin-Madison. He is a member of the ACM and the IEEE.', 'Direct questions and comments about this article to Tingting Sha, Dept. of Computer and Information Science, University of Pennsylvania, 3330 Walnut St., Philadelphia, PA 19104, shatingt@cis.upenn.edu.', 'For more information on this or any other computing topic, please visit our Digital Library at http://computer.org/publications/dlib.']}} %*NoSQ: Store-Load Communication without a Store Queue %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4205130 %f/micro/a6rzc0wywmhjg4y5n71bd2oixnvtidfa.pdf %m550c38b967824b8bb0f23c540a772f2f %cmicro %@[{'name': 'Yuan Lin', 'affiliation': 'University of Michigan at Ann Arbor', 'bio': {'p': ['Yuan Lin is a PhD candidate in electrical engineering and computer science at the University of Michigan at Ann Arbor. His research interests include architecture and compiler design for embedded and signal processing applications. Lin has a BS in electrical engineering from Cornell University.']}}, {'name': 'Hyunseok Lee', 'affiliation': 'University of Michigan at Ann Arbor', 'bio': {'p': ['Hyunseok Lee is a PhD candidate in electrical engineering and computer science at the University of Michigan at Ann Arbor. His research interests include digital hardware systems for baseband signal processing and L2/L3 protocols for wireless commu-nication.']}}, {'name': 'Mark Woh', 'affiliation': 'University of Michigan at Ann Arbor', 'bio': {'p': ['Mark Woh is a PhD candidate in electrical engineering and computer science at the University of Michigan Ann Arbor. His research interests include low-power micro-architecture and wireless communication. Woh has a BS in electrical engineering and computer science from the University of Michigan at Ann Arbor.']}}, {'name': 'Yoav Harel', 'affiliation': 'Intel', 'bio': {'p': ['Yoav Harel is a component design engineer in the Graphics Department at Intel. His research interests include DSP algorithms and low-power architecture. Harel has a MS in electrical engineering and computer science from the University of Michigan at Ann Arbor.']}}, {'name': 'Scott Mahlke', 'affiliation': 'University of Michigan at Ann Arbor', 'bio': {'p': ['Scott Mahlke is an associate professor in the Electrical Engineering and Computer Science Department at the University of Michigan, where he leads the Compilers Creating Custom Processors group. His research interests include application-specific processors, high-level synthesis, compiler optimization, and computer architecture. Mahlke has a PhD from the University of Illinois, Urbana-Champaign. He is a member of the IEEE and ACM.']}}, {'name': 'Trevor Mudge', 'affiliation': 'University of Michigan at Ann Arbor', 'bio': {'p': ['Trevor Mudge is the first Bredt Family Professor of Electrical Engineering and Computer Science at the University of Michigan at Ann Arbor. He also operates Idiot Savants, a chip design consultancy. His research interests include computer architecture, CAD, and compilers. Mudge has a PhD in computer science from the University of Illinois, Urbana-Champaign. He is a member of the ACM, Institution of Engineering and Technology, and British Computer Society and a fellow of the IEEE.']}}, {'name': 'Chaitali Chakrabarti', 'affiliation': 'Arizona State University', 'bio': {'p': ['Chaitali Chakrabarti is a professor of electrical engineering at Arizona State University. Her research interests are in VLSI architectures and algorithms for signal processing and communications and low- power system design. She serves as the Technical Committee Chair of Design and Implementation of Signal Processing Systems for the IEEE Signal Processing Society. Chakrabarti received her PhD from the University of Maryland, College Park.']}}, {'name': 'Krisztian Flautner', 'affiliation': 'ARM Ltd.', 'bio': {'p': ['Krisztian Flautner is director of research at ARM Limited. His research interests include high-performance, low-energy processing platforms that support advanced software environments. Flautner has a PhD in electrical engineering and computer science from the University of Michigan at Ann Arbor. He is a member is the ACM and IEEE.', 'Direct questions and comments about this article to Trevor Mudge, Univ. of Michigan at Ann Arbor, 2260 Hayward, Ann Arbor, MI 48109–2121, tnm@eecs. umich.edu.', 'For more information on this or any other computing topic, please visit our Digital Library at http://computer.org/publications/dlib.']}} %*SODA: A High-Performance DSP Architecture for Software-Defined Radio %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4205131 %f/micro/orgc4uuhdlcy7imkfflwyg61bm8ezsjr.pdf %ma7b62460fc8011d3f54e5db10973f1d9 %cmicro %@[{'name': 'Richard Stern', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/4205111/4205132/4205132-photo-1-small.gif', 'p': ['']}} %*West Coast Federal Appeals Court Upholds Chip Protection Act Violation Finding %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4205132 %f/micro/7glpwxc13f8gufbpmudndc0iyizskvjl.pdf %m1c3c4502bb2138ffe3fbf84729c0bff7 %cmicro %@[{'name': 'Richard Mateosian'} %*Economics %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4205134 %f/micro/6zahssyxw8btfnjcrtdfe17v2mqgalkg.pdf %m30e1acfae8ecd41c8c08a8293f8add65 %cmicro %@[{'name': 'Philip Emma', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/4205111/4205136/4205136-photo-1-small.gif', 'p': ['']}} %*Reinventing Entrepreneurial Inventing for the 21st Century %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4205136 %f/micro/xyhctps62qjlwe485wokcyvmr3dfx1uv.pdf %mbfb21ce9408d6aa7d82468fb1e114157 %cmicro %@[{'name': 'David H. Albonesi', 'affiliation': 'Cornell University'} %*Editor in Chief's Message: Truly "hot" chips--Do we still care? %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4287389 %f/micro/qxjsumutlalwf7rn2vy4jwfoeyb1izpc.pdf %mebd4f9397bb764bfa0fcc34d0350593c %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'Kellogg Graduate School of Management', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/4287384/4287390/4287390-photo-1-small.gif', 'p': ['Shane Greenstein greenstein@kellogg.northwestern.edu']}} %*Wagging Wikipedia's long tail %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4287390 %f/micro/imzoecwqc4wd6h07f3esfxbhkkpunjg1.pdf %md900ffd29f7c360ffc69716d5588611d %cmicro %@[{'name': 'John Kubiatowicz', 'affiliation': 'University of California, Berkeley', 'bio': {'p': ['John Kubiatowicz is an associate professor of electrical engineering and computer science at the University of California, Berkeley. His specialties include computer architecture, operating systems, and networking. His research interests include speculative approaches for computer design, such as quantum, biological, and autonomic computing, as well as issues in Internet-scale systems design, namely security, privacy, and denial-of-service resilience. He currently leads the OceanStore research effort (http://oceanstore.org), which is exploring a utility storage architecture that targets millions of servers and billions of users. He is also exploring architectures for quantum transport in quantum computers. Kubiatowicz has a PhD in electrical engineering and computer science from the Massachusetts Institute of Technology, where he was one of the principal designers of the Alewife multiprocessor. He also holds dual BS degrees in electrical engineering and physics, as well as MS degrees in electrical engineering and computer science, from MIT.']}}, {'name': 'Howard Sachs', 'affiliation': 'Telairity', 'bio': {'p': ['Howard Sachs is president and CEO of Telairity. Sachs has held a long list of strategic positions with industry-leading companies dealing in computer hardware-software design, microprocessor design, and ASIC design. He held management positions with Fujitsu Microelectronics, Intergraph Corporation, Fairchild Semiconductor Corporation, and Cray Laboratories, among others. He has dedicated many years to solving SoC problems as president of the Virtual Socket Industry Alliance and with Fujitsu Microelectronics. He holds many major industry patents that have contributed significantly to cache memory and VLIW design today. Sachs has a BSE from California State University, Los Angeles, and an MSEE from the UniversitY of Southern California.']}} %*Guest Editors' Introduction: Hot Chips 18 %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4287391 %f/micro/nsxaw3b2zldib1qam0nzyetf8cgfvgrh.pdf %m783c6e26a899e332ff8410c96c27c3d2 %cmicro %@[{'name': 'Pat Conway', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ['Pat Conway is a principal member of technical staff at AMD where he is responsible for developing scalable, highperformance server architectures. His work experience includes the design and development of server hardware, cache coherence and message passing protocols. He has a M. Eng. Sc from University College Cork, Ireland, and an MBA from Golden Gate University. He is a member of the IEEE.']}}, {'name': 'Bill Hughes', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ['Bill Hughes is a senior fellow at AMD. He was one of the initial Opteron architects working on HyperTransport and the on-chip memory controller and also worked on the load-store and data cache units on Athlon. He currently leads the Northbridge and HyperTransport microarchitecture and RTL team. He has a BS from Manchester University, England, and a PhD from Leeds University, England.']}} %*The AMD Opteron Northbridge Architecture %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4287392 %f/micro/cuhsvoj2fzqdjmgtkna6spx0p1na8ilg.pdf %m40f35b7ee0b94e3d96e9d978b994a719 %cmicro %@[{'name': 'Sivakumar Radhakrishnan', 'affiliation': 'Intel', 'bio': {'p': ['Sivakumar Radhakrishnan is a staff architect in the Intel Digital Enterprise Group, Advanced Chipset Division, in Hillsboro, Oregon. His research interests include chipset technologies, memory and parallel architectures, I/O communication and networking protocols, and performance modeling and analysis. Radhakrishnan has a BEng in computer science and engineering from Sri Venkateswara College of Engineering (affiliated with the University of Madras, India) and MS and PhD degrees in electrical engineering from the University of Victoria, Canada.']}}, {'name': 'Sundaram Chinthamani', 'affiliation': 'Intel', 'bio': {'p': ['Sundaram Chinthamani is a senior performance architect in the Digital Enterprise Group at Intel, Hillsboro, Oregon. His research interests include chipset microarchitecture, mathematical modeling, simulation modeling, and performance validation. Sundaram has BEng and MS degrees in computer science and engineering from the Indian Institute of Science, Bangalore, and a PhD in computer science from the University of Saskatchewan, Canada.']}}, {'name': 'Kai Cheng', 'affiliation': 'Intel', 'bio': {'p': ['Kai Cheng is a senior staff engineer in the Xeon UP/DP Processor Architecture team of the Digital Enterprise Group, Microprocessor Architecture and Performance Division of Intel in Hillsboro, Oregon. His research interests include microcomputers and chipset design. Cheng graduated with BSEE from the College of Engineering at Rutgers, the State University of New Jersey. He also completed many years of graduate study at Syracuse University.']}} %*The Blackford Northbridge Chipset for the Intel 5000 %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4287393 %f/micro/vkhguniy5gon4v9msjoxr7descplqfai.pdf %m99a65f0f03265afb32e13fa83a218124 %cmicro %@[{'name': 'Bevan Baas', 'affiliation': 'University of California, Davis', 'bio': {'p': ['Bevan Baas is an assistant professor in the Department of Electrical and Computer Engineering at the University of California, Davis. He currently leads projects in architecture, hardware, software tools, and applications for VLSI computation with an emphasis on DSP workloads. Baas has a PhD and MS in electrical engineering from Stanford University and a BS in electronic engineering from California Polytechnic State University, San Luis Obispo.']}}, {'name': 'Zhiyi Yu', 'affiliation': 'University of California, Davis', 'bio': {'p': ['Zhiyi Yu is a PhD candidate in electrical and computer engineering at the University of California, Davis. His research interests include high-performance and energy-efficient digital VLSI design with an emphasis on many-core GALS clocking and efficient processor interconnects. Yu has an MS and BS in electrical engineering from Fudan University.']}}, {'name': 'Michael Meeuwsen', 'affiliation': 'University of California, Davis', 'bio': {'p': ['Michael Meeuwsen is a hardware engineer with Intel Digital Enterprise Group. His research interests include digital circuit design and 802.11a/g algorithm mapping. Meeuwsen has an MS in electrical and computer engineering from the University of California, Davis, and BS degrees in electrical engineering and computer engineering from Oregon State University.']}}, {'name': 'Omar Sattari', 'affiliation': 'University of California, Davis', 'bio': {'p': ['Omar Sattari is a software engineer at CornerTurn. His research interests include FFT and DSP algorithms and digital hardware design. Sattari has an MS and BS in electrical and computer engineering, both from the University of California, Davis.']}}, {'name': 'Ryan Apperson', 'affiliation': 'University of California, Davis', 'bio': {'p': ['Ryan Apperson is an IC design engineer at Boston Scientific CRM Division. His research interests include multiclock domain systems and SRAM design. Apperson has an MS in electrical and computer engineering from the University of California, Davis, and a BS in electrical engineering from the University of Washington.']}}, {'name': 'Eric Work', 'affiliation': 'University of California, Davis', 'bio': {'p': ['Eric Work is an MS student in electrical and computer engineering at the University of California, Davis. His research interests include the mapping of arbitrary task graphs to processor networks and software tool flow. Work has a BS from the University of Washington.']}}, {'name': 'Jeremy Webb', 'affiliation': 'University of California, Davis', 'bio': {'p': ['Jeremy Webb is an MS student in electrical and computer engineering at the University of California, Davis, and a hardware engineer at Agilent. His research interests include high-speed board design and system interfacing. Webb has a BS from the University of California, Davis.']}}, {'name': 'Michael Lai', 'affiliation': 'University of California, Davis', 'bio': {'p': ['Michael Lai is a design engineer at Altera. His research interests include the design of high-speed arithmetic units and control. Lai has an MS and BS in electrical and computer engineering from the University of California, Davis.']}}, {'name': 'Tinoosh Mohsenin', 'affiliation': 'University of California, Davis', 'bio': {'p': ['Tinoosh Mohsenin is a PhD candidate in electrical and computer engineering at the University of California, Davis. Her research interests include Low Density Parity Check (LDPC) algorithms and architectures, and processor design. Mohsenin has an MS in electrical and computer engineering from Rice University and a BS in electrical engineering from Sharif University.']}}, {'name': 'Dean Truong', 'affiliation': 'University of California, Davis', 'bio': {'p': ['Dean Truong is a PhD student in electrical and computer engineering at the University of California, Davis. His research interests include high-speed processor architectures and VLSI design. Truong has a BS in electrical and computer engineering from the University of California, Davis.']}}, {'name': 'Jason Cheung', 'affiliation': 'University of California, Davis', 'bio': {'p': ['Jason Cheung is a software developer at Seven Networks. His research interests are in many-core compilers. Cheung has a BS in computer science and engineering from the University of California, Davis.']}} %*AsAP: A Fine-Grained Many-Core Platform for DSP Applications %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4287394 %f/micro/e3rtcvdjlaq9xi5frymgj6yqsl07wda2.pdf %m57e7a70be005ec3c041730d87adbcf50 %cmicro %@[{'name': 'John Wawrzynek', 'affiliation': 'University of California, Berkeley', 'bio': {'p': ['John Wawrzynek is a professor of electrical engineering and computer sciences at the University of California, Berkeley. He currently teaches courses in computer architecture, VLSI system design, and reconfigurable computing. He is codirector of the Berkeley Wireless Research Center and principal investigator of the Research Accelerator for Multiple Processors (RAMP) project. He holds a PhD and MS in computer science from the California Institute of Technology and a MS in electrical engineering from the University of Illinois, Urbana-Champaign. He is a member of the IEEE and the ACM.']}}, {'name': 'David Patterson', 'affiliation': 'University of California, Berkeley', 'bio': {'p': ['David Patterson is the Pardee Professor and Director of RAD Lab at the University of California, Berkeley. His research interests are in design and automatic management of datacenters and in hardware-software architectures of highly parallel microprocessors. He is a fellow of IEEE, recipient of the IEEE von Neumann and IEEE Mulligan Education medals, fellow and past president of the ACM, and a member of the American Academy of Arts and Sciences, the National Academy of Engineering, the National Academy of Sciences, and the Silicon Valley Engineering Hall of Fame.']}}, {'name': 'Mark Oskin', 'affiliation': 'University of Washington', 'bio': {'p': ['Mark Oskin is an assistant professor at the University of Washington. His research interests include computer systems architecture, performance modeling, and architectures for emerging technologies. With a large team of graduate students, he is the coinventor of WaveScalar, the first dataflow machine capable of executing applications written in imperative languages, and brick and mortar, a low-cost technique for manufacturing SoC devices. He received his PhD in computer science from the University of California, Davis.']}}, {'name': 'Shih-Lien Lu', 'affiliation': 'Intel', 'bio': {'p': ["Shih-Lien Lu has a BS in electrical engineering and computer sciences from the University of California, Berkeley, and an MS and a PhD, both in computer science and engineering, from the University of California, Los Angeles. He served on the faculty of the Electrical and Computer Sciences Department at Oregon State University from 1991 to 2001. In 1999, he took a two-year leave from OSU and joined Intel. He is currently a principal research scientist in the microarchitecture lab of Intel's Microprocessor Technology Lab in Oregon. His research interests include computer microarchitecture, circuits, and FPGA systems design."]}}, {'name': 'Christoforos Kozyrakis', 'affiliation': 'Stanford University', 'bio': {'p': ['Christoforos Kozyrakis is an assistant professor of electrical engineering and computer science at Stanford University. His research focuses on architectural support for parallel computing, system security, and energy management. He is currently working on transactional memory techniques that can greatly simplify parallel programming for the average developer. He has a PhD in computer science from the University of California, Berkeley.']}}, {'name': 'James C. Hoe', 'affiliation': 'Carnegie Mellon University', 'bio': {'p': ['James C. Hoe is an associate professor of electrical and computer engineering at Carnegie Mellon University. His research interests include computer architecture and high-level hardware description and synthesis. He has a PhD in electrical engineering and computer science from the Massachusetts Institute of Technology. He is a member of the IEEE and the ACM.']}}, {'name': 'Derek Chiou', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ['Derek Chiou is an assistant professor at the University of Texas at Austin. His research interests include computer system simulation, computer architecture, parallel computer architecture, and Internet router architecture. He received his PhD, SM, and SB degrees in electrical engineering and computer science from the Massachusetts Institute of Technology. He is a senior member of the IEEE and a member of the ACM.']}}, {'name': 'Krste Asanovic', 'affiliation': 'Massachusetts Institute of Technology', 'bio': {'p': ['Krste Asanović is an associate professor in the Department of Electrical Engineering and Computer Science at MIT and a member of the MIT Computer Science and Artificial Intelligence Laboratory. His research interests include computer architecture and VLSI design. Asanović has a BA in electrical and information sciences from the University of Cambridge and a PhD in computer science from the University of California, Berkeley. He is a member of the IEEE and the ACM.']}} %*RAMP: Research Accelerator for Multiple Processors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4287395 %f/micro/ygr34pvj5nyub6djusklhpfrcclqngex.pdf %m9fc4f747643557c023fec22cf8d05be2 %cmicro %@[{'name': 'Arjan Bink', 'affiliation': 'Handshake Solutions', 'bio': {'p': ['Arjan Bink is chief design engineer at Handshake Solutions. Previously, he worked at Philips Research on numerous processor-related projects and in the Strategic ASIC Group at Philips Semiconductors working on advanced prototyping architectures and SoC design. Bink has an MSc in computer science and a professional doctorate in engineering from the Technical University in Eindhoven.']}}, {'name': 'Richard York', 'affiliation': 'ARM', 'bio': {'p': ["Richard York is product manager for many of ARM's advanced CPU products, including the ARM SecurCore family of microprocessors and a new range of deeply embedded CPUs in development. He has also been closely involved with the design of ARM7TDMI core and was an architect in ARM's advanced research and development group. He is the principal architect of the ARM RealTrace debugging system. Before joining ARM, York worked in the Amulet group at the University of Manchester, researching asynchronous implementations of the ARM architecture."]}} %*ARM996HS: The First Licensable, Clockless 32-Bit Processor Core %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4287396 %f/micro/rvxum3bvietga5rjftxpdodwjsaz1s40.pdf %me404bbf2210e440a14701f220ea8c5ca %cmicro %@[{'name': 'Tse-Yu Yeh', 'affiliation': 'P.A. Semi', 'bio': {'p': ['Tse-Yu Yeh is the director of architecture and verification at P.A. Semi. He received his PhD from the Electrical Engineering and Computer Science Department at the University of Michigan. One of his papers was elected to be among the 41 most influential papers in ISCA. He is a member of IEEE.']}} %*Low-Power, High-Performance Architecture of the PWRficient Processor Family %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4287397 %f/micro/y2l5gt8sjv1c6jxrvoieakxmo0hwzfku.pdf %mc878dae5234537271e5fc9bbdc1d1d94 %cmicro %@[{'name': 'Richard Stern', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/4287384/4287398/4287398-photo-1-small.gif', 'p': ['']}} %*Coming down the home stretch in the Rambus standardization skullduggery saga: To levy or not to levy royalties %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4287398 %f/micro/pueg0b5tcxj3zrykfvuczad8awqhg6oe.pdf %mc9fd1f272428258bbe66b2da27b9555d %cmicro %@[{'name': 'Richard Mateosian'} %*Looking Back %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4287399 %f/micro/f9o7ncmjitvoyzf3dipequgarw5k2hv1.pdf %mcdc1d78f628f5efe75e54cf892df9172 %cmicro %@[{'name': 'Philip Emma', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/4287384/4287400/4287400-photo-1-small.gif', 'p': ['']}} %*Supercharging Your Creative Skills %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4287400 %f/micro/38hb4hnan9yddxyekf6wcfijguzwvstm.pdf %mac1073ff7e808e5abfbd189a3bfef967 %cmicro %@[{'name': 'David H. Albonesi', 'affiliation': 'Cornell University'} %*More Hot Stuff %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4292051 %f/micro/zxhbsrgkwmxcaqegfonq09wyupaoj78d.pdf %maaa422281e34ee38236c14ce9bde8f35 %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'Kellogg Graduate School of Management', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/4292046/4292052/4292052-photo-1-small.gif', 'p': ['']}} %*Did the Price of the Internet Drop? %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4292052 %f/micro/dmgj6yzsqkuj9mhvkep52cvifpgbobey.pdf %m39fa9f8a80453f2d8183f35185ac8d45 %cmicro %@[{'name': 'Tim Harris', 'affiliation': 'Microsoft Research', 'bio': {'p': ['Tim Harris is a researcher at Microsoft Research Cambridge where he works on the design and implementation of programming languages and runtime systems with a particular focus on the needs of multicore processors and systems problems. He received his BA and PhD from the University of Cambridge Computer Laboratory and is a professional member of the ACM.']}}, {'name': 'Adrián Cristal', 'affiliation': 'Barcelona Supercomputing Center', 'bio': {'p': ['Adrian Cristal is a senior researcher in the Barcelona Supercomputing Center. His interests include high-performance microarchitecture, multi- and many-core chip multiprocessors, transactional memory, and programming models. He received a PhD from the Computer Architecture Department at the Polytechnic University of Catalonia (UPC), Spain, and he has a BS and an MS in computer science from the University of Buenos Aires, Argentina.']}}, {'name': 'Osman S. Unsal', 'affiliation': 'Barcelona Supercomputing Center', 'bio': {'p': ['Osman S. Unsal is a senior researcher at the Barcelona Supercomputing Center. His current research interests include computer architecture, reliability, and ensuring programmer productivity. He holds BS, MS, and PhD degrees in electrical and computer engineering from Istanbul Technical University, Brown University, and University of Massachusetts, Amherst, respectively.']}}, {'name': 'Eduard Ayguade', 'affiliation': 'Barcelona Supercomputing Center and Universitat Politècnica de Catalunya', 'bio': {'p': ['Eduard Ayguade is a full professor in the Computer Architecture Department at Universitat Politecnica de Catalunya (UPC), Spain. He is also associate director for research on Computer Sciences at the Barcelona Supercomputing Center (BSC). His research interests cover the areas of multicore architectures and programming models and compilers for high-performance architectures. He has an Engineering degree in telecommunications and a PhD in computer science, both from UPC.']}}, {'name': 'Fabrizio Gagliardi', 'affiliation': 'Microsoft', 'bio': {'p': ['Fabrizio Gagliardi is Europe, Middle East, Africa, and Latin America director for scientific and technical computing in the Advanced Strategies and Policy Division at Microsoft. He joined Microsoft after a long career at CERN, the world leader laboratory for particle physics in Geneva, Switzerland. There, he served as director of the EU Grid project EGEE, director of the EU Data-Grid project, head of mass storage services, leader of the EU project GPMIMD2, and cofounder and member of the International Advisory Committee of the Global Grid Forum. Gagliardi received a doctoral degree in computer science from the University of Pisa. He is a longtime member of the IEEE.']}}, {'name': 'Burton Smith', 'affiliation': 'Microsoft', 'bio': {'p': ['Burton Smith is a Technical Fellow at Microsoft. His main interest is general-purpose parallel computer architecture. Earlier in his career, he was a Fellow at the Supercomputing Research Center of the Institute for Defense Analyses in Maryland, Vice President, Research and Development at Denelcor, and chief architect of the HEP computer system. He received a BSEE from the University of New Mexico and an ScD from MIT. Smith is a fellow of both the ACM and the IEEE and winner of the 1991 IEEE-ACM Eckert-Mauchly award. He was elected to the National Academy of Engineering and received the Seymour Cray award, both in 2003.']}}, {'name': 'Mateo Valero', 'affiliation': 'Barcelona Supercomputing Center and Universitat Politècnica de Catalunya', 'bio': {'p': ['Mateo Valero is a professor in the Computer Architecture Department at UPC and director of the Barcelona Supercomputer Center. His research interests include high-performance architectures. Valero has a PhD in telecommunications from UPC. He is an IEEE Fellow, an Intel Distinguished Research Fellow, and an ACM Fellow. He is a founding member of the Royal Spanish Academy of Engineering.']}} %*Transactional Memory: An Overview %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4292053 %f/micro/m7scbngdjpiykqlwef4gf35dmhyubk9x.pdf %m4535f8eccd1ac04692466e39a72c891e %cmicro %@[{'name': 'Gabriel H. Loh', 'affiliation': 'Georgia Institute of Technology', 'bio': {'p': ['Gabriel H. Loh is an assistant professor in the College of Computing at the Georgia Institute of Technology. His research interests include computer architecture, processor microarchitecture, circuit design, and 3D integration technology. He received his PhD in computer science from Yale University. He is a recipient of the National Science Foundation CAREER award.']}}, {'name': 'Yuan Xie', 'affiliation': 'Pennsylvania State University', 'bio': {'p': ["Yuan Xie is an assistant professor in the Computer Science and Engineering Department at Pennsylvania State University. His research interests include VLSI design, computer architecture, and embedded systems design. He received his PhD in computer engineering from Princeton University. He is a recipient of Semiconductor Research Corporation's Inventor Recognition Award and National Science Foundation CAREER award."]}}, {'name': 'Bryan Black', 'affiliation': 'Intel', 'bio': {'p': ['Bryan Black is the research manager at Intel Labs in Austin, Texas. His research interests are in computing systems, computer architecture, and emerging process technologies. He received his PhD in electrical and computer engineering from Carnegie Mellon University.', 'Direct questions and comments about this article to Gabriel H. Loh, 265 Ferst Drive., KACB 2404, Georgia Inst. of Technology, College of Computing, Atlanta, GA 30332–0765, loh@cc.gatech.edu.', 'For further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/publications/dlib.']}} %*Processor Design in 3D Die-Stacking Technologies %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4292055 %f/micro/knylv1tnoehfw8cp3ytg0p2hoczd9a7s.pdf %m48abde66bf0d0de445163c3c544c6793 %cmicro %@[{'name': 'David Brooks', 'affiliation': 'Harvard University', 'bio': {'p': ['David Brooks is an associate professor of computer science at Harvard University. His research interests include power and thermal-efficient hardware-software system design, and approaches to cope with reliability and variability in next-generation computing systems. He has a BS from the University of Southern California, and an MA and a PhD from Princeton University, all in electrical engineering.']}}, {'name': 'Robert P. Dick', 'affiliation': 'Northwestern University', 'bio': {'p': ['Robert P. Dick is an assistant professor of electrical engineering and computer science at Northwestern University. His research interests span a broad area in computer engineering, with a recent focus on embedded systems and temperature-aware and low-power design. He has a BS computer engineering from Clarkson University and a PhD in electrical engineering from Princeton University.']}}, {'name': 'Russ Joseph', 'affiliation': 'Northwestern University', 'bio': {'p': ['Russ Joseph is an assistant professor of electrical engineering and computer science at Northwestern University. His research interests focus primarily on power- and reliability-aware computer architecture. He has a BS in electrical and computer engineering, with an additional major in computer science, from Carnegie Mellon University and a PhD in electrical engineering from Princeton University.']}}, {'name': 'Li Shang', 'affiliation': "Queen's University", 'bio': {'p': ["Li Shang is an assistant professor in the Department of Electrical and Computer Engineering at Queen's University, Canada. His research interests include computer architecture, interconnection networks, design automation for embedded systems, and design for nanotechnologies. He has a BE from Tsinghua University and a PhD from Princeton University, both in electrical engi-neenng."]}} %*Power, Thermal, and Reliability Modeling in Nanometer-Scale Microprocessors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4292056 %f/micro/wohkdeqjslvbs94nwf6cyxglczrpjmxq.pdf %m421bc99fb3f4ba237a14eb3aba3fb66e %cmicro %@[{'name': 'Kenneth Hoste', 'affiliation': 'Ghent University', 'bio': {'p': ['Kenneth Host is a doctoral student in the Electronics and Information Systems Department of Ghent University, Belgium. His research interests include computer architecture in general and workload char- acterization in particular. Hoste has an MS in computer science from Ghent University.']}}, {'name': 'Lieven Eeckhout', 'affiliation': 'Ghent University', 'bio': {'p': ['Lieven Eeckhout is an assistant professor in the Electronics and Information Systems Department of Ghent University, Belgium. His research interests include computer architecture, virtual machines, performance analysis and modeling, and workload characterization. Eeckhout has a PhD in computer science and engineering from Ghent University. He is a member of the IEEE.', 'Direct questions and comments about this article to Kenneth Houste and Lieven Eeckhout, ELIS, Ghent University, SintPieternieuwstraat 41, B-9000 Gent, Belgium, kehoste@elis.UGent.be and leeckhou@elis.ugent.be.']}} %*Microarchitecture-Independent Workload Characterization %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4292057 %f/micro/vsnotupdu76ma92fo4zwqskyrmqhixij.pdf %m4501bb1d1ce5d80dfd3529b448d23147 %cmicro %@[{'name': 'Benjamin C. Lee', 'affiliation': 'Harvard University', 'bio': {'p': ['Benjamin C. Lee is a doctoral candidate in computer science at Harvard University. His research interests include modeling and optimization for power-efficient, high-per-formance computer architectures (such as heterogeneous and adaptive multicores) and applications (such as scientific computing and numerical methods). Lee has a BS from the University of California at Berkeley in electrical engineering and computer science and an MA from Harvard University in computer science.']}}, {'name': 'David M. Brooks', 'affiliation': 'Harvard University', 'bio': {'p': ['David M. Brooks is an associate professor of computer science at Harvard University. His research interests include power - and thermal-efficient hardware-software system design and approaches to cope with reliability and variability in next-generation computing systems. Brooks has a BS from the University of Southern California and an MA and a PhD from Princeton Univer-sity, all in electrical engineering.', 'Direct questions and comments about this article to Benjamin C. Lee, School of Engineering and Applied Sciences, Harvard University, Maxwell Dworkin 307, 33 Oxford St., Cambridge, MA 02138, bclee@seas.harvard.edu.', 'For further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/ publications/dlib.']}} %*Spatial Sampling and Regression Strategies %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4292059 %f/micro/fvp73lkrus5y9rqtz6cjaxzo1jfhnsed.pdf %m998d9fd83913b39a0af429a4f4677df7 %cmicro %@[{'name': 'Serag GadelRab', 'affiliation': 'Double-Pole Technologies', 'bio': {'p': ['Serag GadelRab is founder and chief technology officer of Double-Pole Technologies. His technical interests include network I/O controllers, chipset design methods, and high-speed packet switch architectures. He has a PhD in electrical engineering from the University of Waterloo.']}} %*10-Gigabit Ethernet Connectivity for Computer Servers %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4292060 %f/micro/xwi5qkotq6mayv34f0lgm8exvjfsrhin.pdf %mc97cfd5db3cd501637a7bff9c9e9271c %cmicro %@[{'name': 'Richard Stern', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/4292046/4292061/4292061-photo-1-small.gif', 'p': ['']}} %*Antitrust Division Gives IEEE Standard Setters the Okay to Ask Patentees How RAND They Are %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4292061 %f/micro/zl0xlphywbsfevjnomtupom7rw5k1tic.pdf %m753606dd0f1149f24fd1320348fcb36b %cmicro %@[{'name': 'Philip Emma', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/4292046/4292062/4292062-photo-1-small.gif', 'p': ['']}} %*Arcane Facts and New Words: Expanding Your Creative Talent %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4292062 %f/micro/3chcntm0wiyxlhs46pfifdpqn1dv9te5.pdf %m6d6433ea16435a00ec17c1d7c566fc2b %cmicro %@[{'name': 'David H. Albonesi', 'affiliation': 'Cornell University'} %*Mixing It Up %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4343374 %f/micro/mf0d9vqcjxorahxslwkvfs2r4qbg1yz7.pdf %m948e2c375a83db951e9be2169a4a3fd5 %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'Kellogg Graduate School of Management', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/4343300/4343375/4343375-photo-1-small.gif', 'p': []}} %*The 15-Billion-Dollar Broadband Bonus %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4343375 %f/micro/utndeho6mjbsfgyfnaqvzpkw3ezllvpg.pdf %m10209a376e063cc81578c02de29afc69 %cmicro %@[{'name': 'Assaf Shacham', 'affiliation': 'Columbia University', 'bio': {'p': ['Assaf Shacham completed the work described in this article at Columbia University, where his doctoral dissertation was tided “Architectures of Optical Interconnection Networks for High Performance Computing.” He is now employed by Aprius, where he is engaged in developing high-performance computer interconnects. Shacham has published more than 20 papers in peer-reviewed journals and conferences. He has a PhD and an MS in electrical engineering from Columbia, and a BSc in computer engineering from the Technion, Israel Institute of Technology.']}}, {'name': 'Keren Bergman', 'affiliation': 'Columbia University', 'bio': {'p': ['Keren Bergman is a professor of electrical engineering at Columbia University, where she heads the Lightwave Research Laboratory. Her research includes optical interconnection networks, photonic packet switching, and nanophotonic networks on chips. Bergman has a BS from Bucknell University and an MS and a PhD from the Massachusetts Institute of Technology, all in electrical engineering. She is a senior member of the IEEE and a Fellow of the Optical Society of America (OSA). She serves as Associate Editor for IEEE Photonic Technology Letters and the OSA Journal of Optical Networking.']}} %*Building Ultralow-Latency Interconnection Networks Using Photonic Integration %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4343376 %f/micro/kuvcnyxz45j8buftdwqllm9waakpcdvf.pdf %m5ed5cda72473bd844721c7e6ef5a7445 %cmicro %@[{'name': 'Li Zhao', 'affiliation': 'Systems Technology Lab, Intel Corporation', 'bio': {'p': ['Li Zhao is a senior engineer in the Systems Technology Laboratory at Intel. Her research interests include computer architecture, network computing, and performance evaluation. Zhao has a PhD in computer science from the University of California, Riverside. She is a member of the IEEE.']}}, {'name': 'Ravi Iyer', 'affiliation': 'Systems Technology Lab, Intel Corporation', 'bio': {'p': ['Ravi Iyer is a principal engineer with the Systems Technology Lab at Intel. His current research is on large-scale CMP architectures. Iyer has a PhD in computer science from Texas A & M University. Iyer has published more than 70 papers in computer architecture, I/O acceleration, and performance evaluation. He is an associate editor for IEEE Transactions on Parallel and Distributed Systems.']}}, {'name': 'Jaideep Moses', 'affiliation': 'Systems Technology Lab, Intel Corporation', 'bio': {'p': ['Jaideep Moses is a senior engineer in the Systems Technology Lab at Intel. His current research focus is on large-scale CMP platform architecture analysis and design. His earlier work was I/O acceleration research focusing on modeling, simulation, and analysis of platform architecture. Moses has an MS in computer science from University of Texas at E1 Paso.']}}, {'name': 'Ramesh Illikkal', 'affiliation': 'Systems Technology Lab, Intel Corporation', 'bio': {'p': ["Ramesh Illikkal is a senior researcher in the System Technology Lab at Intel. His research interests are in CMP, server architectures, virtualization, and memory hierarchy. Illikkal has a master's degree in electronics from Cochin University of Science and Technology."]}}, {'name': 'Srihari Makineni', 'affiliation': 'Systems Technology Lab, Intel Corporation', 'bio': {'p': ["Srihari Makineni is a senior engineer in the Systems Technology Lab at Intel. His current research focuses on developing efficient memory hierarchies for multicore platforms. Previously, he has worked on accelerating packet-processing applications on Intel's server platforms. Makineni has an MS in electrical and computer engineering from Lamar University, Texas."]}}, {'name': 'Don Newell', 'affiliation': 'Systems Technology Lab, Intel Corporation', 'bio': {'p': ['Don Newell is a senior principal engineer in the System Technology Lab at Intel. His research interests include server architecture, networking, and I/O acceleration. Newell has a BS in computer science from the University of Oregon.']}} %*Exploring Large-Scale CMP Architectures Using ManySim %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4343377 %f/micro/7pyilfgwtjca0mfidhrqnx4szs6zxugu.pdf %m5e01dfdd69e40a8aabd138dcec41739c %cmicro %@[{'name': 'Jianwei Chen', 'affiliation': 'University of Southern California', 'bio': {'p': ['Jianwei Chen is a PhD candidate in computer engineering at the University of Southern California. His research interests include computer architecture and performance evaluation with a focus on simulation infrastructure, reconfigurable architecture, and chip multiprocessing. Chen has a BS in microelectronics from Peking University and an MS in electrical engineering from Tsinghua University, China.']}}, {'name': 'Michel Dubois', 'affiliation': 'University of Southern California', 'bio': {'p': ['Michel Dubois is a professor in the Department of Electrical Engineering of the University of Southern California. His research interests include computer architecture and parallel processing, with a focus on multiprocessor architecture, performance, and algorithms. Dubois has a PhD from Purdue University, an MS from the University of Minnesota, and an engineering degree from the Faculté Polytechnique de Mons. Belgium, all in electrical engineering. He is a Fellow of the IEEE and the ACM.']}}, {'name': 'Per Stenström', 'affiliation': 'Chalmers University of Technology', 'bio': {'p': ['Per Stenström is a professor of computer architecture at Chalmers University of Technology, Sweden. His main research interest is computer architecture with emphasis on design principles for chip multiprocessors. Stenström has a PhD in computer engineering and an MS in electrical engineering, both from Lund University, Sweden. He is a member of the ACM and a senior member of the IEEE.']}} %*SimWattch: Integrating Complete-System and User-Level Performance and Power Simulators %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4343378 %f/micro/8p7zmhxvfcmefwqnkrbsladsuinupzvt.pdf %me5fc27359a7da758bc29f4d6abc07b3b %cmicro %@[{'name': 'Ivan Gonzalez', 'affiliation': 'George Washington University', 'bio': {'p': ['Ivan Gonzalez is a postdoctoral researcher at the High Performance Computing Laboratory at George Washington University. His main research interests are FPGA-based reconfigurable computing applications, with a special focus on dynamic partial reconfiguration and embedded systems. Other interests include high-performance reconfigurable computing and robotics. He received his PhD in computer engineering from Universidad Autonoma de Madrid.']}}, {'name': 'Estanislao Aguayo', 'affiliation': 'CIEMAT', 'bio': {'p': ["Estanislao Aguayo is currently participating in several European research projects at CIEMAT (Spain's public research agency for energy and environment). His research interests are in complex algorithms implemented in hardware, from optimal control to radioisotope emission image reconstruction, as well as real-time scheduling systems for large sensor arrays. He received his electrical engineering degree from University of Granada, Spain."]}}, {'name': 'Sergio Lopez-Buedo', 'affiliation': 'Universidad Autonoma de Madrid', 'bio': {'p': ['Sergio Lopez-Buedo currently holds a lecturer position in the area of computer architecture at Universidad Autonoma de Madrid. FPGA technology is his main research interest, especially low-power, high-speed design, self-reconfiguration, high-performance reconfigurable computing, and communication applications. He received his PhD in computer engineering from Universidad Autonoma de Madrid. He is a member of the IEEE.']}} %*Self-Reconfigurable Embedded Systems on Low-Cost FPGAs %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4343379 %f/micro/pwrgpquy6cwhbe1sqzmoltmof2z8hkdf.pdf %mfcc9e0cf0b39856ba991574c36664ea3 %cmicro %@[{'name': 'Richard Mateosian'} %*Thinking about Technology (Talbott, S.; 2007) [Book review] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4343380 %f/micro/78ntwyldwzmhxik9eso120fupiqvrj5q.pdf %m2ced9b07746f759f1ac009239918878f %cmicro %@[{'name': 'Philip Emma', 'affiliation': 'IBM T.J. Watson Research Center'} %*Innovation or Notoriety? %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4343381 %f/micro/vlgbcdziyynrhmjawk8z9sd0o5rnfuq3.pdf %m811bbd1fcec9712965c32ba1601229f6 %cmicro %@[{'name': 'David H. Albonesi', 'affiliation': 'Cornell University', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/4437705/4437712/4437712-photo-1-small.gif', 'p': []}} %*Productive and Healthy Debate %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4437712 %f/micro/wco7xs3sk0ygave952ukzmul6f4x1cml.pdf %m11459c6484ed86449887733d9f8bfc35 %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'Kellogg Graduate School of Management'} %*Innovation at the Edges %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4437714 %f/micro/zy1amz6spjwh38ksqidxoevbf5pwtrca.pdf %m3a0694dca7ff96e3afc8e647ecd40167 %cmicro %@[{'name': 'Richard Stern'} %*Supreme Court to Hear Semiconductor Chip Patent "Exhaustion" Case %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4437715 %f/micro/dqs0wcidhwaggkickxzpxv2y5rmljtm8.pdf %mcdffa7da80e50cb7ce082d5ddbcdb73a %cmicro %@[{'name': 'Joel Emer', 'affiliation': 'Intel', 'bio': {'p': ['Joel Emer is an Intel Fellow and director of microarchitecture research at Intel, where he leads the VSSAD group. He also teaches part-time at the Massachusetts Institute of Technology. His current research interests include performance-modeling frameworks, parallel and multithreaded processors, cache organization, processor pipeline organization, and processor reliability. Emer has a PhD in electrical engineering from the University of Illinois. He is an ACM Fellow and a Fellow of the IEEE.']}}, {'name': 'Mark D. Hill', 'affiliation': 'University of Wisconsin-Madison', 'bio': {'p': ['Mark D. Hill is a professor in both the Computer Sciences and Electrical and Computer Engineering Departments at the University of Wisconsin-Madison, where he also coleads the Wisconsin Multifacet project with David Wood. His research interests include parallel computer system design, memory system design, computer simulation, and transactional memory. Hill has a PhD in computer science from the University of California, Berkeley. He is a Fellow of the IEEE and the ACM.']}}, {'name': 'Yale N. Patt', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ['Yale N. Patt is the Ernest Cockrell Jr. Centennial Chair in Engineering at the University of Texas at Austin. His research interests focus on harnessing the expected benefits of future process technology to create more effective microarchitectures for future microprocessors. He is a Fellow of the IEEE and the ACM.']}}, {'name': 'Joshua J. Yi', 'affiliation': 'Freescale Semiconductor', 'bio': {'p': ['Joshua J. Yi is a performance analyst at Freescale Semiconductor in Austin, Texas. His research interests include high-performance computer architecture, simulation, low-power design, and reliable computing. Yi has a PhD in electrical engineering from the University of Minnesota, Minneapolis. He is a member of the IEEE and the IEEE Computer Society.']}}, {'name': 'Derek Chiou', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ['Derek Chiou is an assistant professor in the Electrical and Computer Engineering Department at the University of Texas at Austin. His research interests include com-puter system simulation, computer architecture, parallel computer architecture, and Internet router architecture. Chiou has a PhD in electrical engineering and computer science from the Massachusetts Institute of Technology. He is a senior member of the IEEE and a member of the ACM.']}}, {'name': 'Resit Sendag', 'affiliation': 'University of Rhode Island', 'bio': {'p': ['Resit Sendag is an assistant professor in the Department of Electrical and Computer Engineering at the University of Rhode Island, Kingston. His research interests include high-performance computer archi-tecture, memory systems performance issues, and parallel computing. Sendag has a PhD in electrical and computer engineering from the University of Minnesota, Minneapolis. He is a member of the IEEE and the IEEE Computer Society.', 'For more information on this or any other computing topic, please visit our Digital Library at http://computer.org/csdl.']}} %*Single-Threaded vs. Multithreaded: Where Should We Focus? %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4437716 %f/micro/m0jn3pwtxtv6n5yuluegihslbsbkdcqj.pdf %mf6329e2b5783f103597b054f519f3aa0 %cmicro %@[{'name': 'Shay Gueron', 'affiliation': 'University of Haifa and Intel Corporation', 'bio': {'p': ["Shay Gueron is a professor in the Department of Mathematics, Faculty of Science and Science Education, at the University of Haifa, Israel, and a security architect at Intel Corporation (Israel Design Center). Gueron's research interests include applied security, cryptography, and algorithms. He has a PhD in applied mathematics from Technion-Israel Institute of Technology."]}}, {'name': 'Jean-Pierre Seifert', 'affiliation': 'University of Innsbruck and Samsung Electronics', 'bio': {'p': ["Geoffrey Strongin is an AMD Fellow and AMD's chief platform security architect. He was a founding board member of the Trusted Computing Group. He has a BSEE degree from Arizona State University."]}}, {'name': 'Geoffrey Strongin', 'affiliation': 'Advanced Micro Devices', 'bio': {'p': ["Jean-Pierre Seifert is affiliated with the Universities of Haifa and Innsbruck and is directing Samsung's Trusted Platform Research Lab in San Jose. He previously worked for Intel and Infineon Technologies, where as a principal engineer he led research and development in the Smartcard and SecurityIC business unit. There, he received the Inventor of the Year award and initiated and managed several EU-funded projects."]}}, {'name': 'Derek Chiou', 'affiliation': 'University of Texas at Austin'}, {'name': 'Resit Sendag', 'affiliation': 'University of Rhode Island'}, {'name': 'Joshua J. Yi', 'affiliation': 'Freescale Semiconductor'} %*Where Does Security Stand? New Vulnerabilities vs. Trusted Computing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4437717 %f/micro/dbwej4tl2u93nsfcfykh6porgz1iwqax.pdf %m150ef36e584aca6eb32f09fe9a508080 %cmicro %@[{'name': 'Antonio Gonzalez', 'affiliation': 'Intel', 'bio': {'p': ['Antonio Gonzalez is the founding director of the Intel-UPC Barcelona Research Center and a professor of computer architecture at Universitat Politècnica de Catalunya. His research focuses on computer architecture, with particular emphasis on processor micro architecture and code generation techniques. González is an associate editor of IEEE Transactions on Computers, IEEE Transactions on Parallel and Distributed Systems, ACM Transactions on Architecture and Code Optimization, and Journal of Embedded Computing.']}}, {'name': 'Scott Mahlke', 'affiliation': 'University of Michigan', 'bio': {'p': ['Scott Mahlke is an associate professor in the Electrical Engineering and Computer Science Department at the University of Michigan, where he directs the Compilers Creating Custom Processors research group. His research interests include application-specific processors, high-level synthesis, compiler optimization, and computer architecture. Mahlke has a PhD from the University of Illinois, Urbana-Champaign. He is a member of the IEEE and ACM.']}}, {'name': 'Shubu Mukherjee', 'affiliation': 'Intel', 'bio': {'p': ['Shubu Mukherjee is a principal engineer and director of SPEARS (Simulation and Pathfinding of Efficient and Reliable Systems) at Intel. The SPEARS Group spearheads architectural innovation in the delivery of microprocessors and chipsets by building and supporting simulation and analytical models of performance, power, and reliability. Mukherjee has a PhD computer science from the University of Wisconsin–Madison.', 'The biographies of Resit Sendag, Derek Chiou, and Joshua J. Yi appear on p. 24.', 'For more information on this or any other computing topic, please visit our Digital Library at http://computer.org/csdl.']}}, {'name': 'Resit Sendag', 'affiliation': 'University of Rhode Island'}, {'name': 'Derek Chiou', 'affiliation': 'University of Texas at Austin'}, {'name': 'Joshua J. Yi', 'affiliation': 'Freescale Semiconductor'} %*Reliability: Fallacy or Reality? %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4437718 %f/micro/onys1jnmvxwq4uvr2opzyulstai8hkac.pdf %mfd4feefc39cf1b6cd17aadd822a209c0 %cmicro %@[{'name': 'Kevin Skadron', 'affiliation': 'University of Virginia', 'bio': {'p': ['Kevin Skadron is an associate professor in the Department of Computer Science at the University of Virginia. His research interests include power-and temperature-aware design and architecture of many-core and graphics processors. Skadron has a PhD in computer science from Princeton University. He is a senior member of the IEEE, the IEEE Computer Society, and the IEEE Circuits and Systems Society, and a senior member of the ACM. He is a cofounder and associate editor in chief of IEEE Computer Architecture Letters.']}}, {'name': 'Pradip Bose', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ['Pradip Bose is a research staff member and manager at the IBM T.]. Watson Research Center. His research interests include highperformance computer architectures, power-and reliability-aware design, and computer-aided design. Bose has a PhD in electrical and computer engineering from the University of Illinois, Urbana-Champaign. He is a Fellow of the IEEE and the IEEE Computer Society, and a member of the ACM. Bose is also a former editor in chief of IEEE Micro.']}}, {'name': 'Kanad Ghose', 'affiliation': 'State University of New York Binghamton', 'bio': {'p': ['Kanad Ghose is a professor in and chair of the Department of Computer Science at the State University of New York, Binghamton. His research interests include microarchitectures and compilation techniques for low power, active memory systems, and highperformance networking. He has a PhD in computer science from Iowa State University. He is a member of the IEEE, the IEEE Computer Society, and ACM, and an associate editor for the computer architecture area of IEEE Transactions on Computers.']}}, {'name': 'Resit Sendag', 'affiliation': 'University of Rhode Island'}, {'name': 'Joshua J. Yi', 'affiliation': 'Freescale Semiconductor'}, {'name': 'Derek Chiou', 'affiliation': 'University of Texas at Austin'} %*Low-Power Design and Temperature Management %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4437719 %f/micro/urzxqg2etabhpqdf7s136dcjyc5ryjvv.pdf %m3b165f058eadc17a4fe1d3ff0463cce2 %cmicro %@[{'name': 'Richard Mateosian'} %*Advice for Investigators %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4437722 %f/micro/viu7thnlx01ckyw2jrolpu4yfkgoxb5f.pdf %ma6f309f1d369273d76108b06986127d3 %cmicro %@[{'name': 'Philip Emma', 'affiliation': 'IBM T.J. Watson Research Center'} %*You're Invited to a Party! (How To Hold a Collaborative IP-Development Session) %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4437723 %f/micro/t8ir4omuyeq2bldmbqlaxzoctevu3hw7.pdf %m98ad946deef2e0174174a737764aaba3 %cmicro %@[{'name': 'P. Bose', 'affiliation': 'IBM Corp.', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/33689/1603489/1603489-photo-1-small.gif', 'p': ['IEEE Micro']}} %*Measuring the impact of microarchitectural ideas %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1603489 %f/micro/sxelhw0u3lc7ginqxf9ay6fjv5dr8z1o.pdf %m4fa3eba9147491edec7cb85de401c12a %cmicro %@[{'name': 'S. Greenstein', 'affiliation': 'Northwestern University', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/33689/1603490/1603490-photo-1-small.gif', 'p': ['']}} %*Format wars all over again %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1603490 %f/micro/s8ejkjbdwxaltc27ufryevgk3t9c0pzz.pdf %m28c6ac61c3eeb6e252e338d75fc5ba56 %cmicro %@[{'name': 'J. Torrellas', 'affiliation': 'University of Illinois, Urbana-Champaign', 'bio': {'p': ['Josep Torrellas is a professor of computer science and Willett Faculty Scholar at the University of Illinois, Urbana-Champaign. He is also the chair of the IEEE Technical Committee on Computer Architecture (TCCA). His research interests include multiprocessor computer architecture, thread-level speculation, low-power design, reliability, and debuggability. Torrellas has a PhD in electrical engineering from Stanford University. He is a Fellow of the IEEE and a member of the ACM.', 'Direct questions and comments about this issue to Josep Torrellas, Dept. of Computer Science, University of Illinois, Urbana, IL 61801, http://www.cs.uiuc.edu/~torrellas.']}} %*Guest Editor's Introduction: Micro's Top Picks from Microarchitecture Conferences %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1603491 %f/micro/3oyz18skrttpeebkiycwwuprdlxvjxqf.pdf %m60ff263530d034c9338dec26307ecb49 %cmicro %@[{'name': 'O. Mutlu', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ['Onur Mutlu is a PhD candidate in computer engineering at the University of Texas at Austin. His research interests include computer architectures, with a focus on high-performance energy-efficient microarchitectures, data prefetching, runahead execution, and novel latency-tolerance techniques. Mutlu has an MS in computer engineering from UT Austin and BS degrees in psychology and computer engineering from the University of Michigan. He is a student member of the IEEE and the ACM.']}}, {'name': ' Hyesoon Kim', 'affiliation': 'Texas Univ., Austin, TX', 'bio': {'p': ["Hyesoon Kim is a PhD candidate in electrical and computer engineering at the University of Texas at Austin. Her research interests include high-performance energy-efficient microarchitectures and compiler-microarchi- tecture interaction. Kim has master's degrees in mechanical engineering from Seoul National University and in computer engineering from UT Austin. She is a student member of the IEEE and the ACM."]}}, {'name': 'Y.N. Patt', 'affiliation': 'Texas Univ., Austin, TX', 'bio': {'p': ['Yale N. Patt is the Ernest Cockrell Jr. Centennial Chair in Engineering at the University of Texas at Austin. His research interests include harnessing the expected fruits of future process technology into more effective microarchitectures for future microprocessors. Patt has a PhD in electrical engineering from Stanford University. He is co-author of Introduction to Computing Systems: From Bits and Gates to C and Beyond, (McGraw-Hill, 2nd edition, 2004). His honors include the 1996 IEEE/ACM Eckert-Mauchly Award and the 2000 ACM Karl V. Karlstrom Award. He is a Fellow of both the IEEE and the ACM.', 'Direct questions and comments about this article to Onur Mutlu, 2501 Lake Austin Blvd., Apt. N204, Austin, TX 78703, onur@ece.utexas.edu.', 'For further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/publications/dlib.']}} %*Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1603492 %f/micro/amjkqwxtntghe8s2rq1vifuympdglhib.pdf %m34b7e0b8b86bb33474dc937dffa31824 %cmicro %@[{'name': 'I. Hur', 'affiliation': 'IBM Corp. and The University of Texas at Austin', 'bio': {'p': ['Ibrahim Hur is a staff engineer in the Future Processor Performance Department of IBM Corp. and a PhD candidate at the University of Texas at Austin. His research interests include novel microprocessor architectures, memory systems, performance analysis, and performance modeling. Hur has a MSc in computer science from Southern Methodist University. He is a member of the ACM and the IEEE.']}}, {'name': 'C. Lin', 'bio': {'p': ['Calvin Lin is an associate professor in the Department of Computer Sciences at the University of Texas at Austin. His research interests include languages, compilers, and microarchitecture. Lin has a PhD in computer science from the University of Washington. He is a member of the ACM and the IEEE.', 'Direct questions and comments about this article to Ibrahim Hur, ihur@cs.utexas.edu.', 'For further information on this or any other computing topic, visit our Digital Library at http://computer.org/publications/dlib.']}} %*Adaptive History-Based Memory Schedulers for Modern Processors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1603494 %f/micro/6w8zumlp9gn0pklxciq5bhyx2zvtqe1s.pdf %m1441f735ab645b2b2e34ee41e511b498 %cmicro %@[{'name': 'A. Gandhi', 'affiliation': 'Intel Corp.', 'bio': {'p': ['Amit Gandhi is a senior design engineer in the Intel Platform Validation and Enabling group, Hillsboro, Oregon. His primary research interest is microprocessor architecture. Gandhi has a BE in instrumentation and control from the University of Pune, India, and an MS and a PhD in electrical and computer engineering from Portland State University. He is a member of the IEEE.']}}, {'name': 'H. Akkary', 'bio': {'p': ['Haitham Akkary is a principal research scientist at the Intel Microprocessor Technology Lab, Hillsboro, Oregon. His primary research interest is microprocessor architecture. Akkary has a BS and an MS from Louisiana State University, and a PhD from Portland State University, all in electrical and computer engineering. He is a member of the IEEE and the ACM.']}}, {'name': 'R. Rajwar', 'bio': {'p': ['Ravi Rajwar is a staff research scientist at the Intel Microprocessor Technology Lab, Hillsboro, Oregon. His research interests include the theoretical and practical aspects of computer architecture. Rajwar has a PhD in computer science from the University of Wisconsin-Madison. He is a member of the IEEE and the ACM.']}}, {'name': 'S.T. Srinivasan', 'bio': {'p': ['Srikanth T. Srinivasan is a staff research scientist at the Intel Microprocessor Technology Lab, Hillsboro, Oregon. His research focuses on scalable and efficient microarchitectures. Srinivasan has a BE from the Birla Institute of Technology and Science, Pilani, India, and a PhD from Duke University, both in computer science. He is a member of the IEEE and the ACM.']}}, {'name': 'K. Lai', 'bio': {'p': ["Konrad Lai is a senior principal research scientist at Intel's Microprocessor Technology Lab, Hillsboro, Oregon. His research interests include microprocessor, memory, and system architectures. Lai has a BS in electrical engineering from Princeton University and an MS in computer engineering from Carnegie Mellon University. He is a member of the IEEE and the ACM.", 'Direct questions and comments about this article to Haitham Akkary, Microprocessor Technology Lab, M/S JF3–332 Intel Corp., 2111 NE 25th Ave., Hillsboro, OR 97124, haitham.h.akkary@intel.com.', 'For further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/publications/dlib.']}} %*Scalable Load and Store Processing in Latency-Tolerant Processors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1603495 %f/micro/nbhjy4z3aixc56wgupu82odjxldkagpf.pdf %m357409d60b80c87e8bb0222581ea8887 %cmicro %@[{'name': 'R.D. Barnes', 'affiliation': 'George Mason University', 'bio': {'p': ['Ronald D. Barnes is an assistant professor at George Mason University. His research interests include complexity-effective microarchitectures, program-phase detection, and binary and runtime optimization. Barnes has a PhD in electrical engineering from the University of Illinois, Urbana-Champaign. He is a member of the IEEE and the ACM.']}}, {'name': 'S. Ryoo', 'bio': {'p': ['Shane Ryoo is a graduate student in electrical engineering at the University of Illinois, Urbana-Champaign. His research interests include interprocedural analysis techniques for identifying coarse-grained parallelism and efficient algorithms for computer architectures and compilers. Ryoo has an MS in electrical engineering from the University of Illinois, Urbana-Champaign. He is a student member of the IEEE.']}}, {'name': ' Wen-mei W. Hwu', 'bio': {'p': ['Wen-mei W. Hwu is the Sanders-AMD Endowed Chair Professor in the Department of Electrical and Computer Engineering, University of Illinois, Urbana-Champaign. He is the director of the Illinois Microarchitecture Project utilizing Advanced Compiler Technology (Impact) lab, which delivers new compiler and computer architecture technologies to the computer industry. His research interests include architecture, implementation, and software for high-performance computer systems. Hwu has a BSEE from the National Taiwan University and a PhD in computer science from the University of California, Berkeley. He is a Fellow of the IEEE and the ACM.', 'For further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/publications/dlib.']}} %*Tolerating Cache-Miss Latency with Multipass Pipelines %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1603496 %f/micro/e8itod1xiuhsphwmmgybnlyo0vtf4klc.pdf %m42c1e813acfe39c572bda1280e050fce %cmicro %@[{'name': ' Hyesoon Kim', 'affiliation': 'University of Texas at Austin', 'bio': {'p': ["Hyesoon Kim is a PhD candidate in electrical and computer engineering at the University of Texas at Austin. Her research interests include high-performance energy-efficient microarchitectures and compiler-microarchi-tecture interaction. Kim has master's degrees in mechanical engineering from Seoul National University, and in computer engineering from UT Austin. She is a student member of the IEEE and the ACM."]}}, {'name': 'O. Mutlu', 'affiliation': 'Texas Univ., Austin, TX', 'bio': {'p': ['Onur Mutlu is a PhD candidate in computer engineering at the University of Texas at Austin. His research interests include computer architectures, with a focus on highperformance energy-efficien microarchi-tectures, data prefetching, runahead execution, and novel latency-tolerance techniques. Mutlu has an MS in computer engineering from UT Austin and BS degrees in psychology and computer engineering from the University of Michigan. He is a student member of the IEEE and the ACM.']}}, {'name': 'Y.N. Patt', 'bio': {'p': ['Yale N. Patt is the Ernest Cockrell, Jr. Centennial Chair in Engineering at the Universi-ty of Texas at Austin. His research interests include harnessing the expected fruits of future process technology into more effective microarchitectures for future microprocessors. He is co-author of Introduction to Computing Systems: From Bits and Gates to C and Beyond (McGraw-Hill, 2nd edition, 2004). His honors include the 1996 IEEE/ACM Eckert-Mauchly Award and the 2000 ACM Karl V. Karlstrom Award. He is a Fellow of both the IEEE and the ACM.']}}, {'name': 'J. Stark', 'bio': {'p': ["Jared Stark is a computer architect at Intel's Israel Development Center in Haifa, Israel. His research interests include front-end microarchitecture, in particular, branch prediction, dynamic instruction sched-uling, and techniques for tolerating cache and memory latencies. Stark has a BSE in electrical engineering and MSE and PhD in computer science and engineering from the University of Michi-gan, Ann Arbor. He is a member of the IEEE.", 'For further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/publications/dlib.']}} %*Wish Branches: Enabling Adaptive and Aggressive Predicated Execution %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1603497 %f/micro/supprx1gtfcdzwzb3vbeqea8trn5onvc.pdf %me5f532dcd0a0df5da0fbad3d7b966a66 %cmicro %@[{'name': 'C.S. Ananian', 'affiliation': 'Massachusetts Institute of Technology', 'bio': {'p': ['C. Scott Ananian is a PhD candidate in electrical engineering and computer science at MIT. His research interests include compilers, language design, embedded systems, and transactions. Ananian has a BSE in electrical engineering from Princeton University and an MSc in electrical engineering and computer science from MIT. He is a member of the IEEE and the ACM.']}}, {'name': 'K. Asanovic', 'affiliation': 'Dept. of Electr. Eng. & Comput. Sci., Massachusetts Inst. of Technol.', 'bio': {'p': ['Krste Asanovic is an associate professor in the Department of Electrical Engineering and Computer Science at MIT and a member of the MIT Computer Science and Artificial Intelligence Laboratory. His research interests include computer architecture and VLSI design. Asanovic has a BA in electrical and information sciences from the University of Cambridge and a PhD in computer science from the University of California, Berkeley. He is a member of the IEEE and the ACM.']}}, {'name': 'B.C. Kuszmaul', 'bio': {'p': ['Bradley C. Kuszmaul is a research scientist in the Supercomputing Technologies Group of the MIT Computer Science and Artificial Intelligence Laboratory. His research interests include developing computer systems with provably good performance. Kuszmaul has a PhD in computer science from MIT. He is a member of the IEEE and the ACM.']}}, {'name': 'C.E. Leiserson', 'bio': {'p': ['Charles E. Leiserson is a professor of computer science and engineering in the MIT Computer Science and Artificial Intelligence Laboratory, a member of its Theory of Computation Group, and head of its Supercomputing Technologies Group. His research interests include algorithms, multithreading, and computing machinery theory. Leiserson has a BS in computer science and mathematics from Yale University and a PhD in computer science from Carnegie Mellon University. He is a member of the ACM, the IEEE, and SIAM. Sean Lie is a design engineer in the architecture group at Advanced Micro Devices. His research interests include high-performance computer architecture and VLSI design. He has a BS and an MEng, both in electrical engineering and computer science, from MIT, where he participated in the work described here.', 'Direct questions and comments to Charles E. Leiserson, MIT Computer Science and Artificial Intelligence Laboratory, 32 Vassar St., #32-G768, Cambridge, MA 02139, cel@mit.edu.', 'For further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/publications/dlib.']}}, {'name': 'S. Lie'} %*Unbounded Transactional Memory %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1603498 %f/micro/kfbosu4g8z6kmjoygjuelipw0s5ny31i.pdf %m256fa09e79c41a75842cd1911943bff7 %cmicro %@[{'name': 'J.F. Cantin', 'affiliation': 'University of Wisconsin-Madison', 'bio': {'p': ['Jason F. Cantin is pursuing a PhD in the Department of Electrical and Computer Engineering at the University of Wisconsin-Madison. His research interests include shared-memory multiprocessor systems, fault-tolerant computing, and VLSI. Cantin has BS degrees in electrical engineering and computer engineering from the University of Cincin-nati and an MS in computer engineering from the University of Wisconsin.']}}, {'name': 'J.E. Smith', 'affiliation': 'Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI', 'bio': {'p': ['James E. Smith is a professor in the Department of Electrical and Computer Engineering at the University of Wisconsin-Madison. His research interests include high-performance and power-efficient processor implementations, processor performance modeling, and virtual machines. Smith has a PhD in computer science from the University of Illinois. He is a member of the IEEE and the ACM.']}}, {'name': 'M.H. Lipasti', 'affiliation': 'Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI', 'bio': {'p': ['Mikko H. Lipasti is an associate professor in the Department of Electrical and Computer Engineering at the University of Wisconsin-Madison. His research interests include highperformance processor and multiprocessor architecture and the interaction between hardware and modern system software. Lipasti has a PhD in electrical and computer engineering from Carnegie Mellon University. He is a member of the IEEE and Tau Beta Pi.']}}, {'name': 'A. Moshovos', 'bio': {'p': ['Andreas Moshovos is an assistant professor in the Electrical and Computer Engineering Department of the University of Toronto. His research interests include microarchitectural optimizations for high-performance processors and systems. Moshovos has a Ptyhion degree and an MSc, both in computer science, from the University of Crete, Greece, and a PhD in computer science from the University of Wisconsin-Madison. He is a member of IEEE and the ACM.']}}, {'name': 'B. Falsafi', 'bio': {'p': ['Babak Falsafi is an associate professor of electrical and computer engineering and a Sloan Research Fellow at Carnegie Mellon University. His research interests include computer architecture with emphasis on high-performance memory systems, architectural support for gigascale integration, and computer system performance evaluation tools. Falsafi has a PhD in computer science from the Univer- sity of Wisconsin. He is a member of the IEEE and the ACM.', 'Direct questions and comments about this article to Jason F. Cantin, Dept. of Electrical and Computer Engineering, University of Wisconsin, 1415 Engineering Dr., Madison, WI 53706, jason@jasoncantin.com.', 'For further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/publications/dlib.']}} %*Coarse-Grain Coherence Tracking: RegionScout and Region Coherence Arrays %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1603499 %f/micro/96pb8hzewxuwaji7rful02ha4bnctgrn.pdf %ma24e03989643bb3162a7c9d0ce78569d %cmicro %@[{'name': 'J. Renau', 'affiliation': 'University of California at Santa Cruz', 'bio': {'p': ['Jose Renau is an assistant professor of computer engineering at the University of Califor-nia, Santa Cruz. His research interests include design effort and complexity estimators, CMPs, energy-performance trade-offs, thread-level speculation, processors in memory, and check-pointed architectures. Renau has a PhD in computer science from the University of Illi-nois, Urbana-Champaign. He is a member of the IEEE Computer Society and the ACM.']}}, {'name': 'K. Strauss', 'bio': {'p': ['Karin Strauss is a PhD candidate in computer science at the University of Illinois, Urbana-Champaign. Her research interests include multiprocessor systems and cache coherence protocols. Strauss has a BEng and MEng in electrical engineering from the University of São Paulo, Brazil. She is a student member of the IEEE, IEEE Computer Society, ACM, and ACM SIGARCH and SIGMICRO.']}}, {'name': 'L. Ceze', 'bio': {'p': ['Luis Ceze is a PhD candidate in computer science at the University of Illinois, Urbana-Champaign. His research interests include memory system optimizations for large-window processors, speculative multiprocessor architectures, and compiler support for such systems. Ceze has a BEng and MEng in electrical engineering from the University of São Paulo, Brazil. He is a student member of the IEEE, ACM, and ACM SIGARCH and SIGMICRO.']}}, {'name': ' Wei Liu', 'bio': {'p': ['Wei Liu is a research scientist in the Department of Computer Science at the University of Illinois, Urbana-Champaign. His research interests include computer architecture, compilers for thread-level speculation, and software debugging and testing. Liu has a PhD in computer science from Tsinghua University. He is a member of the IEEE Computer Society and the ACM.']}}, {'name': 'S.R. Sarangi', 'bio': {'p': ['Smruti R. Sarangi is a PhD student in computer science at the University of Illinois, Urbana-Champaign. His research interests include thread-level speculation systems, power management schemes, and processor reliability. Sarangi has a BTech in computer science and engineering from the Indian Institute of Technology, Kharagpur, and an MS in computer science from UIUC. He is a student member of the IEEE.']}}, {'name': 'J. Tuck', 'bio': {'p': ['James Tuck is a PhD candidate in computer science at the University of Illinois, Urbana-Champaign. His research interests include multiprocessor architectures, compilation for speculative multiprocessor architectures, and memory system optimizations. Tuck has a BE in computer engineering from Vanderbilt University and an MS in electrical and computer engineering from UIUC. He is a student member of the IEEE, IEEE Computer Society, ACM, and ACM SIGARCH and SIGMICRO.']}}, {'name': 'J. Torrellas', 'bio': {'p': ['Josep Torrellas is a professor of computer science and Willett Faculty Scholar at the University of Illinois, Urbana-Champaign. He is also chair of the IEEE Technical Committee on Computer Architecture (TCCA). His research interests include multiprocessor computer architecture, thread-level speculation, low-power design, reliability, and debugga-bility. Torrellas has a PhD in electrical engineering from Stanford University. He is an IEEE Fellow and a member of the ACM.']}} %*Energy-Efficient Thread-Level Speculation %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1603500 %f/micro/g3j16jhd2gec4ilwoqsdxkpfax0sfevl.pdf %m8b82c11b0981deae4432ca02320989b9 %cmicro %@[{'name': 'M.A. Gomaa', 'affiliation': 'Purdue University', 'bio': {'p': ['Mohamed A. Gomaa is pursuing a PhD in computer engineering at Purdue University. His research interests include fault tolerance and computer system reliability, particularly architectural methods to incorporate transient-fault detection and recovery techniques in modern processors. Gomaa has a BS and an MS, both in computer engineering, from Cairo University, Egypt. He is a student member of the IEEE and the ACM.']}}, {'name': 'T.N. Vijaykumar', 'bio': {'p': ['T. N. Vijaykumar is an associate professor in the School of Electrical and Computer Engineering at Purdue University. His research interests include computer architecture, chip multiprocessor, low-power microarchitecture, hard- and soft-error tolerance, and high-speed network routers. Vijaykumar has a PhD in computer science from the University of Wisconsin-Madison, and a BE in electrical and electronics engineering and MSc in computer science both from Birla Institute of Technology and Science, Pilani, India.', 'Direct questions and comments about this article to Mohamed A. Gomaa, Purdue University, School of Electrical and Computer Engineering, Electrical Engineering Building, 465 Northwestern Ave., West Lafayette, IN 47907, gomaa@ecn.purdue.edu.', 'For further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/publications/dlib.']}} %*Opportunistic Transient-Fault Detection %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1603501 %f/micro/fdeshqgvy3y2zcixftzavdea0hmo4l8g.pdf %m091594c1f876bf8bb88c6da8a7b3486b %cmicro %@[{'name': 'S. Narayanasamy', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Satish Narayanasamy is a PhD candidate in the computer science department at the University of California, San Diego. His research interests include computer architecture, hardware and software support to improve programmer productivity, and system security. Narayanasamy has an MS from the University of California, San Diego, and a BE from Anna University, the College of Engineering, Guindy, Chennai, India, both in computer science. He is a member of ACM and IEEE.']}}, {'name': 'G. Pokam', 'bio': {'p': ['Gilles Pokam is a postdoctoral researcher in the Department of Computer Science and Engineering at the University of California, San Diego. His research interests include computer architecture and parallel programming models. Pokam has an MS in computer engineering from the Technical University of Berlin, Germany, and a PhD in computer science from the University of Rennes I, France. He is a member of IEEE and ACM.']}}, {'name': 'B. Calder', 'bio': {'p': ['Brad Calder is a professor of computer science and engineering at the University of California, San Diego. His research interests include computer architecture, compilers, and systems. Calder has a PhD in computer science from the University of Colorado, Boulder, and a BS in computer science and a BS in mathematics from the University of Washington. He is a recipient of an NSF Career Award and is a senior member of IEEE and member of ACM.', 'Direct questions and comments about this article to Brad Calder, University of California, San Diego, Department of Computer Science and Engineering, 9500 Gilman Dr., La Jolla, CA 92093-0404, calder@cs.ucsd.edu.']}} %*BugNet: Recording Application-Level Execution for Deterministic Replay Debugging %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1603502 %f/micro/cnjwvyuxq68yzedts1ca9ghkkftporhb.pdf %mf7b2eb2d8508649c80527dd6bffec93f %cmicro %@[{'name': ' Lin Tan', 'affiliation': 'University of Illinois, Urbana-Champaign', 'bio': {'p': ['Lin Tan is a PhD student in computer science at the University of Illinois, Urbana-Cham-paign. Her research interests include software debugging, applying machine learning techniques to improve software reliability, and specialized processors targeted to the domains of networking, communications, and security. Tan has a BS in computer science from Zhejiang University, China. She is a member of ACM.']}}, {'name': 'T. Sherwood', 'bio': {'p': ['Timothy Sherwood is an assistant professor in computer science at the University of Cal-ifornia, Santa Barbara. His research interests include program phase analysis (SimPoint) and specialized processors targeted to the domains of networking, communications, and securi-ty. Sherwood has an MS and a PhD in computer science from the University of California, San Diego, and a BS in computer engineering from the University of California, Davis. He is a member of IEEE and ACM.', 'Direct questions and comments about this article to Lin Tan, Department of Computer Science, University of Illinois, Urbana-Cham-paign, 201 N. Goodwin Ave., Urbana, IL 61801–2987, lintan2@cs.uiuc.edu.', 'For further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/publications/dlib.']}} %*Architectures for Bit-Split String Scanning in Intrusion Detection %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1603503 %f/micro/9cprav4doeycitrhbegdq3w25fztu1j0.pdf %mb9a024183977a100c5e37ea7a839b168 %cmicro %@[{'name': ' Qiang Wu', 'affiliation': 'Princeton University', 'bio': {'p': ["Qiang Wu is a PhD candidate in Princeton University's Computer Science Department. His research interests include power-aware microprocessor design and control. Wu has an MSc in electrical engineering from the University of Sydney. He is a student member of the IEEE and the ACM."]}}, {'name': 'M. Martonosi', 'bio': {'p': ['Margaret Martonosi is a professor of electrical engineering at Princeton University. Her research interests include computer architecture and hardware-software interfaces, with a focus on power-efficient systems and mobile computing. Martonosi has a BS from Cornell University and an MS and a PhD from Stanford University, all in electrical engineering. She is a senior member of the IEEE and a member of the ACM.']}}, {'name': 'D.W. Clark', 'bio': {'p': ['Douglas W. Clark is a professor of computer science at Princeton University. His research interests include computer architecture, low-power techniques, and clocking and timing in digital systems. Clark has a BS in engineering and applied science from Yale University and a PhD in computer science from Carnegie-Mellon University.']}}, {'name': 'V.J. Reddi', 'bio': {'p': ['Vijay Janapa Reddi is pursuing a PhD in the Department of Electrical and Computer Engineering at the University of Colorado at Boulder. His research interests include the design of dynamic code transformation systems for deployment in everyday computing environments. Reddi has a BSc in computer engineering from Santa Clara University.']}}, {'name': 'D. Connors', 'bio': {'p': ['Dan Connors is an assistant professor in the Department of Electrical and Computer Engineering and the Department of Computer Science at the University of Colorado at Boulder and the leader of the DRACO research group on runtime code transformation. His research interests include modern compiler optimization and multithreaded multicore architecture design. Connors has an MS and PhD in electrical engineering from the University of Illinois at Urbana-Champaign.']}}, {'name': ' Youfeng Wu', 'bio': {'p': ["Youfeng Wu is a principal engineer in Intel's Corporate Technology Group and leads a research team on multiprocessor compilation and dynamic binary optimizations. His research interests include codesigned power-efficient computer systems, binary and dynamic optimizations, and security and safety enhancement via compiler and binary tools. Wu has an MS and PhD in computer science from Oregon State University. He is a member of the ACM and the IEEE."]}}, {'name': ' Jin Lee', 'bio': {'p': ['Jin Lee is the president and CEO of Amicus Wireless Technology. He previously worked at Intel, where he participated in the work described in this article. His research interests include compiler technology, network processors, and semiconductor fabrication technologies. Lee has an MS and PhD in mechanical engineering from Stanford University.']}}, {'name': 'D. Brooks', 'bio': {'p': ['David Brooks is an assistant professor of computer science at Harvard University. His research interests include architectural-level power modeling and power-efficient design of hardware and software for embedded and high-performance computer systems. Brooks has a BS from the University of Southern California and an MA and PhD from Princeton University, all in electrical engineering. He is a member of the IEEE.', 'Direct questions and comments about this article to Qiang Wu, Dept. of Computer Science, Princeton University, Princeton, NJ 08544, jqwu@princeton.edu.', 'For further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/publications/dlib.\n']}} %*Dynamic-Compiler-Driven Control for Microprocessor Energy and Performance %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1603505 %f/micro/jz3cgdygcpam9kxpkfenq7ndqlszuhlw.pdf %m53f2066dc29b6ffd6508b42f079e55af %cmicro %@[{'name': ' Li Shang', 'affiliation': "Queen's University", 'bio': {'p': ["Li Shang is an assistant professor of electrical and computer engineering at Queen's University. His research interests include computer architecture, computer-aided design of ICs and systems, thermal and power modeling and optimization, and mobile computing. Shang has a PhD in electrical engineering from Princeton University. He is a member of the IEEE and ACM."]}}, {'name': 'L. Peh', 'bio': {'p': ['Li-Shiuan Peh is an assistant professor of electrical engineering at Princeton University. Her research interests include interconnection networks and parallel computer architectures. Peh has a BS from the National University of Singapore and a PhD from Stanford University, both in computer science. She is a member of the IEEE and ACM.']}}, {'name': 'A. Kumar', 'bio': {'p': ['Amit Kumar is a PhD student in the Department of Electrical Engineering at Princeton University. His research interests include interconnection networks and power- and ther-mal-aware system design. Kumar has a BTech from the Indian Institute of Technology and an MA from Princeton University, both in electrical engineering. He is a student member of the IEEE and ACM.']}}, {'name': 'N.K. Jha', 'bio': {'p': ['Niraj K. Jha is a professor of electrical engineering at Princeton University. His research interests include low-power hardware and software design, computer-aided design of ICs and systems, digital system testing and distributed computing. Jha has a BTech in electronics and electrical communication engineering from the Indian Institute of Tech-nology, an MS in electrical engineering from State University of New York at Stony Brook, and a PhD in electrical engineering from the University of Illinois. He is a fellow of the IEEE and ACM.', "For questions about this article, contact Li Shang, Dept. of Electrical and Computer Engineering, Queen's University, Kingston, ON, K7L 3N6, Canada, li.shang@queensu.ca.", 'For further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/publications/dlib.']}} %*Temperature-Aware On-Chip Networks %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1603506 %f/micro/8px40n2keakyj3jqrlhlsdrqdi7xmgof.pdf %m20d0888e7bf96df5aff3073fbc889ff2 %cmicro %@[{'name': 'R. Mateosian', 'affiliation': 'EMC/Documentum'} %*The future will soon be here %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1603507 %f/micro/wodspzqj4pyirtgrovn5k2lftxyqmbe9.pdf %m69354ec71e9011a26019650d3422d5e1 %cmicro %@[{'name': 'P. Emma', 'affiliation': 'IBM Corp.', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/33689/1603508/1603508-photo-1-small.gif', 'p': ['']}} %*How to write a patent %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1603508 %f/micro/ulm6v7lzrkaxfgoq5jih2iswhqkx9tft.pdf %maa746e86ede51c1f1c9e1e84a0e7b500 %cmicro %@[{'name': 'P. Bose', 'affiliation': 'IBM Corp.', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/34097/1624320/1624320-photo-1-small.gif', 'p': ['IEEE Micro']}} %*Workload characterization: A key aspect of microarchitecture design %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1624320 %f/micro/zzpoq1cfow2akbryamhuxlhvvieke0iy.pdf %m3a6c1547251e061d58413bb259844a6c %cmicro %@[{'name': 'S. Greenstein', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/34097/1624321/1624321-photo-1-small.gif', 'p': ['SHANE GREENSTEIN']}} %*Andy's acceleration and Moore's momentum %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1624321 %f/micro/pad7nh6kjtclzvc2fqu8is3uggyexdjs.pdf %m3ec4d23c8e672c2af75274a1d51e63c7 %cmicro %@[{'name': 'J. Sell', 'affiliation': 'Microsoft Corp.', 'bio': {'p': ['John Sell is an architect and silicon lead for Xbox at Microsoft. He has a background in processors and graphics as a senior fellow at Advanced Micro Devices, CTO of The 3DO Company, and a distinguished engineer and chief architect of the initial PowerPC architecture and chips for Apple in partnership with IBM and Motorola. Sell has an MS in electrical engineering and computer science from the University of California, Berkeley. He is a member of the ACM and Siggraph. Sell was program committee cochair for Hot Chips 17 and is the conference vice chair for Hot Chips 18.']}}, {'name': 'A.J. Smith', 'bio': {'p': ["Alan Jay Smith is a professor in the Computer Science Division of the Department of Electrical Engineering and Computer Sciences at University of California, Berkeley. His research interests include analyzing and modeling computer systems and devices, computer architecture, and operating systems. Smith has a PhD degree in computer science from Stanford University. He is a fellow of the IEEE, the ACM, and the American Association for the Advancement of Science. Smith received the 2006 Harry Goode award of the IEEE Computer Society and the 2003 A. A. Michelson Award of the Computer Measurement Group (CMG). He was program committee cochair for Hot Chips 17 and is currently chair of the conference's steering committee.", 'Direct questions and comments about this special issue to John Sell, Microsoft Corp., 1065 La Avenida, Mountain View, CA 94043, jsell@microsoft.com, or Alan Jay Smith, Computer Science Division, EECS Dept., University of California, Berkeley, CA 94720.']}} %*Guest Editors' Introduction: Hot Chips 17 %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1624322 %f/micro/ffnbodt2iwjyglscwo30lkzuvsp85nku.pdf %m5cdc0788c2975c1bf535183d19b03c9d %cmicro %@[{'name': 'M. Gschwind', 'affiliation': 'IBM', 'bio': {'p': ['Michael Gschwind is a microarchitect and design lead for a future system at IBM T.J. Watson Research Center, where he helped develop the concept for the Cell Broadband Engine Architecture, was a lead architect in defining the Synergistic Processor architecture, and developed the first Cell BE compiler. His research interests include power-efficient highperformance computer architecture and compilation techniques. Gschwind has a PhD in computer science from Technische Universität Wien. He is an IBM Master Inventor and a senior member of the IEEE.']}}, {'name': 'H.P. Hofstee', 'bio': {'p': ["H. Peter Hofstee is the chief scientist for the Cell BE and chief architect of Cell's synergistic processor element architecture at IBM Austin, and helped develop the concept for the Cell Broadband Engine Architecture. His research interests are future processor and system architectures and the broader use of the Cell. Hofstee has a Doctorandus in theoretical physics from the University of Groningen and a PhD in computer science from the California Institute of Technology."]}}, {'name': 'B. Flachs', 'bio': {'p': ['Brian Flachs is architect, microarchitect, and SPU team lead at IBM Austin. His research interests include in low-latency, high-frequency processors, computer architecture in general, image processing, and machine learning. Flachs has a PhD from Stanford University.']}}, {'name': 'M. Hopkins', 'bio': {'p': ['Martin Hopkins is retired after 30 years at IBM. He was a pioneer in the development of optimizing compilers using register coloring and multiple target architectures, which led to work on the instruction set for the IBM 801, the first RISC computer. He is an IBM Fellow.']}}, {'name': 'Y. Watanabe', 'bio': {'p': ['Yukio Watanabe is with Toshiba Corp., where he designs and develops high-performance microprocessors. Watanabe has a BE in electronic engineering and an ME in information science, both from Tohoku University, Sendai. While assigned to the STI design center in Austin, he helped develop the Cell processor.']}}, {'name': 'T. Yamazaki', 'bio': {'p': ['Takeshi Yamazaki is a member of the Microprocessor Development Division at Sony Computer Entertainment. His work includes processor and system architecture definition with a focus on scalability and controlability. Yamazaki has a BS and an MS in computer science and a PhD in electronics and information engineering from University of Tsukuba. He is a member of the IEEE.', 'For further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/publications/dlib.']}} %*Synergistic Processing in Cell's Multicore Architecture %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1624323 %f/micro/auzl7ubqw0ertdb6thyndkyj1sfohzi2.pdf %m0bd6357b03874c0ef7a18890fbff5c47 %cmicro %@[{'name': 'J. Andrews', 'affiliation': 'Microsoft Corp.', 'bio': {'p': ["Jeff Andrews is a CPU architect and project leader in Microsoft's Xbox Console Architecture Group, focusing on the Xbox 360 launch CPU. Andrews has a BS in computer engineering from the University of Illinois Urbana-Champaign."]}}, {'name': 'N. Baker', 'affiliation': 'Microsoft Corp., CA', 'bio': {'p': ['Nick Baker is the director of Xbox console architecture at Microsoft. His responsibilities include managing the Xbox Console Architecture, System Verification, and Test Software teams. Baker has an MS in electrical engineering from Imperial College London.']}} %*Xbox 360 System Architecture %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1624324 %f/micro/94jsjcaue28pnbuslyo7md1nrxbflfkq.pdf %maff2c8710df4d8b5c2ab4ed1440de367 %cmicro %@[{'name': 'B. Murmann', 'affiliation': 'Stanford University', 'bio': {'p': ['Boris Murmann is an assistant professor of electrical engineering at Stanford University. His research interests include mixed-signal IC design, with special emphasis on data converters and sensor interfaces. Murmann has a PhD in electrical engineering from the University of California, Berkeley. He is a member of the IEEE.', 'For further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/publications/dlib.']}} %*Digitally Assisted Analog Circuits %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1624325 %f/micro/ctzuojvgn47tesm0iyepxskdfw5rc9i3.pdf %m31b28db9950e128b4f9b695ea06e2eff %cmicro %@[{'name': 'V. Lindenstruth', 'affiliation': 'University of Heidelberg', 'bio': {'p': ['Volker Lindenstruth is an endowed chair of computer science and computer engineering at the University of Heidelberg. His research interests include computer architecture applications in natural science, particularly physics. Lindenstruth has a PhD in nuclear physics from the University of Frankfurt. He is a member of the German physics society.', 'For further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/publications/dlib.']}} %*An Extreme Processor for an Extreme Experiment %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1624326 %f/micro/4qoqaslyxpwmf5emba16t92dheuhpyrc.pdf %m371b4c16347a75095f0d74a756071bfd %cmicro %@[{'name': 'C. Gunn', 'affiliation': 'Luxtera Inc.', 'bio': {'p': ['Cary Gunn is cofounder and vice president of technology at Luxtera Inc. His research interests include silicon photonics and CMOS processing. Gunn has a PhD in electrical engineering from Caltech and a BS in applied physics from the US Air Force Academy. He is a member of IEEE LEOS.']}} %*CMOS Photonics for High-Speed Interconnects %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1624327 %f/micro/ivsdmpj0eennt27rfmxwgyh1asw6kb9c.pdf %mb41213d1561bf194733e849575cdb5f4 %cmicro %@[{'name': 'A. Agarwal', 'affiliation': 'Intel Corp.', 'bio': {'p': ['Amit Agarwal is a research engineer in circuit research lab at Intel. His research interests include low-power, high-performance, process-tolerant cache and register file design, low-power integrated device, circuit, architecture design, and reconfigurable architecture design with unreliable components for yield improvement. Agarwal has an MS and PhD in electrical and computer engineering from Purdue University and a BTech in electrical engineering from the Indian Institute of Technology, Kanpur, India. He is a member of the IEEE.']}}, {'name': 'S. Mukhopadhyay', 'bio': {'p': ['Saibal Mukhopadhyay is a PhD candidate in electrical and computer engineering at Purdue University. His research interests include the analysis and design of low-power and robust circuits using nanoscale CMOS and circuit design using double-gate transistors. Mukhopadhyay has a BE in electronics and telecommunication electrical engineering from Jadavpur University, Calcutta, India. He is a student member of the IEEE.']}}, {'name': 'A. Raychowdhury', 'bio': {'p': ['Arijit Raychowdhury is a PhD candidate in electrical and computer engineering at Purdue University. His research interests include device and circuit design for scaled silicon and nonsilicon devices. Raychowdhury has a BE in electronics and telecommunication engineering from Jadavpur University, Calcutta, India.']}}, {'name': 'K. Roy', 'bio': {'p': ['Kaushik Roy is the Roscoe H. George professor of electrical and computer engineering at Purdue University. His research interests include VLSI design and CAD for nanoscale silicon and nonsilicon technologies, low-power electronics for portable computing and wireless communications, circuit-level system integration testing and verification, and reconfigurable computing. Roy has a PhD in electrical and computer engineering from the University of Illinois at Urbana-Champaign and a BTech degree in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, India. He is a Fellow of the IEEE.']}}, {'name': 'C.H. Kim', 'bio': {'p': ['Chris H. Kim is an assistant professor in the electrical and computer engineering department at the University of Minnesota. His research interests include theoretical and experimental aspects of VLSI system design in nanoscale technologies. Kim has a PhD in electrical and computer engineering from Purdue University, and an MS in biomedical engineering and BS in electrical engineering from Seoul National University, Korea. He is a member of IEEE.']}} %*Leakage Power Analysis and Reduction for Nanoscale Circuits %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1624329 %f/micro/nib0ihu2ogeksz5pftmnycqmglwedrdj.pdf %m99cda93113208a18de95b087a03bdbd2 %cmicro %@[{'name': 'P.G. Emma', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/34097/1624330/1624330-photo-1-small.gif', 'p': ['PHILIP G. EMMA']}} %*The best patents of all %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1624330 %f/micro/3dsi68zbqagqzl5n2jcrjwxviknc190h.pdf %m822438dcfb29a16ecd38a202f8650083 %cmicro %@[{'name': 'P. Bose', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/34602/1650174/1650174-photo-1-small.gif', 'p': []}} %*Robust On-Chip Communication %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1650174 %f/micro/lxnqegjdx15fvsbhiiaobrfompgrt3c8.pdf %mf4887de7ce7a13e8174ac1c2125d821f %cmicro %@[{'name': 'S. Greenstein', 'affiliation': 'Kellog Graduate School of Management', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/34602/1650175/1650175-photo-1-small.gif', 'p': []}} %*Room for a Thousand Flowers to Bloom %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1650175 %f/micro/afrdyhckpgusberx3uzmx60d8lewwbn9.pdf %m97f3de5a932e5b6fbe31b000c7b72d41 %cmicro %@[{'name': 'F. Petrini', 'affiliation': 'Pacific Northwest National Laboratory', 'bio': {'p': ['Fabrizio Petrini is a laboratory fellow in the Applied Computer Science Group of the Computational Sciences and Mathematics Division at Pacific Northwest National Laboratory. His research interests include various aspects of supercomputers, such as high-performance interconnection networks and network interfaces, multicore processors, job-scheduling algorithms, parallel architectures, operating systems, and parallel-programming languages. Petrini has a Laurea and a PhD in computer science from the University of Pisa, Italy. He is a member of the IEEE Computer Society.']}}, {'name': 'O. Lysne', 'bio': {'p': ['Olav Lysne is a research director at Simula Research Laboratory and a professor in computer science at the University of Oslo. His early research was in the field of algebraic specification and term rewriting. His recent research interests include interconnects, focusing on effective routing, fault tolerance, and quality of service. In this field, he has served on program committees of several of the most renowned conferences, participated in a series of European projects, and published around 70 academic papers. Lysne received an MS and a DSc in computer science from the University of Oslo. He is a member of the IEEE.']}}, {'name': 'R. Brightwell', 'bio': {'p': ['Ron Brightwell is a principal member of the technical staff at Sandia National Laboratories. His research interests include high-performance scalable communication interfaces and protocols for system-area networks, and operating systems for massively parallel processing. Brightwell has a BS in mathematics and an MS in computer science from Mississippi State University. He is a member of the IEEE Computer Society and the ACM.']}} %*Guest Editors' Introduction: High-Performance Interconnects %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1650176 %f/micro/anzt2zseou5xrkbo6fqjubv8ps0ajwwm.pdf %m0256a052f0b60fe58cb7ce93e3da3012 %cmicro %@[{'name': 'M. Kistler', 'affiliation': 'IBM Austin Research Laboratory', 'bio': {'p': ['Michael Kistler is a senior software engineer in the IBM Austin Research Laboratory. His research interests include parallel and cluster computing, fault tolerance, and full-system simulation of high-performance computing systems. Kistler has an MS in computer science from Syracuse University.']}}, {'name': 'M. Perrone', 'bio': {'p': ["Michael Perrone is the manager of the IBM TJ Watson Research Center's Cell Solutions Department. His research interests include algorithmic optimization for the Cell processor, parallel computing, and statistical machine learning. Perrone has a PhD in physics from Brown University."]}}, {'name': 'F. Petrini', 'bio': {'p': ['Fabrizio Petrini is a laboratory fellow in the Applied Computer Science Group of the Computational Sciences and Mathematics Division at Pacific Northwest National Laboratory. His research interests include various aspects of supercomputers, such as high-performance interconnection networks and network interfaces, multicore processors, job-scheduling algorithms, parallel architectures, operating systems, and parallel-programming languages. Petrini has a Laurea and a PhD in computer science from the University of Pisa, Italy.', 'Direct questions and comments about this article to Fabrizio Petrini, Applied Computer Science Group, MS K7–90, Pacific Northwest National Laboratory, Richland, WA 99352, fabrizio.petrini@pnl.gov.']}} %*Cell Multiprocessor Communication Network: Built for Speed %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1650177 %f/micro/cpqsyobansvapejr4kt8biidgfwrkg2u.pdf %me81c3f564497cf8fd161f83a19db0f3d %cmicro %@[{'name': 'P. Balaji', 'affiliation': 'Ohio State University', 'bio': {'p': ['Pavan Balaji is a doctoral student in computer science and engineering at Ohio State Universi ty. His research interests include high-speed networks, efficient IP-based protocols (TCP, UDP, iWARP) and the sockets programming interface for cluster and grid computing. Balaji has a BTech in computer science and engineering from the Indian Institute of Technology at Madras. He is a student member of the IEEE.']}}, {'name': ' Wu-chun Feng', 'bio': {'p': ['Wu-chun Feng is an associate professor of computer science with a joint appointment in electrical and computer engineering at Virginia Tech. His research interests include highperformance networking and computing. He has a BS and an MS in computer engineering and a BS in music—all from Pennsylvania State University—and a PhD in computer science from the University of Illinois at Urbana-Champaign. He is a senior member of the IEEE.']}}, {'name': 'D.K. Panda', 'bio': {'p': ['Dhabaleswar K. Panda is a professor of computer science and engineering at Ohio State University. His research interests include parallel computer architecture, high-performance networking, and network-based computing. Panda has a PhD in computer engineering from the University of Southern California at Los Angeles. He is a senior member of the IEEE Computer Society and a member of ACM.', 'For/further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/publications/dlib.']}} %*Bridging the Ethernet-Ethernot Performance Gap %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1650178 %f/micro/krkxwvjchczmoqiuvwht9lx0obfi3ape.pdf %mc368b2a01a9a42eade18ee054d6dfd43 %cmicro %@[{'name': 'R. Brightwell', 'affiliation': 'Sandia National Laboratories', 'bio': {'p': ['Ron Brightwell is a principal member of the technical staff at Sandia National Laboratories. His research interests include high-performance scalable communication interfaces and protocols for system-area networks and operating systems for massively parallel processing. Brightwell has a BS in mathematics and an MS in computer science from Mississippi State University. He is a member of the IEEE Computer Society and the ACM.']}}, {'name': 'K.T. Pedretti', 'bio': {'p': ['Kevin T. Pedretti is a senior member of the technical staff at Sandia National Laboratories. His research interests include low-latency, high-throughput hardware for MPI, and lightweight compute node operating systems. Pedretti has a BS and an MS in electrical and computer engineering from the University of Iowa. He is a member of the IEEE and the IEEE Computer Society.']}}, {'name': 'K.D. Underwood', 'bio': {'p': ['Keith D. Underwood is a senior member of the technical staff at Sandia National Laboratories. His research interests include reconfigurable computing, the role of FPGAs in high-performance computing, and network (and network interface) architectures for highperformance computing. Underwood has a BS and a PhD in computer engineering from Clemson University.']}}, {'name': 'T. Hudson', 'bio': {'p': ['Trammell Hudson is a senior partner at OS Research, a high-performance and embedded-system firm. His primary research interests are low latency, OS bypass message passing systems, and embedded Linux systems. Hudson has a BS in computer science from Tulane University. He is a member of AUVSI.', 'For further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/publications/dlib.']}} %*SeaStar Interconnect: Balanced Bandwidth for Scalable Performance %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1650179 %f/micro/vp1uc2y0t3hih7ricfnrt4vxsogyodsm.pdf %m6852be43750957a41ce68aa14d52f758 %cmicro %@[{'name': 'C. Minkenberg', 'affiliation': 'IBM Zurich Research Laboratory', 'bio': {'p': ['Cyriel Minkenberg is a research staff member at the IBM Zurich Research Laboratory, where he is responsible for the architecture and performance evaluation of the Osmosis crossbar scheduler. His research interests include switch architectures, networking protocols, performance modeling, and simulation. Minkenberg has a PhD in electrical engineering from Eindhoven University of Technology, the Netherlands.']}}, {'name': 'F. Abel', 'affiliation': 'IBM Zurich Res. Lab., Ruschlikon', 'bio': {'p': ["François Abel is a research staff member at the IBM Zurich Research Laboratory, where he is responsible for the architecture and implementation of the Osmosis scheduler. His research interests include the architecture and VLSI design of high-speed, low-latency switching systems. Abel has a BS in engineering from the École Nationale d'Ingénieurs, Belfort, France, and an MS in electrical engineering from the École Supérieure d'Ingénieurs, Marseille, France. He is a member of the IEEE."]}}, {'name': 'P. Muller', 'affiliation': 'IBM Zurich Res. Lab., Ruschlikon', 'bio': {'p': ['Peter Müller is a research staff member at the IBM Zurich Research Laboratory. His research interests include distributed computing systems architecture, communications and interconnect technology, device physics, nanoscience, and computer modeling. Mueller has a diploma in computer science from Brugg University. He is a member of the IEEE, the ECS, and the SPS.']}}, {'name': 'R. Krishnamurthy', 'affiliation': 'IBM Zurich Res. Lab., Ruschlikon', 'bio': {'p': ['Raj Krishnamurthy is a visiting scientist at the IBM Zurich Research Laboratory, where he works on the US Department of Energy Osmosis program and the DARPA HPCS program. His research interests include operating systems, computer architecture, and system implementation complexity. Krishnamurthy has a PhD from the Georgia Institute of Technology.']}}, {'name': 'M. Gusat', 'affiliation': 'IBM Zurich Res. Lab., Ruschlikon', 'bio': {'p': ['Mitchell Gusat is a researcher at the IBM Zurich Research Laboratory. His research interests include scheduling, flow control, and congestion management for interconnection networks. Gusat has an MS in electrical engineering from the University of Timisoara, Romania, and in computer engineering from the University of Toronto. He is a member of the IEEE and the ACM.']}}, {'name': 'P. Dill', 'affiliation': 'IBM Zurich Res. Lab., Ruschlikon', 'bio': {'p': ['Peter Dill is a researcher at the IBM Zurich Research Laboratory. His research interests include design of communications and networking system prototypes and design of high-speed and RF printed circuit boards. Dill has a diploma as a physics technician from the Swiss Federal Institute.']}}, {'name': 'I. Iliadis', 'affiliation': 'IBM Zurich Res. Lab., Ruschlikon', 'bio': {'p': ['Ilias Iliadis is a research staff member at the IBM Zurich Research Laboratory. His research interests include performance evaluation of computer communication networks, traffic control and engineering for networks, switch architectures, and stochastic systems. Iliadis has a PhD in electrical engineering from Columbia University. He is a senior member of the IEEE and a member of IFIP WG 6.3, Sigma Xi, and the Technical Chamber of Greece.']}}, {'name': 'R. Luijten', 'affiliation': 'IBM Zurich Res. Lab., Ruschlikon', 'bio': {'p': ['Ronald Luijten manages the server interconnect fabrics team at the IBM Zurich Research Laboratory, where he is working on the Osmosis optical switch demonstrator. His research interests include high-speed switching system design, including electronic crossbars and alloptical switches, and high-speed, high-density electro-optical interconnects. Luijten has an MSc in electronic engineering from the Eindhoven University of Technology.']}}, {'name': 'B.R. Hemenway', 'bio': {'p': ['B. Roe Hemenway manages Optical Physics Research at Corning Inc. His research interests include high-power fiber lasers and amplifiers, photonic crystal structures, scalable integrated WDM networks, MOEM devices silicon optical modulators, and high-speed laser diodes. Hemenway has a PhD from Stanford University. He is a member of the Optical Society of America and IEEE.']}}, {'name': 'R. Grzybowski', 'bio': {'p': ['Richard Grzybowski is the research director of systems engineering and program management at Corning Inc. His research interests include optical interconnect networks for high-performance supercomputers, and system applications for operation in harsh environments. Grzybowski has a PhD in electrical engineering, electromagnetics and antenna design from the University of Connecticut. He is a senior member of the IEEE and president of the Finger Lakes Chapter of the International Council on Systems Engineering (INCOSE).']}}, {'name': 'E. Schiattarella', 'bio': {'p': ['Enrico Schiattarella is a postdoctoral researcher at Politecnico di Torino, Italy. His research interests include high-performance switching architectures and interconnection networks. Schiattarella has a PhD in electronics and communication engineering.', 'Direct questions and comments about this article to Cyriel Minkenberg, IBM Research GmbH, Zurich Research Laboratory, CH-8803 Rueschlikon, Switzerland, sil@zurich.ibm.com.']}} %*Designing a Crossbar Scheduler for HPC Applications %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1650180 %f/micro/ntrjvmkvfgm0e1hqw5xup9yelk36jrzy.pdf %m67a61d13b34301047f3c6a9b38041174 %cmicro %@[{'name': ' Li Zhao', 'affiliation': 'University of California, Riverside', 'bio': {'p': ['Li Zhao is a senior engineer in the System Technology Laboratory at Intel Corp. She has $a$ PhD in computer science from the University of California, Riverside. Her research interests include computer architecture, network computing, and performance evaluation. She is a member of the IEEE.']}}, {'name': ' Yan Luo', 'affiliation': 'California Univ., Riverside, CA', 'bio': {'p': ['Yan Luo is an assistant professor in the Department of Electrical and Computer Engineering at University of Massachusetts, Lowell. His research interests include network processor architecture, Internet router and Web server, network security, and performance evaluation. Luo has a PhD in computer science from the University of California, Riverside. He is a member of the IEEE and ACM.']}}, {'name': 'L.N. Bhuyan', 'affiliation': 'California Univ., Riverside, CA', 'bio': {'p': ['Laxmi N. Bhuyan is a professor of computer science and engineering at the University of California, Riverside. His research interests include network processor architecture, Internet routers, and parallel and distributed processing. Bhuyan has a PhD from Wayne State University. He is a Fellow of the IEEE, the ACM, and the American Association for the Advancement of Science.']}}, {'name': 'R. Iyer', 'bio': {'p': ['Ravi Iyer is a principal engineer in the Systems Technology Laboratory at Intel an associate editor for IEEE Transactions on Parallel and Distributed Systems. His research interests include computer architecture, server design, network protocols and acceleration, workload characterization, and performance evaluation, his current emphasis is on large-scale CMP architectures and technologies. He has a PhD in computer science from Texas A&M University.', 'Direct questions and comments about this article to Li Zhao, Intel Corp., 2111 NE 25th Ave., M/S JF2–58, Hillsboro, OR 97124, li.zhao@intel.com.']}} %*A Network Processor-Based, Content-Aware Switch %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1650181 %f/micro/ffjlnvz3reciyxoza1wxsnkhqwp7cok9.pdf %m39ba3dbc7e6e13fd9ea7b538ddba50f8 %cmicro %@[{'name': 'R. Mateosian'} %*More on Old Topics %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1650183 %f/micro/sx53efjwdyhlmwkqrus2ynn7ovbtgvq9.pdf %m70641e7536d7a2224332abab75c3819e %cmicro %@[{'name': 'R. Stern', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/34602/1650184/1650184-photo-1-small.gif', 'p': []}} %*Court Dismisses "Copyright Champion's" Source Code Copyright Suit %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1650184 %f/micro/eixu5hrqgblwjpblic2m0h1m37utp96j.pdf %m092424eae69255139fcb3ad815b1bd5d %cmicro %@[{'name': 'P.G. Emma', 'affiliation': 'IBM T.J. Watson Research Center'} %*Patent Claims Revisited: Examiners and Trolls %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1650187 %f/micro/lp6iaxz358mdsgfo0vjhqnt7suw1ltq9.pdf %m59b06205de5fe25431c1ca71a1e66452 %cmicro %@[{'name': 'P. Bose', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/35278/1677496/1677496-photo-1-small.gif', 'p': []}} %*Pre-Silicon Modeling and Analysis: Impact On Real Design %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1677496 %f/micro/sze8cw1zrhcd7fmn4h0qwx6knkql5ijy.pdf %m447d882a8cc5438214cd519e09a239a6 %cmicro %@[{'name': 'S. Greenstein', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/35278/1677497/1677497-photo-1-small.gif', 'p': []}} %*Legislating Entrepreneurship: An Oxymoron? %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1677497 %f/micro/qwashtz2ezvcuigcm89bqln1ijg4pwry.pdf %mc6f978e66013f01ad13288a08b967f9c %cmicro %@[{'name': 'T. Sherwood', 'affiliation': 'University of California, Santa Barbara', 'bio': {'p': ['Timothy Sherwood is an assistant professor in the Computer Science Department at University of California, Santa Barbara. His primary research interests are in architectures and techniques that allow the continuous streaming analysis of systems, including network processing, security accelerators, and methods for program phase analysis and introspection. He has a BS from University of California, Davis, and an MS and PhD in computer science from University of California, San Diego. He is a member of the ACM and the IEEE.']}}, {'name': ' Joshua J. Yi', 'bio': {'p': ['Joshua J. Yi is a performance analyst at Freescale Semiconductor in Austin, Texas. His research interests include high-performance computer architecture, simulation, bench-marking, low-power design, and reliable computing. He has a BS, an MS, and a PhD—all in electrical engineering—from the University of Minnesota in Minneapolis. He is a member of the IEEE and the IEEE Computer Society.']}} %*Guest Editors' Introduction: Computer Architecture Simulation and Modeling %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1677498 %f/micro/hxcca4ydqmgivz0f3lbt2jdq8oiewypl.pdf %m3fd2565a9e94e3b8e3094d20dc91f928 %cmicro %@[{'name': 'A.R. Alameldeen', 'affiliation': 'Intel Corporation', 'bio': {'p': ['Alaa R. Alameldeen is a research scientist in the Oregon Microarchitecture Lab at Intel Corporation in Hillsboro, Oregon. His research interests include memory and cache system design for multiprocessors and chip multiprocessors, and performance analysis of multithreaded workloads. He received a BSc and an MSc in computer science from Alexandria University, Egypt, and an MSc and a PhD from the University of Wisconsin-Madison, also in computer science.']}}, {'name': 'D.A. Wood', 'bio': {'p': ['David A. Wood is a professor in both the Computer Sciences and Electrical and Computer Engineering departments at the University of Wisconsin-Madison. Along with Mark Hill, he leads the Wisconsin Multifacet project (http://www.cs.wisc.edu/multifacet), which explores techniques for improving the availability, designability, programmability, and performance of commercial multiprocessor servers. His research interests include chip multiprocessors and transactional memory. Wood has a PhD in computer sciences from the University of California, Berkeley. He is a fellow of the IEEE and the ACM, and a member of the IEEE Computer Society.']}} %*IPC Considered Harmful for Multiprocessor Workloads %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1677499 %f/micro/5wq8bd2pfjzumid1uoni0xfvcbr3shge.pdf %m82a105fdb3b82e5cacb11225c0733b73 %cmicro %@[{'name': 'T.F. Wenisch', 'affiliation': 'Carnegie Mellon University', 'bio': {'p': ['Thomas F. Wenisch is a PhD candidate in electrical and computer engineering at Carnegie Mellon University. His research interests include multiprocessor computer architecture, memory system design, and computer system performance evaluation methodology. Wenisch has an MS from Carnegie Mellon and a BS from the University of Rhode Island, both in computer engineering. He is a student member of the IEEE and ACM.']}}, {'name': 'R.E. Wunderlich', 'affiliation': 'Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA', 'bio': {'p': ['Roland E. Wunderlich is a PhD candidate in electrical and computer engineering at Carnegie Mellon University. His research interests focus on the application of statistical modeling techniques to computer architecture and automated software tuning. Wunderlich has a BS in computer engineering from Rutgers University and an MS from Carnegie Mellon. He is a student member of the IEEE and ACM.']}}, {'name': 'M. Ferdman', 'affiliation': 'Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA', 'bio': {'p': ['Michael Ferdman is a PhD candidate in electrical and computer engineering at Carnegie Mellon University. His research interests include computer architecture with an emphasis on proactive memory system design. Ferdman has a BS in computer science, and a BS and an MS in electrical and computer engineering from Carnegie Mellon. He is a student member of the ACM.']}}, {'name': 'A. Ailamaki', 'bio': {'p': ['Anastassia Ailamaki is an assistant professor of computer science and a Sloan Research Fellow at Carnegie Mellon University. Her research interests focus on database systems and applications, with an emphasis on database system behavior on modern processor hardware and disks. Ailamaki has a BSc in computer engineering from the Polytechnic School of the University of Patra, Greece, an MSc in computer engineering from the Technical University of Crete, Greece, an MSc in computer science from the University of Rochester, New York, and a PhD in computer science from the University of Wisconsin-Madison. She is a member of the IEEE and the ACM.']}}, {'name': 'B. Falsafi', 'bio': {'p': ['Babak Falsafi is an associate professor of electrical and computer engineering and a Sloan Research Fellow at Carnegie Mellon University, His research interests include computer architecture with an emphasis on high-performance memory systems, architectural support for gigascale integration, and computer system performance evaluation tools. Falsafi has a PhD in computer science from the University of Wisconsin. He is a member of the IEEE and the ACM.']}}, {'name': 'J.C. Hoe', 'bio': {'p': ['James C. Hoe is an associate professor of electrical and computer engineering at Carnegie Mellon University. His research interests include computer architecture and high-level hardware description and synthesis. Hoe has a PhD in electrical engineering and computer science from MIT. He is a member of the IEEE and ACM.']}} %*SimFlex: Statistical Sampling of Computer System Simulation %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1677500 %f/micro/uvxzo562uc7haylzdpwgr0feyrgoviam.pdf %m38c8eb0b012f375b9adf9ed8de12d53a %cmicro %@[{'name': 'M. Van Biesbrouck', 'affiliation': 'University of California, San Diego', 'bio': {'p': ['Michael Van Biesbrouck is a PhD student at the University of California, San Diego. His research interests include simulation methodology for computer architecture studies and the interaction between computer architecture and operating systems. He obtained his BMath and MMath in computer science from the University of Waterloo. He is a student member of IEEE.']}}, {'name': 'B. Calder', 'affiliation': 'California Univ., CA', 'bio': {'p': ['Brad Calder is a professor of computer science and engineering at the University of California, San Diego, and an architect at Microsoft in the Windows Core operating system. His research interests focus on understanding program behavior toward software and hardware optimization. He cofounded ACM Transactions on Architecture and Code Optimization, and the International Conference on Code Generation and Optimization. He is a cofounder of three startups— TracePoint (×86 binary instrumentation tools), Entropia (desktop grid computing), and BitRaker (ARM binary instrumentation tools). He has a BS in computer science and a BS in mathematics from the University of Washington and a PhD in computer science from University of Colorado, Boulder. He is a senior member of IEEE.']}}, {'name': 'L. Eeckhout', 'bio': {'p': ['Lieven Eeckhout is a postdoctoral fellow of the Fund for Scientific Research Flanders (Belgium) affiliated with Ghent University. His research interests include computer architecture and performance modeling. He has a PhD in computer science and engineering from Ghent University. He is a member of the IEEE.', 'For further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/publications/dlib.']}} %*Efficient Sampling Startup for SimPoint %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1677501 %f/micro/ihzna2ef0yh5cgwt9pvjnxy8surl7wlo.pdf %mca760ae7046c58392114a6dfcaf1e8bf %cmicro %@[{'name': 'S. Gurumurthi', 'affiliation': 'University of Virginia', 'bio': {'p': ['Sudhanva Gurumurthi is an assistant professor in the Computer Science Department of the University of Virginia. His research interests include computer architecture and storage systems. Gurumurthi has a PhD from Pennsylvania State University and a BE from the College of Engineering, Guindy, Anna University, India, both in computer science and engineering. He is a member of the ACM.']}}, {'name': ' Youngjae Kim', 'bio': {'p': ['Youngjae Kim is a graduate student in the Computer Science and Engineering Department of Pennsylvania State University. His research interests include operating systems and power and thermal management of storage systems. Kim has a BS from Sogang University and an MS from Korea Advanced Institute of Science and Technology.']}}, {'name': 'A. Sivasubramaniam', 'bio': {'p': ['Anand Sivasubramaniam is a professor in the Computer Science and Engineering Department of Pennsylvania State University. His research interests include computer architecture, operating systems, parallel and distributed computing, and performance evaluation. Sivasubramaniam has a BTech from the Indian Institute of Technology, Madras, and an MS and a PhD from Georgia Institute of Technology, all in computer science. He is a member of the IEEE and the ACM.']}} %*Using STEAM for Thermal Simulation of Storage Systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1677502 %f/micro/ftqtn08w6sga4pjuqcsmdhjiubvliyzx.pdf %m580c9f428b178b8277d14fb31aaa27af %cmicro %@[{'name': 'N.L. Binkert', 'affiliation': 'University of Michigan', 'bio': {'p': ['Nathan L. Binkertis a researcher at Hewlett-Packard Laboratories and principal developer of M5. His research interests include system architecture, networking, operating systems, and simulation. As an intern at Compaq VSSAD, he was involved in the initial development of the ASIM simulator, currently in use at Intel. Binkert has a BSE in electrical engineering and an MSE and a PhD in computer science and engineering, all from the University of Michigan.']}}, {'name': 'R.G. Dreslinski', 'affiliation': 'Comput. Sci. & Eng., Michigan Univ., MI', 'bio': {'p': ["Ronald G. Dreslinskiis a PhD candidate in the Electrical Engineering and Computer Science Department at the University of Michigan, and the main developer of M5's memory system. His research interests include multiprocessor cache organization, memory design, and 3D wafer stacked memories. Dreslinski has a BSE in electrical engineering, a BSE in computer engineering, and an MSE in computer science and engineering, all from the University of Michigan."]}}, {'name': 'L.R. Hsu', 'affiliation': 'Comput. Sci. & Eng., Michigan Univ., MI', 'bio': {'p': ["Lisa R. Hsuis a PhD candidate in the EECS Department at the University of Michigan, and was the developer of M5's Ethernet network interface model. Her research interests include chip multiprocessing, memory hierarchy design, and cache placement algorithms. Hsu has a BSE in electrical engineering from Princeton University and an MSE in computer science and engineering from the University of Michigan."]}}, {'name': 'K.T. Lim', 'affiliation': 'Comput. Sci. & Eng., Michigan Univ., MI', 'bio': {'p': ["Kevin T. Limis pursuing a PhD in the EECS Department at the University of Michigan, and is the developer of M5's detailed CPU model. His research interests include simulators, simulation techniques, and microarchitecture. Lim has a BSE in computer engineering and an MSE in computer science and engineering, both from the University of Michigan."]}}, {'name': 'A.G. Saidi', 'affiliation': 'Comput. Sci. & Eng., Michigan Univ., MI', 'bio': {'p': ['Ali G. Saidiis a PhD candidate in the EECS Department at the University of Michigan, and wrote much of the platform code for Linux full-system simulation of Alpha and Sparc. His research interests include architecture and OS interaction, networking, and networking performance analysis. Saidi has a BS in electrical engineering from the University of Texas at Austin and an MSE in computer science and engineering from the University of Michigan.']}}, {'name': 'S.K. Reinhardt', 'affiliation': 'Comput. Sci. & Eng., Michigan Univ., MI', 'bio': {'p': ['Steven K. Reinhardtis an associate professor in the EECS Department at the University of Michigan, a managing engineer at Reservoir Labs, Inc., and a principal developer of M5. His research interests include computer systems architecture, networking, and system simulation. Reinhardt has a BS from Case Western Reserve University and an MS from Stanford University, both in electrical engineering, and a PhD in computer science from the University of Wisconsin-Madison. While at Wisconsin, he was the principal developer of the Wisconsin Wind Tunnel parallel architecture simulator.']}} %*The M5 Simulator: Modeling Networked Systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1677503 %f/micro/bvp1gucbkvjwtml96qskue3admrew02x.pdf %m3928d6f6b4b5c488b3267a8df0480cde %cmicro %@[{'name': ' Yong-Joon Park', 'affiliation': 'Iowa State University', 'bio': {'p': ['Yong-Joon Park is a PhD student in the Department of Electrical and Computer Engineering at Iowa State University. His research interests include microprocessor design and computer and network system security. Park has a BS in electrical and computer engineering from Iowa State University.']}}, {'name': ' Zhao Zhang', 'bio': {'p': ['Zhao Zhang is an assistant professor of computer engineering at Iowa State University. His research interests include computer architecture and parallel and distributed systems. Zhang has a PhD in computer science from the College of William and Mary. He is a member of the IEEE and the ACM.']}}, {'name': ' Gyungho Lee', 'bio': {'p': ['Gyungho Lee is a professor of computer engineering at the University of Illinois at Chicago. His research interests include computer architecture, microporcessor design, and computer and network system security. Lee has a PhD in Computer Science from University of Illinois at Urbana-Champaign. He is editor of IEEE Transactions on Parallel and Distributed Systems and the Journal of Parallel and Distributed Computing.']}} %*Microarchitectural Protection Against Stack-Based Buffer Overflow Attacks %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1677505 %f/micro/lucy6j3ramdbiq047zsvz2njwpog1r98.pdf %m9de092d95490f1be109b5cc022b55044 %cmicro %@[{'name': 'J. Alastruey', 'affiliation': 'University of Zaragoza', 'bio': {'p': ['Jesús Alastruey is an assistant professor and a PhD candidate in the Informática e Ingeniería de Sistemas (IIS) Department at the University of Zaragoza (UZ), Spain. His research interests include memory hierarchy and processor microarchitecture. Alastruey has an MS in telecommunications from UZ.']}}, {'name': 'J.L. Briz', 'affiliation': 'Informatica e Ingenieria de Sistemas Dept., Zaragoza Univ.', 'bio': {'p': ["José Luis Briz is an associate professor in the IIS Department at UZ. His research interests include memory hierarchy and processor microarchitecture. He has MS degrees in geology and computer science and a PhD in computer engineering, all from UZ. Briz is a member of the IEEE, the ACM, and UZ's Instituto de Investigación en Ingeniería de Aragón (I3A)."]}}, {'name': 'P. Ibanez', 'affiliation': 'Informatica e Ingenieria de Sistemas Dept., Zaragoza Univ.', 'bio': {'p': ['Pablo Ibáñez is an associate professor in the IIS Department at UZ. His research interests include memory hierarchy, processor microarchitecture, and parallel computer architecture. He has an MS in computer science from Universitat Politècnica de Catalunya and a PhD in computer engineering from UZ. Ibáñez is a member of the IEEE, the ACM, and the 13A.']}}, {'name': 'V. Vinals', 'affiliation': 'Informatica e Ingenieria de Sistemas Dept., Zaragoza Univ.', 'bio': {'p': ['Victor Viñals is a professor in the IIS Department at UZ. His research interests include processor microarchitecture, memory hierarchy, and parallel computer architecture. He has an MS in telecommunications and a PhD in computer science, both from Universitat Politècnica de Catalunya, where he also served on the faculty. Viñals is a member of the IEEE, the ACM, and the 13A.', 'For further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/publications/dlib.']}} %*Software Demand, Hardware Supply %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1677506 %f/micro/o5b9gyc2ltsp1jm0aquwgyxki7n3wdri.pdf %m338af490af76528e12a8b1223564beb8 %cmicro %@[{'name': 'R. Mateosian'} %*Old and New %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1677507 %f/micro/zlna591wjvdpnowksphcibxfscggy2u0.pdf %mdc4daa86ac6256f1972a8109776ee40e %cmicro %@[{'name': 'P.G. Emma', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/35278/1677508/1677508-photo-1-small.gif', 'p': ['Philip G. Emma pemma@us.ibm.com']}} %*The Mechanics of Filing a Patent %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1677508 %f/micro/kkndjgwyc7oallwu6vmq5dfu0arqoecs.pdf %mfc7b02b5810a450fe25f13ce6e09d229 %cmicro %@[{'name': 'P. Bose', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/36071/1709815/1709815-photo-1-small.gif', 'p': ['IEEE Micro']}} %*Designing reliable systems with unreliable components %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1709815 %f/micro/apaxlyvibmcsmtwtb5q9u2foie431shn.pdf %m3fdb4e892d16ed28cc1a0699af891a59 %cmicro %@[{'name': 'S. Greenstein', 'affiliation': 'Kellogg Graduate School of Management', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/36071/1709816/1709816-photo-1-small.gif', 'p': ['Shane Greenstein greenstein@kellogg.northwestern.edu']}} %*Ubiquitous clicks and complements %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1709816 %f/micro/4g5gvhljhmqpe1vfzsfbqsrt379olda6.pdf %m1830967dfaf191206a51aa63aef70294 %cmicro %@[{'name': 'R. Stern', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/36071/1709817/1709817-photo-1-small.gif', 'p': []}} %*New Jersey federal court holds Qualcomm's unFRANDly acts no antitrust violation %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1709817 %f/micro/exws9bojghpcf8sugnyea0ihri5qdo1m.pdf %mc8c7f96edcafdf2790f0e70a71bbca1a %cmicro %@[{'name': 'E.H. Neto', 'affiliation': 'Universidade Estadual do Rio Grande do Sul', 'bio': {'p': ['Egas Henes Neto is an undergraduate student in digital systems engineering at the Universidade Estadual do Rio Grande do Sul, Guaíba, Brazil, where he is a member of the research group in micro-and nanoelectronics. His research interests include fault modeling, fault tolerance techniques, and radiation effects on digital circuits.']}}, {'name': 'I. Ribeiro', 'affiliation': 'Univ. Estadualdo Rio Grande do Sul', 'bio': {'p': ['Ivandro Ribeiro is an undergraduate student in digital systems engineering at the Universidade Estadual do Rio Grande do Sul and a member of the research group in micro-and nanoelectronics. His research interests include fault modeling, fault tolerance techniques, and radiation effects on digital circuits.']}}, {'name': 'M. Vieira', 'affiliation': 'Univ. Estadualdo Rio Grande do Sul', 'bio': {'p': ['Michele Vieira is an undergraduate student in digital systems engineering at the Universidade Estadual do Rio Grande do Sul, where she is a member of the research group in micro-and nanoelectronics. Her research interests include fault modeling, fault tolerance techniques, and radiation effects on digital circuits.']}}, {'name': 'G. Wirth', 'affiliation': 'Univ. Estadualdo Rio Grande do Sul', 'bio': {'p': ['Gilson Wirth is a professor in the Computer Engineering Department at the Universidade Estadual do Rio Grande do Sul, and head of the research group in micro and nanoelectronics. His research interests include low-frequency noise, radiation effects on circuits and devices, and analog and mixed-signal circuit design. He has a BSEE and an MSc from the Federal University of Rio Grande do Sul and a Dr.-Ing. in electrical engineering from the University of Dortmund, Dortmund, Germany. Wirth is a member of the IEEE, the IEEE Electron Devices Society, and the IEEE Circuits and Systems Society.']}}, {'name': 'F.L. Kastensmidt', 'bio': {'p': ['Fernanda Lima Kastensmidt is a professor in the Computer Science Department at the Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil. Her research interests include VLSI testing and design, fault effects, fault tolerance techniques, and programmable architectures. She has a BS in electrical engineering and an MS and a PhD in computer science and microelectronics from the Federal University of Rio Grande do Sul. She is a member of the IEEE.']}} %*Using Bulk Built-in Current Sensors to Detect Soft Errors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1709818 %f/micro/8ldcnlch5dgvxzpphfqjymsatsrgbznu.pdf %mc62106bdb5084bb1745233163f8062b9 %cmicro %@[{'name': 'K. Nepal', 'affiliation': 'Brown University', 'bio': {'p': ['Kundan Nepalis pursuing a PhD in electrical and computer engineering in the Division of Engineering of Brown University. His research interests include fault-tolerant computing for nanoarchitectures, VLSI system design, and computer-aided design of digital integrated circuits. Nepal has a BS in electrical engineering from Trinity College, Hartford, and an MSEE from the University of Southern California. He is a student member of the IEEE.']}}, {'name': 'R.I. Bahar', 'affiliation': 'Brown Univ., Providence, RI', 'bio': {'p': ['R. Iris Baharis an associate professor in the Division of Engineering of Brown University. Her research interests include computer architecture, computer-aided design for synthesis, verification, and low-power applications, and design, test, and reliability for nanoscale systems. Bahar has BS and MS degrees in computer engineering from the University of Illinois, Urbana-Champaign, and a PhD in electrical and computer engineering from the University of Colorado, Boulder. She is a member of the IEEE.']}}, {'name': 'J. Mundy', 'affiliation': 'Brown Univ., Providence, RI', 'bio': {'p': ['Joseph Mundyis a professor of engineering in the Engineering Division of Brown University. His research interests include video-based object recognition and nanoarchitecture. Mundbyhas a BS and a PhD in electrical engineering from Rensselaer Polytechnic Institute.']}}, {'name': 'W.R. Patterson', 'affiliation': 'Brown Univ., Providence, RI', 'bio': {'p': ['William R. Pattersonis a senior lecturer and senior research engineer in the Electrical Sciences Group of the Division of Engineering of Brown University. His research interests include low-power analog circuit design for biomedical applications, probabilistic-logic circuits and architectures, and geological-spectroscopy instrumentation. Patterson has an ScB in physics and an ScM in electrical engineering, both from Brown University. He is a member of the IEEE.']}}, {'name': 'A. Zaslavsky', 'affiliation': 'Brown Univ., Providence, RI', 'bio': {'p': ['Alexander Zaslavskyis an associate professor of engineering and physics at Brown University. His research interests include tunneling semiconductor physics and devices, alternative device materials such as carbon nanotubes and germanium-on-insulator, flexible electronics, and CMOS-compatible probabilistic computing. Zaslavsky has an AB in physics from Harvard University and a PhD in electrical engineering from Princeton University. He is a member of the American Physical Society.']}} %*MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1709819 %f/micro/kbg1rkuz4qshp3e0fnoxwbayfm6cpm7u.pdf %ma3f6494b1fe987a06ec098372d95c3d2 %cmicro %@[{'name': 'R. Teodorescu', 'affiliation': 'University of Illinois at Urbana-Champaign', 'bio': {'p': ['Radu Teodorescu is a PhD candidate in the Computer Science Department of the University of Illinois at Urbana-Champaign. His research interests include processor design for reliability, debuggability, and variability tolerance. Teodorescu has a BS in computer science from the Technical University of Cluj-Napoca, Romania, and an MS in computer science from University of Illinois at Urbana-Champaign. He is a student member of the IEEE.']}}, {'name': ' Jun Nakano', 'affiliation': 'Dept. of Comput. Sci., Illinois Univ., Urbana, IL', 'bio': {'p': ['Jun Nakano is an Advisory IT Specialist at IBM Japan. His research interests include reliability in computer architecture and variability in semiconductor manufacturing. Nakano has an MS in physics from the University of Tokyo and a PhD in computer science from the University of Illinois at Urbana-Champaign. He is a member of the IEEE and the ACM.']}}, {'name': 'J. Torrellas', 'affiliation': 'Dept. of Comput. Sci., Illinois Univ., Urbana, IL', 'bio': {'p': ['Josep Torrellas is a professor of computer science and Willett Faculty Scholar at the University of Illinois at Urbana-Champaign. He also chairs the IEEE Technical Committee on Computer Architecture (TCCA). His research interests include multiprocessor computer architecture, thread-level speculation, low-power design, reliability, and debuggability. Torrellas has a PhD in electrical engineering from Stanford University. He is an IEEE Fellow and a member of the ACM.']}} %*SWICH: A Prototype for Efficient Cache-Level Checkpointing and Rollback %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1709820 %f/micro/ujmuggl9cmroib0t8423hecrfxzsxdkq.pdf %m43f4e033d94c3a325a580ede866d786f %cmicro %@[{'name': 'R.E. Gonzalez', 'affiliation': 'Stretch', 'bio': {'p': ['Ricardo E. Gonzalez is a senior architect at Stretch, where he leads the development of next-generation, software-configurable processors. He has a BS, an MS, and a PhD in electrical engineering from Stanford University.']}} %*A Software-Configurable Processor Architecture %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1709822 %f/micro/w5ipgvuhrcyjb8zyz1qa4jxslhpkinlq.pdf %mf7bd14c9c18714bb345e5b4e2ebdb3ae %cmicro %@[{'name': 'P.J. Garcia', 'affiliation': 'University of Castilla-La Mancha', 'bio': {'p': ['Pedro J. García is an assistant professor of computer architecture and technology and a PhD candidate in the Computer Systems Department (DSI) at the University of Castilla-La Mancha, Spain. His research interests are highperformance interconnection networks—mainly congestion management and deadlock-avoidance techniques, but also reconfiguration and routing algorithms. He has a degree in communication engineering from the Technical University of Valencia, Spain.']}}, {'name': 'F.J. Quiles', 'affiliation': 'Univ. of Castilla-La Mancha', 'bio': {'p': ['Francisco J. Quiles is a professor of computer architecture and technology and Vice-Rector of Research at the University of Castilla-La Mancha. His research interests include high-performance networks, parallel algorithms for video compression, and video transmission. He has a degree in physics (electronics and computer science) and a PhD in computer science from the University of Valencia, Spain.']}}, {'name': 'J. Flich', 'bio': {'p': ['José Flich is an associate professor of computer architecture and technology in the Department of Computer Engineering at Technical University of Valencia. His research interests include high-performance interconnection networks for multiprocessor systems and clusters of workstations. He has an MS and a PhD in computer science from the Technical University of Valencia, Spain. He is a member of the IEEE Computer Society.']}}, {'name': 'J. Duato', 'bio': {'p': ['José Duato is a professor in the Department of Computer Engineering at Universidad Politecnica de Valencia, Spain. His research interests include interconnection networks and multiprocessor architectures. His research results contributed to the design of the Alpha 21364 microprocessor and the Cray T3E and IBM BlueGene/L supercomputers. He has a PhD in electrical engineering from the Technical University of Valencia. He is a member of the IEEE and has served as associate editor of IEEE Transactions on Parallel and Distributed Systems and IEEE Transactions on Computers.']}}, {'name': 'I. Johnson', 'bio': {'p': ['Ian Johnson is Chief Scientist at Xyratex. Previously, he worked in the Mainframe Systems Technology Developoment Division of ICL/Fujitsu, and he went on to found Power X, a UK company that operated in the communications sector of the IT industry. His research interests range widely across many aspects of computing, communications, and storage systems architectures, IC design, and silicon manufacturing processes.']}}, {'name': 'F. Naven', 'bio': {'p': ["Finbar Naven is a chief architect of switch architectures at VirtenSys. His research interests include switch architectures and congestion management strategies, and he has many years' experience in the architectural development and implementation of silicon devices for computing and switching. He has a BSc in electrical engineering from the University of Salford, UK."]}} %*Efficient, Scalable Congestion Management for Interconnection Networks %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1709823 %f/micro/ytlxmdg25ybcegz0w9vmribdouuvscne.pdf %mc5eded92003b33e34898343c16a3123a %cmicro %@[{'name': 'V. Salapura', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'p': ['Valentina Salapura is a system architect at IBM T.J. Watson Research Center who has contributed to several generations of Blue Gene systems since the inception of the Blue Gene program. Her research interests include high-performance computer architecture and parallel architectures. Salapura has a PhD in computer science from Technische Universitat Wien, Vienna, and MS degrees in computer science and electrical engineering from the University of Zagreb.']}}, {'name': 'R. Walkup', 'affiliation': 'IBM Thomas J. Watson Res. Center, NY', 'bio': {'p': ['Robert Walkup is a research staff member at IBM T.J. Watson Research Center. His research interests include high-performance computing algorithms. Walkup has a PhD in physics from the Massachusetts Institute of Technology.']}}, {'name': 'A. Gara', 'affiliation': 'IBM Thomas J. Watson Res. Center, NY', 'bio': {'p': ['Alan Gara is an IBM fellow at IBM T.J. Watson Research Center. He is the chief architect of the Blue Gene/L supercomputer. Gara has a PhD in physics from the University of Wisconsin at Madison.']}} %*Exploiting Workload Parallelism for Performance and Power Optimization in Blue Gene %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1709824 %f/micro/uenbtppi6gloqrjwfk01fo2uamshy947.pdf %m73a4b6eeff82d5b131820831474de3e9 %cmicro %@[{'name': 'R. Mateosian'} %*So many books %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1709825 %f/micro/zrc75yk3tstivdaf0mzwmx1eo9kpsojn.pdf %mc49310cecbd3e04ed1b497e6f47a4dbb %cmicro %@[{'name': 'P.G. Emma', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/36071/1709826/1709826-photo-1-small.gif', 'p': ['Philip G. Emma']}} %*Prosecuting your patent %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1709826 %f/micro/9x6rltuwrnvpwsfdejxs7glhcqzbkhab.pdf %maecd9193e9a426ceb63a46fd490fa6b3 %cmicro %@[{'name': 'Pradip Bose', 'affiliation': 'IBM T.J. Watson Research Center'} %*Looking briefly back, and then forward... %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4042624 %f/micro/dktpxgwyfmi7w9zuxvhqtgae4z6bd0i3.pdf %mdf8482d9f19d278c8d0e9710b9385211 %cmicro %@[{'name': 'Shane Greenstein', 'affiliation': 'Kellogg Graduate School of Management', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/4042616/4042627/4042627-photo-1-small.gif', 'p': []}} %*Four nightmares for net neutrality %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4042627 %f/micro/wzyr0mm3gbcjetnclyjhfxqklsi6voq7.pdf %m4de5dddcb3efbef5d36f6ba30041de34 %cmicro %@[{'name': 'D. Gracia Perez', 'affiliation': 'CEA LIST, Saclay', 'bio': {'p': ["Daniel Gracia Pérez is a researcher at CEA LIST—the French Atomic Energy Commission's Lab of Applied Research on Software-Intensive Technologies—in Saclay, France. His research interests include computer architecture, simulation methodology, and simulation speed. He has master's degrees in computer science from Universitat Politècnica de Catalunya, Barcelona, Spain, and Kungliga Tekniska Hogskolan, Stockholm, Sweden, and a PhD in processor simulation from University of Paris Sud/INRIA, France."]}}, {'name': 'H. Berry', 'bio': {'p': ['Hugues Berry is a research scientist with the Alchemy project team at INRIA, the French National Institute for Research in Computer Science and Control, in Orsay, France. His research interests include biologically inspired approaches to computer architecture, computational neuroscience, and complex systems approaches. Berry has a PhD in biophysics from Université de Technologie de Compiègne, France.']}}, {'name': 'O. Temam', 'bio': {'p': ['Olivier Temam is a senior researcher at INRIA Futurs, Paris, where he heads the Alchemy group. His research interests include processor architecture and simulation, program optimization, emerging technologies and their impact on long-term architecture and programming. He has a PhD in computer science from the University of Rennes.']}} %*A Sampling Method Focusing on Practicality %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4042628 %f/micro/5ltt6uvfwk1pzn4fq0vobulgdzqrmnkx.pdf %m221a366b7cd570d3eb5389e1024da9d4 %cmicro %@[{'name': 'Osman S. Unsal', 'affiliation': 'Barcelona Supercomputing Center', 'bio': {'p': ['Osman S. Unsal is a senior research associate at the Barcelona Supercomputing Center. His research interests include computer architecture, reliability, and programmer productivity. He performed the work described in this article while working for the Intel Barcelona Research Center. Unsal has a BS from Istanbul Technical University, an MS from Brown University, and a PhD from the University of Massachusetts, Amherst, all in electrical and computer engineering.']}}, {'name': 'James W. Tschanz', 'affiliation': 'Circuits Research Lab, Intel Microprocessor Technology Labs', 'bio': {'p': ['James W. Tschanz is a circuits researcher at Intel Laboratories, Hillsboro, Oregon. He is also an adjunct faculty member at the Oregon Graduate Institute in Beaverton, Oregon. His research interests include low-power digital circuits, design techniques, and methods for tolerating parameter variations. Tschanz has a BS in computer engineering and an MS in electrical engineering, both from the University of Illinois at Urbana-Champaign.']}}, {'name': 'Keith Bowman', 'affiliation': 'Circuits Research Lab, Intel Microprocessor Technology Labs', 'bio': {'p': ['Keith Bowman is a senior researcher at Intel Circuit Research Labs, Hillsboro, Oregon. His current research focuses on the development of circuit design solutions to mitigate the impact of parameter variations on circuit performance and power. Bowman received a BS from North Carolina State University, and an MS and PhD from Georgia Institute of Technology, all in electrical engineering.']}}, {'name': 'Vivek De', 'affiliation': 'Circuits Research Lab, Intel Microprocessor Technology Labs', 'bio': {'p': ["Vivek De is a senior principal engineer and a chief scientist in Intel's Circuits Research Lab, Hillsboro, Oregon. He has been with Intel since 1996, leading long-term research in the area of low power circuit technology. De has a BTech from IIT Chennai, an MS from Duke University, and a PhD from Rensselaer Polytechnic Institute, all in electrical engineering."]}}, {'name': 'Xavier Vera', 'affiliation': 'Intel Barcelona Research Center', 'bio': {'p': ['Xavier Vera is a senior researcher at Intel Barcelona Research Center. His research interests include reliable and variation-aware microarchitectures. Vera has an MS in computer science from the Universitat Politecnica de Catalunya, Barcelona, and a PhD in Informatics from Malardalens Högskola at Väsrerås, Sweden.']}}, {'name': 'Antonio Gonzalez', 'affiliation': 'Universitat Polit¿cnica de Catalunya & Intel Barcelona Research Center', 'bio': {'p': ['Antonio González is a professor in the Computer Architecture Department of the Universitat Politècnica de Catalunya (UPC). He is the founding director of the Intel-UPC Barcelona Research Center, which focuses on new microarchitecture paradigms and code generation techniques. González has an MS in informatics engineering and a PHD in computer architecture from the Universitat Politècnica de Catalunya.']}}, {'name': 'Oguz Ergin', 'affiliation': 'TOBB University of Economics and Technology, Ankara', 'bio': {'p': ['Oguz Ergin is an assistant professor in the Department of Computer Engineering of TOBB University of Economics and Technology, Ankara, Turkey. His research interests include computer architectures and VLSI design. He performed the work described in this article while working for the Intel Barcelona Research Center. Ergin has MS and PhD degrees in computer science from the State University of New York at Binghamton.']}} %*Impact of Parameter Variations on Circuits and Microarchitecture %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4042630 %f/micro/renbf42t51poszadns7kcftb0ov3wpuw.pdf %ma1f95ea57191c806ec65524c91af721b %cmicro %@[{'name': 'Rajeev Balasubramonian', 'affiliation': 'University of Utah', 'bio': {'p': ['Rajeev Balasubramonian is an assistant professor in the School of Computing at the University of Utah. His research interests include the design of high-performance microprocessors that can efficiently tolerate long on-chip wire delays, high power densities, and frequent soft errors. Balasubramonian has a BTech in computer science and engineering from the Indian Institute of Technology, Bombay, and an MS and a PhD, both in computer science, from the University of Rochester. He is a member of the IEEE.']}}, {'name': 'Naveen Muralimanohar', 'affiliation': 'University of Utah', 'bio': {'p': ["Naveen Muralimanohar is pursuing a PhD in computer science at the University of Utah. His research interests include interconnect design for future communication-bound processors and microarchitectural techniques to exploit special wires in an on-chip network. Muralimanohar has a bachelor's degree in electrical and electronics engineering from the University of Madras, India."]}}, {'name': 'Karthik Ramani', 'affiliation': 'University of Utah', 'bio': {'p': ["Karthik Ramani is pursuing a PhD in the School of Computing at the University of Utah. His research interests include workload characterization of computationally intensive applications, compilation techniques for embedded architectures, and temperature-aware interconnect architectures. Ramani has a bachelor's degree in electronics and communication engineering from the University of Madras, India, and an MS in electrical engineering from the University of Utah. He is a student member of the IEEE and the ACM."]}}, {'name': 'Liqun Cheng', 'affiliation': 'University of Utah', 'bio': {'p': ['Liqun Cheng is pursuing a PhD in the School of Computing at the University of Utah. His research interests include computer architecture, parallel and distributed computing, system simulators, performance analysis, and advanced memory systems. Cheng has a BS in computer science from Shanghai Jiao Tong University. He is a student member of the IEEE, the IEEE Computer Society, and the ACM.']}}, {'name': 'John B. Carter', 'affiliation': 'University of Utah', 'bio': {'p': ['John B. Carter is an associate professor in the School of Computing at the University of Utah. His research interests include computer architecture, operating systems, distributed systems, networking, and parallel computing, with particular emphasis on memory and storage systems. Carter has a BS in electrical and computer engineering and an MS and a PhD, both in computer science, all from Rice University.']}} %*Leveraging Wire Properties at the Microarchitecture Level %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4042631 %f/micro/jl3qshe8cv9j5v1z7qpcue6kgouiwfgs.pdf %mb9110abb18cdf62842214533542ffe69 %cmicro %@[{'name': 'Philip G. Emma', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/4042616/4042638/4042638-photo-1-small.gif', 'p': ['Philip G. Emma']}} %*Five strategies for overcoming obviousness %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4042638 %f/micro/icqjadfvonysgpvebxwnrcuho451wus9.pdf %mb1b8cc6aa58c526055124a6114e4d117 %cmicro %@[{'name': 'P. Bose', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/30580/1411708/1411708-photo-1-small.gif', 'p': []}} %*The "power" of communication %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1411708 %f/micro/af8bqsmun79b5gpchedopszv06ne2dka.pdf %m9fd0905093bd4464ed6d24c558502b06 %cmicro %@[{'name': 'R.H. Stern', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/30580/1411709/1411709-photo-1-small.gif', 'p': []}} %*FTC cracks down on spyware and PC hijacking, but not true lies %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1411709 %f/micro/63lwqx7kqcyfspdbiowratmjagnnczsy.pdf %m6b53b954374c97c585c619bc44e44d20 %cmicro %@[{'name': 'J.P.G. Sterbenz', 'affiliation': 'University of Massachusetts, Amherst Lancaster University, UK', 'bio': {'p': ['James P.G. Sterbenz a visiting research scientist at the University of Massachusetts, Amherst, and a visiting professor of computing at Lancaster University, UK. He previously held senior staff and research management positions at BBN Technologies, GTE Laboratories, and IBM Research. His research interests include survivable, resilient, and disruption-tolerant mobile and wireless networking, active and programmable networks, and high-speed networking and com-ponents. Sterbenz has a DSc in computer science from Washington University in St. Louis. He is a senior member of the IEEE, and member of lEE (UK), IEICE (Japan), ACM, and ISOC Interplanetary SIG.']}}, {'name': 'D. Stiliadis', 'bio': {'p': ['Dimitrios Stiliadis is a distinguished member of technical staff at Bell Laboratories, Lucent Technologies. His research interests include data networking with an emphasis on router architectures, switch fabrics, traffic management, and packet classification. Stiliadis has a PhD and an MS in computer engineering from the University of California, Santa Cruz. He is a member of the IEEE.', 'Direct questions and comments about this special issue to James P.G. Sterbenz, PO Box 187, Hopkinton MA 01748-0187, jpgs@ieee.org, www.comp.lancs.ac.uk/computing/users/jpgs.']}} %*Guest Editors' Introduction: Hot Interconnects 12 %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1411710 %f/micro/9o6snaxjfqf0udzylvjora5krpk4esit.pdf %mffabcc70e3a155ec248f4c5009c7b57f %cmicro %@[{'name': 'V. Krishnan', 'bio': {'p': ['Venkata Krishnan is an architect at Stargen, where he focuses on chip and system-level performance issues. His research interests include networking, microprocessor architecture, compilers and simulation methodologies. He received a BTech from the Indian Institute of Technology, Madras, and a PhD in computer science from the University of Illinois at Urbana-Champaign. He is a member of the IEEE and ASI SIG technical committees.']}}, {'name': 'D. Mayhew', 'bio': {'p': ['David Mayhew is a cofounder and chief scientist at Stargen. His research interests include high performance networking, next generation I/O technologies and object-oriented design principles. He is coauthor of Efficient C++: Performance Programming Techniques (Prentice Hall, 2000). Mayhew has a PhD in computer science from Virginia Tech. He is a member and chair of ASI SIG technical committees.']}} %*Localized congestion control in advanced switching interconnects %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1411711 %f/micro/mlcdb1grxtlifwacwhn6ejen0vg79zkq.pdf %m395095581c3aa9122bd3a6d60c108780 %cmicro %@[{'name': ' Jiuxing Liu', 'affiliation': 'IBM Thomas J. Watson Res. Center, NY, USA', 'bio': {'p': ['Jiuxing Liu is a research staff member at the IBM T.J. Watson Research Center. His research interests include high-speed inter-connects, cluster computing, server I/O architecture, and storage systems. Liu has a PhD from The Ohio State University. He is a member of the IEEE and the ACM.']}}, {'name': 'A. Mamidala', 'bio': {'p': ["Amith Mamidala is a PhD student in Department of Computer Science and Engineering at The Ohio State University. His research interests include collective communication in MPI over InfiniBand. Mamidala has an MS in computer science and engineering from The Ohio State University and a bachelor's degree in computer science and engineering from the Indian Institute of Technology Madras, India. He is a member of the IEEE."]}}, {'name': 'A. Vishnu', 'bio': {'p': ['Abhinav Vishnu is a PhD student in Department of Computer Science and Engineering at The Ohio State University. His research interests include message-passing algorithms for high-speed interconnects, cluster computing, and subnet management in InfiniBand. Vishnu has a BS in computer science and engineering from the Institute of Technology, Banaras Hindu University, India. He is a member of the IEEE.']}}, {'name': 'D.K. Panda', 'bio': {'p': ['Dhabaleswar K. Panda is a professor of computer science at The Ohio State University. His research interests include parallel computer architecture, high-performance computing, user-level communication protocols, interprocessor communication and synchronization, network-based computing, and quality of service. Panda has a PhD in computer engineering from the University of Southern California. He is a senior member of the IEEE and a member of the ACM.']}} %*Evaluating InfiniBand performance with PCI Express %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1411713 %f/micro/eqaqlggk6cvz08chjxbmdfjnsywfu7uw.pdf %m2d9dd9c5583f8d0bfcc1c6464b9d2a44 %cmicro %@[{'name': 'T.H. Dunigan', 'affiliation': 'Oak Ridge Nat. Lab., TN, USA', 'bio': {'p': ['Thomas H. Dunigan Jr. is a senior R & D staff member in the Computer Science and Mathematics Division of Oak Ridge National Laboratory. His research interests include the performance characterization and analysis of parallel computers and their communication subsystems, and computer and network security. Dunigan has a PhD in computer science from the University of North Carolina at Chapel Hill.']}}, {'name': 'J.S. Vetter', 'affiliation': 'Oak Ridge Nat. Lab., TN, USA', 'bio': {'p': ['Jeffrey S. Vetter is a senior R & D staff member in the Computer Science and Mathematics Division of Oak Ridge National Laboratory, where he leads the Future Technologies Group. His research interests include experimental software systems and architectures for high-end computing. Vetter has a PhD in computer science from the Georgia Institute of Technology. He is a member of IEEE and the ACM.']}}, {'name': 'J.B. White', 'affiliation': 'Oak Ridge Nat. Lab., TN, USA', 'bio': {'p': ['James B. White III (Trey) is an R & D staff member and a technical lead of the Scientific Application Support group in the Center for Computational Sciences at Oak Ridge National Laboratory. His research interests include enabling new science through high-end computation and improving the productivity of computational scientists. White has an MS in physics from the Ohio State University.']}}, {'name': 'P.H. Worley', 'affiliation': 'Oak Ridge Nat. Lab., TN, USA', 'bio': {'p': ['Patrick H. Worley is a senior R & D staff member in the Computer Science and Mathematics Division of Oak Ridge National Laboratory. His research interests include parallel algorithm design and implementation (especially as applied to atmospheric and ocean simulation models) and the performance evaluation of parallel applications and computer systems. Worley has a PhD in computer science from Stanford University. He is a member of the ACM and the Society for Industrial and Applied Mathematics.', 'Direct questions and comments about this article to Jeffrey S. Vetter, Oak Ridge National Laboratory, MS-6173, Oak Ridge, TN 37831–6173, vetter@computer.org.']}} %*Performance evaluation of the Cray X1 distributed shared-memory architecture %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1411714 %f/micro/nmrjhk5fndgtimbaewqj2x1sa4hekfuo.pdf %m01d2ee30b9c2eb1c9d8081f6043107ad %cmicro %@[{'name': 'F. Yu', 'affiliation': 'Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA', 'bio': {'p': ['Fang Yu is a PhD candidate in the Electrical Engineering and Computer Science Department at the University of California, Berkeley. Her research interests include high-speed deep packet inspection and optical networks. Yu has an undergraduate degree in computer science from Fudan University, China, and an MS in computer science from the University of California, Berkeley.']}}, {'name': 'R.H. Katz', 'affiliation': 'Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA', 'bio': {'p': ['Randy H. Katz is the United Microelectronics Corporation Distinguished Professor in Electrical Engineering and Computer Science at the University of California, Berkeley. His research interests include reliable, adaptive, distributed systems. Katz has an AB from Cornell University, and an MS and a PhD from the University of California, Berkeley, all in computer science. He is a Fellow of the ACM and the IEEE and a member of the National Academy of Engineering and the American Academy of Arts and Sciences.']}}, {'name': 'T.V. Lakshman', 'bio': {'p': ["T.V. Lakshman is the director of the HighSpeed Networking Research Department at Bell Laboratories, Holmdel, New Jersey. His research interests include traffic characterization and provision of quality of service, architectures, and algorithms for IP routers. Lakshman has a master's degree in physics from the Indian Institute of Science, Bangalore, India, and a PhD in computer science from the University of Maryland, College Park. He is a Fellow of the IEEE.", 'Direct questions and comments about this article to Fang Yu, 475 Soda Hall, University of California, Berkeley, CA 94706, fyu@eecs.berkeley.edu.', 'For further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/publications/dlib.']}} %*Efficient multimatch packet classification and lookup with TCAM %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1411716 %f/micro/8uvznjha2ipdh1equrssygq3d0ax9cb4.pdf %m4c4cf92617f233cc8d556cecabf3eb78 %cmicro %@[{'name': 'B. Madhusudan', 'affiliation': 'Washington Univ., St. Louis, MO, USA', 'bio': {'p': ['Bharath Madhusudan was a student at Washington University in St. Louis. His research interests include the design and implementation of high-speed networking systems. Madhusudan has an MS in computer science from Washington University in St. Louis and a BS in computer science from the University of Maryland at College Park.']}}, {'name': 'J.W. Lockwood', 'affiliation': 'Washington Univ., St. Louis, MO, USA', 'bio': {'p': ['John W. Lockwood is an assistant professor in the Department of Computer Science and Engineering at Washington University in St. Louis. His research interests include the design and implementation of networking systems in reconfigurable hardware. Lockwood and his research group developed the Field-Programmable Port Extender (FPX) to enable rapid prototype of extensible network modules. He has a BS, an MS, and a PhD in electrical engineering from the University of Illinois, Urbana-Champaign. He is a member of the IEEE, the ACM, Tau Beta Pi, and Eta Kappa Nu.', 'Direct questions and comments about this article to John Lockwood, Dept. of Computer Science and Engineering, Washington University, 1 Brookings Dr., Campus Box 1045, St. Louis, MO 63130, lockwood@arl.wustl.edu.']}} %*A hardware-accelerated system for real-time worm detection %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1411717 %f/micro/j2kqzmw17ghqpbmdwkyrx5x8h0etfuro.pdf %md209263e42211f6505da01c745e0418c %cmicro %@[{'name': ' Srikanth Arekapudi', 'affiliation': 'Stanford Univ., CA, USA', 'bio': {'p': ['Srikanth Arekapudi is a circuit design engineer at Advanced Micro Devices in the Computation Products Group. His research interests include low-power, high-performance circuit design. Arekapudi has a BTech in electronics and communication engineering from the National Institute of Technology, Warangal, an MS in electrical and computer engineering from the University of Massachusetts at Amherst, and a DEng in electrical engineering from Stanford University.']}}, {'name': 'S.-T. Chuang', 'affiliation': 'Stanford Univ., CA, USA', 'bio': {'p': ['Shang-Tse (Da) Chuang is an architect at Nvidia Corp. His research interests include switch-scheduling algorithms, router architectures, and packet-buffer and linecard design. Chuang has a BS from the University of California at Berkeley, and an MS and a PhD from Stanford University, all in electrical engineering. He is a member of the IEEE.']}}, {'name': 'I. Keslassy', 'bio': {'p': ['Isaac Keslassy is an assistant professor of electrical engineering at the Technion, Israel Institute of Technology. His research interests include the design and analysis of highperformance routers, load balancing, packet buffering, and scheduling algorithms in optical and wireless networks. Keslassy has a PhD in electrical engineering from Stanford University. He is the American Technion Society-Women Division Career Development Chair and a member of the IEEE.']}}, {'name': 'N. McKeown', 'bio': {'p': ["Nick McKeown is the ST Microelectronics Professor of electrical engineering and computer science at Stanford University. His research interests include the architecture, analysis, and design of high-performance switches and Internet routers, Internet Protocol lookup and classification algorithms, scheduling algorithms, optical switches, congestion control, and network design. McKeown has a PhD in electrical engineering and computer science from the University of California, Berkeley. He is the Robert Noyce Faculty Fellow at Stanford, a fellow of the Alfred P. Sloan Foundation and the Powell Foundation, and a recipient of the National Science Foundation's Career award. He is a fellow of the Royal Academy of Engineering and of the IEEE.", 'Direct questions about this article to Shang-Tse (Da) Chuan, Gates Bldg., Room 350, Stanford, CA 94305, stchuang@yuba.stanford.com.']}} %*Using hardware to configure a load-balanced switch %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1411718 %f/micro/zjdpcoq2nkfiyuwdgtio7xhbq8lw4m5a.pdf %m7570c0c724668ea436b6eff74dc189df %cmicro %@[{'name': 'A. Falcon', 'affiliation': 'Hewlett-Packard Labs., Barcelona, Spain', 'bio': {'p': ['Ayose Falcón is a research scientist at Hewlett-Packard Labs in Barcelona. His research interests include fetch unit optimizations, especially branch prediction and instruction prefetching, and microprocessor simulation. Falcón has a BS and an MS in computer science from the University of Las Palmas de Gran Canaria, and a PhD in computer science from the Universitat Politècnica de Catalunya (UPC). He is a member of the ACM.']}}, {'name': 'J. Stark', 'bio': {'p': ["Jared Stark is a research scientist at Intel's Microarchitecture Research Lab in Hillsboro, Oregon. His research interests include branch prediction, dynamic instruction scheduling, and aggressive speculation. Stark has a BS in electrical engineering and an MS and a PhD in computer engineering, all from the University of Michigan. He is a member of the IEEE."]}}, {'name': 'A. Ramirez', 'bio': {'p': ['Alex Ramirez is an assistant professor in the Computer Architecture Department at UPC. His research interests include profile-guided compiler optimizations, code layout optimizations, performance studies of user and system code like database applications, and the design and implementation of the fetch stage of superscalar and multithreaded processors. Ramirez has a BS, an MS, and a PhD in computer science from UPC. He is a member of the ACM.']}}, {'name': 'K. Lai', 'bio': {'p': ["Konrad Lai is a senior principal research scientist at Intel's Microprocessor Technology Laboratories, Hillsboro, Oregon. His research interests include microprocessor, memory, and system architectures. Lai has a BS in electrical engineering from Princeton University and an MS in computer engineering from Carnegie Mellon University. He is a member of the ACM and the IEEE."]}}, {'name': 'M. Valero', 'bio': {'p': ['Mateo Valero is a professor in the Computer Architecture Department at UPC. His research interests include high-performance computer architectures. Valero has a BS in telecommunication engineering from the Polytechnic University of Madrid and a PhD in telecommunications from UPC. He is a Fellow of the IEEE and the ACM.', 'Direct questions and comments about this article to Ayose Falcón Hewlett-Packard, Avda. Graells 501, 08714, Sant Cugat del Valles, Barcelona, Spain, ayose.falcon@hp.com.']}} %*Better branch prediction through prophet/critic hybrids %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1411720 %f/micro/rletlxeg7zqk1zimvumjht3cq4x9svwc.pdf %mc5acfa2cd5532694b7eeeb47a9e02630 %cmicro %@[{'name': 'K.J. Nesbit', 'affiliation': 'Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA', 'bio': {'p': ['Kyle J. Nesbit is a PhD candidate in the Department of Electrical and Computer Engineering at the University of Wisconsin-Madison. His research interests include processor performance modeling, power-efficient processor design, virtual machines, and memory optimization. Nesbit has a BS in electrical engineering from the University of Wisconsin-Madison. He is a student member of the IEEE.']}}, {'name': 'J.E. Smith', 'affiliation': 'Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA', 'bio': {'p': ['James E. Smith is a professor in the Department of Electrical and Computer Engineering at the University of Wisconsin-Madison. His current research interests include high-performance and power-efficient processor implementations, processor performance modeling, and virtual machines. Smith has a PhD in computer science from the University of Illinois. He is a member of the IEEE and ACM.']}} %*Data cache prefetching using a global history buffer %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1411721 %f/micro/71isnvcpwtx4gdejmuuiyvx3wrkhzsfg.pdf %m73ea6f8c4f4529d52814c3050f08c686 %cmicro %@[{'name': 'R. Mateosian', 'affiliation': 'xrm@pacbell.net'} %*Too much information %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1411722 %f/micro/9mwvou06bofjqczxet2wsy8cnkbfpilz.pdf %m9cc1c5e72d84ef01a45fc582a91398b8 %cmicro %@[{'name': 'S. Greenstein', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/30580/1411723/1411723-photo-1-small.gif', 'p': ['']}} %*Not a mellifluous march to maturity [computer market] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1411723 %f/micro/finj02hqu7dgcbqcdn3ko9uzrsphfevl.pdf %m9d28f207685cbd198962ed6fcdc0f492 %cmicro %@[{'name': 'P. Bose', 'affiliation': 'IBM', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/31213/1453481/1453481-photo-1-small.gif', 'p': ['']}} %*Variation-tolerant design %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1453481 %f/micro/wnxmftljebys7m016ycgtufn4aazpxgl.pdf %m96596173bfabd19c88b46a76db5e1269 %cmicro %@[{'name': 'R. Mateosian'} %*Thinking about history and design %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1453482 %f/micro/zroofxu3sj6bmkyqin1rgtkmyvihcfnw.pdf %m61aa22ef5ceb33b8249c588c65638eb7 %cmicro %@[{'name': 'B. Dally', 'affiliation': 'Stanford University', 'bio': {'p': ['Bill Dally is a professor of electrical engineering and computer science and chair of the computer science department at Stanford University. His research interests include streaming supercomputers, image and signal processors, and scalable network fabrics. Dally has a PhD in computer science from Caltech, an MS in electrical engineering from Stanford University, and a BS in electrical engineering from Virginia Polytechnic Institute. He is a Fellow of the IEEE and the ACM, and received the ACM Maurice Wilkes Award in 2000 and the IEEE Seymour Cray Award in 2004.']}}, {'name': 'K. Diefendorff', 'bio': {'p': ['Keith Diefendorff is chief microprocessor architect at Apple Computer, where he works on next-generation high-performance microprocessors. He has been the chief architect of several high-performance processors including AltiVec/G4 at Apple and PowerPC and the 88110 at Motorola, and for two years was editor-in-chief of Microprocessor Report. Diefendorff has an MSEE from the University of Akron and holds 12 U.S. patents. He is a member of the IEEE and the IEEE Computer Society', 'Direct questions and comments about this special issue to Bill Dally, Stanford University, Computer Systems Laboratory, Gates Room 301, Stanford, CA 94305, billd@csl.stanford.edu.']}} %*Hot Chips 16: Power, Parallelism, and Memory Performance %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1453483 %f/micro/ao1mrxgybfj8znhlgpz3nve2ujh4xsil.pdf %m0f4db2ea097ad92258d429f587eb2d78 %cmicro %@[{'name': 'C. McNairy', 'affiliation': 'Intel Corp., Fort Collins, CO, USA', 'bio': {'p': ['Cameron McNairy is an architect for the Montecito program at Intel. He was also a microarchitect for the Itanium 2 processor, contributing to its design and final validation. In future endeavors, McNairy plans to focus on performance, reliability, availability, and serviceability, and system interface issues in Itanium processor design. He received a BSEE and an MSEE from Brigham Young University and is a member of the IEEE.']}}, {'name': 'R. Bhatia', 'affiliation': 'Intel Corp., Fort Collins, CO, USA', 'bio': {'p': ['Rohit Bhatia is an Itanium processor microarchitect at Intel. His research interests include computer architecture, Itanium processor microarchitecture, and the functional verification of microprocessors. Bhatia has an MSEE from the University of Minnesota and an MS in engineering management from Portland State University.']}} %*Montecito: a dual-core, dual-thread Itanium processor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1453484 %f/micro/k6b5i7uwapsomdenn0ymthu9lwpc31tx.pdf %mf70377cbea09d5960d97f9984e763942 %cmicro %@[{'name': 'P. Kongetira', 'affiliation': 'Sun MicroSystems Inc., Sunnyvale, CA, USA', 'bio': {'p': ['Poonacha Kongetira is a director of engineering at Sun Microsystems and was part of the development team for the Niagara processor. His research interests include computer architecture and methodologies for SOC design. Kongetira has a MS from Purdue University and BS from Birla Institute of Technology and Science, both in electrical engineering. He is a member of the IEEE.']}}, {'name': 'K. Aingaran', 'affiliation': 'Sun MicroSystems Inc., Sunnyvale, CA, USA', 'bio': {'p': ['Kathirgamar Aingaran is a senior staff engineer at Sun Microsystems and was part of the development team for Niagara. His research interests include architectures for low power and low design complexity. Aingaran has an MS from Stanford University and a BS from the University of Southern California, both in electrical engineering. He is a member of the IEEE.']}}, {'name': 'K. Olukotun', 'bio': {'p': ['Kunle Olukotun is an associate professor of electrical engineering and computer science at Stanford University. His research interests include computer architecture, parallel programming environments, and formal hardware verification. Olukotun has a PhD in computer science and engineering from the University of Michigan. He is a member of the IEEE and the ACM.']}} %*Niagara: a 32-way multithreaded Sparc processor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1453485 %f/micro/erehndj8ay4dgtpqc6yopjix3zb19bsu.pdf %m91f8deb10779005ed5c5afa7351fe807 %cmicro %@[{'name': ' Rajesh Kota', 'affiliation': 'Newisys Inc., Austin, TX, USA', 'bio': {'p': ['Rajesh Kota is a Horus architect at Newisys. His research interests include system engineering, microprocessor architectures, and low-power design. Kota has a BE in electronics and communication engineering from Osmania University, India, and an MS in computer engineering from the University of Maryland.']}}, {'name': 'R. Oehler', 'affiliation': 'Newisys Inc., Austin, TX, USA', 'bio': {'p': ['Rich Oehler has been chief technology officer at Newisys since its founding in 2000. His research interests include processor, system, and I/O architectures, operating systems, and compilers. He was a major contributor to the IBM 801, one of the first RISC machines, the IBM RS/6000 and PowerPC, and the IBM Summit chipset. Oehler has a BA in mathematics from St. Johns University.']}} %*Horus: large-scale symmetric multiprocessing for Opteron systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1453486 %f/micro/xnkxl5ooik8ze1shymfblq97far60b2v.pdf %m347995c48b2f4f55f60043c149ed0abf %cmicro %@[{'name': 'H. Eberle', 'affiliation': 'Sun MicroSystems Inc., CA, USA', 'bio': {'p': ['Hans Eberle is a distinguished engineer at Sun Microsystems Laboratories. His research interests include networks and security. Eberle has a MS in electrical engineering and a PhD in technical sciences from the Swiss Federal Institute of Technology, Zurich. He is a member of the IEEE.']}}, {'name': 'S. Shantz', 'affiliation': 'Sun MicroSystems Inc., CA, USA', 'bio': {'p': ['Sheueling Chang Shantz is a distinguished engineer at Sun Microsystems Laboratories. Her research interests include next-generation Internet security, efficient software implementation and hardware acceleration of Elliptic Curve Cryptosystems. Chang Shantz has a PhD in computer science from California Institute of Technology.']}}, {'name': 'V. Gupta', 'affiliation': 'Sun MicroSystems Inc., CA, USA', 'bio': {'p': ['Vipul Gupta is a senior staff engineer at Sun Microsystems Laboratories. His research interests include Internet security and small wireless devices. Gupta has a MS and PhD in computer science from Rutgers University. He is an active participant in the Internet Engineering Task Force (IETF).']}}, {'name': 'N. Gura', 'affiliation': 'Sun MicroSystems Inc., CA, USA', 'bio': {'p': ['Nils Gura is a member of technical staff at Sun Microsystems Laboratories. His research interests include efficient algorithms and hardware acceleration for next-generation cryptographic technologies, primarily Elliptic Curve Cryptography. Gura has a MS in computer science from the University of Ulm, Germany. He is a member of the IEEE.']}}, {'name': 'L. Rarick', 'affiliation': 'Sun MicroSystems Inc., CA, USA', 'bio': {'p': ['Leonard Rarick is a senior staff hardware engineer at Sun Microsystems Laboratories. His research interests include cryptographic algorithms, floating point hardware design, and linear programming. Rarick has a PhD degree in computer science from Columbia University.']}}, {'name': 'L. Spracklen', 'affiliation': 'Sun MicroSystems Inc., CA, USA', 'bio': {'p': ['Lawrence Spracklen is a senior processor architect at Sun Microsystems Laboratories in the Advanced Processor Architecture group. His research interests include next-generation chip multithreaded processors. Spracklen has a PhD in electrical engineering from the University of Aberdeen.']}} %*Accelerating next-generation public-key cryptosystems on general-purpose CPUs %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1453488 %f/micro/4owphagjblntu3yib8z1xerefsdwdx5y.pdf %m391a74ad76b9969b69713f8b645ab9f5 %cmicro %@[{'name': 'J. Keller', 'affiliation': 'Fachbereich Informatik, Fern Univ., Hagen, Germany', 'bio': {'p': ['Jörg Keller is an associate professor of computer science at Fern Universität Hagen, Germany. His research interests include parallel algorithms and architectures, fault tolerance, IT security, and new media in distance teaching. Keller has MS and PhD degrees in computer science from Universität des Saarlandes, Saarbrücken, Germany. He is a member of the IEEE Computer Society and the German Society of Informatics (GI).']}}, {'name': 'A. Gravinghoff', 'bio': {'p': ['Andreas Grävinghoff is a research staff member at ETAS GmbH, Stuttgart, Germany. His research interests include parallel programming systems and hardware design. Gräving-hoff has an MS in computer science from Universität des Saarlandes, Saarbrücken, Germany, and a PhD in computer science from FernUniversität Hagen, Germany.']}} %*Thread-based virtual duplex systems in embedded environments %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1453489 %f/micro/xyefi1p4lfh7la5rtu0dajbc3eokdgvy.pdf %mc389a2d26782c33d0b94e2684c76bc69 %cmicro %@[{'name': 'S. Greenstein', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/31213/1453490/1453490-photo-1-small.gif', 'p': ['']}} %*Communications consolidation after an era of no restraints %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1453490 %f/micro/zypxufcn4jw0ylirtvzh7v9tkhio56mu.pdf %m31074c31dec5c429e32981c17af9a2c1 %cmicro %@[{'name': 'P. Bose', 'affiliation': 'pbose@us.ibm.com', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/31458/1463177/1463177-photo-1-small.gif', 'p': []}} %*Integrated microarchitectures %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1463177 %f/micro/5gmbsinqm7v463dnweztrwjul8vxdkcf.pdf %m9b792af6e17bf5d77b718719518a178e %cmicro %@[{'name': 'R.H. Stern', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/31458/1463178/1463178-photo-1-small.gif', 'p': ['']}} %*The antitrust ghost in the standard-setting machine [IEEE standards and RAND licensing] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1463178 %f/micro/mywef53ppfsqbxdoikb2c9al0z8wv1n7.pdf %m745e2b203faa7b0cfa13ef1017a9d7b6 %cmicro %@[{'name': 'S. Greenstein', 'affiliation': 'Northwestern Univ., Evanston, IL, USA', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/31458/1463179/1463179-photo-1-small.gif', 'p': ['']}} %*The anatomy of foresight traps [foresight management] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1463179 %f/micro/pb6agel7tq35uoyxxjhj0ni8zkfgvvyw.pdf %mf0342a067401f9fd2b0d772d2bb6e137 %cmicro %@[{'name': 'R. Mateosian', 'affiliation': 'xrm@pacbell.net', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/31458/1463180/1463180-photo-1-small.gif', 'p': ['']}} %*Dealing with globalization %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1463180 %f/micro/qhe4lc5aa83fpkomfubdzrvw7izskt2g.pdf %mb6da3736a74d81685aac1099e669f54a %cmicro %@[{'name': 'M.J. Flynn', 'affiliation': 'Stanford Univ., CA, USA', 'bio': {'p': ['Michael J. Flynn is professor emeritus of electrical engineering at Stanford University. He began his engineering career at IBM as a designer of mainframe computers, at Stanford he founded, and continues research at, the Architecture and Arithmetic group. Flynn has a BS from Manhattan College, an MS from Syracuse University, and a PhD from Purdue University. He is a Fellow of the IEEE and ACM.']}}, {'name': 'P. Hung', 'affiliation': 'Stanford Univ., CA, USA', 'bio': {'p': ['Patrick Hung is consulting assistant professor of electrical engineering at Stanford University. His research interests include microprocessor design and system-level computer-aided design tools. Hung has a BS from the University of Hong Kong, and an MS and a PhD from Stanford University. He is a member of the IEEE and ACM.']}} %*Microprocessor design issues: thoughts on the road ahead %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1463181 %f/micro/18cxkjqnpxfl0bfugdiw43wq6um7odpc.pdf %m8126ca7f9a7d529f1e0475712ec72bea %cmicro %@[{'name': 'S. Chaudhry', 'affiliation': 'Sun MicroSyst. Inc., Mountain View, CA, USA', 'bio': {'p': ['Shailender Chaudhry is a distinguished engineer at Sun Microsystems where he is chief architect of the Rock processor. His experience includes work on the MAJC architecture, picoJava II, microJava, and space-time computing. His research interests include computer systems architecture, algorithms, and protocols. Chaudhry has a BS and an MS in computer engineering from Syracuse University.']}}, {'name': 'P. Caprioli', 'affiliation': 'Sun MicroSyst. Inc., Mountain View, CA, USA', 'bio': {'p': ['Paul Caprioli is a senior staff engineer at Sun Microsystems where he is the Rock core architect and leads the performance modeling group. His research interests include computer architectures and high-performance technical computing. Caprioli has an MS and a PhD in mathematics from Rensselaer Polytechnic Institute.']}}, {'name': 'S. Yip', 'affiliation': 'Sun MicroSyst. Inc., Mountain View, CA, USA', 'bio': {'p': ['Sherman Yip is an engineer at Sun Microsystems where he is a member of the Rock architecture team and responsible for performance modeling. His research interests include processor simulation, visualization, and Java performance and design. Yip has a BS in computer science from the University of California at Davis.']}}, {'name': 'M. Tremblay', 'affiliation': 'Sun MicroSyst. Inc., Mountain View, CA, USA', 'bio': {'p': ['Marc Tremblay is a Sun Fellow and distinguished engineer at Sun Microsystems, where he is chief architect of the Scalable Systems Group. His research interests include chip multiprocessing, chip multithreading, speculative multithreading, and assist threading. Tremblay has an MS and a PhD in computer science from UCLA and a BS in physics engineering from Laval University in Canada. He holds 97 US patents in various areas of computer architecture. He is a member of the IEEE and the ACM.']}} %*High-performance throughput computing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1463182 %f/micro/tqyxi0oypubgjcdna5edmzhkie1h4jrm.pdf %m8ebf631a066f431ad13b36f7f6d4f0f4 %cmicro %@[{'name': 'A. Cristal', 'affiliation': 'Comput. Archit. Dept., Univ. Politecnica de Catalunya, Barcelona, Spain', 'bio': {'p': ['Adrián Cristal is an assistant professor and a doctoral candidate in the Computer Architecture Department at the Polytechnic University of Catalonia (UPC), Spain. His research interests include processor microarchitecture and, in particular, kilo-instruction processors. Cristal has a BS and an MS in computer science from the University of Buenos Aires, Argentina.']}}, {'name': 'O.J. Santana', 'affiliation': 'Comput. Archit. Dept., Univ. Politecnica de Catalunya, Barcelona, Spain', 'bio': {'p': ['Oliverio J. Santana is a collaborator professor in the Computer Architecture Department at UPC. His research interests include complexity-effective fetch and decoding architectures for high-performance processors. Santana has a PhD in computer science from UPC, as well as a BS and an MS in computer science from the University of Las Palmas de Gran Canaria (ULPGC), Spain.']}}, {'name': 'F. Cazorla', 'affiliation': 'Comput. Archit. Dept., Univ. Politecnica de Catalunya, Barcelona, Spain', 'bio': {'p': ['Francisco Cazorla is a doctoral candidate in the Computer Architecture Department at UPC. His research interests include fetch policies for simultaneous multithreaded architectures. Cazorla has a BS and an MS in computer science from ULPGC.']}}, {'name': 'M. Galluzzi', 'affiliation': 'Comput. Archit. Dept., Univ. Politecnica de Catalunya, Barcelona, Spain', 'bio': {'p': ['Marco Galluzzi is a doctoral candidate in the Computer Architecture Department at UPC. His research interests include coherence and consistence multiprocessor protocols, and their relationships with techniques for tolerating the memory latency. Galluzzi has a BS and an MS in computer science from ULPGC.']}}, {'name': 'T. Ramirez', 'affiliation': 'Comput. Archit. Dept., Univ. Politecnica de Catalunya, Barcelona, Spain', 'bio': {'p': ['Tanausú Ramírez is a doctoral candidate in the Computer Architecture Department at UPC. His research interests include techniques for overcoming the memory wall problem. Ramírez has a BS and an MS in computer science from ULPGC.']}}, {'name': 'M. Pericas', 'affiliation': 'Comput. Archit. Dept., Univ. Politecnica de Catalunya, Barcelona, Spain', 'bio': {'p': ['Miquel Pericàs is a researcher at the Barcelona Supercomputing Center and a doctoral candidate in the Computer Architecture Department at UPC. His research interests include efficient kilo-instruction processor implementations. Pericàs has an MS in telecommunications from UPC.']}}, {'name': 'M. Valero', 'affiliation': 'Comput. Archit. Dept., Univ. Politecnica de Catalunya, Barcelona, Spain', 'bio': {'p': ['Mateo Valero is a professor in the Computer Architecture Department at UPC. His research interests include high-performance architectures. Valero has a PhD in telecommunications from UPC. He is an IEEE Fellow, an Intel Distinguished Research Fellow, and an ACM Fellow. Since 1994, he is a foundational member of the Royal Spanish Academy of Engineering.']}} %*Kilo-instruction processors: overcoming the memory wall %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1463185 %f/micro/waxchvjsfp085llf29onu1ouqact6isn.pdf %mfa8d7f1b8092694aa551022b40fea3b2 %cmicro %@[{'name': 'T. Agerwala', 'bio': {'p': ["Tilak Agerwala is vice president, systems, at IBM Research. His primary research area is high-performance computing systems. He is responsible for all of IBM's advanced systems research programs in servers and supercomputers. Agerwala has a PhD in electrical engineering from The Johns Hopkins University. He is a fellow of the IEEE, and a member of ACM."]}}, {'name': 'S. Chatterjee', 'bio': {'p': ['Siddhartha Chatterjee is a research staff member and manager at IBM Research. His research interests include all aspects of highperformance systems and software quality. Chatterjee has a PhD in computer science from Carnegie Mellon University. He is a senior member of IEEE, and a member of ACM and SIAM.']}} %*Computer architecture: challenges and opportunities for the next decade %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1463186 %f/micro/26fwndeyalklojniuzehqdbfhr4t7ik3.pdf %m47f7e1c24becf0c32eb29345916305b6 %cmicro %@[{'name': ' Jayanth Srinivasan', 'affiliation': 'Illinois Univ., Urbana, IL, USA', 'bio': {'p': ['Jayanth Srinivasan is a PhD candidate in computer science at the University of Illinois at Urbana-Champaign. His research focuses on reliability, power and temperature constraints for future architectures, and adaptive processors and systems. Srinivasan has an MS in computer science from the University of Illinois and a BTech from the Indian Institute of Technology, Madras. He is a recipient of the IBM PhD Fellowship and a student member of the IEEE and ACM. The bulk of the work in this article was performed while Srinivasan was an intern at IBM T.J. Watson Research Center during the summers of 2003 and 2004.']}}, {'name': 'S.V. Adve', 'affiliation': 'Illinois Univ., Urbana, IL, USA', 'bio': {'p': ['Sarita V. Adve is an associate professor in the Department of Computer Science at the University of Illinois at Urbana-Champaign. Her research interests are computer architecture, with a current focus on power-efficient and reliable systems. Adve received a PhD in computer science from the University of Wisconsin-Madison.']}}, {'name': ' Pradip Bose', 'bio': {'p': ['Pradip Bose is a research staff member and manager at the IBM T.J. Watson Research Center, as well as editor in chief of IEEE Micro. His current research interests include high-performance computer architectures, power- and complexity-aware design, and reliable systems. Bose has a PhD in electrical and computer engineering from the University of Illinois, Urbana-Champaign. He is a senior member of the IEEE and the IEEE CS and a member of the ACM.']}}, {'name': 'J.A. Rivers', 'bio': {'p': ['Jude A. Rivers is a research staff member at the IBM T.J. Watson Research Center. His research interests focus on high-performance computer architectures, and include memory systems architecture and power-, temperature-, and reliability-aware design. Rivers has a PhD in computer science and engineering from the University of Michigan, Ann Arbor. He is a member of the IEEE and ACM.']}} %*Lifetime reliability: toward an architectural solution %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1463187 %f/micro/vwasapziv4u6idsmq3hoz8gy0xnr2ec7.pdf %maf0373d1760673bd6159b6bb7f917bda %cmicro %@[{'name': 'M. Anguita', 'affiliation': 'Granada Univ., Spain', 'bio': {'p': ['Mancia Anguita is a professor at the Departamento de Arquitectura $y$ Tecnología de Computadores, Universidad de Granada. Her research interest included code optimization and parallel processing. Anguita has a PhD degree in computer science from the Universidad de Granada.']}}, {'name': 'J.M. Martinez-Lechado', 'bio': {'p': ['J. Manuel Martinez-Lechado is an engineer at Vitelcom Mobile Technology, a Spanish handset manufacturer. His experience includes working on projects for multimedia communication over the Internet and photographic stitching. Martinez-Lechado has an MSc in computer engineering from the Universidad de Granada.']}} %*MP3 optimization exploiting processor architecture and using better algorithms %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1463188 %f/micro/r4n6pzo80xcpimudl1vuqetgiyslchvn.pdf %m4a312fb53194609f02164313e4580cd2 %cmicro %@[{'name': 'P.G. Emma', 'affiliation': 'pemma@us.ibm.com', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/31458/1463189/1463189-photo-1-small.gif', 'p': ['Philip G. Emma is manager of the Systems Technology and Microarchitecture group at the IBM T.J. Watson Research Center. His research interests include computer architecture and microarchitecture, systems design, circuit design, electronic packaging, materials, interconnection technology, and optics. Emma has a BS, an MS, and a PhD in electrical engineering from the University of Illinois. He holds more than 100 patents and is an IBM Master Inventor. Emma is a member of the IBM Academy of Technology and a Fellow of the IEEE.']}} %*Inventions and the creative process %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1463189 %f/micro/2u0n3d1lhgthyipojbqxxvevebysao5w.pdf %m206e2e1a8b4bb581627c153969a10b60 %cmicro %@[{'name': 'P. Bose', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/32188/1498733/1498733-photo-1-small.gif', 'p': []}} %*Presilicon modeling: challenges in the late CMOS era %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1498733 %f/micro/14ehnvyqnsigp8ac7dxyzu6lqjj2hx0r.pdf %mc09db548bea904d86c08d4102bec5155 %cmicro %@[{'name': 'P.G. Emma', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/32188/1498734/1498734-photo-1-small.gif', 'p': ['']}} %*What is patentable? %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1498734 %f/micro/2f3qc5lehiywon7oxub4rtddmwktmaz1.pdf %m9d0696724c31f6c4f23eec5819b393f2 %cmicro %@[{'name': ' Zhichun Zhu', 'affiliation': 'Electr. & Comput. Eng., Illinois Univ., Chicago, IL, USA', 'bio': {'p': ['Zhichun Zhu is an assistant professor of electrical and computer engineering at the University of Illinois at Chicago. Her research interests include computer architecture, performance evaluation, and low-power designs. Zhu has a BS in computer engineering from Huazhong University of Science and Technology, China, and a PhD in computer science from the College of William and Mary. She is a member of the IEEE and the ACM.']}}, {'name': ' Xiadong Zhang', 'bio': {'p': ['Xiaodong Zhang is the Lettie Pate Evans Professor of Computer Science and the department chair at the College of William and Mary. His research interests include parallel and distributed computing and systems and computer architecture. Zhang has a BS in electrical engineering from Beijing Polytechnic University and an MS and a PhD, both in computer science, from the University of Colorado at Boulder. He is a senior member of the IEEE.']}} %*Look-ahead architecture adaptation to reduce processor power consumption %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1498735 %f/micro/nkzepg1qpj9rxoiaukdfanwmygbsrsbm.pdf %mada147429b29b402580894b2a6efd991 %cmicro %@[{'name': ' Yen-Jen Chang', 'affiliation': 'Dept. of Comput. Sci., Nat. Chung-Hsing Univ., Taichung, Taiwan', 'bio': {'p': ['Yen-Jen Chang is an assistant professor in the Department of Computer Science at National Chung-Hsing University, Taiwan. His research interests include computer architecture, low-power VLSI design, and embedded-system and SoC design. Chang has an MS in computer science and information engineering from Chung-Yuan Christian University, and a PhD in computer science and information engineering from National Taiwan University. He is a member of the IEEE.']}}, {'name': ' Feipei Lai', 'bio': {'p': ['Feipei Lai is a professor in the Department of Computer Science Information Engineering and the Department of Electrical Engineering at National Taiwan University. He is also the director of the Computer and Information Network Center at National Taiwan Uni-versity, His research interests include low-power computing, computer architectures, and VLSI SoC design. Lai has a BSEE from National Taiwan University and an MS and a PhD, both in computer science, from the University of Illinois at Urbana-Champaign. He is a senior member of the IEEE.']}} %*Dynamic zero-sensitivity scheme for low-power cache memories %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1498736 %f/micro/l6akw1cpai7hbvm3dujysvgxwq8lfz5n.pdf %m31d70ff660e9edbf7f27598beadc27ad %cmicro %@[{'name': 'J. Beecroft', 'bio': {'p': ['Jon Beecroft is the head of the hardware development team at Quadrics, where he is responsible for the design and development of the ASICs used in QsNet and QsNetII. His research interests include very high-performance general-purpose computing, especially methods for reducing latency to improve scalability. Beecroft has an honors degree in computer engineering from Manchester University.']}}, {'name': 'D. Addison', 'bio': {'p': ['David Addison is a senior software engineer at Quadrics, where he is responsible for the QsNetII message-passing libraries. His research interests include low-latency message-passing, advanced RDMA protocols and fault-tolerant runtime systems. Addison has a first-class honors degree in computer science from Warwick University.']}}, {'name': 'D. Hewson', 'bio': {'p': ['David Hewson is a senior design engineer at Quadrics, where he is responsible for software architecture for ultra-low latency interconnects and the development of the kernel-messaging system that TruCluster and Lustre use on Quadrics-powered supercomputers. Hewson has a first-class honors degree in mathematics from Durham University. He is a member of the Institute of Mathematics.']}}, {'name': 'M. McLaren', 'bio': {'p': ['Moray McLaren is the R&D manager at Quadrics, where he has overseen the development of the QsNet and QsNetII interconnects. His research interests include high-speed network design and supercomputer architecture. McLaren has a BSc in microelectronics from the University of Edinburgh.']}}, {'name': 'D. Roweth', 'bio': {'p': ['Duncan Roweth is a software research and development manager for Quadrics. His research interests include fault tolerance in parallel systems and the optimization of collectives. Roweth has a PhD in particle physics from Edinburgh University.']}}, {'name': 'F. Petrini', 'bio': {'p': ['Fabrizio Petrini is a laboratory fellow in the Applied Computer Science Group in the Computational Sciences and Mathematics Division at Pacific Northwest National Laboratory. His research interests include various aspects of supercomputers, such as high-performance interconnection networks and network interfaces, job-scheduling algorithms, parallel architectures, operating systems, and parallel-programming languages. Petrini has a Laurea and a PhD in computer science from the University of Pisa, Italy. He has received numerous awards from the Department of Energy for contributions to supercomputing projects, and from other organizations for scientific publications.']}}, {'name': 'J. Nieplocha', 'bio': {'p': ['Jarek Nieplocha is a laboratory fellow and the technical group leader of the Applied Computer Science Group in the Computational Sciences and Mathematics Division of the Fundamental Science Division at Pacific Northwest National Laboratory. He is also the chief scientist for the High-Performance Computing in Computational Sciences and Mathematics Division. His research interests include optimizing collective and one-sided communication operations on modern networks, runtime systems, parallel I/O, and scalable programming models. Nieplocha received a PhD in electrical and computer engineering from the University of Alabama.']}} %*QSNET/sup II/: defining high-performance network design %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1498738 %f/micro/85ewiby0wnkcguhqkgpayvpctrlz1osj.pdf %mbc87dbcc9ca4917a40cf1dbaad2b3d37 %cmicro %@[{'name': 'M.J. Akhbarizadeh', 'affiliation': 'Dept. of Electr. Eng., Texas Univ., Dallas, TX, USA', 'bio': {'p': ['Mohammad J. Akhbarizadeh is a PhD candidate in the Department of Electrical Engineering at the University of Texas at Dallas, and a student at the Center for Integrated Circuits and Systems. His research interests include all aspects of network processing systems. Akhbarizadeh has a BS in computer engineering from the University of Tehran, Iran, and an MS in electrical engineering from the University of Texas, Dallas. He is a student member of the IEEE.']}}, {'name': 'M. Nourani', 'affiliation': 'Dept. of Electr. Eng., Texas Univ., Dallas, TX, USA', 'bio': {'p': ['Mehrdad Nourani is an associate professor of electrical engineering at the University of Texas at Dallas. His research interests include SoC design and test, and packet processing devices. Nourani has a BS and an MS in electrical engineering from the University of Tehran, Iran, and a PhD in computer engineering from Case Western Reserve University, Cleveland, Ohio. He is a senior member of the IEEE Computer Society and the ACM.', 'Direct questions and comments about this article to Mehrdad Nourani, Center for Integrated Circuits and Systems, The University of Texas at Dallas, Richardson, TX 75083, nourani@utdallas.edu']}}, {'name': 'C.D. Cantrell', 'affiliation': 'Dept. of Electr. Eng., Texas Univ., Dallas, TX, USA', 'bio': {'p': ['Cyrus D. Cantrell is a professor of electrical engineering and physics, director of the Photonic Technology and Engineering Center, and associate dean of the School of Engineering and Computer Science at the University of Texas at Dallas. His research interests include nonlinear optics, fiber optic amplifiers, and optical communication systems. Cantrell has a BS in physics from Harvard University, and an MS and a PhD in physics from Princeton University. Cantrell is a Fellow of the IEEE and a recipient of the IEEE Third Millennium Medal.']}} %*Prefix segregation scheme for a TCAM-based IP forwarding engine %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1498739 %f/micro/atnhxj9iicary7ndk3obveyu5zk2vqgg.pdf %m60d1f58589a741589c7f89c80524c97f %cmicro %@[{'name': ' Weidong Wu', 'affiliation': 'Dept. of Electron. & Inf. Eng., Huazhong Univ. of Sci. & Technol., Hubei, China', 'bio': {'p': ["Weidong Wu is a PhD candidate in the Department of Electronics and Information Engineering at Huazhong University of Science and Technology, Wuhan, Hubei, People's Republic of China. His research interests include algorithms to improve Internet router performance and network management. Wu has a BS in mathematics from Central China Normal University. He is a member of the China Mathematics Association.", 'Direct questions and comments about this article to Weidong Wu, Department of Electronics and Information Engineering, Huazhong University of Science and Technology, Wuhan, 430074, P. R. China, wwdtylwt@public.wh.hb.cn.']}}, {'name': ' Jian Shi', 'affiliation': 'Dept. of Electron. & Inf. Eng., Huazhong Univ. of Sci. & Technol., Hubei, China', 'bio': {'p': ['Jian Shi is an associate professor in the Department of Electronics and Information Engineering at Huazhong University of Science and Technology. His research interests include quality of service (QoS) routing protocols and optimization in wireless/mobile networks, distributed network management and security technologies, and wireless sensor network architectures and protocols. Shi has a PhD in electronic science and technology from Huahzong University of Science and Technology. He is a member of the China Communication Association.']}}, {'name': ' Ling Zuo', 'affiliation': 'Dept. of Electron. & Inf. Eng., Huazhong Univ. of Sci. & Technol., Hubei, China', 'bio': {'p': ['Ling Zou is an associate professor in the Department of Electronics and Information Engineering at Huazhong University of Science and Technology. Her research interests include QoS guarantee in wireless and mobile networks, network traffic modeling and performance analysis, and flow and congestion control mechanisms. Zou has a PhD in electronic science and technology from Huazhong University of Science and Technology. She is a member of the China Communication Association.']}}, {'name': ' Bingxin Shi', 'affiliation': 'Dept. of Electron. & Inf. Eng., Huazhong Univ. of Sci. & Technol., Hubei, China', 'bio': {'p': ['Bingxin Shi is a professor in the Department of Electronics and Information Engineering at Huazhong University of Science and Technology. His research interests include computer network management, network simulation and performances analysis, mobile IP, and network performance monitoring. Shi has a BS from Huazhong University of Science and Technology. He is a member of the Expert Group of China Education and Research Network.']}} %*Power-efficient TCAMs for bursty access patterns %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1498740 %f/micro/pupwx3nsvakmygfmtzc5e0i1u6nr7i2s.pdf %m30ad8d3d284cb2e828d0a6bc210569a4 %cmicro %@[{'name': 'R.H. Stern', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/32188/1498741/1498741-photo-1-small.gif', 'p': []}} %*Standardization skullduggery update: UMTS standard %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1498741 %f/micro/dgp7lacekjtyphztq6xaez5risvk1u0d.pdf %m30268fb4555c2a232e7967f598fc0d8d %cmicro %@[{'name': 'S. Greenstein', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/32188/1498742/1498742-photo-1-small.gif', 'p': ['']}} %*Explorers and expanders, both early and late [commercial technology markets] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1498742 %f/micro/casp6ztgxf42bo5rnnmvabhf9whke8zq.pdf %mc15db4149f4fcc3f637e7ec33322f2d9 %cmicro %@[{'name': 'R. Mateosian', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/32188/1498743/1498743-photo-1-small.gif', 'p': []}} %*Going through the database %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1498743 %f/micro/6lbsofpzgbio2thvdm5etraucxnvnjha.pdf %m72043982f5fd62f02e360617e6a95d71 %cmicro %@[{'name': 'P. Bose', 'affiliation': 'IBM T.J. Watson Research Center', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/32640/1528449/1528449-photo-1-small.gif', 'p': ['']}} %*High performance at affordable power %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1528449 %f/micro/hisrjcbdyjwut3sq08wmpm7f6eco5y9z.pdf %mb87428a237adabd084de9e6757fc6739 %cmicro %@[{'name': 'K. Uchiyama', 'affiliation': 'Hitachi', 'bio': {'p': ["Kunio Uchiyama is a a senior chief researcher in Hitachi's Central Research Laboratory, where he is responsible for the research and development of microprocessors and SoCs. His interests include microprocessors, SoC architecture, and design automation tools. Uchiyama has a PhD in advanced applied electronics from the Tokyo Institute of Technology. He was awarded the Japanese national Medal of Honor with Purple Ribbon, and is a senior member of the IEEE."]}}, {'name': 'P. Bose', 'bio': {'p': ['Pradip Bose is a research staff member and manager at the IBM T.J. Watson Research Center, he is also editor in chief of IEEE Micro. His research interests include high-performance computer architectures, power-and reliability-aware design, and computer-aided design. Bose has a PhD in electrical and computer engineering from the University of Illinois, Urbana-Champaign. He is a senior member of the IEEE and the IEEE Computer Society, and a member of the ACM.']}} %*Guest Editors' Introduction: Energy-Efficient Design %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1528450 %f/micro/qnn4iusbf2zdw9cochkmu86f5xpy0jib.pdf %m1b2646b93741cc457410070838a53875 %cmicro %@[{'name': 'O. Takahashi', 'bio': {'p': ['Osamu Takahashi is an IBM senior technical staff member and the manager of the circuit design team for the synergistic processor element (SPE) developed at the Sony-Toshiba-IBM Design Center. Takahashi has a BS in engineering physics and an MS in electrical engineering, both from the University of California, Berkeley. He has a PhD in computer and mathematical sciences from Tohoku University, Sendai, Japan.']}}, {'name': 'S. Cottier', 'bio': {'p': ['Scott Cottier is responsible for memory arrays in the SPE of the Cell processor at the Sony-Toshiba-IBM Design Center. Cottier has a BS in electrical engineering from Texas A & M University.']}}, {'name': 'S.H. Dhong', 'bio': {'p': ['Sang H. Dhong is the chief hardware engineer at the Sony-Toshiba-IBM Design Center. His research interests include microprocessor design and CMOS technology. Dhong has a PhD in electrical engineering from the University of California, Berkeley. He is an IEEE Fellow.']}}, {'name': 'B. Flachs', 'bio': {'p': ['Brian Flachs served as architect, microarchitect, and unit logic lead for the SPE team at IBM Systems and Technology Group. His research interests include low-latency, high-frequency processors. Flachs has a BSEE from New Mexico State University and an MS and a PhD from Stanford University.']}}, {'name': 'J. Silberman', 'bio': {'p': ['Joel Silberman is a research staff member at the IBM T.J. Watson Research Center in Yorktown Heights, New York. His research interests include tradeoffs in microarchitecture and circuit performance of advanced cache memory and instruction issue logic. Silberman has a PhD in electrical engineering from Stanford University.']}} %*Power-conscious design of the Cell processor's synergistic processor element %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1528451 %f/micro/e5jqsruztmz3wyirghvx2a7ni9gjc64h.pdf %mc363427d3b7dde6369f7aa30ce18c678 %cmicro %@[{'name': 'S. Maeda', 'affiliation': 'Toshiba Corp., Japan', 'bio': {'p': ['Seiji Maeda is a research scientist at Toshiba Corp. His research interests include parallel and distributed computing, scheduling algorithms, and digital media application. Maeda has an MS in electrical engineering from Waseda University. He is a member of the IEEE, IEEE CS and IPSJ.', 'Direct questions and comments about this article to Seiji Maeda, Computer and Network Systems Laboratory, Corporate Research and Development Center, Toshiba Corp., 1, Komukai-Toshiba-cho, Saiwai-ku, Kawasaki, 212-8582, Japan, seiji.maeda@toshiba.co.jp.']}}, {'name': 'S. Asano', 'affiliation': 'Toshiba Corp., Japan', 'bio': {'p': ['Shigehiro Asano is a senior research scientist at Toshiba Corp. His research interests include parallel processors, media processors, and reconfigurable processors. Asano has an MS in information engineering from the Tokyo Institute of Technology. He is a member of the IEEE and IEEE CS.']}}, {'name': 'T. Shimada', 'affiliation': 'Toshiba Corp., Japan', 'bio': {'p': ['Tomofumi Shimada is a senior manager of the Embedded System Platform Development Core Technology Center at Toshiba Digital Media Network Co. His research interests include parallel and distributed computing, and the software architecture of consumer electronic devices. Shimada has an MS in theoretical physics from Waseda University. He is a member of the IEEE CS and IPSJ.']}}, {'name': 'K. Awazu', 'affiliation': 'Toshiba Corp., Japan', 'bio': {'p': ["Koichi Awazu is the manager of Toshiba's LSI Development Center. His research interests include distributed computing systems and companion applications. Awasu has a BS in mechanical engineering from the Nagoya Institute of Technology."]}}, {'name': 'H. Tago', 'affiliation': 'Toshiba Corp., Japan', 'bio': {'p': ['Haruyuki Tago is a design manager at Toshiba Corp. His research interests include highperformance microprocessor architecture, high-speed and low-power VLSI circuits, and VLSI design methodology. Tago has an MS in instrumentation engineering from Keio University. He is a member of the IEEE and IEICE.']}} %*A real-time software platform for the Cell processor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1528453 %f/micro/uhiltzkbfd2cjstsqbpamwf7gj5ke4oq.pdf %ma17729ff02b8511b3ffc0ccc96b35f14 %cmicro %@[{'name': 'T. Asano', 'affiliation': 'IBM Eng. & Technol. Service, Japan', 'bio': {'p': ['Toru Asano is a project manager at IBM Engineering and Technology Services, Japan. His research interests include semiconductor circuit design. Asano has a BS in electronic engineering from Keio University, Japan.', 'Direct questions and comments about this article to Toru Asano, 415–10 Kitanosho-cho, Omihachiman-shi, Shiga, 523–0806, Japan, tasano@jp.ibm.com.']}}, {'name': 'J. Silberman', 'bio': {'p': ['Joel Silberman is a researcher at the IBM T.J. Watson Research Center. His research interests include tradeoffs in the microarchitecture and circuit performance of advanced cache memory and instruction issue logic. Silberman has a PhD in electrical engineering from Stanford University.']}}, {'name': 'S.H. Dhong', 'bio': {'p': ['Sang H. Dhong is the chief hardware engineer at the Sony-Toshiba Design Center. His research interests include microprocessor design and CMOS technology. Dhong has a PhD in electrical engineering from the University of California at Berkeley. He is a Fellow of the IEEE.']}}, {'name': 'O. Takahashi', 'bio': {'p': ['Osamu Takahashi is a senior technical staff member and manager at IBM Systems and Technology Group. His research interests include circuit design for the synergistic processor element. Takahashi has a BS in engineering physics and MS in electrical engineering from the University of California, Berkeley.']}}, {'name': 'M. White', 'bio': {'p': ['Michael White is a logic and circuit designer at IBM Systems and Technology Group. His research interests include logic and circuit design./White has a BS in computer engineering from the Georgia Institute of Technology.']}}, {'name': 'S. Cottier', 'bio': {'p': ['Scott Cottier is responsible for memory arrays within the SPE of a Cell processor at IBM in Austin, Texas. His research interests include circuit design aspects of high-performance processors. Cottier has a BS in electrical engineering from Texas A&M University.']}}, {'name': 'T. Nakazato', 'bio': {'p': ['Takaaki Nakazato is a staff member at Broadband System LSI Development Center, Semiconductor Co., Toshiba Corp., Japan. His research interests include circuit design of SRAM macro in the cell processor. Nakazato has a BE and ME electronics engineering from the University of Tokyo.']}}, {'name': 'A. Kawasumi', 'bio': {'p': ['Atsushi Kawasumi is a staff member at Broadband System LSI Development Center, Semiconductor Co., Toshiba Corp., Japan. His research interests include research and development of ultra-high speed SRAM. Kawasumi has a BS and MS in pure and applied sciences from the University of Tokyo.']}}, {'name': 'H. Yoshihara', 'bio': {'p': ['Hiroshi Yoshihara is a circuit designer for memory arrays within the SPE of a Cell processor at Sony Computer Entertainment of America. His research interests include development and design of ultra-high speed SRAM. Yoshihara has a BE and ME in electronic engineering from the University of Kyushu.']}} %*Low-power design approach of 11FO4 256-Kbyte embedded SRAM for the synergistic processor element of a Cell processor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1528454 %f/micro/zg3uy5pok9zfaqdbkai64mgejxv0epht.pdf %m2f28c18dc6b37ca03d84cb31114b0b75 %cmicro %@[{'name': 'C. Isci', 'bio': {'p': ['Canturk Isci is a PhD candidate in the electrical engineering department at Princeton University. He was an intern at IBM T.J. Watson Research Center in summer of 2005, and summer and fall of 2004. His research interests include power-aware computing and workload characterizations for dynamic management. Isci has an MSc in VLSI system design from University of Westminster, London, an MA in electrical engineering from Princeton University, and a BS in electrical engineering from Bilkent University, Ankara, Turkey. He is a member of the IEEE.']}}, {'name': 'A. Buyuktosunoglu', 'bio': {'p': ['Alper Buyuktosunoglu is a research staff member at the IBM T.J. Watson Research Center. His research interests include high-performance, low-power computer architectures and digital microelectronic design. Buyuktosunoglu has a PhD and an MS in electrical and computer engineering from the University of Rochester and a BS in electrical engineering from Middle East Technical University, Ankara, Turkey. He is a member of the IEEE.']}}, {'name': 'M. Martonosi', 'bio': {'p': ['Margaret Martonosi is a professor of electrical engineering at Princeton University. Her research interests include computer architecture and the hardware-software interface, with particular focus on power-efficient systems and mobile computing. Martonosi has a PhD and an MS in electrical engineering from Stanford University and a BS in electrical engineering from Cornell University. She is a senior member of IEEE and a member of ACM, where she is vice-chair of ACM SIGARCH and recently served two terms on the board of directors for ACM SIGMETRICS.', 'Direct questions and comments about this article to Alper Buyuktosunoglu, IBM T.J. Watson Research Center, Yorktown Heights, NY 10598, alperb@us.ibm.com.']}} %*Long-term workload phases: duration predictions and applications to DVFS %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1528455 %f/micro/0rivxgkk3exs5u9lznjmzhigo6t8ndpw.pdf %md5193f2b12f03f5e3540bcca2e85c4ce %cmicro %@[{'name': 'Q. Wu', 'affiliation': 'Dept. of Comput. Sci., Princeton Univ., NJ, USA', 'bio': {'p': ["Qiang Wu is a PhD candidate in Princeton University's computer science department. His research interests include power-aware microprocessor design and control. Wu has an MS in electrical engineering from the University of Sydney and a BS in electrical engineering from Southeast University in China. He is a student member of the IEEE and ACM."]}}, {'name': 'P. Juang', 'bio': {'p': ['Philo Juang is a graduate student at Princeton University. His research interests include chip multiprocessors and sensor networks. Juang has a BSEE from the University of Virginia. He is a student member of IEEE.']}}, {'name': 'M. Martonosi', 'bio': {'p': ['Margaret Martonosi is a professor of electrical engineering at Princeton University. Her research interests include computer architecture and the hardware-software interface, with particular focus on power-efficient systems and mobile computing. Martonosi has a PhD and an MS from Stanford University, and a BS from Cornell University, all in electrical engineering. She is a senior member of IEEE and a member of ACM, where she is the vice chair of ACM SIGARCH.']}}, {'name': 'L.-S. Peh', 'bio': {'p': ['Li-Shiuan Peh is an assistant professor of electrical engineering at Princeton University. Her research interests include interconnection networks and parallel computer architectures. Peh has a PhD in computer science from Stanford University. She is a member of the IEEE and ACM.']}}, {'name': 'D.W. Clark', 'bio': {'p': ['Douglas W. Clark is a professor of computer science at Princeton University. His research interests include computer architecture, low-power techniques, and clocking and timing in digital systems. Clark has a PhD in computer science from Carnegie-Mellon University and a BS in engineering and applied science from Yale University.', 'Direct questions and comments about this article to Margaret Martonosi, Dept. of Electrical Engineering, Princeton University, Princeton, NJ 08544–5263, mrm@princeton.edu.']}} %*Formal control techniques for power-performance management %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1528456 %f/micro/zmkfbb3owqie8ztawrn7o94kyyhshtga.pdf %md6c8fa2fd717779ba5fcfd451875c152 %cmicro %@[{'name': 'D. Marculescu', 'affiliation': 'Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA', 'bio': {'p': ['Diana Marculescu is an associate professor of electrical and computer engineering at Carnegie Mellon University. Her research interests include energy-aware computing, CAD tools for low power systems, and emerging technologies (such as electronic textiles or ambient intelligent systems). Marculescu has an MS in computer science from “Politehnica” University of Bucharest, Romania, and a PhD in computer engineering from the University of Southern California.', 'Direct questions and comments about this article to Diana Marculescu, ECE Dept., Carnegie Mellon University, Hammerschlag Hall, 5000 Forbes Ave., Pittsburgh, PA 15213-3890, dianam@ece.cmu.edu.']}}, {'name': 'E. Talpes', 'affiliation': 'Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA', 'bio': {'p': ['Emil Talpes is a postdoctoral researcher in the Electrical and Computer Engineering Department of Carnegie Mellon University. His research interests include computer architecture and energy-aware computing. Talpes has an MS in computer science from the Polytechnic University of Bucharest, Romania, and a PhD in electrical and computer engineering from Carnegie Mellon University.']}} %*Energy awareness and uncertainty in microarchitecture-level design %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1528458 %f/micro/s90egzsa8ynahvivcutjkr1odq4m5twp.pdf %m89efea36ab9d54babf3f85602d05b7d1 %cmicro %@[{'name': 'J.B. Fromm', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/32640/1528459/1528459-photo-1-small.gif', 'p': ['', 'Jeffery B. Fromm is counsel in the Intellectual Property Practice Group at the Drinker Biddle & Reath law firm. He is an intellectual property attorney with more than 32 years experience at Hewlett-Packard and a principal focus on computing and imaging technologies. His areas of expertise include managing intellectual property portfolios and litigation, preparing and prosecuting patent applications (having prepared more than 100 in the patent area), and preparing IP infringement and validity opinions, allegations, and defenses. Fromm has a BS in physics and a BS in electrical engineering from the University of Pennsylvania and a JD magna cum laude from the Delaware Law School of Widener University. He is a member of the bar in Pennsylvania, California, and Colorado, and a registered patent attorney with the US Patent and Trademark Office.']}}, {'name': 'R.A. Skitol', 'bio': {'p': ['Robert A. Skitol is a senior partner in the Antitrust Practice Group within the Litigation Department at Drinker Biddle & Reath. He has over 30 years experience in all facets of antitrust and trade regulation, with a particular focus on antitrust aspects of mergers, acquisitions, and joint ventures. He is a former attorney-advisor to the chairman of the FTC and former special assistant to the director of the Bureau of Consumer Protection. Skitol has a BA in history from Hobart College and a JD degree from New York University Law School (Order of the Coif). He is a member of the American Bar Association, ABA Section of Antitrust Law (past cochair of the Computer Industry Committee), the DC Bar Antitrust and Trade Regulation Committee (past chair), and the Advisory Board of The American Antitrust Institute.']}} %*Update on the antitrust ghost in the standard-setting machine [patents] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1528459 %f/micro/zbdf9bc0sk2pmjanactevjmxyuu5hlp7.pdf %m45789600fa31d5e912045918cd25f177 %cmicro %@[{'name': 'P. Emma', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/32640/1528460/1528460-photo-1-small.gif', 'p': ['']}} %*Patents: to file or not to file? %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1528460 %f/micro/ddxzu2wtvsyxbswh0gvklocqhmlafmji.pdf %mc17a464117467715ba1a25e5e5b97e12 %cmicro %@[{'name': 'S. Greenstein', 'affiliation': 'Northwestern University', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/32640/1528462/1528462-photo-1-small.gif', 'p': []}} %*Outsourcing and climbing a value chain %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1528462 %f/micro/ffx6rhd8xpkosj3skqozatqrzm4cuwnc.pdf %m7fae0d07c94c8214b7eaddf48cfd458b %cmicro %@[{'name': 'P. Bose', 'affiliation': 'IBM', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/33228/1566548/1566548-photo-1-small.gif', 'p': []}} %*Designing microprocessors with robust functionality and performance %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1566548 %f/micro/qfloml4pyowavhaics2vbyrdtj1n87td.pdf %me09b8ca987b3039f27c104af08f20fdd %cmicro %@[{'name': 'S. Greenstein', 'affiliation': 'Northwestern University', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/33228/1566549/1566549-photo-1-small.gif', 'p': []}} %*Wireless access and electrical markets: Becoming similar? %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1566549 %f/micro/srhqyv7cxro6uqaztmdpybpfufixe9ow.pdf %m0668bb5017b1d9f374bec53a99bf9132 %cmicro %@[{'name': 'S.V. Adve', 'affiliation': 'University of Illinois at Urbana-Champaign', 'bio': {'p': ['Sarita V. Adve is a professor of computer science at the University of Illinois at Urbana-Champaign. Her research interests include energy-, temperature-, and reliability-aware computer architectures and systems. Adve has a PhD in computer science from the University of Wisconsin-Madison. She is a recipient of an Alfred P. Sloan Fellowship, a University Scholar of the University of Illinois, and a member of the IEEE, IEEE CS, and ACM SIGArch.']}}, {'name': 'P. Sanda', 'bio': {'p': ['Pia Sanda is a senior technical staff member with the IBM Systems and Technology Group. Her research interests include reliability and manufacturability-aware computing. Sanda is one of the founders of PICA (Picosecond Imaging Circuit Analysis) and has implemented PI CA for assuring robust microprocessors. She is currently studying the system effects of logic soft errors. She holds patents in PICA, accelerated soft-error testing, design algorithms for phase shift masks, and silicon device processing. Sanda has a PhD in physics and a BS in engineering, both from Cornell University. She is a senior member of the IEEE.', 'Direct questions and comments about this special issue to Sarita Adve, sadve@cs.uiuc.edu, or Pia Sanda, sanda@us.ibm.com.']}} %*Guest Editor's Introduction: Reliability-Aware Microarchitecture %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1566550 %f/micro/orhhks2an89bpfiud1qaty0evcjuyfbe.pdf %m257745301a1ebf6c182e79249d590f2d %cmicro %@[{'name': 'S. Borkar', 'affiliation': 'Intel Corp., Hillsboro, OR, USA', 'bio': {'p': ['Shekhar Borkar is director of microprocessor research at Intel Corp. His research interests include high-performance and low-power digital circuits, and high-speed signaling. Borkar has an MSc in physics from the University of Bombay and an MSEE from the University of Notre Dame. He is a member of IEEE and an Intel Fellow.', 'Direct questions and comments about this article to Shekhar Borkar, 2111 N.E. 25th Ave., Hillsboro, OR 97124, shekhar.y. borkar@intel.com.']}} %*Designing reliable systems from unreliable components: the challenges of transistor variability and degradation %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1566551 %f/micro/tb4uumlj2pbnhhalx8wkvsgyqjedvk3o.pdf %m8914c03464f06abd8e38a50f904496cf %cmicro %@[{'name': 'R.K. Iyer', 'affiliation': 'Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA', 'bio': {'p': ['Ravishankar K. Iyer is the George and Ann Fisher Distinguished Professor of Engineering and Director of the Coordinated Science Laboratory at the University of Illinois at Urbana-Champaign. His research interests include reliable and secure computing. Iyer has a PhD in electrical engineering from the University of Queensland, Australia. He is a Fellow of the IEEE, the ACM, and an Associate Fellow of the American Institute for Aeronautics and Astronautics.']}}, {'name': 'N.M. Nakka', 'affiliation': 'Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA', 'bio': {'p': ['Nithin M. Nakka is a doctoral student in the Coordinated Science Laboratory at the University of Illinois at Urbana-Champaign. His research interests include hardware-implemented techniques for reliability, security, and recovery. Nakka has an MS in electrical and computer engineering from the University of Illinois at Urbana-Champaign.', 'Zbigniew T. Kalbarczyk is a research professor in the Coordinated Science Laboratory at the University of Illinois at Urbana-Champaign. His research interests include automated design, implementation, and evaluation of dependable and secure computing systems. Kalbarczyk has a PhD in computer science from the Bulgarian Academy of Sciences. He is a member of the IEEE and the IEEE Computer Society.']}}, {'name': 'Z.T. Kalbarczyk', 'affiliation': 'Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA', 'bio': {'p': ['Subhasish Mitra is a principal engineer at Intel and a consulting assistant professor in the electrical engineering department of Stanford University. His research interests include robust system design, VLSI design and test, VLSI CAD, and computer architecture. Mitra has a PhD in electrical engineering from Stanford University.', 'Direct questions and comments about this article to Nithin M. Nakka, University of Illinois at Urbana Champaign, Coordinated Science Laboratory, 1308 West Main St., Urbana, IL 61801, nakka@crhc.uiuc.edu.', 'For further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/publications/dlib.']}}, {'name': 'S. Mitra'} %*Recent advances and new avenues in hardware-level reliability support %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1566553 %f/micro/pjwcit0cpz7h2uxgv8il9blnbmsg3km4.pdf %md6fc24d1d297482e7aa232e8bed9e37f %cmicro %@[{'name': 'G.P. Saggese', 'affiliation': 'Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA', 'bio': {'p': ['Giacinto P. Saggese is a postdoctoral research associate at the Center for Reliable and High-Performance Computing, University of Illinois, Urbana-Champaign. His research interests include system dependability and security, computer architecture, and the design and evaluation of high-performance systems targeting FPGAs and ASICs. Saggese has a PhD in electrical and computer engineering from the University of Naples, Italy. He is a member of the IEEE.']}}, {'name': 'N.J. Wang', 'bio': {'p': ['Nicholas J. Wang is a PhD candidate in the electrical and computer engineering department at the University of Illinois, Urbana-Champaign. His research interests include fault-tolerant computer architectures. Wang has an MS and a BS in electrical and computer engineering from the University of Illinois, Urbana-Champaign. He is a student member of the IEEE.']}}, {'name': 'Z.T. Kalbarczyk', 'bio': {'p': ['Zbigniew T. Kalbarczyk is a research professor in the Coordinated Science Laboratory at the University of Illinois at Urbana-Champaign. His research interests include automated design, implementation, and evaluation of dependable and secure computing systems. Kalbarczyk has a PhD in computer science from the Bulgarian Academy of Sciences. He is a member of the IEEE and the IEEE Computer Society.']}}, {'name': 'S.J. Patel', 'bio': {'p': ['Sanjay J. Patel is an associate professor of electrical and computer engineering, and the Willett Faculty Scholar at the University of Illinois, Urbana-Champaign. He is also chief architect at Ageia Technologies. His research interests include processor microarchitecture, computer architecture, and high-performance and reliable computer systems. Patel has a PhD, an MS, and a BS in computer science and engineering, all from the University of Michigan, Ann Arbor. He is a member of the IEEE.']}}, {'name': 'R.K. Iyer', 'bio': {'p': ['Ravishankar K. Iyer is the director of the Coordinated Science Laboratory and the George and Ann Fisher Distinguished Professor of Engineering at the University of Illinois, Urbana-Champaign. His research interests include reliable and secure computing. Iyer has a PhD in electrical engineering from University of Queensland, Australia. He is an IEEE and ACM Fellow, and an Associate Fellow of the American Institute for Aeronautics and Astronautics.', 'Direct questions and comments about this article to Giacinto Saggese, 260 CSL, 1308 West Main, Urbana, IL 61801, saggese@uiuc.edu.', 'For further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/publications/dlib.']}} %*An experimental study of soft errors in microprocessors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1566554 %f/micro/dz8v7toj203rfjvaglku1rm6cxtzbyos.pdf %mbe926766ff11df57526a832ecde7bbd7 %cmicro %@[{'name': 'Z. Lu', 'affiliation': 'Charles L. Brown Dept. of Electr. & Comput. Eng., Virginia Univ., Charlottesville, VA, USA', 'bio': {'p': ['Zhijian Lu is a PhD candidate in the Charles L. Brown Department of Electrical and Computer Engineering at the University of Virginia. His research interests include low-power, high-performance computing systems and system-level design automation. Lu has a BE in automation engineering from Tsinghua University, China. He is a student member of the IEEE and the ACM.']}}, {'name': 'J. Lach', 'affiliation': 'Charles L. Brown Dept. of Electr. & Comput. Eng., Virginia Univ., Charlottesville, VA, USA', 'bio': {'p': ['John Lach is an assistant professor in the Charles L. Brown Department of Electrical and Computer Engineering at the University of Virginia. His research interests include dynamically adaptable and real-time embedded systems, fault-and defect-tolerant hardware design, and CAD techniques for VLSI. Lach has a BS from Stanford University and an MS and a PhD, both in electrical engineering, from UCLA.']}}, {'name': 'M.R. Stan', 'affiliation': 'Charles L. Brown Dept. of Electr. & Comput. Eng., Virginia Univ., Charlottesville, VA, USA', 'bio': {'p': ['Mircea R. Stan is an associate professor in the Charles L. Brown Department of Electrical and Computer Engineering at the University of Virginia. His research interests include high-performance, low-power VLSI, temperature-aware circuits and architecture, embedded systems, and nanoelectronics. Stan has a diploma in electronics and communications from Politechnica University in Bucharest, Romania, and MS and PhD degrees in electrical and computer engineering from the University of Massachusetts at Amherst. He is a senior member of the IEEE, and a member of the ACM, Usenix, Eta Kappa Nu, Phi Kappa Phi, and Sigma Xi.']}}, {'name': 'K. Skadron', 'bio': {'p': ['Kevin Skadron is an associate professor in the Department of Computer Science at the University of Virginia. His research interests include how multi-threaded and multi-core organizations in the context of power, temperature, and reliability constraints are changing processor architecture. Skadron has a PhD in computer science from Princeton University and a BS in computer science from Rice University. He is a member of Eta Kappa Nu, Omicron Delta Epsilon, ACM, and a senior member of IEEE and the IEEE Computer Society and Circuits and Systems Society.', 'Direct questions and comments about this article to Zhijian Lu, Dept. of Electrical and Computer Engineering, University of Virginia, 351 McCormick Road, Charlottesville, VA 22904, z14j@virginia.edu.']}} %*Improved thermal management with reliability banking %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1566555 %f/micro/nequovikfruvcxialnqs4hjyel1zt5dx.pdf %m9010eb32afe05a020fea7ac38f21a8b0 %cmicro %@[{'name': 'B.T. Gold', 'affiliation': 'Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA', 'bio': {'p': ['Brian T. Gold is a PhD student in electrical and computer engineering at Carnegie Mellon University. His research interests include reliable computer systems and parallel computer architectures. Gold has an MS in computer engineering from Virginia Tech. He is a student member of the IEEE and ACM.']}}, {'name': 'J. Kim', 'affiliation': 'Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA', 'bio': {'p': ['Jangwoo Kim is a PhD student in electrical and computer engineering at Carnegie Mellon University. His research interests include reliable server architecture and full system simulation. Kim has an MEng in computer science from Cornell University. He is a student member of the IEEE.']}}, {'name': 'J.C. Smolens', 'affiliation': 'Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA', 'bio': {'p': ['Jared C. Smolens is a PhD student in electrical and computer engineering at Carnegie Mellon University. His research interests include microarchitecture, multiprocessor architecture, and performance modeling. Smolens has an MS in electrical and computer engineering from Carnegie Mellon University. He is a student member of the IEEE.']}}, {'name': 'E.S. Chung', 'affiliation': 'Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA', 'bio': {'p': ['Eric S. Chung is a PhD student in electrical and computer engineering at Carnegie Mellon University. His research interests include designing and prototyping scalable, reliable server architectures and transactional memory. Chung has a BS in electrical and computer engineering from the University of California at Berkeley. He is a student member of the IEEE and ACM.']}}, {'name': 'V. Liaskovitis', 'affiliation': 'Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA', 'bio': {'p': ['Vasileios Liaskovitis is an MS student in electrical and computer engineering at Carnegie Mellon University. His research interests include computer architecture and algorithms for pattern recognition. Liaskovitis has a BS in electrical and computer engineering from the National Technical University of Athens, Greece. He is a student member of IEEE and ACM.']}}, {'name': 'E. Nurvitadhi', 'affiliation': 'Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA', 'bio': {'p': ['Eriko Nurvitadhi is a PhD student in electrical and computer engineering at Carnegie Mellon University. He received an MS in computer engineering from Oregon State University. His research interests are in computer architecture, including prototyping and transactional memory. He is a student member of the IEEE and ACM.']}}, {'name': 'B. Falsafi', 'affiliation': 'Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA', 'bio': {'p': ['Babak Falsafi is an associate professor of electrical and computer engineering and Sloan Research Fellow at Carnegie Mellon University. His research interests include computer architecture with emphasis on high-performance memory systems, nanoscale CMOS architecture, and tools to evaluate computer system performance. Falsafi has a PhD in computer science from the University of Wisconsin and is a member of the IEEE and ACM.']}}, {'name': 'J.C. Hoe', 'affiliation': 'Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA', 'bio': {'p': ['James C. Hoe is an associate professor of electrical and computer engineering at Carnegie Mellon University. His research interests include computer architecture and high-level hardware description and synthesis. Hoe has a PhD in electrical engineering and computer science from MIT. He is a member of the IEEE and ACM.']}}, {'name': 'A.G. Nowatzyk', 'bio': {'p': ['Andreas G. Nowatzyk is the associate director of the Minimally Invasive Surgery Technology Institute at the Cedars-Sinai Medical Center, where he works on highly reliable, high-performance computer systems that process real-time image data in operating rooms. Nowatzyk has a PhD in computer science from Carnegie Mellon University. He is a member of the IEEE and ACM.', 'Direct questions and comments about this article to Babak Falsafi, Electrical and Computer Engineering Dept., Carnegie Mellon University, 5000 Forbes Ave, Pittsburgh, PA 15213, babak@ece.cmu.edu.']}} %*TRUSS: a reliable, scalable server architecture %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1566557 %f/micro/rvpxtuyusoy2nfksdc5xlboql0g7an9v.pdf %m7172161324a4604709aac8a313739318 %cmicro %@[{'name': 'M.W. Rashid', 'affiliation': 'Dept. of Electr. & Comput. Eng., Rochester Univ., NY, USA', 'bio': {'p': ['M. Wasiur Rashid is a PhD candidate in the Department of Electrical and Computer Engineering at the University of Rochester. His research interests include energy-aware and fault-tolerant microprocessor architectures. He has an MS in Electrical Engineering from the University of Rochester. He is a student member of IEEE. Contact him at rashid@ece.rochester.edu.']}}, {'name': 'E.J. Tan', 'affiliation': 'Dept. of Electr. & Comput. Eng., Rochester Univ., NY, USA', 'bio': {'p': ['Edwin J. Tan is a doctoral candidate in the Department of Electrical and Computer Engineering at the University of Rochester. His research interests include fault-tolerant computer architectures, digital and analog VLSI circuit design, and image processing. He has an MS in Electrical Engineering from the University of Rochester. He is a student member of IEEE, TBP, and HKN. Contact him at etan@ece.rochester.edu.']}}, {'name': 'M.C. Huang', 'affiliation': 'Dept. of Electr. & Comput. Eng., Rochester Univ., NY, USA', 'bio': {'p': ['Michael C. Huang is an assistant professor in the Department of Electrical and Computer Engineering and the Department of computer Science at the University of Rochester. His research interests include computer system architecture and processor microarchitecture, with emphases on adaptive architecture, power-aware design, reliability, and system optimization. Huang has a PhD in computer science from the University of Illinois at Urbana-Champaign. He is a member of the IEEE Computer Society and the ACM.']}}, {'name': 'D.H. Albonesi', 'bio': {'p': ['David H. Albonesi is an associate professor in the Computer Systems Laboratory at Cornell University. His research interests span single and multiple processors and threads, with particular interests in adaptive, power-efficient, and reliability-aware computer architectures, and microarchitectures exploiting new technologies. Albonesi has a PhD in computer engineering from the University of Massachusetts Amherst. He is a senior member of the IEEE Computer Society and a member of the ACM.', 'Direct questions and comments about this article to Michael C. Huang, 414 Computer Studies Building, Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY 14627, michael.huang@rochester.edu']}} %*Power-efficient error tolerance in chip multiprocessors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1566558 %f/micro/pdbmhjcfiprtmwyfs3av41jzescgblew.pdf %m80ab96774286c14725e1803f857de71e %cmicro %@[{'name': 'D. Stasiak', 'affiliation': 'Syst. & Technol. Group, IBM Corp., Austin, TX, USA', 'bio': {'p': ['Daniel Stasiak is with the Systems and Technology Group (STG) at IBM in Austin, Texas, and served at the power team lead in the Cell processor development project.']}}, {'name': 'R. Chaudhry', 'affiliation': 'Syst. & Technol. Group, IBM Corp., Austin, TX, USA', 'bio': {'p': ['Rajat Chaudhry is with STG at IBM in Austin, Texas, and was one of the lead developers for the Capet methodology within the Cell processor power estimation and management team.']}}, {'name': 'D. Cox', 'bio': {'p': ['Dennis Cox is a distinguished engineer within STG at IBM in Rochester, Minnesota, engaged in general research and development work related to the Engineering and Technology Services function within STG.']}}, {'name': 'S. Posluszny', 'bio': {'p': ['Stephen Posluszny is with STG at IBM in Austin, Texas, and is a member of the STI Design Center Tools and Methodology department.']}}, {'name': 'J. Warnock', 'bio': {'p': ['Jim Warnock is a distinguished engineer within STG at IBM in Yorktown Heights, New York. He served at the circuit team lead for the Cell processor project.']}}, {'name': 'S. Weitzel', 'bio': {'p': ['Steve Weitzel is with STG at IBM in Austin, Texas, and he was a contributing member of the Cell power team.']}}, {'name': 'D. Wendel', 'bio': {'p': ['Dieter Wendel is a distinguished engineer within the eServer hardware development team of STG at IBM in Boeblingen, Germany.']}}, {'name': 'M. Wang', 'bio': {'p': ['Michael Wang is within the PowerPC microprocessor development team, part of STG at IBM in Austin, Texas, he was a contributing member of the Cell power team.', 'Direct questions and comments about this article to Dan Stasiak, IBM Corp., 11501 Burnet Road, Bldg. 906, Austin, TX 78758, stasiak@us.ibm.com.']}} %*Cell processor low-power design methodology %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1566559 %f/micro/0sqakex4dtrlthy97wxakvbcir6zyqjc.pdf %m10429fead640ffcc587ea2c795b58b2b %cmicro %@[{'name': 'P. Emma', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/33228/1566560/1566560-photo-1-small.gif', 'p': ['']}} %*Writing the claims for a patent %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1566560 %f/micro/yewv4pjpkta5jtq3sbalcycnfokb68gh.pdf %m1fd6cde3519eea342585b79f3bbd6e05 %cmicro %@[{'name': 'R. Mateosian', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/33228/1566561/1566561-photo-1-small.gif', 'p': []}} %*Year-end cleanup %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1566561 %f/micro/p3bjrfdivwelh56cxh0c27fxa1ytodus.pdf %me40235bf9551bab31995cf70e9f82e5b %cmicro %@[{'name': 'R.H. Stern', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/33228/1566562/1566562-photo-1-small.gif', 'p': []}} %*Transnational electronic systems and patent infringement %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1566562 %f/micro/zmgbv4yqouwyldw6uhnxljethdxqmpke.pdf %m7aac52495e835793a35290d0d4efa924 %cmicro %@[{'name': 'P. Bose', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/28393/1268971/1268971-photo-1-small.gif', 'p': []}} %*EIC's Message New challenges and burning issues %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1268971 %f/micro/852jp7emqwuxrvyos9mkiclrp64of3eb.pdf %m365d80c8031c464cbaffbafe6ed9c6a1 %cmicro %@[{'name': 'R.H. Stern', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/28393/1268979/1268979-photo-1-small.gif', 'p': ['Richard H. Stern']}} %*Micro law %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1268979 %f/micro/7mzkbkecyibg1jawpueqfo8n2loytard.pdf %m5739e7a908213aaeb74b4f9549f3858b %cmicro %@[{'name': 'J.B. Lyles', 'affiliation': 'Sprint', 'bio': {'p': ['J. Bryan Lyles is an independent consultant. He has been senior scientist at Sprint, a member of the research staff at Xerox Palo Alto Research Center, and an acting professor at Linkoping University, Sweden. His research interests include networking and distributed systems. Lyles has a PhD in computer science from The University of Rochester. He has served on numerous program committees and was the program committee chair for Hot Interconnects 11 He is a member of the IEEE and the ACM.', 'Direct questions and comments about this special issue to J. Bryan Lyles, 2403 Laura Lane Ave., Mountain View, CA 94043, jblyles@acm.org.']}} %*Guest editor's introduction - hot interconnects 11- solving network bottlenecks %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1268983 %f/micro/ek4rsmvjdl5n6yf9uoq0n1w8lysemgq7.pdf %m9723189813d4ec82ea713186dd89747b %cmicro %@[{'name': 'J. Hurwitz', 'affiliation': 'Div. of Comput. & Computational Sci., Los Alamos Nat. Lab., NM, USA', 'bio': {'p': ["Justin (Gus) Hurwitz is a member of the Research and Development in Advanced Network Technology (Radiant) team in the Computer and Computational Sciences Division at Los Alamos National Laboratory. His research interests include protocol and operating-system design for high-performance networking and general approaches to fair utilization and optimization of finite resources. Hurwitz has a bachelor's degree in liberal arts from St. John's College and will pursue graduate degrees in intellectual property and constitutional law and computer science starting this fall."]}}, {'name': 'W.-C. Feng', 'affiliation': 'Div. of Comput. & Computational Sci., Los Alamos Nat. Lab., NM, USA', 'bio': {'p': ['Wu-chun Feng is a technical staff member and team leader of the Research and Development in Advanced Network Technology (Radiant) team in the Computer and Computational Sciences Division at Los Alamos National Laboratory and a fellow of the Los Alamos Computer Science Institute. His research interests include high-performance networking and computing, network protocols and architecture, bioinformatics, and cybersecurity. Feng has a BS in electrical and computer engineering and music, and an MS in computer engineering from Pennsylvania State University. He has a PhD in computer science from the University of Illinois at Urbana-Champaign. He is a member of the IEEE and the ACM.', "Direct questions and comments about this article to Gus Hurwitz, Computer and Computational Sciences Division, Los Alamos Nat'l Lab., PO Box 1663, MS D451, Los Alamos, NM 87545, ghurwitz@lanl.gov."]}} %*End-to-end performance of 10-gigabit Ethernet on commodity systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1268985 %f/micro/cbxglxi12vonfm3zqumyw7zpq5bfks8r.pdf %m7e2d4fbddd63bbf4a7152702eb13b67f %cmicro %@[{'name': 'G. Regnier', 'affiliation': 'Intel Corp., USA', 'bio': {'p': ["Greg Regnier is a principal engineer in Intel's Corporate Technology Group. His industry experience includes massively parallel computing systems, such as the FPS T-Series, the Touchstone Delta Supercomputer, and the Intel Paragon Supercomputer, he was a principal developer of the Virtual Interface Architecture. His current research interest is improving the scalability and performance of data center networks using standard networking media and protocols. Regnier has a BS in computer science from St. Cloud State University in Minnesota. He is a member of IEEE Computer Society."]}}, {'name': 'D. Minturn', 'affiliation': 'Intel Corp., USA', 'bio': {'p': ["Dave Minturn is a senior architect and software engineer in Intel's Corporate Technology Group. His industry experience includes work on parallel supercomputers, I/O sub-systems, networking protocols, network processors, and file systems, current research interests include investigating threading models and other optimizations to efficiently scale TCP/IP packet processing on IA-32 processors. Minturn has a BS in computer science from Northern Arizona University."]}}, {'name': 'G. McAlpine', 'affiliation': 'Intel Corp., USA', 'bio': {'p': ["Gary McAlpine is a system architect in Intel's Communications Technology Lab. His industry experience includes the founding of a company, Aptec Computer Systems, where he developed high-speed multiprocessor systems for use in high-end data collection and realtime applications for signal and image processing. At Intel, he helped develop the Virtual Interface architecture, NGIO (Next-Generation I/O, an InfiniBand precursor), PCI-Express Advanced Switching, and ETA."]}}, {'name': 'V.A. Saletore', 'affiliation': 'Intel Corp., USA', 'bio': {'p': ['Vikram A. Saletore is a staff software engineer with Intel Research and Development, where he works on kernel-and user-level ETA. His research interests include high-speed TCP, network interfaces, operating systems, and distributed computing. Saletore has an MS in electrical engineering from the University of California, Berkeley, and a PhD in electrical engineering from the University of Illinois, Urbana-Champaign. He is a Member of the IEEE Computer Society.']}}, {'name': 'A. Foong', 'affiliation': 'Intel Corp., USA', 'bio': {'p': ['Annie Foong is a senior research engineer at Intel Research and Development. Her research interests include implementation issues for improving network protocol performance. Foong has a PhD in electrical and computer engineering from the University of Wisconsin-Madison.', "Information in this document is provided in connection with Intel products. No license, express or implied, to any Intellectual property rights is granted by this document. Except as provided in Intel's terms and conditions of sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right."]}} %*ETA: experience with an Intel Xeon processor as a packet processing engine %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1268989 %f/micro/6yeekm8bdtr7j4tnqcgds3hqaoijusyu.pdf %m08d533028b767111c4ee55ee46ff424b %cmicro %@[{'name': 'A. Lines', 'bio': {'p': ['Andrew Lines is CTO and cofounder of Fulcrum Microsystems where his responsibilities include asynchronous-circuit design, architecture, CAD tools, and general technology development. Lines has an MS in computer science from the California Institute of Technology. He is a member of the IEEE.', 'Direct questions and comments about this article to Andrew Lines, Fulcrum Microsysterns, 26775 Malibu Hills Rd., Calabasas, CA 91301, lines@fulcrummicro.com.']}} %*Asynchronous interconnect for synchronous SoC design %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1268991 %f/micro/yt1wsl6ojz0xe4pggxiezctbjk2kb5v8.pdf %m5481f29bf745f79d8f3ff84051d9b89d %cmicro %@[{'name': 'J. Liu', 'affiliation': 'Ohio State Univ., Columbus, OH, USA', 'bio': {'p': ['Jiuxing Liu is a PhD student in the Computer and Information Science Department at The Ohio State University. His research interests include high-speed interconnects, cluster computing, and storage systems. Liu has a BS and an MS in computer science from Shanghai Jiao Tong University, China. He is a member of the IEEE.']}}, {'name': ' Balasubramanian Chandrasekaran', 'affiliation': 'Ohio State Univ., Columbus, OH, USA', 'bio': {'p': ['Balasubramanian Chandrasekaran is a systems engineer at the Scalable Enterprise Computing Lab, Dell Computer Corp. His research interests include high-speed interconnects, high-performance computing, and virtualization of data centers. Chandrasekaran has an MS in computer science from The Ohio State University. He is a member of the IEEE and ACM.']}}, {'name': 'W. Yu', 'affiliation': 'Ohio State Univ., Columbus, OH, USA', 'bio': {'p': ['Weikuan Yu is a PhD student in the Computer and Information Science Department at The Ohio State University. His research interests include cluster computing, resource management, and bioinformatics. Yu has an MS in molecular, cellular, and developmental biology from The Ohio State University. He is a member of the IEEE Computer Society.']}}, {'name': 'J. Wu', 'affiliation': 'Ohio State Univ., Columbus, OH, USA', 'bio': {'p': ['Jiesheng Wu is a PhD student in the Computer and Information Science Department at The Ohio State University. His research interests include parallel and distributed computing with a focus on file, storage, and communication systems. He is a member of the IEEE and the Usenix Association.']}}, {'name': 'D. Buntinas', 'affiliation': 'Ohio State Univ., Columbus, OH, USA', 'bio': {'p': ['Darius Buntinas is a postdoctoral researcher in the Mathematical and Computer Science Division of the Argonne National Laboratory. His research interests include communication support for programming models and using programmable network interface cards to improve cluster performance. Buntinas has a PhD in computer science from The Ohio State University, and an MS and a BS in computer science from Loyola University in Chicago. He is a member of the IEEE and the IEEE Computer Society.']}}, {'name': ' Sushmitha Kini', 'affiliation': 'Ohio State Univ., Columbus, OH, USA', 'bio': {'p': ['Sushmitha Kini is a software engineer with the Windows Server group, Microsoft Corp. Her research interests include collective communication, high-performance computing, and directory services. Kini has an MS in computer and information science from The Ohio State University. She is a member of the IEEE.']}}, {'name': 'D.K. Panda', 'affiliation': 'Ohio State Univ., Columbus, OH, USA', 'bio': {'p': ["Dhabaleswar K. Panda is a professor of computer science at The Ohio State University. His research interests include parallel computer architecture, high-performance computing, user-level communication protocols, interprocessor communication and synchronization, network-based computing, and quality of service. Panda has a PhD in computer engineering from the University of Southern California. He received a National Science Foundation Faculty Early Career Development Award, The Ohio State University's Lumley Research Award, and an Ameritech Faculty Fellow Award. He is a member of the IEEE Computer Society and ACM."]}}, {'name': 'P. Wyckoff', 'bio': {'p': ['Pete Wyckoff is a research scientist at the Ohio Supercomputer Center. His research interests include high-performance networking and parallel file systems. Wyckoff has a PhD from the Massachusetts Institute of Technology. He is a member of the ACM.', 'Direct questions and comments about this article to Jiuxing Liu, 395 Dreese Lab, Computer and Information Science Department, 2015 Neil Ave., Columbus, OH 43210, liuj@cis.ohio-state.edu.']}} %*Microbenchmark performance comparison of high-speed cluster interconnects %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1268994 %f/micro/fr9txjgoga2kbm5edsr0cwzulx7mickn.pdf %m3505c124c2eea4eef614e82e15e44ebc %cmicro %@[{'name': ' Sarang Dharmapurikar', 'affiliation': 'Washington Univ., St. Louis, MO, USA', 'bio': {'p': ['Sarang Dharmapurikar is a PhD student in the Department of Computer Science and Engineering, Washington University in St. Louis. His research interests include various aspects of high-speed networking system design, including packet classification and forwarding, payload inspection and intrusion detection, and packet buffering and queuing. Dharmapurikar has a BS in electrical and electronics engineering from the Birla Institute of Technology and Science, Pilani, India.']}}, {'name': ' Praveen Krishnamurthy', 'affiliation': 'Washington Univ., St. Louis, MO, USA', 'bio': {'p': ['Todd S. Sproull is a PhD student in computer engineering and a research assistant at the Applied Research Laboratory, Washington University in St. Louis. His research interests include the control and configuration of reprogrammable systems, and distributed computing. Sproull has a BS in electrical engineering from Southern Illinois University, Edwardsville, and an MS in computer engineering from Washington University in St. Louis.']}}, {'name': 'T.S. Sproull', 'affiliation': 'Washington Univ., St. Louis, MO, USA', 'bio': {'p': ["Praveen Krishnamurthy is a PhD student at Washington University in St. Louis. His research interests include networking systems design, data mining, and optical interconnection networks. Krishnamurthy has a bachelor's degree in engineering from the University of Madras, India, and an MS in computer engineering from Washington University in St. Louis."]}}, {'name': 'J.W. Lockwood', 'affiliation': 'Washington Univ., St. Louis, MO, USA', 'bio': {'p': ['John W. Lockwood is an assistant professor at Washington University in St. Louis. His research interests include the design and implementation of networking systems in reconfigurable hardware. He developed the Field-Programmable Port Extender (FPX) to enable rapid prototyping of extensible network modules. Lockwood has a BS, an MS, and a PhD from the University of Illinois, Urbana-Champaign. He is a member of the IEEE, the ACM, Tau Beta Pi, and Eta Kappa Nu.', 'Direct questions and comments about this article to Sarang Dharmapurikar, sarang@arl.wustl.edu. Additional information about the project is online at http://www.arl.wustl.edu/arl/projects/fpx/reconfig.htm.']}} %*Deep packet inspection using parallel bloom filters %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1268997 %f/micro/hyfdbuxvqs9lnt4h5rbtveolazpjd8ck.pdf %m1443927feb855a2c60ac66c04a42fdb9 %cmicro %@[{'name': 'D.V. Schuehler', 'affiliation': 'Washington Univ., St. Louis, MO, USA', 'bio': {'p': ['David V. Schuehler is a PhD candidate in the Applied Research Laboratory at Washington University in St. Louis. He is also vice president of research and development for Reuters. His research interests include realtime processing, embedded systems, and high-speed networking. Schuehler has a BS in aeronautical and astronautical engineering from Ohio State University and an MS in computer science from the University of Missouri-Rolla. He is a member of the IEEE and the ACM.']}}, {'name': 'J. Moscola', 'affiliation': 'Washington Univ., St. Louis, MO, USA', 'bio': {'p': ['James Moscola is a PhD candidate at Washington University in St. Louis. His research interests include digital content protection and deep packet inspection. Moscola has a BS in physical science from Muhlenberg College, and a BS in computer engineering and an MS in computer science, both from Washington University in St. Louis.']}}, {'name': 'J.W. Lockwood', 'affiliation': 'Washington Univ., St. Louis, MO, USA', 'bio': {'p': ['John W. Lockwood is an assistant professor at Washington University in St. Louis. His research interests include designing and implementing networking systems in reconfigurable hardware, and he developed the Field-Programmable Port Extender to enable rapid prototyping of extensible network modules. Lockwood has a BS, an MS, and a PhD in electrical and computer engineering from the University of Illinois. He is a member of the IEEE, the ACM, Tau Beta Pi, and Eta Kappa Nu.']}} %*Architecture for a hardware-based, TCP/IP content-processing system %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1269000 %f/micro/rylt6umarsuqojwskbxqfveifzhx4ndb.pdf %mccb124869c806fd96643bc0a7254de3f %cmicro %@[{'name': 'R. Mateosian'} %*Micro Review - Single sourcing mount fuji %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1269006 %f/micro/xfwn5uf1nswytebcoqc93hamivbj7jde.pdf %m92d49a388f3330f8f99e06f954ff9d17 %cmicro %@[{'name': ' ', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/28393/1269009/1269009-photo-1-small.gif', 'p': ['Shane Greenstein']}} %*Why inventors are not famous %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1269009 %f/micro/1f0u4xocxw9jluma6mhpsqifacksjzny.pdf %me9001d091e27e332dbe967832cc2d84e %cmicro %@[{'name': 'C. Moore', 'affiliation': 'The University of Texas at Austin', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/28393/1269011/1269011-photo-1-small.gif', 'p': ["Charles Moore is a senior research Fellow at The University of Texas at Austin. Previously, he was the chief engineer on IBM's Power4 and PowerPC 601 micro-processors."]}} %*Parting Thoughts - Managing the transition from complexity to elegance: design convergence %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1269011 %f/micro/ajcds3psxkevjz7frmnx0llkcwb5yuq8.pdf %m3ee707ae749c37b2b089bc004f7d396f %cmicro %@[{'name': 'P. Bose', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/28738/1289253/1289253-photo-1-small.gif', 'p': ['Pradip Bose']}} %*Chip-level microarchitecture trends %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1289253 %f/micro/7fqxhkdwatrjsqbu2ti4enprlc6p35dw.pdf %m9286303a2dd5b151f2b7c35e6ae67941 %cmicro %@[{'name': 'R.H. Stern', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/28738/1289271/1289271-photo-1-small.gif', 'p': ['Richard H. Stern']}} %*Challenging search engines and pop-ups under copyright law-part 3 %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1289271 %f/micro/zalxf7ekcok8oepcjwnbzypwbt26xfql.pdf %me0f2f3f06a1668ab45141ea3863ead4d %cmicro %@[{'name': 'M. Flynn', 'affiliation': 'Stanford University', 'bio': {'p': ['Michael Flynn is emeritus professor of electrical engineering at Stanford University. His early work experience was at IBM, where he was a design manager for various early mainframe computers, including the IBM System 360 Model 91. Beginning in 1975 Flynn directed the computer architecture and arithmetic group at Stanford until his retirement in 1999. Flynn has a PhD from Purdue University in electrical engineering. He received the ACM/IEEE Eckert-Mauchley Award, the IEEE CS Harry Goode Memorial Award, and the Tesla Medal from the International Tesla Society (Belgrade). He also has an honorary doctor of science from Trinity College, Ireland, and is a Fellow of the IEEE and the ACM.']}}, {'name': 'P. Dubey', 'bio': {'p': ["Pradeep Dubey is a senior principal engineer and manager of innovative platform architecture in the Corporate Technology Group at Intel. His research interests include computer architectures for new application paradigms in future computing environments. Dubey previously worked at the IBM T.J. Watson Research Center and at Broadcom. He was one of the principal architects for the AltiVec multimedia extension to the PowerPC architecture. He also worked on the design, architecture, and performance issues of various microprocessors, including Intel's 80386, 80486, and Pentium processors. Dubey has a BS in electronics and communication engineering from Birla Institute of Technology, India, an MSEE from the University of Massachusetts at Amherst, and a PhD in electrical engineering from Purdue University. He holds 18 patents and is an IEEE Fellow."]}} %*Hot chips 15 - scaling the silicon mountain %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1289275 %f/micro/hrsz1zacrajjilhne9wmcmdwukoyuxq0.pdf %m11de1d236c66d615e02e6fbe115b5c79 %cmicro %@[{'name': 'S. Rusu', 'affiliation': 'Intel Corp., Santa Clara, CA, USA', 'bio': {'p': ["Stefan Rusu is a senior principal engineer at Intel's Enterprise Processor Division, leading the technology and special-circuits design group for Itanium. His research interests include high-speed clocking, power distribution, I/O buffers, and low-power and high-speed circuit design techniques. Rusu has an MSEE from the Polytechnic Institute in Bucharest, Romania. He is a senior member of the IEEE and has served on the technical program committee for the European Solid-State Circuit Conference for many years. He holds 17 US patents."]}}, {'name': 'H. Muljono', 'affiliation': 'Intel Corp., Santa Clara, CA, USA', 'bio': {'p': ['Harry Muljono is a senior staff engineer at Intel. His research interests include I/O design and validation. Muljono has a BS in electrical engineering from University of Pordand, and a MEng in electrical engineering from Cornell University. He holds 16 patents.']}}, {'name': 'B. Cherkauer', 'affiliation': 'Intel Corp., Santa Clara, CA, USA', 'bio': {'p': ["Brian Cherkauer is a design engineer at Intel's Enterprise Processor Division, working on next-generation Itanium processors. His research interests include power estimation and power reduction techniques. Cherkauer has a BSEE from the State University of New York, Buffalo, and a PhD in electrical engineering from the University of Rochester."]}} %*Itanium 2 processor 6M: higher frequency and larger L3 cache %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1289279 %f/micro/pof4vu2fsy8mlxveeaxityc7dgdnzgnl.pdf %m1731956a1980708ea482698bcf30a8cf %cmicro %@[{'name': ' Sanjiv Kapil', 'affiliation': 'Sun MicroSystems, Sunnyvale, CA, USA', 'bio': {'p': ['Sanjiv Kapil is the lead architect for the processor design. His research interests include modeling microprocessor performance and high-speed interconnect architectures. He has an MTech in computer science from the Indian Institute of Technology, New Delhi.']}}, {'name': 'H. McGhan', 'affiliation': 'Sun MicroSystems, Sunnyvale, CA, USA', 'bio': {'p': ['Harlan McGhan is the strategic marketing manager for UltraSparc processors. His research interests include the history of computers and trends in microprocessor design. He has a BA in philosophy from Michigan State University and is pursuing a PhD in the history and logic of science from Princeton University.']}}, {'name': 'J. Lawrendra', 'affiliation': 'Sun MicroSystems, Sunnyvale, CA, USA', 'bio': {'p': ["Jesse Lawrendra is the senior engineering manager for the processor's front-end design. His research interests include design reusability and effective approaches to building a system on a chip integrating multiple complex IPs. He has an MS in electrical engineering from the University of California, Davis, and an MBA from UC Berkeley."]}} %*A chip multithreaded processor for network-facing workloads %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1289288 %f/micro/ycvalgemjtoxi8l0e6mxpcahpfnz5qy1.pdf %ma0bf8aebec285a1020f0f03e89365f34 %cmicro %@[{'name': ' Deepu Talla', 'affiliation': 'Imaging & Audio Group, Texas Instruments, Dallas, TX, USA', 'bio': {'p': ['Deepu Talla is a system architect in the Imaging and Audio Group at Texas Instruments. His research interests include computer architecture, workload characterization, performance evaluation and benchmarking, multimedia processing, and application-specific integrated circuit and field-programmable gate array design. Talla has a PhD in computer engineering from The University of Texas at Austin. He is a member of the IEEE, the IEEE Computer Society, the IEEE Signal Processing Society, the ACM, and the ACM SIGARCH.']}}, {'name': 'C.-Y. Hung', 'affiliation': 'Imaging & Audio Group, Texas Instruments, Dallas, TX, USA', 'bio': {'p': ['Ching-Yu Hung is a system architect in the Imaging and Audio Group and a senior member of technical staff at Texas Instruments. His research interests include parallel computer architecture, imaging and video algorithms, and hardware/software algorithms. Hung has a PhD in electrical engineering from the University of California at Santa Barbara. He is a member of the IEEE, the IEEE Computer Society, and the IEEE Signal Processing Society.']}}, {'name': ' Raj Talluri', 'affiliation': 'Imaging & Audio Group, Texas Instruments, Dallas, TX, USA', 'bio': {'p': ['Raj Talluri is general manager of the Imaging and Audio Group and an emeritus distinguished member of the technical staff at Texas Instruments. Talluri has a PhD in electrical engineering from The University of Texas at Austin. He is a member of the IEEE.']}}, {'name': 'F. Brill', 'affiliation': 'Imaging & Audio Group, Texas Instruments, Dallas, TX, USA', 'bio': {'p': ['Frank Brill is a program manager in the Imaging and Audio Group and a member of the group technical staff at Texas Instruments. His research interests are computer vision, robotics, and autonomous video monitoring. Brill has a PhD in computer science from the University of Virginia at Charlottesville.']}}, {'name': 'D. Smith', 'affiliation': 'Imaging & Audio Group, Texas Instruments, Dallas, TX, USA', 'bio': {'p': ['David Smith is a senior design engineer in the Imaging and Audio Group and a member of the group technical staff at Texas Instruments. Smith has an MS in engineering from Harvey Mudd College.']}}, {'name': 'D. Brier', 'affiliation': 'Imaging & Audio Group, Texas Instruments, Dallas, TX, USA', 'bio': {'p': ['David Brier is a senior design engineer in the Imaging and Audio Group and a senior member of the technical staff at Texas Instruments.']}}, {'name': 'B. Xiong', 'affiliation': 'Imaging & Audio Group, Texas Instruments, Dallas, TX, USA', 'bio': {'p': ['Bruce Xiong is a design engineer in the Imaging and Audio Group at Texas Instruments. He has an MS in electrical engineering from the University of Houston. Xiong is a member of the IEEE, the IEEE Communications Society, the IEEE Computer Society, and the IEEE Signal Processing Society.']}}, {'name': 'D. Huynh', 'affiliation': 'Imaging & Audio Group, Texas Instruments, Dallas, TX, USA', 'bio': {'p': ['Derek Huynh is a design and verification engineer in the Imaging and Audio Group at Texas Instruments.']}} %*Anatomy of a portable digital mediaprocessor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1289289 %f/micro/dy2khnersjxpueaiyrk8vq1fvi9pm4x6.pdf %m5e6cce26996b7ee686bea781df9d38b1 %cmicro %@[{'name': 'R. Kalla', 'bio': {'p': ['Ron Kalla is the lead engineer for IBM Power5 systems, specializing in processor core development. His research interests include computer micro-architecture and post-silicon hardware verification. Kalla has a BSEE in electrical engineering from the University of Minnesota.']}}, {'name': ' Balaram Sinharoy', 'bio': {'p': ['Balaram Sinharoy is the chief scientist for the IBM Power5 microprocessor. His research interests include advanced microprocessor design, computer architecture, and performance analysis. Sinharoy has a BS in physics, a BTech in computer science and electrical engineering from the University of Calcutta, and an MS and a PhD in computer science from Rensselaer Polytechnic Institute. He is an IBM Master Inventor and a senior member of the IEEE.']}}, {'name': 'J.M. Tendler', 'bio': {'p': ["Joel M. Tendler is the program director of technology assessment for the IBM Systems and Technology Group in Austin, Texas. His research interests include computer systems design, architecture, and performance. Tendler has a bachelor's degree in engineering from The Cooper Union, and a PhD in electrical engineering from Syracuse University. He is a member of the IEEE and the Computer Society."]}} %*IBM Power5 chip: a dual-core multithreaded processor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1289290 %f/micro/q9fuvdr2hujgy1mlyfohro68lczebxsg.pdf %mc730bf34987cfebdd2f3eef39a074963 %cmicro %@[{'name': 'U. Cummings', 'affiliation': 'Fulcrum Microsystems, CA, USA', 'bio': {'p': ['Uri Cummings is cofounder and vice president of product development at Fulcrum Microsystems. His research interests include optical component design and asynchronous circuit design. Cummings has a BS and an MS in electrical engineering from Caltech.']}} %*PivotPoint: clockless crossbar switch for high-performance embedded systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1289291 %f/micro/lmgj9ube8cpewvpotsr7uc3nkoyyadgt.pdf %me85185e0bb956482e25264a54fc6b4dc %cmicro %@[{'name': 'V.C. Ravikumar', 'affiliation': 'Texas A&M Univ., College Station, TX, USA', 'bio': {'p': ['Ravikumar V.C. is a system designer at Hewlett-Packard. His research interests include networking, operating systems, and embedded systems. He has an MS degree in computer science from Texas A&M University.']}}, {'name': 'R.N. Mahapatra', 'affiliation': 'Texas A&M Univ., College Station, TX, USA', 'bio': {'p': ['Rabi N. Mahapatra is an associate professor with the Department of Computer Science at Texas A&M University. His research interests include embedded-system codesign, system on chips, VLSI design, and system architectures. Mahapatra has a PhD from the Indian Institute of Technology, Kharagpur. He is a senior member of the IEEE Computer Society.', 'Direct questions and comments to Rabi N. Mahapatra, Dept. of Computer Science, Texas A&M Univ., College Station, TX 77845, rabi@cs.tamu.edu.']}} %*TCAM architecture for IP lookup using prefix properties %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1289292 %f/micro/ucmw50rekqfnfvao6burimdatxiyzwdo.pdf %mca4219f58962f01ef6d969d8885cdd5f %cmicro %@[{'name': 'S. Greenstein', 'affiliation': 'Northwestern Univ., Evanston, IL, USA', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/28738/1289293/1289293-photo-1-small.gif', 'p': ['Shane Greenstein']}} %*The paradox of commodities %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1289293 %f/micro/x4j0wr7siptoeffqmhjhu6ovut1zlkkd.pdf %m32967038a48f7641ecd7f8163cdba055 %cmicro %@[{'name': 'C. Moore', 'affiliation': 'Texas Univ., Austin, TX, USA', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/28738/1289295/1289295-photo-1-small.gif', 'p': ["Charles Moore is a senior fellow at Advanced Micro Devices where he is responsible for the architecture of a next-generation microprocessor. Previously, he was the chief engineer on IBM's Power4 and PowerPC 601 microprocessors, and most recently, he was a senior research fellow at The University of Texas at Austin."]}} %*Getting it right [functional microprocessor verification] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1289295 %f/micro/7k6ayympdhjvwx8tcgzf2r3nfjmks0vt.pdf %m63e17ae9638426c825cfb6390dde022a %cmicro %@[{'name': 'P. Bose', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/29085/1310259/1310259-photo-1-small.gif', 'p': []}} %*EIC's Message: General-purpose versus application-specific processors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1310259 %f/micro/cv9u5qr0ehanzxe2mv1ldyghn46sapjd.pdf %mef6b5b82753ec7d41474c6122339f252 %cmicro %@[{'name': 'R.H. Stern', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/29085/1310260/1310260-photo-1-small.gif', 'p': []}} %*Collecting patent infringement damages on unpatented products %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1310260 %f/micro/zju7cqp4rflciywauqbkmgbx0owryths.pdf %mceee63ef622aafe77f0d04cfe14d9f3e %cmicro %@[{'name': 'A. Veidenbaum', 'affiliation': 'University of California, Irvine', 'bio': {'p': ['Alex Veidenbaum is an associate professor in the Department of Computer Science at the University of California at Irvine. His research interests include computer architecture, com-pilers, and embedded systems. Veidenbaum has a PhD in computer science from the University of Illinois at Urbana-Champaign. He is a member of the IEEE Computer Society and the ACM', 'Direct questions and comments about this issue to Alex Veidenbaum, Department of Computer Science, University of California at Irvine, Irvine, CA 92697-3425, alexv@ics.uci.edu.']}} %*Guest Editor's Introduction: Application-Specific Processors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1310261 %f/micro/bzjxkr8ami93qq4cyjnondplwolcrgke.pdf %m5f43c9aede22fe77de34d0d6f509e2ca %cmicro %@[{'name': 'P. Petrov', 'affiliation': 'Dept. of Comput. Sci. & Eng., California Univ., San Diego, CA, USA', 'bio': {'p': ['Peter Petrov is pursuing a PhD in computer science and engineering at the University of California, San Diego. His research interests include application-specific embedded processors, low-power processors, and hardware-software codesign. Petrov has a BS and an MS, both in computer science, from Sofia University, Sofia, Bulgaria.']}}, {'name': 'A. Orailoglu', 'affiliation': 'Dept. of Comput. Sci. & Eng., California Univ., San Diego, CA, USA', 'bio': {'p': ['Alex Orailoglu is a professor of computer science and engineering at the University of California, San Diego. His research interests include digital and analog test, fault-tolerant computing, computer-aided design, and embedded processors. Orailoglu has an SB in applied mathematics from Harvard University and an MS and a PhD, both in computer science, from the University of Illinois, Urbana-Champaign. He is a member of the IEEE Test Technology Technical Council (TTTC) Executive Committee and a Golden Core member of the IEEE Computer Society.']}} %*Transforming binary code for low-power embedded processors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1310263 %f/micro/s3hvsaqyxpmzcb8kq6mcjwoinhabpwyk.pdf %md9efcbf34c8398ed0d7c3b0443b5f22c %cmicro %@[{'name': 'A. Hodjat', 'affiliation': 'Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA', 'bio': {'p': ['Alireza Hodjat is pursuing a PhD in the Electrical Engineering Department at the University of California, Los Angeles. His research interests include hardware architectures and VLSI implementation for embedded and domain-specific processors and coprocessors. Hodjat has an MS in embedded computing systems from UCLA. He is a student member of the IEEE.']}}, {'name': 'I. Verbauwhede', 'affiliation': 'Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA', 'bio': {'p': ['Ingrid Verbauwhede is an associate professor in the Electrical Engineering Department at UCLA. Her research interests include architecture design, VLSI implementation, and design methods for low-power embedded systems. Verbauwhede has a PhD from KU Leuven, Belgium. She is a senior member of the IEEE.']}} %*High-throughput programmable cryptocoprocessor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1310264 %f/micro/3w9j5yzt7ubvxn1k0iqdegmor8b4ilgq.pdf %m751bee70ae154a150dfcef5cd3987d82 %cmicro %@[{'name': 'M. Meyer', 'affiliation': 'Stuttgart Univ., Germany', 'bio': {'p': ['Matthias Meyer is a research group leader at the Institute of Communication Networks and Computer Engineering at the University of Stuttgart, Germany. His research interests include digital systems design, computer architecture, compiler construction, garbage collection, and Java. Meyer has a Diploma degree from the University of Stuttgart in Electrical Engineering.']}} %*A novel processor architecture with exact tag-free pointers %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1310265 %f/micro/jkt1zrw9cmcvudbl58ag4sxeyfxitqdp.pdf %m421a4e341f2d0b34a4edbadd7db42810 %cmicro %@[{'name': 'F. Karim', 'affiliation': 'STMicroelectronics, La Jolla, CA, USA', 'bio': {'p': ["Faraydon Karim is an ST Fellow at STMicro-electronics, and he leads a group of researchers in ST's Advanced System Technology Laboratory in La Jolla, Calif His research interests include computer architecture and multi-processing. Karim has a PhD in computer engineering from LaSalle University."]}}, {'name': 'A. Mellan', 'affiliation': 'STMicroelectronics, La Jolla, CA, USA', 'bio': {'p': ["Alain Mellan leads the MLCA research team in STMicroelectronics' Advanced System Technology Lab. His research interests include embedded parallel architectures, system design automation, and functional programming languages. Mellan has an Engineering Diploma from Ecole Nationale Superieure des Arts et Metiers, Paris."]}}, {'name': 'A. Nguyen', 'affiliation': 'STMicroelectronics, La Jolla, CA, USA', 'bio': {'p': ["Anh Nguyen is a research engineer in STMicroelectronics' Advanced Computing Lab. His research interests include performance analysis, resource allocation, and algorithm development. Nguyen has a PhD in electrical engineering from UCLA."]}}, {'name': 'U. Aydonat', 'bio': {'p': ['Utku Aydonat is a graduate student in the Edward S. Rogers Sr. Department of Electrical and Computer Engineering at the University of Toronto. His research interests include computer architecture and compilers. Aydonat has BSc in electrical and electronics engineering from the Middle East Technical University of Ankara.']}}, {'name': 'T. Abdelrahman', 'bio': {'p': ['Tarek Abdelrahman is a professor of electrical and computer engineering at the University of Toronto. His research interests include compiler optimizations for parallelism and virtual machine design. Abdelrahman has a PhD in computer science and engineering from the University of Michigan at Ann Arbor. He is a member of the ACM and the Advanced Computing Systems Association (USENIX).', 'Direct questions and comments about this article to Alain Mellan, STMicroelectronics, 4690 Executive Dr., PO Box 919028, San Diego, CA 92121, alain.mellan@st.com.', 'For further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/publications/dlib.']}} %*A multilevel computing architecture for embedded multimedia applications %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1310266 %f/micro/de20631qjnexortfck9rswvzuihbfb7g.pdf %m310c3a287fcb49001fadd0f70366c009 %cmicro %@[{'name': 'S. Greenstein', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/29085/1310267/1310267-photo-1-small.gif', 'p': ['']}} %*Imitation happens [micro economics] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1310267 %f/micro/nfqmds3rewju970talxqzcbs5fragbux.pdf %mc989eee4687669ecc0c0978f3f2295e1 %cmicro %@[{'name': 'R. Mateosian', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/29085/1310268/1310268-photo-1-small.gif', 'p': []}} %*Back to the future %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1310268 %f/micro/ajgh0fnztbvskeguxklni64u3rf1iycy.pdf %m02c5bc7eed6e06fa7d9d81604b312938 %cmicro %@[{'name': 'P. Bose', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/29395/1331270/1331270-photo-1-small.gif', 'p': []}} %*Editor in Chief's Message: Saving power-Lessons from embedded systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1331270 %f/micro/j2scqwfugetl7mjtad5yrkzwn3comlaq.pdf %mdf3458cd66ef3265e7f85b13951c4955 %cmicro %@[{'name': 'R.H. Stern', 'affiliation': 'r.stern@computer.org', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/29395/1331271/1331271-photo-1-small.gif', 'p': ['']}} %*FTC turns back challenge on patent coverage %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1331271 %f/micro/3poyiujevsa9jnz4c2hkqxpezg8rybim.pdf %m96e461e60ab59b560979dc545bda1ca8 %cmicro %@[{'name': 'A. Bechini', 'affiliation': 'University of Pisa, Italy', 'bio': {'p': ["Alessio Bechini is a researcher at Dipartimento di Ingegneria dell'Informazione, University of Pis a, Italy. His research interests include theoretical and practical aspects of concurrent computing, particularly in the field of system-level design/analysis of embedded systems. Bechini has an MS in electronics engineering and a PhD in information engineering, both from the University of Pisa. He is a member of the IEEE Computer Society."]}}, {'name': 'T.M. Conte', 'bio': {'p': ['Thomas M. Conte is a professor of electrical and computer engineering and director of the Center for Embedded Systems Research at North Carolina State University. His research interests include computer architecture, computer optimization, performance analysis, and embedded system design. Conte has an MS and a PhD, both in electrical engineering from the University of Illinois, Urbana-Champaign. He is a member of the IEEE Computer Society and the ACM.']}}, {'name': 'C.A. Prete', 'bio': {'p': ["Cosimo Antonio Prete is a professor of information engineering at Dipartimento di Ingegneria dell'Informazione, University of Pis a, Italy. His research interests include embedded system design, performance evaluation, and multiprocessor architecture and usability. Prete has an MS and a PhD, both in information engi-neering, from the University of Pis a, Italy. He is a member of the IEEE Computer Society.", 'Direct questions and comments about this issue to Thomas M. Conte, Center for Embedded Systems Research, North Carolina State University, Raleigh, NC 27695, conte@ncsu.edu.']}} %*Guest Editors' Introduction: Opportunities and Challenges in Embedded Systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1331272 %f/micro/7fsqto8b3qdv1wzmdizrw5r0yyeaxchb.pdf %m052747dd332242292fa82b26ee3b493f %cmicro %@[{'name': 'A.G. Dean', 'affiliation': 'North Carolina State Univ., Raleigh, NC, USA', 'bio': {'p': ['Alexander G. Dean is an assistant professor at North Carolina State University and is associate director of the Center for Embedded Systems Research. His research interests in embedded systems include compilers, computer architecture, and networks. Dean has a PhD and an MS in Computer Engineering from Carnegie Mellon University. He is a member of the IEEE and ACM.']}} %*Efficient real-time concurrency on low-cost microcontrollers %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1331273 %f/micro/e6rkxwmzapdh24plhuo3tiyi7sb9tu0c.pdf %m19d0f0ed27ca60a1ea98e3cfdb39efda %cmicro %@[{'name': 'F.J. Cazorla', 'affiliation': 'Polytech Univ. Catalonia, Spain', 'bio': {'p': ['Francisco J. Cazorla is a doctoral candidate at the Polytechnic University of Catalonia (UPC), Spain. His research interests include instruction fetch policies for SMT architectures. Cazorla has BS and MS degrees in computer science from the University of Las Palmas de Gran Canaria, Spain.']}}, {'name': 'A. Ramirez', 'affiliation': 'Polytech Univ. Catalonia, Spain', 'bio': {'p': ['Alex Ramirez is an assistant professor in the Computer Architecture Department at UPC. His research interests include profile-guided compiler optimization, code layout optimization, and design and implementation of superscalar and multithreaded processors. Ramirez has a PhD in computer science from UPC.']}}, {'name': 'M. Valero', 'affiliation': 'Polytech Univ. Catalonia, Spain', 'bio': {'p': ['Mateo Valero is a professor in the Computer Architecture Department at UPC. His research interests include high-performance architectures. Valero has a PhD in telecomunications from UPC. He is an IEEE Fellow, an Intel Distinguished Research Fellow, and an ACM Fellow. Since 1994 he is a foundational member of the Royal Spanish Academy of Engineering.']}}, {'name': 'P.M.W. Knijnenburg', 'bio': {'p': ['Peter M.W. Knijnenburg is an assistant professor of computer science at the Leiden Institute of Advanced Computer Science, Leiden University, The Netherlands. His research interests include adaptive and iterative compilation, interaction of compilers and computer architectures, and computer architecture. He has a PhD in computer science from Utrecht University.']}}, {'name': 'R. Sakellariou', 'bio': {'p': ['Rizos Sakellariou is a lecturer in computer science at the Department of Computer Science, University of Manchester, UK. His research interests include high-performance, parallel and distributed systems. He has a PhD in computer science from University of Manchester. Enrique Fernández is a professor in the Computer Science and Systems Department at the University of Las Palmas de Gran Canaria (ULPGC). His research interests include high-performance architectures. He has an industrial engineering degree from the Polytechnic University of Las Palmas and a PhD in computer science from ULPGC.']}}, {'name': 'E. Fernandez', 'bio': {'p': ['Enrique Fernandez is a professor in the Computer Science and Systems Department at the University of Las Palmas de Gran Canaria (ULPGC). His research interests include high-performance architectures. He has an industrial engineering degree from the Polytechnic University of Las Palmas and a PhD in computer science from ULPGC']}} %*QoS for high-performance SMT processors in embedded systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1331275 %f/micro/fxu5dvigw1bplka8rq7zlmetczyadcbf.pdf %mff943eefbc73e416fa74484909ba8121 %cmicro %@[{'name': 'T. Suh', 'affiliation': 'Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA', 'bio': {'p': ['Taeweon Suh is a PhD student in the School of Electrical and Computer Engineering, Georgia Institute of Technology. His research interests include embedded systems, computer architecture, DSPs, and networks. Suh has a BS in electrical engineering from Korea University and an MS in electronics engineering from Seoul National University. He is a student member of ACM.']}}, {'name': 'H.-H.S. Lee', 'affiliation': 'Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA', 'bio': {'p': ['Hsien-Hsin S. Lee is an assistant professor in the School of Electrical and Computer Engineering, Georgia Institute of Technology. His research interests include microarchitecture, low-power systems, design automation, and security. Lee has a BSEE from National Tsinghua University, Taiwan, and an MSE and PhD in computer science and engineering from the University of Michigan. He is a member of ACM and IEEE.']}}, {'name': 'D.M. Blough', 'affiliation': 'Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA', 'bio': {'p': ['Douglas M. Blough is a professor of electrical and computer engineering at the Georgia Institute of Technology. His research interests include parallel and distributed systems, dependability and security, and wireless ad hoc networks. Blough has a BS in electrical engineering and MS and PhD degrees in computer science from the Johns Hopkins University, Baltimore. He is a senior member of IEEE.', 'Send questions and comments to Taeweon Suh, Hsien-Hsin S. Lee, and Douglas M. Blough, School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia 30332–0250, {suhtw, leehs, doug.blough}@ece.gatech.edu.']}} %*Integrating cache coherence protocols for heterogeneous multiprocessor systems. 1 %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1331277 %f/micro/9dv8npzhgqfmvcn7tzrxxydw2ujwgske.pdf %m1b1c046dee217883b7bb0f551d147acb %cmicro %@[{'name': 'D. Andrews', 'affiliation': 'Kansas Univ., Lawrence, KS, USA', 'bio': {'p': ['David Andrews is an associate professor in the Electrical Engineering and Computer Science Department at the University of Kansas. His research interests include embedded systems architectures, and parallel and reconfigurable computing. Andrews has a BS and an MS, both in electrical engineering, from the University of Missouri, Columbia, and a PhD in computer science from Syracuse University. He is a senior member of the IEEE.']}}, {'name': 'D. Niehaus', 'affiliation': 'Kansas Univ., Lawrence, KS, USA', 'bio': {'p': ['Douglas Niehaus is an associate professor in the Electrical Engineering and Computer Science Department at the University of Kansas. His research interests include the design and implementation of real-time and distributed systems, operating systems, system and network performance evaluation, and tools for programming environments. Niehaus has a PhD in computer science from the University of Massachusetts, Amherst.']}}, {'name': 'R. Jidin', 'affiliation': 'Kansas Univ., Lawrence, KS, USA', 'bio': {'p': ['Razali Jidin is a research assistant at the Information and Telecommunication Technology Center and a PhD candidate in electrical engi-neering at the University of Kansas. His research interests include embedded system, hardware-software codesign, and computer architecture. Jidin has an MSEE from the University of Bridgeport, Connecticut, and an MSEE from the University of Leeds, England. He is a member of IEEE.']}}, {'name': 'M. Finley', 'affiliation': 'Kansas Univ., Lawrence, KS, USA', 'bio': {'p': ['Michael Finley is pursuing an MS in computer science at the University of Kansas. His research interests include the use of FPGAs to simplify system software by moving traditional software functionality to within FPGAs. Finley has a BS in electrical engineering from the University of Kansas.']}}, {'name': 'W. Peck', 'affiliation': 'Kansas Univ., Lawrence, KS, USA', 'bio': {'p': ['Wesley Peck is a research assistant at the Information and Telecommunication Technology Center and a PhD candidate in computer science at the University of Kansas. His research interests include algorithm design, hardware-software codesign and real-time operating systems. Peck has a BS in computer science from the University of Kansas.']}}, {'name': 'M. Frisbie', 'affiliation': 'Kansas Univ., Lawrence, KS, USA', 'bio': {'p': ['Michael Frisbie is a staff engineer at Garmin International Inc. His research interests include embedded systems software and operating systems design. Frisbee has an MS and a BS in computer science from the University of Kansas.']}}, {'name': 'J. Ortiz', 'affiliation': 'Kansas Univ., Lawrence, KS, USA', 'bio': {'p': ['Jorge Ortiz is a PhD candidate and is a research assistant in electrical engineering at the University of Kansas. His research interests include hardware-software codesign and reconfigurable hardware for real-time and embedded systems. Ortiz has a BS and an MS in computer engineering from the University of Kansas.']}}, {'name': ' Ed Komp', 'affiliation': 'Kansas Univ., Lawrence, KS, USA', 'bio': {'p': ['Ed Komp is a research engineer at the Information and Telecommunication Technology Center at the University of Kansas. His research interests include specialized computer language design for application-specific domains, functional programming, software development environments, and networking. Komp has a BA in mathematics and an MS in computer science from the University of Kansas.']}}, {'name': 'P. Ashenden', 'bio': {'p': ['Peter Ashenden is director of Ashenden Designs Pty Ltd. His research interests include electronic design automation and computer architecture. Ashenden has a BS and a PhD in electrical engineering from Adelaide University, South Australia. He is a senior member of the IEEE and a member of the ACM.']}} %*Programming models for hybrid FPGA-cpu computational components: a missing link %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1331278 %f/micro/xi0urgoekmeanlshfrz4mi3c6ya9upt5.pdf %m639d86cbcbc64eed2d32f0e4da85daba %cmicro %@[{'name': ' Sridhar Rajagopal', 'bio': {'p': ['Sridhar Rajagopal is a member of the technical staff at WiQuest Communications. His research interests include wireless communication systems, computer architecture, computer arithmetic, and parallel computing. Rajagopal has PhD and MS degrees in electrical and computer engineering from Rice University, where he participated in the work described in this article, and a BE in electronics engineering from Mumbai University, India. He is a member of the IEEE.']}}, {'name': 'J.R. Cavallaro', 'bio': {'p': ["Joseph R. Cavallaro is a professor of electrical and computer engineering at Rice University and associate director of the university's Center for Multimedia Communication. His research interests include computer arithmetic, VLSI and FPGA design, and architectures and algorithms for wireless communication systems. Cavallaro has a BS from the University of Penn-sylvania, an MS from Princeton University, and a PhD from Cornell University, all in electrical engineering. He is a member of the IEEE."]}}, {'name': 'S. Rixner', 'bio': {'p': ['Scott Rixner is an assistant professor of computer science and electrical and computer engineering at Rice University. His research interests include media, network, and communications processing, memory system architecture, and the interaction between operating systems and computer architectures. Rixner has BS and MEng degrees in computer science and engineering and a PhD in electrical engineering, all from the Massachusetts Institute of Technology. He is a member of the ACM.']}} %*Design space exploration for real-time embedded stream processors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1331279 %f/micro/9fv1eilrtu3x5rlwzmt0kgaqcycssnuz.pdf %mf96120eaf2e4887e7138b25eafa83e2f %cmicro %@[{'name': 'A. Krall', 'affiliation': 'Dept. of Comput. Sci., Vienna Univ. of Technol., Austria', 'bio': {'p': ['Andreas Krall is a professor of computer science at the Vienna University of Technology, Austria. His research interests include compilers, programming languages and computer architectures. Krall has a PhD in computer science from the University of Technolgy in Vienna. He is a member of the IEEE and ACM.']}}, {'name': 'I. Pryanishnikov', 'affiliation': 'Dept. of Comput. Sci., Vienna Univ. of Technol., Austria', 'bio': {'p': ['Ulrich Hirnschrott is a computer scientist and a PhD student at the Vienna University of Technology, Austria. His research interests include power-saving compilation techniques and parameterizable compiler design. Hirnschrott has an MS in computer science from Vienna University of Technology.']}}, {'name': 'U. Hirnschrott', 'affiliation': 'Dept. of Comput. Sci., Vienna Univ. of Technol., Austria', 'bio': {'p': ['Christian Panis is pursuing a PhD in “Scalable DSP Core Architectures Addressing Compiler Requirements” at Tampere University of Technology, Finland. His research interests include digital signal processor architectures. Panis has an MS in industrial electronics and control theory from Vienna University of Technology.']}}, {'name': 'C. Panis', 'bio': {'p': ['Ivan Pryanishnikov is a computer scientist and a PhD student at the Vienna University of Technology, Austria. His research interests include computer architectures, compilation, and parallel computations. Pryanishnikov has an MS in computer science from the Technical University of Tashkent.']}} %*XDSPCORE: a compiler-based configurable digital signal processor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1331280 %f/micro/bye3gn9e0t6xmplvszcoukm1w4l5hxht.pdf %m11dd4e9383696853d73edb04411a8fb1 %cmicro %@[{'name': 'S. Greenstein', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/29395/1331281/1331281-photo-1-small.gif', 'p': []}} %*The diamond-wafer paradox: a modern mystery %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1331281 %f/micro/qe3mpn5rbqupuoildhoksga1wnlsgi4v.pdf %mfe96fa8193c620ce150a56f4f40d865d %cmicro %@[{'name': 'R. Mateosian', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/29395/1331284/1331284-photo-1-small.gif', 'p': []}} %*Attacking complexity %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1331284 %f/micro/guldxkgc7v1f3p2ixhhctsfasmywl48y.pdf %me7f6d8f73e6d181cdda5ca1c51f6f4a6 %cmicro %@[{'name': 'P. Bose', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/29729/1353195/1353195-photo-1-small.gif', 'p': []}} %*Communication versus Computation %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1353195 %f/micro/j2nycyaue3lzziut8skmbodqwwhv4nf0.pdf %m8a7269de00df0fc72a1c70a096895e1c %cmicro %@[{'name': 'R.H. Stern', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/29729/1353196/1353196-photo-1-small.gif', 'p': ['']}} %*Vicarious liability for infringement %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1353196 %f/micro/a5gfdmsxiw3nia8ychj4wp6vun9qbetl.pdf %mf902a79bd663df489ce8cdf624d64673 %cmicro %@[{'name': 'I. Papaefstathiou', 'affiliation': 'Ellemedia Technologies Technical University of Crete', 'bio': {'p': ['Ioannis Papaefstathiou has recently been elected an assistant professor at the Technical University of Crete, Greece. He is also a technical consultant at Ellemedia Technologies and a research associate at the Institute of Computer Science, Foundation for Research and Technology-Hellas (ICS-FORTH). His research interests include architectures for network processors and specific-purpose networking systems. Papaefstathiou has a BSc from the University of Crete, an MSc from Harvard University, and a PhD in computer science from the University of Cambridge.']}}, {'name': 'N.A. Nikolaou', 'bio': {'p': ['Nikos A. Nikolaou is a technical manager at Ellemedia Technologies. His research interests include communication protocols and QoS. Nikolaou has a BS in computer engineering and information science from the University of Patras and a PhD in electrical and computer engineering from the National Technical University of Athens. He is a member of the IEEE and the Technical Chamber of Greece.']}}, {'name': 'B. Doshi', 'bio': {'p': ['Bharat Doshi is a senior director in the Advanced Communications Technology Center at Bell Laboratories, Lucent Technologies. His research interests include frame relay, ATM, SONET/SDH, optical networks, wireless networks, and Internet/intranet applications over wireline and mobile access networks. Doshi has a BS from the Indian Institute of Technology, and an MS and PhD in from Cornell University, New York.']}}, {'name': 'E. Grosse', 'bio': {'p': ['Eric Grosse is director of Secure Networking Research at Bell Laboratories, Lucent Technologies. His research interests include pervasive crypto, secure VoIP, and high availability networking. Grosse has a BS in mathematics from Michigan State University and a PhD in computer science from Stanford University. He is a member of IEEE, SIAM, and ACM.', 'Direct questions and comments about this issue to Ioannis Papaefstathiou, ICS-FORTH, Vassilika Vouton, PO Box 1385, Heraklion, Crete, GR7110, Greece, ygp@ics.forth.gr.']}} %*Guest Editors' Introduction: Network Processors for Future High-End Systems and Applications %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1353197 %f/micro/osnhlv8moxknxuqye4cgj7r02zqmp6pj.pdf %me7973acbc62f1b063085b9c3c3fcee8e %cmicro %@[{'name': 'J. Carlstrom', 'bio': {'p': ['Jakob Carlström is a senior systems architect at Xelerated. Prior to joining Xelerated in 2001, he was a postdoctoral researcher at the Department of Electrical Engineering of the Technion, Israel Institute of Technology. Carlström has an MS in engineering physics and a PhD in computer systems, both from Uppsala University, Sweden. He is a member of the IEEE.']}}, {'name': 'T. Boden', 'bio': {'p': ['Thomas Bodén is Chief Systems Architect for Xelerated and one of its co-founders. His previous work experience was in embedded systems design for the mobile telecommunications industry, ASIC design, and software research. Bodén has an MS in computer science and mathematics from Linköping Institute of Technology, Sweden.']}} %*Synchronous dataflow architecture for network processors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1353198 %f/micro/ondyelha3cgzrde5wnu2ftx9z1wfqkvb.pdf %m52dc09bf1bb4e617afdddf8d331b74c4 %cmicro %@[{'name': 'I. Papaefstathiou', 'affiliation': 'Tech. Univ. of Crete, Greece', 'bio': {'p': ['Ioannis Papaefstathiou has recently been elected an assistant professor at the Technical University of Crete, Greece. He is also a technical consultant at Ellemedia Technologies, Athens, and a research associate at the Institute of Computer Science, Foundation for Research and Technology-Hellas (ICS-FORTH). His research interests include architectures for network processors and specific-purpose networking systems. Papaefstathiou has a BSc from the University of Crete, an MSc from Harvard University, and a PhD in computer science from the University of Cambridge.']}}, {'name': 'S. Perissakis', 'bio': {'p': ['Stylianos Perissakis designs data transmission and network-processing ICs at Ellemedia Technologies. His research interests include full and semicustom IC design with emphasis on reconfigurable and embedded DRAM architectures. Perissakis has a diploma in electrical and computer engineering from the National Technical University of Athens and MSc and PhD degrees in computer science from the University of California, Berkeley.']}}, {'name': 'T.G. Orphanoudakis', 'bio': {'p': ['Theofanis G. Orphanoudakis leads R&D activities in broadband networking components at Ellemedia Technologies. His research interests include network processors, performance evaluation of broadband access networks, and resource management. Orphanoudakis has a Dipling in electrical and computer engineering and a PhD in telecommunications, both from the National Technical University of Athens. He is a member of the IEEE and the Technical Chamber of Greece.']}}, {'name': 'N.A. Nikolaou', 'bio': {'p': ['Nikos A. Nikolaou is a Technical Manager at Ellemedia Technologies. His research interests mainly include Communication protocols and QoS. Nikolaou has a diploma in computer engineering and information science from the University of Patras and a PhD in electrical and computer engineering from the National Technical University of Athens. He is a member of the IEEE and the Technical Chamber of Greece.']}}, {'name': 'G. Komaros', 'bio': {'p': ['George Kornaros is an acting technical manager of the Broadband Networking Components Group at Ellemedia Technologies. His research interests include high-speed network processors and communication architectures, and VLSI design. Kornaros has a BS in computer engineering from Patras University, Patras, Greece, and an MS in computer science from the University of Crete. He is a member of the Technical Chamber of Greece.']}}, {'name': 'N.A. Zervos', 'bio': {'p': ['Nicholas A. Zervos is managing director of Ellemedia Technologies. His research interests include exploratory development of core network technologies in home networking, wireline/wireless systems, and broadband networking components. Zervos has a diploma in electrical and mechanical engineering from the National Technical University of Athens, an MSc in systems and computing science form Carleton University, Ottawa, and a PhD in electrical engineering from the University of Toronto. He is a member of the IEEE.']}}, {'name': 'G. Konstantoulakis', 'bio': {'p': ['George Konstantoulakis is cofounder and CTO of InAccess Networks. His research interests include residential networks and high-speed networking devices. Konstantoulakis has a diploma in electrical and computer engineering and a PhD in telecommunications, both from the National Technical University of Athens. He has initiated and managed the PRO3 project. He is a member of the IEEE and the Technical Chamber of Greece.']}}, {'name': 'D.N. Pnevmatikatos', 'bio': {'p': ['Dionisios N. Pnevmatikatos is an associate professor of electrical and computer engineering at the Technical University of Crete and a research associate at ICS-FORTH. His research interests include the architecture and design of computer systems, networking systems, and system software. Pnevmatikatos has a BS in computer science from the University of Crete and an MSc and a PhD, both in computer science, from the University of WisconsinMadison. He is a member of the IEEE.']}}, {'name': 'K. Vlachos', 'bio': {'p': ['Kyriakos Vlachos is a professor in the Computer Engineering and Informatics Department of the University of Patras. Earlier, he was a member of the technical staff of Bell Laboratories, Lucent Technologies, the Netherlands, where he participated in the work described in this article. His research interests include high-speed communication systems, network processors, optical packet switching, and optical labeling techniques. Vlachos has a Dipling and a PhD, both in electrical and computer engineering, from the National Technical University of Athens. He is a member of the IEEE.']}} %*PR03: a hybrid NPU architecture %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1353200 %f/micro/jszpi59ogsehfuco8e13mlghfpbt2ura.pdf %m5b47fdb54b1642735b5d6882c98b3468 %cmicro %@[{'name': ' Yan Luo', 'affiliation': 'Dept. of Comput. Sci. & Eng., California Univ., Riverside, CA, USA', 'bio': {'p': ['Yan Luo is a PhD candidate in the Computer Science and Engineering Department at the University of California, Riverside. His research interests include network processors, low-power microprocessor architecture, Internet routers, and parallel and distributed processing. He has an ME from Huazhong University of Science and Technology, China, and is a student member of the IEEE.']}}, {'name': ' Jun Yang', 'affiliation': 'Dept. of Comput. Sci. & Eng., California Univ., Riverside, CA, USA', 'bio': {'p': ['Jun Yang is an assistant professor in the Computer Science and Engineering Department at the University of California, Riverside. Her research interests include network processors, low-power microprocessor architecture, and secure microprocessor designs. Yang has a PhD in computer science from the University of Arizona. She is a member of the IEEE and the ACM.']}}, {'name': 'L.N. Bhuyan', 'affiliation': 'Dept. of Comput. Sci. & Eng., California Univ., Riverside, CA, USA', 'bio': {'p': ['Laxmi N. Bhuyan is a professor of computer science and engineering at the University of California, Riverside. His research interests include network processor architecture, Internet routers, and parallel and distributed processing. Bhuyan has a PhD from Wayne State University. He is a Fellow of the IEEE, the ACM, and the American Association for the Advancement of Science.']}}, {'name': ' Li Zhao', 'affiliation': 'Dept. of Comput. Sci. & Eng., California Univ., Riverside, CA, USA', 'bio': {'p': ['Li Zhao is a PhD candidate in the Computer Science and Engineering Department at the University of California, Riverside. Her research interests include computer architecture, networking software, and performance evaluation. She has a BS in scientific information from Xidian University, China, and an MS in physics from the Institute of High Energy Physics, Chinese Academy of Science. Zhao is a student member of IEEE.']}} %*NePSim: a network processor simulator with a power evaluation framework %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1353201 %f/micro/zgjg4fnoolhvhswe5ca7fmqdrwk9dvis.pdf %m304697657b73d48c8cf0e46ef5471a0b %cmicro %@[{'name': ' Niraj Shah', 'affiliation': 'Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA', 'bio': {'p': ['Niraj Shah is a PhD student in the EECS Department at the University of California, Berkeley. His research interests include methodologies and tools for designing highperformance programmable embedded systems. Shah has a BS in computer engineering from the University of Arizona and an MS in electrical engineering from the University of California, Berkeley. He is a student member of IEEE.']}}, {'name': 'W. Plishker', 'affiliation': 'Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA', 'bio': {'p': ['William Plishker is a PhD student in the Electrical Engineering and Computer Sciences (EECS) Department at the University of California, Berkeley. His research interests include design automation techniques for programmable embedded systems. Plishker has a BS in computer engineering from the Georgia Institute of Technology. He is a student member of IEEE.']}}, {'name': ' Kaushik Ravindran', 'affiliation': 'Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA', 'bio': {'p': ['Kaushik Ravindran is a PhD student in the EECS Department at the University of California, Berkeley. His research activities include reconfigurable computing and embedded system design. Ravindran has a BS in computer engineering from the Georgia Institute of Technology. He is a student member of IEEE.']}}, {'name': 'K. Keutzer', 'affiliation': 'Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA', 'bio': {'p': ['Kurt Keutzer is a professor in the EECS Department at the University of California, Berkeley. His research interests include software support for the design of application-specific instruction processors. Keutzer has a BS in mathematics from Maharishi International University, Fairfield, Iowa, and an MS and a PhD in computer science from Indiana University. He is a fellow of the IEEE.', 'Direct questions and comments about this article to William Plishker, c/o Jennifer Stone, 211 Cory Hall, #1722, Berkeley, CA 94720, plishker@eecs.berkeley.edu.', 'For further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/publications/dlib.']}} %*NP-Click: a productive software development approach for network processors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1353202 %f/micro/jyeqncsjsg4lr9vthryi6oxx0bkokpiu.pdf %m740df6bad836e98bd3e4b210c53c441c %cmicro %@[{'name': ' Zhangxi Tan', 'affiliation': 'Dept. of Comput. Sci., Tsinghua Univ., Beijing, China', 'bio': {'p': ['Zhangxi Tan is an ME student in the Department of Computer Science at Tsinghua University, China. His research interests include computer architecture, network processors, performance evaluation, and resource management in computer networks. Tan has a BE in electronic engineering from Tsinghua University. He received the 2002 Outstanding Graduate Student Award from both Tsinghua University and the City of Beijing, and the 2004 Outstanding Chinese Student Scholarship from IBM.']}}, {'name': ' Chuang Lin', 'affiliation': 'Dept. of Comput. Sci., Tsinghua Univ., Beijing, China', 'bio': {'p': ["Chuang Lin is a professor and the head of the Department of Computer Science at Tsinghua University. His research interests include computer networks, performance evaluation, network security, and Petri net theory and applications. Lin has a PhD in computer science from Tsinghua University. He serves as the general chair for ACM SIGCOMM's 2005 Asia workshop and the associate editor of the IEEE Transactions on Vehicular Technology. He is a senior member of the IEEE."]}}, {'name': ' Hao Yin', 'affiliation': 'Dept. of Comput. Sci., Tsinghua Univ., Beijing, China', 'bio': {'p': ['CHao Yin is an assistant professor with Department of Computer Science, Tsinghua University. His research interests include multimedia communication, video coding, and network security. Yin has a BS, an ME, and a PhD, all in electrical engineering, from the Huazhong University of Science and Technology, China. He is a member of IEEE.']}}, {'name': ' Bo Li', 'bio': {'p': ["CBo Li is an associate professor with the Department of Computer Science, Hong Kong University of Science and Technology, he is also an adjunct researcher for Microsoft Research. Li has a PhD in electrical and computer engineering from the University of Massachusetts at Amherst. He was cochair of IEEE Infocom 2004's technical program committee.", 'Direct questions and comments to Zhangxi Tan, Department of Computer Science and Technology, Tsinghua University,100084 Beijing China, xtan@csnet1.cs.tsinghua.edu.cn.']}} %*Optimization and benchmark of cryptographic algorithms on network processors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1353203 %f/micro/hlkvnxlcru4oqpwjh7d2u6ms0tbe8ctr.pdf %m2a825af105ca457afccfd96eaa8d2583 %cmicro %@[{'name': 'T. Suh', 'affiliation': 'Dept. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA', 'bio': {'p': ['Taeweon Suh is a PhD student in the School of Electrical and Computer Engineering, Georgia Institute of Technology. His research interests include embedded systems, computer architecture, DSPs, and networks. Suh has a BS in electrical engineering from Korea University and an MS in electronics engineering from Seoul National University. He is a student member of ACM.']}}, {'name': 'H.-H.S. Lee', 'affiliation': 'Dept. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA', 'bio': {'p': ['Hsien-Hsin S. Lee is an assistant professor in the School of Electrical and Computer Engineering, Georgia Institute of Technology. His research interests include microarchitecture, low-power systems, design automation, and security. Lee has a BSEE from National Tsinghua University, Taiwan, and an MSE and a PhD in computer science and engineering from the University of Michigan. He is a member of ACM and IEEE.']}}, {'name': 'D.M. Blough', 'affiliation': 'Dept. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA', 'bio': {'p': ['Douglas M. Blough is a professor of electrical and computer engineering at the Georgia Institute of Technology. His research interests include parallel and distributed systems, dependability and security, and wireless ad hoc networks. Blough has a BS in electrical engineering and an MS and a PhD in computer science from Johns Hopkins University, Baltimore. He is a senior member of IEEE.', 'Send questions and comments to Taeweon Suh, Hsien-Hsin S. Lee, and Douglas M. Blough, School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia 30332–0250, {suhtw, leehs, doug.blough}@ece.gatech.edu.']}} %*Integrating cache coherence protocols for heterogeneous multiprocessor system. Part 2 %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1353204 %f/micro/wvruswcmdqyhfb8upbzjll3xdqt1fmet.pdf %mefe9c80d65a140a607e45666826bc386 %cmicro %@[{'name': 'S. Greenstein', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/29729/1353205/1353205-photo-1-small.gif', 'p': ['']}} %*Creative destruction and deconstruction [microeconomics] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1353205 %f/micro/qud7qtrmbexnh6jt2rykhsfezupfcoav.pdf %m59a4e7a57e4e39756f0258dd53e5b2ed %cmicro %@[{'name': 'R. Mateosian', 'affiliation': 'xrm@pacbell.net', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/29729/1353206/1353206-photo-1-small.gif', 'p': ['']}} %*Seek and Show %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1353206 %f/micro/ox5mnmughthlsz3xd0fos2eijnb4kpla.pdf %me365691ec33e470bdc2f46ef3e40e16f %cmicro %@[{'name': 'P. Bose', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/30203/1388149/1388149-photo-1-small.gif', 'p': []}} %*Computer architecture research: Shifting priorities and newer challenges %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1388149 %f/micro/dxhks01uucyqj4g7pef3ztnamnrl89wb.pdf %m8b12fe263a660e9f8a7e51e4889985c9 %cmicro %@[{'name': 'S. Greenstein', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/30203/1388150/1388150-photo-1-small.gif', 'p': ['']}} %*Canaries, whips, and sails %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1388150 %f/micro/thrlzaqw5i4negsyfcpxsyxkevmo0q7w.pdf %m708fb2b07a5cbc3534465f0e168bb8dd %cmicro %@[{'name': 'D.H. Albonesi', 'bio': {'p': ['David H. Albonesi is an associate professor in the school of electrical and computer engineering at Cornell University. His research interests include micro architecture with an emphasis on adaptive architectures, power-aware computing, and multithreading. Albonesi has a PhD from the University of Massachusetts at Amherst. He is a senior member of the IEEE, and a member of the IEEE Computer Society and the ACM.', 'Direct questions and comments about this special issue to David H. Albonesi, School of Electrical and Computer Engineering, Cornell University, 333 Rhodes Hall, Ithaca, NY 14853, albonesi@csl.cornell.edu.']}} %*Guest Editor's Introduction: Micro's Top Picks from Microarchitecture Conferences %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1388151 %f/micro/mqcs1j35wrn6ag0hue4hdowvtrafqkxd.pdf %m474823d66e9f841b5b39ee2c1593fc50 %cmicro %@[{'name': 'D. Ernst', 'bio': {'p': ['Dan Ernst is a PhD student in computer science and engineering at the University of Michigan. His research interests include efficient microarchitectures, dynamic instruction scheduling, application-specific processing, and reliable computing. Ernst has a BS in computer engineering from Iowa State University and an MS in computer science and engineering from the University of Michigan.']}}, {'name': 'S. Das', 'bio': {'p': ['Shidhartha Das is a graduate student at the University of Michigan, Ann Arbor. His research interests include interconnect analysis and circuit-architectural codesign techniques for low-power digital IC design. Das has a BTech in electrical engineering from the Indian Institute of Technology, Bombay, India. He is a student member of the IEEE.']}}, {'name': 'S. Lee', 'bio': {'p': ['Seokwoo Lee is a PhD student in computer science and engineering at the University of Michigan. His research interests include computer architecture, reliable system design, low-power system design, and computer simulations. Lee has a BS in computer science from the University of Michigan. He is a student member of Gigascale Systems Research Corp.']}}, {'name': 'D. Blaauw', 'bio': {'p': ['David Blaauw is an associate professor of electrical engineering and computer science at the University of Michigan. His research interests include VLSI design and CAD, with particular emphasis on circuit design and optimization problems for high-performance and low-power designs. Blaauw has a BS in physics and computer science from Duke University, and an MS and a PhD in computer science from the University of Illinois, Urbana-Champaign. He is a member of the IEEE and the ACM.']}}, {'name': 'T. Austin', 'bio': {'p': ['Todd Austin is an associate professor of electrical engineering and computer science at the University of Michigan. His research interests include computer architecture, compilers, computer system verification, and performance analysis tools and techniques. Austin has a PhD in computer science from the University of Wisconsin. Austin is a member of ACM and IEEE.']}}, {'name': 'T. Mudge', 'bio': {'p': ['Trevor Mudge, a faculty member at the University of Michigan, Ann Arbor, is the first Bredt Family Professor of Electrical Engineering and Computer Science. He also directs Idiot Savants, a chip design consultancy. His research interests include computer architecture, CAD, and compilers. Mudge has a PhD in computer science from the University of Illinois, Urbana-Champaign, and is a member of the ACM, the IEE, and the British Computer Society, he is a Fellow of the IEEE.']}}, {'name': ' Nam Sung Kim', 'bio': {'p': ['Nam Sung Kim is Senior Research Scientist with the circuit research laboratory at Intel Corp. His research interests include computer architecture and digital circuit and computer-aided design, with particular emphasis on low-power and process-, temperature-, and voltage-variation-tolerant computer system design. Kim has BS and MS degrees in electrical engineering from the Korea Advanced Institute of Science and Technology, Taejon, Korea, and a PhD in computer science and engineering from the University of Michigan, Ann Arbor. He is a member of the IEEE.']}}, {'name': 'K. Flautner', 'bio': {'p': ["Krisztian Flautner is director of advanced research at ARM Limited and the architect of ARM's Intelligent Energy Management technology. His research interests include high-performance, low-energy processing platforms that support advanced software environments. Flautner has a BS, an MS, and a PhD in computer science and engineering from the University of Michigan. He is a member of the ACM and the IEEE.", 'Direct questions and comments about this article to Dan Ernst, Advanced Computer Architecture Lab, University of Michigan, 1301 Beal Ave., Ann Arbor, MI 48109, razor@eecs.umich.edu.', 'For further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/publications/dlib.']}} %*Razor: circuit-level correction of timing errors for low-power operation %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1388152 %f/micro/lczmhe6ovig3qiwymw2tuflkrncqsut4.pdf %m2b38ea14ff542b02ec86f1fbc3636a10 %cmicro %@[{'name': 'J.C. Smolens', 'affiliation': 'Carnegie Mellon Univ., Pittsburgh, PA, USA', 'bio': {'p': ['Jared C. Smolens is a PhD student in electrical and computer engineering at Carnegie Mellon University, where his research interests include reliable computer systems and multiprocessor system design. He received an MS in electrical and computer engineering from Carnegie Mellon University and is a student member of the IEEE.']}}, {'name': 'B.T. Gold', 'affiliation': 'Carnegie Mellon Univ., Pittsburgh, PA, USA', 'bio': {'p': ['Brian T. Gold is a PhD student in electrical and computer engineering at Carnegie Mellon University, where his research interests are reliable computer systems and multiprocessor system design. He received an MS in computer engineering from Virginia Tech and is a student member of the IEEE.']}}, {'name': 'J. Kim', 'affiliation': 'Carnegie Mellon Univ., Pittsburgh, PA, USA', 'bio': {'p': ['Jangwoo Kim is a PhD student in electrical and computer engineering at Carnegie Mellon University. His research interests include reliable computer architecture, multiprocessor architecture, and full computer system simu-lation. Kim received an MEng in computer science from Cornell University and is a student member of the IEEE.']}}, {'name': 'B. Falsafi', 'affiliation': 'Carnegie Mellon Univ., Pittsburgh, PA, USA', 'bio': {'p': ['Babak Falsafi is an associate professor of electrical and computer engineering at Carnegie Mellon University. His research interests are computer architecture with emphasis on highperformance memory systems, nanoscale CMOS architecture, and tools to evaluate computer system performance. He received a PhD in computer science from the University of Wisconsin and is a member of the IEEE and ACM.']}}, {'name': 'J.C. Hoe', 'affiliation': 'Carnegie Mellon Univ., Pittsburgh, PA, USA', 'bio': {'p': ['James C. Hoe is an assistant professor of electrical and computer engineering at Carnegie Mellon University. His research interests are in computer architecture and high-level hardware description and synthesis. He received a PhD in electrical engineering and computer science from MIT and is a member of the IEEE and ACM. Andreas G. Nowatzyk is an associate professor of robotics at Carnegie Mellon University. His research interests are in shared-memory multiprocessor architectures and interconnect structures. He received a PhD in computer science from Carnegie Mellon University and is a member of the IEEE and ACM.', 'Direct questions and comments about this article to Babak Falsafi, Electrical and Computer Engineering Dept., Carnegie Mellon University, 5000 Forbes Ave., Pittsburgh, PA 15213, babak@ece.cmu.edu.', 'For further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/publications/dlib.']}}, {'name': 'A.G. Nowatryk', 'affiliation': 'Carnegie Mellon Univ., Pittsburgh, PA, USA'} %*Fingerprinting: bounding soft-error-detection latency and bandwidth %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1388154 %f/micro/4bvednlistywor6xa0ijoczbexvfwflk.pdf %mce3e730d4cebe45fdfcbd0f9ad94be97 %cmicro %@[{'name': 'C.T. Weaver', 'bio': {'p': ["Christopher T. Weaver is a hardware engineer in the VSSAD labs at Intel's Massachusetts Microprocessor Design Center, where he works in the Fault-Aware Computing Technology Project. His research interests include reliable computing, performance modeling, semi-custom and ASIC design, and power and fault modeling. Weaver has BS degrees in electrical engineering, computer engineering, and multidisciplinary studies from North Carolina State University and an MS in computer science and engineering from the University of Michigan."]}}, {'name': 'J. Emer', 'bio': {'p': ['Joel Emer is an Intel fellow at the Massachusetts Microprocessor Design Center, where he leads the VSSAD Group. His research interests include high-performance microarchitecture, multithreaded processors, processor pipeline organization, processor reliability, and performance-modeling frameworks. Emer has a PhD in electrical engineering from the University of Illinois. He is a Fellow of the IEEE and the ACM.']}}, {'name': 'S.S. Mukherjee', 'bio': {'p': ["Shubhendu S. Mukherjee is the manager and technical leader of Intel's Fault-Aware Computing Technology (FACT) Group. His research interests include processor reliability and interconnection networks. Mukherjee has a BTech in computer science and engineering from the Indian Institute of Technology, Kanpur, and an MS and a PhD, both in computer science, from the University of Wisconsin-Madison. He is a member of the ACM and a senior member of the IEEE."]}}, {'name': 'S.K. Reinhardt', 'bio': {'p': ['Steven K. Reinhardt is an associate professor of electrical engineering and computer science at the University of Michigan in Ann Arbor and a consultant to Intel. His research interests include processor architecture, memory systems, and computer system simulation. Reinhardt has a BS from Case Western Reserve University and an MS from Stanford University, both in electrical engineering, and a PhD in computer science from the University of Wisconsin-Madison. He is a member of the IEEE Computer Society and the ACM.', 'Direct questions and comments about this article to Steven K. Reinhardt, EECS Dept., University of Michigan, 1301 Beal Ave., Ann Arbor, MI 48109, stever@eecs.umich.edu.', 'For further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/publications/dlib.']}} %*Reducing the soft-error rate of a high-performance microprocessor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1388155 %f/micro/vctxrwgcvjs0lmkw4af7iepg3qo6pntk.pdf %mc7e352c8d9e659a6b873c1295642258d %cmicro %@[{'name': ' Xiaodong Li', 'affiliation': 'Illinois Univ., Urbana, IL, USA', 'bio': {'p': ['Xiaodong Li is a PhD student in the Department of Computer Science at the University of Illinois at Urbana-Champaign. His research interests include energy- and reliability-related issues in computer architecture. Li has an MSEE from Purdue University.', 'Zhenmin Li is a PhD student in the Department of Computer Science at the University of Illinois at Urbana-Champaign. His research interests include software debugging, data mining, and storage systems. Li has an ME in computer science from Tsinghua University, China.']}}, {'name': ' Zhenmin Li', 'affiliation': 'Illinois Univ., Urbana, IL, USA', 'bio': {'p': ['Pin Zhou is a PhD student in the Department of Computer Science at the University of Illinois at Urbana-Champaign. Her research interests include architectural support for software debugging, energy management for storage systems, and memory management. Zhou has an MS in computer science from Tsinghua University, China.']}}, {'name': ' Pin Zhou', 'affiliation': 'Illinois Univ., Urbana, IL, USA', 'bio': {'p': ['Yuanyuan Zhou is an assistant professor at the University of Illinois at Urbana-Champaign. Her research interests include database storage, architecture and operating system support for software debugging, power management, and memory management, storage systems. Zhou has an MA and a PhD, both in computer science, from Princeton University. She is a member of IEEE, ACM, and Usenix.']}}, {'name': ' Yuanyuan Zhou', 'affiliation': 'Illinois Univ., Urbana, IL, USA', 'bio': {'p': ['Sarita V. Adve is an associate professor in computer science at the University of Illinois at Urbana-Champaign. Her research interests include energy-, temperature-, and reliability-aware computer architectures and systems. Adve has a PhD in computer science from the University of Wisconsin-Madison. She is a recipient of an Alfred P. Sloan Fellowship, a University Scholar of the University of Illinois, and a member of the IEEE, IEEE CS, and ACM SIGArch.']}}, {'name': 'S.V. Adve', 'affiliation': 'Illinois Univ., Urbana, IL, USA', 'bio': {'p': ['Sanjeev Kumar is a researcher at Intel Labs. His research interests include programming languages and computer architecture. Kumar has an MA and a PhD in computer science from Princeton University, an MS in computer science from Indiana University, and a BTech in computer science and engineering from the Indian Institute of Technology, Madras (now Chennai). He is a member of the IEEE, ACM, and Usenix.', 'Direct questions and comments about this article to Xiaodong Li, Siebel Center for Computer Science, Room 4111, 201 N. Goodwin Ave., Urbana, IL 61801, xli3@uiuc.edu.', 'For further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/publications/dlib.']}}, {'name': 'S. Kumar'} %*Performance-directed energy management for storage systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1388156 %f/micro/qjbkvdprqtlhgomjengezxnf2m7uw6ch.pdf %me32a79666ba0440cf376a1c66e98f42c %cmicro %@[{'name': ' Pin Zhou', 'affiliation': 'Illinois Univ., Urbana, IL, USA', 'bio': {'p': ['Pin Zhou is a PhD student in the Department of Computer Science, University of Illinois at Urbana-Champaign. Her research interests include architectural support for software debugging, energy management for storage system, and memory management. Zhou has an MS in computer science from Tsinghua University, China.']}}, {'name': ' Feng Uin', 'affiliation': 'Illinois Univ., Urbana, IL, USA', 'bio': {'p': ['Feng Qin is a PhD student in the Department of Computer Science, University of Illinois at Urbana-Champaign. His research interests include software debugging with system support. Qin has an ME in software engineering from the Institute of Software, Chinese Academy of Sciences.']}}, {'name': ' Wei Liu', 'affiliation': 'Illinois Univ., Urbana, IL, USA', 'bio': {'p': ['Wei Liu is a research scientist for computer science at the University of Illinois at Urbana-Champaign. His research interests include architecture and compiler support for thread-level speculation and software debugging. Liu has a PhD in computer science from Tsinghua University, China.']}}, {'name': ' Yuanyuan Zhou', 'affiliation': 'Illinois Univ., Urbana, IL, USA', 'bio': {'p': ['Yuanyuan Zhou is an assistant professor at University of Illinois at Urbana-Champaign. Her research interests include database storage, architecture and OS support for software debugging, power management, and memory manage-ment. She has an MA and a PhD, both in computer science, from Princeton University.']}}, {'name': 'J. Torrellas', 'bio': {'p': ['Josep Torrellas is a professor of computer science and Willett Faculty Scholar at the University of Illinois at Urbana-Champaign. He is also vice-chair of the IEEE Technical Committee on Computer Architecture (TCCA). His main research interests are in multi-processor computer architecture, thread-level speculation, low-power design, reliability and debuggability. Torrellas has a PhD in electrical engineering from Stanford University. He is an IEEE Fellow and a member of the ACM.']}} %*iWatcher: simple, general architectural support for software debugging %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1388157 %f/micro/5ubh014lq32xrqvfwnhimuaijx6ylr9j.pdf %mb27fa122285ee575c638724626f40d2b %cmicro %@[{'name': 'B.A. Fields', 'affiliation': 'California Univ., Berkeley, CA, USA', 'bio': {'p': ['Brian Fields is a PhD student at the Universi ty of California, Berkeley, where he is the student leader of the BAFL project (http://www.cs.berkeley.edu/-bfields/baf1). His research interests include performance analysis and developing next-generation microarchitectures. He has a MS in computer science from the University of Wisconsin, Madison, and a BS in computer engineering from the University of Cincinnati.']}}, {'name': 'R. Bodik', 'affiliation': 'California Univ., Berkeley, CA, USA', 'bio': {'p': ['Rastislav Bodik is an assistant professor of computer science at the University of California, Berkeley, where he co-leads the BAFL project with Mark Hill. His research interests range from program analysis and software engineering tools to computer architecture. He has a PhD from the University of Pittsburgh.']}}, {'name': 'M.D. Hill', 'bio': {'p': ['Mark D. Hill is a professor in both the computer sciences department and the electrical and computer engineering department at the University of Wisconsin, Madison, where he co-leads the BAFL project with Ras Bodik and the Wisconsin Multifacet project (http://www.cs.wisc.edu/multifacet/) with David Wood. His research interests include cache design, cache simulation, translation buffers, memory consistency models, parallel simulation, and parallel computer design. He has a PhD from University of California, Berkeley. He is an ACM Fellow and a Fellow of the IEEE.']}}, {'name': 'C.J. Newburn', 'bio': {'p': ['Chris (CJ) Newburn is part of the IA32 architecture team in the Desktop Product Group at Intel. His research interests lie in feedback-directed optimization, managed runtimes, performance analysis, parallelization, virtualization, and enhancements to memory systems. He has a PhD in electrical and computer engineering from Carnegie Mellon University. He is a member of the IEEE and the ACM.', 'Direct questions and comments about this article to Brian Fields, 517 Soda Hall, Computer Science Division, #1776, Univ. of California, Berkeley, Berkeley, CA 94720–1776, bfields@cs.berkeley.edu.', 'For further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/publications/dlib.']}} %*Interaction cost: for when event counts just don't add up %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1388158 %f/micro/bkr13h2wjvgi5fu8m7zqxfxyedcomohe.pdf %md7a3852cfe710f17a711a708582e4630 %cmicro %@[{'name': 'S.T. Srinivasan', 'bio': {'p': ['Srikanth T. Srinivasan is a senior researcher with the Intel Microprocessor Technology Labs. His research focuses on scalable and efficient microarchitectures. Srinivasan has a BE from the Birla Institute of Technology and Science, Pilani, India, and a PhD from Duke University, both in computer science. He is a member of the IEEE and the ACM.']}}, {'name': 'R. Rajwar', 'bio': {'p': ['Ravi Rajwar is with the Intel Microprocessor Technology Labs. His research interests include the theoretical and practical aspects of computer architecture. Rajwar has a PhD in computer science from the University of Wisconsin-Madison.']}}, {'name': 'H. Akkary', 'bio': {'p': ['Haitham Akkary is with the Intel Microprocessor Technology Labs. His primary research interest is microprocessor architecture. Akkary has a BS and an MS from Louisiana State University and a PhD from Portland State University, all in electrical and computer engineering. He is a member of the IEEE and the ACM.']}}, {'name': 'A. Gandhi', 'bio': {'p': ['Amit Gandhi is a PhD candidate in the Electrical and Computer Engineering Department at Portland State University. His primary research interest is microprocessor architecture. Gandhi has a BE in instrumentation and control from the University of Pune, India, and an MS in electrical and computer engineering from Portland State University. He is a member of the IEEE.']}}, {'name': 'M. Upton', 'bio': {'p': ['Michael Upton is a principal engineer with the Intel Microprocessor Technology Labs and one of the architects of the Pentium 4 processor. His main research interest is low-power microarchitecture techniques. Upton has a BS and an MS in electrical engineering from the University of Washington and a PhD in electrical engineering from the University of Michigan.', 'Direct questions and comments about this article to Ravi Rajwar, Intel Microprocessor Technology Labs, M/S JF3–332, Intel Corp., 2111 NE 25th Ave., Hillsboro, OR 97124, ravi.rajwar@intel.com.', 'For further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/publications/dlib.']}} %*Continual flow pipelines: achieving resource-efficient latency tolerance %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1388159 %f/micro/cupxyf8i4epxqrdz62mhkuyzldv09hat.pdf %m589bff2fe4286eb3a7cba96e8de14c29 %cmicro %@[{'name': 'P.H. Wang', 'bio': {'p': ["Perry H. Wang is a staff researcher in the Microprocessor Technology Group of Intel's Microprocessor Technology Labs. His research interests include advanced microarchitectures and compiler optimizations. Wang has an MS in computer science from the University of Michigan, Ann Arbor."]}}, {'name': 'J.D. Collins', 'bio': {'p': ["Jamison D. Collins is a senior researcher in the Microprocessor Technology Group of Intel's Microprocessor Technology Labs. His research interests include helper threads and their application to data prefetching. Collins has a PhD in computer science from the University of California, San Diego."]}}, {'name': ' Dongkeun Kim', 'bio': {'p': ["Hong Wang is a principal engineer in the Microprocessor Technology Group of Intel's Microprocessor Technology Labs. His research interests include architecture innovations for future multicore processor designs and the exploration of novel multithreaded programming paradigms for pragmatic usage models. Hong has a PhD in electrical engineering from the University of Rhode Island."]}}, {'name': 'B. Greene', 'bio': {'p': ["Dongkeun Kim is a doctoral student in the University of Maryland's Electrical and Computer Engineering Department. His research interests include computer architecture, optimizing compilers, and the performance evaluation of computer systems. Kim has a BS in electrical engineering from Seoul National University, Korea. He is a member of the IEEE Computer Society."]}}, {'name': ' Kai-Ming Chan', 'bio': {'p': ['Bill Greene is the manager and technical lead for Itanium firmware development at Intel. His work experience includes development of the first-generation Itanium processor, and firmware development for Itanium, Itanium 2, and future Itanium processors. Greene has an MS in electrical engineering from Purdue University. He is a member of the IEEE Computer Society.']}}, {'name': 'A.B. Yunus', 'bio': {'p': ["Kai-Ming Chan is a senior staff software engineer in Intel's Enterprise Technology Enabling group. His research interests includes database performance. Chan has an MS in computer science and an MBA from Brigham Young University."]}}, {'name': 'T. Sych', 'bio': {'p': ["Aamir B. Yunus is a senior software engineer in Intel's Enterprise Technology Enabling group. His research interests include the performance optimization of cryptographic algorithms. Yunus has an MS in computer science from Arizona State University."]}}, {'name': 'S.F. Moore', 'bio': {'p': ["Terry Sych is a staff software engineer in Intel's Enterprise Technology Enabling group. His research interests include database performance, software optimization, and architecture analysis. Sych has an MS in electrical engineering from the University of Minnesota. He is a member of the IEEE Computer Society."]}}, {'name': 'J.P. Shen', 'bio': {'p': ["Stephen F. Moore is a senior software developer in Intel's Enterprise Technology Enabling group. His work experience includes many years in software development and performance optimization. Moore majored in mathematics at Texas Tech University."]}}, {'name': ' Hong Wang', 'bio': {'p': ['John P. Shen directs the Microarchitecture Research Lab at Intel. Shen has a PhD from the University of Southern California in electrical engineering. He is an IEEE Fellow.', 'Direct questions and comments about this article to Perry H. Wang, Mail stop SC12- 303, Intel Corp., 2200 Mission College Blvd., Santa Clara, CA 95052, perry.wang@ intel.com.', 'For further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/publications/dlib.']}} %*Helper threads via virtual multithreading %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1388160 %f/micro/jlza9qm5e7mettnw0dsboknhckwo63dy.pdf %m0d52f209606f0a4f6ece2d1e6000945d %cmicro %@[{'name': 'B. Krashinsky', 'bio': {'p': ['Ronny Krashinsky is a PhD student in electrical engineering and computer science at MIT. His research interests include high-performance, energy-efficient computer architecture and VLSI design. Krashinsky has a BS from UC Berkeley and an SM from MIT, both in electrical engineering and computer science.']}}, {'name': 'C. Batten', 'bio': {'p': ['Christopher Batten is a PhD candidate in the MIT Department of Electrical Engineering and Computer Science. His research interests include low-power, high-performance computer architectures and synthetic biological systems. Batten has a BS in electrical engineering from the University of Virginia, and a MPhil in engineering from the University of Cambridge.']}}, {'name': 'M. Hampton', 'bio': {'p': ['Mark Hampton is a PhD student in electrical engineering and computer science at MIT. He has BS degrees in computer and systems engineering as well as computer science from Rensselaer Polytechnic Institute and an SM degree in electrical engineering and computer science from MIT.']}}, {'name': 'S. Gerding', 'bio': {'p': ['Steve Gerding is a graduate student in electrical engineering and computer science at MIT. His research interests include energy and performance measurement of high-performance microprocessors. Gerding has a BS in computer science and engineering from UCLA.']}}, {'name': 'B. Pharris', 'bio': {'p': ['Brian Pharris is currently an employee at NVIDIA. He has an MEng in electrical engineering and computer science from MIT.']}}, {'name': 'J. Casper', 'bio': {'p': ['Jared Casper is an undergraduate student in electrical engineering and computer science at MIT. His research interests are in extreme computer architectures.']}}, {'name': 'K. Asanovic', 'bio': {'p': ['Krste Asanović is an associate professor in the MIT Department of Electrical Engineering and Computer Science and a member of the MIT Computer Science and Artificial Intelligence Laboratory. His research interests are computer architecture and VLSI design. He has a PhD in computer science from the University of California, Berkeley. He is a member of the IEEE and the ACM.']}} %*The vector-thread architecture %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1388162 %f/micro/vml8hix0qksna4wqbidvk7tfedt3yore.pdf %ma778bd3b3b02bcebf27d793580daa973 %cmicro %@[{'name': 'L. Hammond', 'affiliation': 'Stanford Univ., CA, USA', 'bio': {'p': ["Brian D. Carlstrom is a PhD candidate in computer science at Stanford University. His research interests include transactional programming models and other aspects of modern programming language design and implementation. Carlstrom has a master's degree in electrical engineering and computer science from the Massachusetts Institute of Technology. He is a member of the ACM."]}}, {'name': 'B.D. Carlstrom', 'affiliation': 'Stanford Univ., CA, USA', 'bio': {'p': ['Vicky Wong is a PhD candidate in computer science at Stanford University. Her research interests include parallel computer architectures and probabilistic reasoning algorithms. Wong has an MS in computer science from Stanford University.']}}, {'name': 'V. Wong', 'affiliation': 'Stanford Univ., CA, USA', 'bio': {'p': ["Michael Chen performed this work while completing his PhD in electrical engineering at Stanford University. He is now a staff researcher in the Programming System Lab at Intel's Microprocessor Research Labs. His research interests include optimization techniques for compiling high-level languages to the Intel IXP network processors."]}}, {'name': 'M. Chen', 'affiliation': 'Stanford Univ., CA, USA', 'bio': {'p': ['Christos Kozyrakis is an assistant professor of electrical engineering and computer science at Stanford University. His research interests include architectures, compilers, and programming models for parallel systems ranging from embedded devices to supercomputer. Kozyrakis has a PhD in computer science from the University of California, Berkeley.']}}, {'name': 'C. Koryrakis', 'affiliation': 'Stanford Univ., CA, USA', 'bio': {'p': ['Kunle Olukotun is an associate professor of electrical engineering and computer science at Stanford University. His research interests include computer architecture, parallel programming environments, and formal hard- ware verification. Olukotun has a PhD in computer science and engineering from the University of Michigan.', 'Direct questions and comments about this article to Kunle Olukotun, Stanford University, Gates Bldg. 3A-302, Stanford, CA, 94305–9030, kunle@stanford.edu.', 'For further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/publications/dlib.']}}, {'name': 'K. Olukotun', 'affiliation': 'Stanford Univ., CA, USA'} %*Transactional coherence and consistency: simplifying parallel hardware and software %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1388164 %f/micro/mzzryugswlngndte1waro8ypvfmcpbuj.pdf %maa18cea4586cf5af73fed1b024f44e1c %cmicro %@[{'name': ' Jaehyuk Huh', 'affiliation': 'Texas Univ., Austin, TX, USA', 'bio': {'p': ['Jaehyuk Huh is a PhD student in computer science at The University of Texas at Austin. His research interests include microarchitecture, multiprocessors, and operating systems. Huh has a BS from Seoul National University, Korea, and an MS from the Department of Computer Sciences at The University of Texas at Austin. He received an IBM PhD research fellowship in 2004.']}}, {'name': 'D. Burger', 'affiliation': 'Texas Univ., Austin, TX, USA', 'bio': {'p': ['Doug Burger is an associate professor of computer sciences at The University of Texas at Austin. His research interests include high-performance, power-efficient, technology-scalable microprocessors. Burger has a BS from Yale University and an MS and a PhD from the University of Wisconsin, all in computer science. He is an Alfred P. Sloan Foundation Fellow, a senior member of the IEEE, and a member of the ACM.']}}, {'name': ' Jichuan Chang', 'bio': {'p': ['Jichuan Chang is a PhD student in computer sciences at the University of Wisconsin-Madison. His research interests include multiprocessor cache coherence and speculation in chip multiprocessors. Chang has a BS and an MS from Beijing University, both in computer sciences.']}}, {'name': 'G.S. Sohi', 'bio': {'p': ['Gurindar S. Sohi chairs the Computer Sciences Department at the University of Wisconsin-Madison. His research interests include the design of high-performance computer systems. Sohi has a BE in electrical and electronics engineering from the Birla Institute of Science and Technology, Pilani, India, and an MS and a PhD in electrical and computer engineering from the University of Illinois. He is a Fellow of the ACM and the IEEE.', 'Direct questions and comments about this article to Doug Burger, Department of Computer Sciences, The University of Texas at Austin, 1 University Station C0500, Austin, TX 78712, dburger@cs.utexas.edu.', 'For further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/publications/dlib.']}} %*Speculative incoherent cache protocols %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1388165 %f/micro/tblejswin6ia9r1gryhuyqk4zjp2zxbe.pdf %m380a93c3b89933567877512ce2ab108a %cmicro %@[{'name': 'H.W. Cain', 'bio': {'p': ['Harold W. Cain is a research staff member at the IBM T.J. Watson Research Laboratory. His research interests include high-performance memory systems, memory consistency model implementation, and end-to-end system optimization. Cain has a BS in computer science from the College of William and Mary, and an MS and PhD in computer science from the University of Wisconsin-Madison. He is a member of the ACM and IEEE.']}}, {'name': 'M.H. Lipasti', 'bio': {'p': ['Mikko H. Lipasti is an assistant professor in the Department of Electrical and Computer Engineering at the University of Wisconsin, Madison. His research interests include the architecture and design of high-performance desktop and server computer systems. Lipasti has a BS in computer engineering from Valparaiso University, and an MS and a PhD in Electrical and Computer Engineering/from Carnegie Mellon University. He is a member of the IEEE.']}} %*Memory ordering: a value-based approach %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1388166 %f/micro/ywmxotcuuqg4if30kspnde2g5wbr71k9.pdf %md73da99dfee96a41e205265eacd345af %cmicro %@[{'name': 'S. Sethumadhavan', 'affiliation': 'Texas Univ., Austin, TX, USA', 'bio': {'p': ['Simha Sethumadhavan is a PhD student in the Department of Computer Sciences at The University of Texas at Austin. His research interests include computer architecture, distributed systems, and application of concepts developed in computer science to other sciences. Sethumadhavan has a B.E. Degree in Computer Science and Engineering from the University of Madras, India.']}}, {'name': 'R. Desikan', 'affiliation': 'Texas Univ., Austin, TX, USA', 'bio': {'p': ['Rajagopalan Desikan is a PhD student in the Department of Electrical and Computer Engineering at UT Austin. His research interests include all aspects of computer architecture. Desikan has a Bachelor of Engineering degree in Electrical Engineering from Regional Engineering College, Trichy, and an M.S.E. degree in Electrical and Computer Engineering from The University of Texas at Austin. He is a member of the ACM.']}}, {'name': 'D. Burger', 'affiliation': 'Texas Univ., Austin, TX, USA', 'bio': {'p': ['Doug Burger is an associate professor of computer sciences at UT Austin. His research interests include high-performance, power-efficient, technology-scalable microprocessors. Burger has a BS from Yale University, and an MS and PhD from the University of Wisconsin, all in computer science. He is an Alfred P. Sloan Foundation Fellow, a senior member of the IEEE, and a member of the ACM.']}}, {'name': 'C.R. Moore', 'affiliation': 'Texas Univ., Austin, TX, USA', 'bio': {'p': ['Charles R. Moore is an AMD Senior Fellow working on next-generation processor designs. His research insterests include technology scalable computer architecture, virtualization, and abstraction. Moore has an MSEE from UT Austin, and an BSEE from Rensselaer Polytechnic Institute.']}}, {'name': 'S.W. Keckler', 'affiliation': 'Texas Univ., Austin, TX, USA', 'bio': {'p': ['Stephen W. Keckler is an associate professor of computer sciences at UT Austin. His research interests include computer architecture and VLSI. Keckler has a BS in electrical engineering from Stanford University, and an MS and a PhD from MIT in computer sci- ences. He is an Alfred P. Sloan Foundation fellow, a member of the ACM, and a senior member of the IEEE.', 'Direct questions and comments about this article to Doug Burger, Department of Computer Sciences, The University of Texas at Austin, 1 University Station C0500, Austin, TX, 78712, dburger@cs.utexas.edu.', 'For further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/publications/dlib.']}} %*Scalable hardware memory disambiguation for high-ILP processors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1388167 %f/micro/so9ngc6pepam7vx8fzioyjdvhm3uthwe.pdf %mfdde2249dd1911d30c40696fb9cab9a4 %cmicro %@[{'name': 'R. Mateosian', 'affiliation': 'xrm@pacbell.net', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/30203/1388172/1388172-photo-1-small.gif', 'p': []}} %*Micro Review: More on old themes %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1388172 %f/micro/ce5bwor6ayotk8f2qvlhdipkxbtzjgwn.pdf %m58438ab2d22fab90d28ae960ee5d411a %cmicro %@[{'name': 'J.W. Lockwood', 'affiliation': 'Washington University', 'bio': {'p': ['John W. Lockwood is a professor of computer science at Washington University in St. Louis. His research interests include design and implementation of networking systems in reconfigurable hardware. Lockwood has BS, MS, and PhD degrees in electrical and computer engineering from the University of Illinois. He will serve as the general chair for the upcoming Hot Interconnects 11 and has served as the program chair for Hot Interconnects 10. He will also serve as the program chair for the upcoming International Conference on Microelectronic Systems Education, and has served on the technical program committee for the International Working Conference on Active Networks. He has reviewed articles for the IEEE Journal on SelectedAreas of Communication, IEEE Transactions on Very Large Scale Integration Systems, ACM Transactions on Embedded Systems, ACM SIGMETRICS, the Computer Networks Journal, and Globecom. He is a member of IEEE, ACM, Tau Beta Pi, and Eta Kappa Nu.']}} %*Hot interconnects 10 - thinking beyond the internet %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1179893 %f/micro/zlfu9xm3otul5kpargipc0o8ec2estnd.pdf %m53a42b38b803af9ebb611801b8752c26 %cmicro %@[{'name': 'F. Abel', 'affiliation': 'IBM Zurich Res. Lab., Ruschlikon, Switzerland', 'bio': {'p': ["François Abel is a research staff member at the IBM Zurich Research Laboratory. His research interests include architecture and VLSI design of high-speed switching systems. Abel has a BS in engineering from the École Nationale d'Ingénieurs Belfort, France, and an MS in electrical engineering from the École Supérieure d'Ingénieurs Marseille, France. He is a member of the IEEE.", 'Direct questions and comments about this article to François Abel, IBM Research, Zurich Research Laboratory, Säumerstrasse 4, CH-8803 Rüschlikon, Switzerland, fab@zurich.ibm.com.']}}, {'name': 'C. Minkenberg', 'affiliation': 'IBM Zurich Res. Lab., Ruschlikon, Switzerland', 'bio': {'p': ['Cyriel Minkenberg is a research staff member in the high-speed switching group at the IBM Zurich Research Laboratory. His work and research interests include architecture design, performance modeling, and simulation in the Prizma project. Minkenberg has an MS and PhD in electrical engineering from the Eindhoven University of Technology, the Netherlands.']}}, {'name': 'R.P. Luijten', 'affiliation': 'IBM Zurich Res. Lab., Ruschlikon, Switzerland', 'bio': {'p': ['Ronald P. Luijten is a research staff member at the IBM Zurich Research Laboratory, where he is manager of the high-speed switching team. His research interests include high-speed switching system design, QoS, network processors, and high-speed and high-density electrooptical interconnects. Luijten has an MS in electronic engineering from the Eindhoven University of Technology, the Netherlands. He coorganized the IEEE International Conference on Computer Communications and Networks in 2001 and 2002.']}}, {'name': 'M. Gusat', 'affiliation': 'IBM Zurich Res. Lab., Ruschlikon, Switzerland', 'bio': {'p': ['Mitchell Gusat is a research staff member at the IBM Zurich Research Laboratory. His research interests include protocols for parallel supercomputing and switching-routing, real-time, QoS, and reconfigurable communication systems, with an emphasis on advanced scheduling and flow control of scalable interconnection networks. Gusat has an MS in electrical engineering from the University of Timisoara, Romania, and an MS in computer engineering from the University of Toronto. He is a member of the IEEE and the ACM.']}}, {'name': 'I. Iliadis', 'affiliation': 'IBM Zurich Res. Lab., Ruschlikon, Switzerland', 'bio': {'p': ['Ilias Iliadis is a research staff member at the IBM Zurich Research Laboratory. His research interests include performance evaluation of computer communication networks, traffic control and engineering for IP and asynchronous transfer mode networks, switch architectures, and stochastic systems. Iliadis has a BS from the National Technical University of Athens, Greece, and an MS and PhD in electrical engineering from Columbia University. He is a member of the Technical Chamber of Greece, IFIP WG 6.3, and Sigma Xi, he is a senior member of the IEEE.']}} %*A four-terabit packet switch supporting long round-trip times %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1179894 %f/micro/fot3fzdqwbsgo8yvuaupenjn5ijzix6d.pdf %m577b46543bc7248b2fee3d5165e48099 %cmicro %@[{'name': ' Hang-Sheng Wang', 'affiliation': 'Dept. of Electr. Eng., Princeton Univ., NJ, USA'}, {'name': ' Li-Shiuan Peh', 'affiliation': 'Dept. of Electr. Eng., Princeton Univ., NJ, USA'}, {'name': 'S. Malik', 'affiliation': 'Dept. of Electr. Eng., Princeton Univ., NJ, USA'} %*A power model for routers: modeling Alpha 21364 and InfiniBand routers %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1179895 %f/micro/vw7zefaarok8veccdtgnyfihlk1ihpom.pdf %mf0914bed78d4f1027a003e9bd62e7b31 %cmicro %@[{'name': ' Rong Pan', 'affiliation': 'Stanford Univ., CA, USA', 'bio': {'p': ['Rong Pan is a research scientist at Stanford University. Her research interests include congestion control, active queue management, TCP performance, and efficient network simulation. Pan has a PhD in electrical engineering from Stanford University.']}}, {'name': 'B. Prabhakar', 'affiliation': 'Stanford Univ., CA, USA', 'bio': {'p': ['Balaji Prabhakar is an assistant professor of electrical engineering and computer science at Stanford University. His research interests include network algorithms, wireless networks, Web caching, network pricing, information theory, and stochastic network theory. Prabhakar has a PhD from the University of California at Los Angeles.']}}, {'name': 'L. Breslau', 'bio': {'p': ['Lee Breslau heads the Internetworking Research Department AT & T Labs—Research in Menlo Park, California. His research interests include packet scheduling, real-time service, network measurement, and routing. Breslau has a PhD from the University of Southern California.']}}, {'name': 'S. Shenker', 'bio': {'p': ["Scott Shenker is group leader at the International Computer Science Institute's Center for Internet Research. His research interests range from computer performance modeling and computer networks to game theory and economics. Shenker has a PhD from the University of Chicago.", 'Direct questions and comments about this article to Rong Pan, Stanford University, Packard Rm. 270, 350 Serra Mall, Stanford, CA 94305–9510, rong@stanford.edu.']}} %*Approximate fair allocation of link bandwidth %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1179896 %f/micro/nanu1pddqj8c9txfk5bszvrg3co7tpke.pdf %m62217eed5e11b9bcf95cfb65bca63327 %cmicro %@[{'name': 'R. Panigrahy', 'affiliation': 'Cisco Syst., Sunnyvale, CA, USA', 'bio': {'p': ["Rina Panigrahy is a software engineer at Cisco Systems. His research interests include theoretical algorithms, TCAM algorithms for forwarding, ACLs, power reduction, RAM-based algorithm for IPv6, and regular expression processing for L7 switching. Panigrahy has a master's degree from MIT, where he worked on Web caching technology that became the basis for founding Akamai Technologies."]}}, {'name': 'S. Sharma', 'affiliation': 'Cisco Syst., Sunnyvale, CA, USA', 'bio': {'p': ['Samar Sharma is a senior software engineer at Cisco Systems. His work experience includes several products involving IP forwarding, TCAMs, network processors, access lists, and storage networking. Sharma has a BTech in computer science from the Indian Institute of Technology, Delhi, and an MS from the University of Maryland. He has coauthored several patent applications and research papers while at Cisco.', 'Direct questions and comments about this article to Samar Sharma, 655 South Fair Oaks Ave., #E204, Sunnyvale, CA 94086, ssharma@cisco.com.']}} %*Sorting and searching using ternary CAMs %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1179897 %f/micro/p5nvskwhqb9lr7ywmij8gzuvnbjemiyf.pdf %m226d2d495165f35947be7fd3ecc6e317 %cmicro %@[{'name': 'D.V. Schuehler', 'affiliation': 'Appl. Res. Lab., Washington Univ., USA', 'bio': {'p': ['David V. Schuehler is a doctoral student in the Applied Research Laboratory of Washington University in St. Louis. He is also vice president of research and development for Reuters. His research interests include realtime processing, embedded systems, and high-speed networking. Schuehler has a BS in aeronautical and astronautical engineering from Ohio State University and an MS in computer science from the University of Missouri- Rolla. He is a member of the IEEE and the ACM.']}}, {'name': 'J.W. Lockwood', 'affiliation': 'Appl. Res. Lab., Washington Univ., USA', 'bio': {'p': ['John W. Lockwood is a professor of computer science at Washington University in St. Louis. His research interests include design and implementation of networking systems in reconfigurable hardware. Lockwood has BS, MS, and PhD degrees in electrical and computer engineering from the University of Illinois. He will serve as the general chair for the upcoming Hot Interconnects 11 and has served as the program chair for Hot Interconnects 10. He will also serve as the program chair for the upcoming International Conference on Microelectronic Systems Education, and has served on the technical program committee for the International Working Conference on Active Networks. He has reviewed articles for the IEEE Journal on SelectedAreas of Communication, IEEE Transactions on Very Large Scale Integration Systems, ACM Transactions on Embedded Systems, ACM SIGMETRICS, the Computer Networks Journal, and Globecom. He is a member of IEEE, ACM, Tau Beta Pi, and Eta Kappa Nu.']}} %*TCP Splitter: a TCP/IP flow monitor in reconfigurable hardware %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1179898 %f/micro/elcksa8xbfgehc5ikti3qnhvjytufgyz.pdf %md7b023089514b214314281ac841626fc %cmicro %@[{'name': 'H. Eberle', 'affiliation': 'Sun Microsystems Labs., Mountain View, CA, USA', 'bio': {'p': ['Hans Eberle is a senior staff engineer at Sun Microsystems Laboratories in Mountain View, California. His research interests include interconnects, networks, and security. He has an MS in electrical engineering and a PhD in technical sciences from the Swiss Federal Institute of Technology, Zurich.', 'For further information on this or any other computing topic, visit our Digital Library at http://computer.org/publications/dlib.']}} %*A radio network for monitoring and diagnosing computer systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1179899 %f/micro/pnmsyi87o15j2jq0hkwdfegdmyxcq3ru.pdf %me567651673f3b0240fd1104986bcef3e %cmicro %@[{'name': 'M.A. Viredaz', 'affiliation': 'Hewlett-Packard Labs., Palo Alto, CA, USA', 'bio': {'p': ['Marc A. Viredaz is a senior member of the technical staff at Hewlett-Packard Laboratories. He performed the work described in this article at Compaq before it merged with Hewlett-Packard. His research interests include handheld and mobile computing, low-power systems, multiprocessor systems, and computer architecture. Viredaz has a PhD in computer engineering from the Swiss Federal Institute of Technology at Lausanne. He is a member of the IEEE and the IEEE Computer Society.']}}, {'name': 'D.A. Wallach', 'bio': {'p': ["Deborah A. Wallach is a software engineer at Google's System Laboratory. She was previously at Compaq, where she performed the work described in this article. Her research interests include mobile computing, operating systems, and power management. Wallach has a PhD in computer science from the Massachusetts Institute of Technology."]}} %*Power evaluation of a handheld computer %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1179900 %f/micro/chaysl6vwcgimjigre3n4qmktfx91b2e.pdf %mf8edd4578097d06748e3a45869efe371 %cmicro %@[{'name': 'R.H. Stern'} %*Weird turn of events in continuing rambus saga %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1179901 %f/micro/jhlykz8160ad9kfuxsrw73xitgsqpgve.pdf %m7e218f38af17dd22a99a0d230ad3f2bb %cmicro %@[{'name': 'R. Mateosian'} %*Leadership annoyances %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1179902 %f/micro/p86d9gs275tlobanhkirwtakueg0hxsq.pdf %m66e64ad7cde06657d849e6015548d45f %cmicro %@[{'name': 'S. Greenstein'} %*Where did the Internet go? [user census] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1179903 %f/micro/zdwrne01mkzvdcnq47b3tyasuvx6hfli.pdf %m824429c429a62d69d4f26bdec2bb0415 %cmicro %@[{'name': 'R. Mateosian', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/26907/1196109/1196109-photo-1-small.gif', 'p': ['Richard Mateosian']}} %*Nuts and bolts %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1196109 %f/micro/vmrxtzxyp0y5dqg8ltne4kkhmhaiones.pdf %m7774220addc7729c489a4e5cf651b69a %cmicro %@[{'name': 'J. Wawrzynek', 'affiliation': 'University of California, Berkeley'}, {'name': 'K. Diefendorff'} %*Hot Chips 14 - Innovation in the face of uncertain economics %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1196110 %f/micro/xuyo4dzdbij6cltaioqpwvnych7j5x1a.pdf %m6af2959198cbce60ae9cf62b77903925 %cmicro %@[{'name': 'A.K. Wong', 'affiliation': 'Dept. of Electr. & Electron. Eng., Hong Kong Univ., China', 'bio': {'p': ['Alfred K. Wong is an associate professor in the Department of Electrical and Electronic Engineering at The University of Hong Kong. His research interests include IC design and fabrication, including resolution enhancement techniques in microlithography, ICs for communications and signal processing, and the synergies between circuit design and fabrication. Wong has a BS, an MS, and PhD in electrical engineering from the University of California, Berkeley. He received the 1990 IEEE Fortescue Fellowship, and serves as the chair of the SPIE Conference on Cost and Performance in IC Creation and as associate editor of the Journal of Microlithography, Microfobrication, and Microsystems.']}} %*Microlithography: trends, challenges, solutions, and their impact on design %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1196111 %f/micro/g26tl9pxykcsruv1zjza5evojbu3chpt.pdf %m31d0d0faf20796b64295d8b6580b3ca4 %cmicro %@[{'name': 'L.A. Barroso', 'bio': {'p': ["Luiz André Barroso is a member of the Systems Lab at Google, where he has focused on improving the efficiency of Google's Web search and on Google's hardware architecture. Barroso has a BS and an MS in electrical engineering from Pontifícia Universidade Católica, Brazil, and a PhD in computer engineering from the University of Southern California. He is a member of the ACM."]}}, {'name': 'J. Dean', 'bio': {'p': ['Jeffrey Dean is a distinguished engineer in the Systems Lab at Google and has worked on the crawling, indexing, and query serving systems, with a focus on scalability and improving relevance. Dean has a BS in computer science and economics from the University of Minnesota and a PhD in computer science from the University of Washington. He is a member of the ACM.']}}, {'name': 'U. Holzle', 'bio': {'p': ['Urs Hölzle is a Google Fellow and in his previous role as vice president of engineering was responsible for managing the development and operation of the Google search engine during its first two years. Hölzle has a diploma from the Eidgenössische Technische Hochschule Zürich and a PhD from Stanford University, both in computer science. He is a member of IEEE and the ACM.', 'For further information on this or any other computing topic, visit our Digital Library at http://computer.org/publications/dlib.']}} %*Web search for a planet: The Google cluster architecture %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1196112 %f/micro/y1bxwv3jig5hwm0h2fdkakba9ruvcixp.pdf %m7e1de048a15e3a674569db2d9e84afda %cmicro %@[{'name': 'J. Nickolls', 'bio': {'p': ['John Nickolls is director of architecture at NVIDIA. He was director of architecture at Broadcom and vice president of architecture at Silicon Spice during the work described here. His interests include processor architecture, parallel systems, and evolutionary computation. Nickolls has a BS in electrical engineering and computer science from the University of Illinois, and MS and PhD degrees in electrical engineering from Stanford University. He is a member of the IEEE and the IEEE Computer, Communications, Signal Processing, and Neural Networks Societies.']}}, {'name': 'L.J. Madar', 'bio': {'p': ["L.J. Madar III is an engineering manager in Broadcom's Custom Integration design group and manages the development of products merging customer logic and Broadcom intellectual property. His research interests include processor architecture, high-performance memory systems, and techniques for low-power design. Madar has a bachelor of electrical engineering from the Georgia Institute of Technology and an MS in electrical engineering from Stanford University."]}}, {'name': 'S. Johnson', 'bio': {'p': ['Scott Johnson is an independent consultant doing hardware research and development for a pair of Silicon Valley start-ups. His research interests include DSP and processor microarchitecture, and verification. Johnson has a BS in computer science and a BS in electrical engineering from Washington University, St. Louis, and an MS in electrical engineering from Stanford University.']}}, {'name': 'V. Rustagi', 'bio': {'p': ["Viresh Rustagi is senior engineering manager for Broadcom's Carrier Access business unit and the architect of Calisto's OS. His research interests include real-time systems and computer architectures. Rustagi has a BS in computer science from Institute of Technology, Banaras Hindu University, India, an MBA from Santa Clara University, and an MS in computer science from Florida State University."]}}, {'name': 'K. Unger', 'bio': {'p': ['Ken Unger is director of engineering for VoIP products at Broadcom. His research interests include real-time systems and software architectures for programmable DSPs. Unger has a BS in electrical engineering from the Universi ty of Saskatchewan.']}}, {'name': 'M. Choudhury', 'bio': {'p': ['Mustafiz Choudhury is an entrepreneur and founder of a new semiconductor start-up company in Silicon Valley. Previously, he led the Carrier Access business unit at Broadcom, where the Calisto product family was developed. His research interests include highperformance processor architectures, methodologies for high-performance IC design, low-power design techniques, and integrated solutions for wireless applications. Choudhury has a BS in electrical engineering from Bangladesh University of Engineering and Technology, and an MS in electrical engineering from Virginia Tech. He is a member of the IEEE and the IEEE Computer and Communication Societies.', 'For further information on this or any other computing topic, visit our Digital Library at http://computer.org/publications/dlib.']}} %*Calisto: A low-power single-chip multiprocessor communications platform %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1196113 %f/micro/ybjklrifo4oxziv8qte2axcf1gwppnht.pdf %m6a590ab2f918264b0cd4b938461acaa5 %cmicro %@[{'name': 'C. McNairy', 'bio': {'p': ['Cameron McNairy is an Itanium 2 processor microarchitect at Intel. His research interests include high-performance technical computing and large-system design issues. McNairy has a BSEE and an MSEE from Brigham Young University. He is a member of the IEEE.']}}, {'name': 'D. Soltis', 'bio': {'p': ['Don Soltis is an Itanium 2 processor micro-architect at Hewlett-Packard. His research interests include microprocessor cache design and microprocessor verification. Soltis has a BSEE and an MSEE from Colorado State University.']}} %*Itanium 2 processor microarchitecture %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1196114 %f/micro/dii2vab0kkrsmo7qxf4tpoq8w1nly9lc.pdf %m85222e1e7d655eb252183970cf6f54e8 %cmicro %@[{'name': 'D. Koufaty', 'bio': {'p': ["David Koufaty is a CPU architect with Intel's Desktop Products Group and is responsible for hyperthreading technology performance. His main research interests are processor microarchitecture and performance. He has BS and MS degrees from Simon Bolivar University, Venezuela, and a PhD in computer science from the University of Illinois at Urbana-Champaign."]}}, {'name': 'D.T. Marr', 'bio': {'p': ['Deborah T. Marr is one of the CPU architects in the Intel Desktop Products Group responsible for hyperthreading technology. Her research interests include high-performance microarchitecture and performance analysis. She has a BS in electrical engineering and computer science from the University of California, Berkeley, and an MS in electrical and computer engineering from Cornell University.']}} %*Hyperthreading technology in the netburst microarchitecture %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1196115 %f/micro/gdklcrwjzqx4p6z9hfan1dgueswmkmbh.pdf %me0fe8032fed32597acf128f8e8daa592 %cmicro %@[{'name': 'C.N. Keltcher', 'bio': {'p': ['Chetana N. Keltcher is a member of the technical staff at Advanced Micro Devices. She worked on the K6 and Athlon microprocessors and is now part of the Opteron architecture team where she is responsible for the load-store and data cache design. Keltcher has a BE in computer science from Bangalore University, India, and an MS and PhD in computer science from the Pennsylvania State University. She is a member of the IEEE.']}}, {'name': 'K.J. McGrath', 'bio': {'p': ["Kevin J. McGrath is a fellow at AMD, California Microprocessor Division. He is the architect of AMD's 64-bit extensions and currently manages the Opteron architecture and RTL team. His work experience includes 20 years in CPU design and verification, first for Hewlett-Packard and later for ELXSI, eventually working on the microarchitecture of the Nx586, K6, and Athlon processors, leading the microcode team for those projects. McGrath has a BS in engineering technology from California Polytechnic University, San Luis Obispo."]}}, {'name': 'A. Ahmed', 'bio': {'p': ['Ardsher Ahmed was a senior member of the technical staff, design engineer, at AMD. His research interests include designing high-performance computer architectures, multiprocessor systems, server development, supercomputing and massively parallel processing, high-bandwidth low-latency interconnection network design, performance evaluation, and microbenchmarking. Ahmed has a BS in electrical engineering from NED University of Engineering and Technology, Karachi, Pakistan, an MS in electrical engineering from the California Institute of Technology, Pasadena, and a PhD in computer engineering from Binghamton University, New York. He is a member of the IEEE.']}}, {'name': 'P. Conway', 'bio': {'p': ['Pat Conway is a senior member of technical staff in the Computational Products Group at AMD where he is responsible for developing scalable, high-performance server architectures. His work experience includes the design and development of server hardware, cache coherence protocols, user-level message passing, and clustering technology. Conway has an MEngSc from the University College Cork, Ireland, and an MBA from Golden Gate University. He is a member of the IEEE.', 'For more information on AMD Opteron, see the Web site at http://www.amd.com/opteron/.']}} %*The AMD Opteron processor for multiprocessor servers %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1196116 %f/micro/c5ifknutzmoxnujx6a3qk4edglepms0p.pdf %m703bd358a8782b1969df530888e8b861 %cmicro %@[{'name': 'S. Greenstein', 'affiliation': 'Northwestern', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/26907/1196117/1196117-photo-1-small.gif', 'p': ['Shane Greenstein']}} %*Too much internet backbone? %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1196117 %f/micro/jlvnmemgkwlcobvsjp8ygd05rnt4q62w.pdf %me508add2b25c0c98d8fd336d566f89e4 %cmicro %@[{'name': 'A. Sangiovanni-Vincentelli', 'affiliation': 'University of California', 'bio': {'p': ['Alberto Sangiovanni-Vincentelli holds the Edgar L. and Harold H. Buttner Chair of Electrical Engineering and Computer Science at the University of California, Berkeley. His research interests include design tools and methodologies, large-scale systems, embedded controllers, and hybrid systems. Sangiovanni-Vincentelli has a DrIng in electrical engineering from the Politecnico di Milano, Italy. He is a cofounder of Cadence and Synopsys, an IEEE Fellow, and a member of the National Academy of Engineering.']}}, {'name': 'L. Lavagno', 'bio': {'p': ['Luciano Lavagno is an associate professor at the Politecnico di Torino, Italy, and a research scientist at Cadence Berkeley Laboratories. Lavagno has a DrIng in electrical engineering from the Politecnico di Torino and a PhD in EECS from the University of California, Berkeley. He is coauthor of two books on asynchronous circuit design and a book on hardware-software codesign for embedded systems. His research interests include the synthesis of asynchronous and low-power circuits, the concurrent design of mixed hardware and software embedded systems, and dynamically reconfigurable processors.', 'Direct questions and comments about this special issue to Luciano Lavagno, Politecnico di Torino, Dipartimento di Elettronica, Corso Duca degli Abruzzi 24, 10129 Torino, Italy, lavagno@polito.it.']}} %*Introduction: trends and directions in microelectronics (Guest Editors' Introduction) %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1209461 %f/micro/2evp7krlcftqcnggi6kubjayx1hlpdfq.pdf %ma92893d0f7e074d3c28ca243445a9c67 %cmicro %@[{'name': 'A. Sangiovanni-Vincentelli', 'affiliation': 'California Univ., Berkeley, CA, USA', 'bio': {'p': ['Alberto Sangiovanni-Vincentelli is a guest editor of this issue. His biography appears on page 9.', 'For further information on this or any other computing topic, visit our Digital Library at http://computer.org/publications/dlib.']}} %*Electronic-system design in the automobile industry %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1209462 %f/micro/focg51knwpxjqtrmlyl7jihybidtuar6.pdf %m46602b82ee374f6afdae610d0c21b945 %cmicro %@[{'name': 'T.A.C.M. Claasen', 'affiliation': 'Philips Semicond., Eindhoven, Netherlands', 'bio': {'p': ['Theo A.C.M. Claasen is executive vice president of technology and strategy at Philips Semiconductors in Eindhoven, The Netherlands, he is also chief technology officer. His research interests include system-level design, IC design, and digital signal processing. Claasen has a PhD in telecommunications from Royal Institute of Technology in Stockholm, Sweden. He is a Fellow of the IEEE.', 'For further information on this or any other computing topic, visit our Digital Library at http://computer.org/publications/dlib.']}} %*System on a chip: changing IC design today and in the future %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1209463 %f/micro/fcdw9xbpgrhjdvr2g4aeyzpn65uykquv.pdf %m5c0d6adcfcdcadbf952b1e125d6a1d93 %cmicro %@[{'name': 'J.D. Meindl', 'affiliation': 'Georgia Inst. of Technol., Atlanta, GA, USA', 'bio': {'p': ["James Meindl is the Director of the Joseph M. Pettit Microelectronics Research Center and holds the Joseph M. Pettit Chair as Professor of Microelectronics at the Georgia Institute of Technology. He is also Director of the Interconnect Focus Center, a multiuniversity research effort managed jointly by the Microelectronics Advanced Research Corp. and the Defense Advanced Research Projects Agency. His research interests include the physical limits of gigascale integration and nanotechnology. Meindl has bachelor's, master's, and doctor's degrees in electrical engineering from the Carnegie Institute of Technology (now Carnegie Mellon University). He is a Life Fellow of IEEE and the American Association for the Advancement of Science, and a member of the American Academy of Arts and Sciences and the National Academy of Engineering."]}} %*Interconnect opportunities for gigascale integration %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1209464 %f/micro/xopdh8j3y4klashrxvyetbe6cj5ubang.pdf %mdc79f474916f92cf2b6a49887e501500 %cmicro %@[{'name': 'B. Murari', 'affiliation': 'STMicroelectronics, Milano, Italy', 'bio': {'p': ["Bruno Murari directs the Castelletto Research and Development laboratories of STMicroelectronics in Cornaredo, Italy. His research interests include developing technologies for smart power ICs, MEMS, and photonics. Murari has a degree in electrical technology from the Pacinotti Technical Institute, Venezia-Mestre, and a postgraduate degree in electronics from the Beltrami Institute, Milan. He also has an honorary degree in electronic engineering from Politecnico di Milano and an honorary degree in information science from Università Ca'Foscari in Venice. He is a member of the Scientific Council for the Laboratory of Chemistry and Technology of Materials and Components for Electronics (Lamel) in Bologna, and the Italian National Research Council commission for the evaluation of funded projects on nanotechnologies and microsystems."]}} %*Integrating nonelectronic components into electronic microsystems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1209465 %f/micro/2gdpdag4kzseq7myt8kffx0zrxle6thw.pdf %ma3875a852829315bc184fdd0484e6526 %cmicro %@[{'name': 'N. Richardson', 'affiliation': 'STMicroelectronics, San Diego, CA, USA', 'bio': {'p': ['Nick Richardson is an STMicroelectronics Fellow, who led the development of the iCore microarchitecture. His research interests include the definition and design of microprocessor, cache memory, and network architectures. Richardson has a BSEE from the University of London.']}}, {'name': ' Lun Bin Huang', 'affiliation': 'STMicroelectronics, San Diego, CA, USA', 'bio': {'p': ['Lun Bin Huang is a senior principal engineer at STMicroelectronics. His contribution to the iCore project includes microarchitecture and design of branch prediction, instructions decode and issue, and operand fetch. His research interests include architecture and design of high-performance CPU cores and network processors. Huang has an MSEE from California State University, Long Beach. He is a member of the IEEE.']}}, {'name': 'R. Hossain', 'affiliation': 'STMicroelectronics, San Diego, CA, USA', 'bio': {'p': ['Razak Hossain is senior principal engineer at STMicroelectronics in La Jolla, Calif. His research interests include the design of high-speed circuits and interconnects. Hossain has a PhD in electrical engineering from the University of Rochester. He is a member of the IEEE.']}}, {'name': 'J. Lewis', 'affiliation': 'STMicroelectronics, San Diego, CA, USA', 'bio': {'p': ["Julian Lewis was the iCore project manager for STMicroelectronics. He has worked as architect, methodologist, verifier, and project manager for ST20 cores. He now works on the architectural definition of ST's DVD chips and manages a team implementing audio software for DVD players. Lewis has a BSc in computer science from the University of Manchester."]}}, {'name': 'T. Zounes', 'affiliation': 'STMicroelectronics, San Diego, CA, USA', 'bio': {'p': ["Tommy Zounes is a senior principal engineer at STMicroelectronics who works in the advanced design group in ST's Central Research and Development Division in La Jolla, developing a Domino style library for synthesis flow. His research interests include custom high-speed digital design solutions, which include front to back designing of standard-cell libraries, RAMs, ROMs, and register files. Zounes has a BSEE and an MSEE from San Diego State University. He is a member of the IEEE."]}}, {'name': 'N. Soni', 'affiliation': 'STMicroelectronics, San Diego, CA, USA', 'bio': {'p': ['Naresh Soni is vice president of US central research and development for STMicroelectronics. His research interests include highperformance circuits and systems. Soni has a BSEE from the University of Bombay, India, and an MSEE from the University of Texas, Austin. He is a member of the IEEE.', 'For more information on this or any other computing topic, visit our Digital Library at http://computer.org/publications/dlib.']}} %*The iCore 520-MHz synthesisable CPU core %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1209466 %f/micro/m2g4gxmxy0finhjktas7jvezwfbncrqr.pdf %m46718694f6b6ff6d7867fd6c59993ae3 %cmicro %@[{'name': 'A. Neve', 'affiliation': 'Univ. Catholique de Louvain, Belgium', 'bio': {'p': ["Amaury Nève is a doctoral candidate and research assistant with the Microelectronics Laboratory of the Université catholique de Louvain (UCL), Louvain-la-Neuve, Belgium. His research interests include the development of design techniques for high-speed and low-power digital circuits in advanced SOI processes. Nève has a master's degree in electrical engineering from UCL. He is a member of the IEEE."]}}, {'name': 'D. Flandre', 'affiliation': 'Univ. Catholique de Louvain, Belgium', 'bio': {'p': ['Denis Flandre is a professor of microelectronics in the Electrical Engineering Department at UCL and cofounder of Cissoid SA, a start-up focusing on SOI circuit design. His research interests include SOI devices, digital and analog circuits, sensors, and micro-electromechanical systems for special applications (such as those for high-speed, low-voltage and low-power, microwave, and']}}, {'name': 'J.-J. Quisquater', 'affiliation': 'Univ. Catholique de Louvain, Belgium'} %*SOI technology for future high-performance smart cards %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1209467 %f/micro/vdpknepgbqutzeixw6fglrr9ya85s1sz.pdf %mbba0084a3514b8e96b6f203009231cfa %cmicro %@[{'name': 'S. Greensteen'} %*An era of error %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1209468 %f/micro/3uolbeu1rtmqdkkl6wxhzi5rjn4snvhj.pdf %mb79014bd4efb2dfa3ab7552516a2e19b %cmicro %@[{'name': 'R. Mateosian'} %*Evolution %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1209469 %f/micro/g0vhwoqxdxupmbce5kpt1bn4imyvzfzh.pdf %mfecc1a9bcbeeab1883bb7f0d74f07851 %cmicro %@[{'name': 'S. Greenstein'} %*Moore meets Malthus in multiples %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1225948 %f/micro/0jv8asg5w6fupcevyzjte92a4fmndiow.pdf %m55075f532dd8e4eafba5c5531d5a7cd1 %cmicro %@[{'name': 'R. Mateosian'} %*Managing software projects %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1225949 %f/micro/vg501a7ncdhqs4fvopxwbmeeqpkrsiuj.pdf %m7096b17ae8133a92a7252fc67ff0ae6a %cmicro %@[{'name': 'C. Constantinescu', 'bio': {'p': ["Cristian Constantinescu is a reliability, availability, and serviceability architect with Intel's Enterprise Architecture Laboratory. His research interests include fault-tolerant computing, validation of highly dependable systems, and dependability modeling. Constantinescu has a PhD in electrical and computer engineering from the Polytechnic University of Bucharest, Romania. He is a senior member of the IEEE."]}} %*Trends and challenges in VLSI circuit reliability %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1225959 %f/micro/h6m5hppxasql9n7ryrkgijamowgt4lvc.pdf %md62aba8f20936bc1a80f9f2c2fb597f6 %cmicro %@[{'name': 'S. Vassiliadis', 'affiliation': 'Delft Univ. of Technol., Netherlands', 'bio': {'p': ['Stamatis Vassiliadis is the chair professor of the Computer Engineering Laboratory in the Electrical Engineering Department at Delft University of Technology, Delft, the Netherlands. His research interests include embedded systems, multimedia processors, computer architecture, hardware design of computer systems, custom computing machines, hardware/software co-design, computer arithmetic, low-power design, nanocomputing, and network processing. Vassiliadis has a PhD in electrical engineering from Politecnico di Milano, Italy. He is an IEEE Fellow and a member of the IEEE Computer Society.']}}, {'name': 'S. Wong', 'affiliation': 'Delft Univ. of Technol., Netherlands', 'bio': {'p': ['Stephan Wong is an assistant professor with the Computer Engineering Laboratory in the Electrical Engineering Department at Delft University of Technology, Delft, the Netherlands. His research interests include embedded systems, multimedia processors, complex instruction set architectures, reconfigurable and parallel processing, microcoded machines, and network processors. Wong has a PhD in computer engineering from Delft University of Technology, Delft, the Netherlands.']}}, {'name': 'S. Cotofana', 'affiliation': 'Delft Univ. of Technol., Netherlands', 'bio': {'p': ['Sorin Cotofana is an associate professor with the Computer Engineering Laboratory in the Electrical Engineering Department at Delft University of Technology, Delft, the Netherlands. His research interests include computer arithmetic, parallel architectures, embedded systems, neural networks, fuzzy logic, computational geometry, and computer-aided design. Cotofana has a PhD in electrical engineering from Delft University of Technology, the Netherlands. He is a senior member of the IEEE Computer Society.']}} %*Microcode processing: Positioning and directions %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1225960 %f/micro/gurv5zxwg2tntefiziylfb9oq4x8kebh.pdf %m8ed1fc0d2feae4d4471e58eba1a89d97 %cmicro %@[{'name': ' Wangyang Lai', 'bio': {'p': ['Wangyang Lai is an IC designer at Agere Systems. His research interests include network processing and computer architecture. Lai has a Mphil in electrical and electronic engineering from the Hong Kong University of Science and Technology.']}}, {'name': ' Chin-Tau Lea', 'bio': {'p': ['Chin-Tau Lea is a professor in the electrical engineering department at the Hong Kong University of Science and Technology. His research interests include the general area of network technologies, the development of crosstalk-free photonic switching theory, and the exploration of the mobility/capacity conversion process in wireless networks. Lea has a BSEE and an MSEE from the National Taiwan University, Republic of China, and a PhD in electrical engineering from the University of Washington. He is a member of the editorial boards of IEEE and Computer Networks.', 'For further information on this or any other computing topics, visit our Digital Library at http://computer.org/publications/dlib.']}} %*A programmable state machine architecture for packet processing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1225965 %f/micro/tr4csm07sfabemf9xy3zwgnzpd6uw1bq.pdf %m1e1abde8e83be0344191b08a6353ced1 %cmicro %@[{'name': 'B. Jacob', 'affiliation': 'Maryland Univ., Baltimore, MD, USA', 'bio': {'p': ['Bruce Jacob is an associate professor in the Electrical and Computer Engineering Department of the University of Maryland, College Park. His research interests include memory systems, embedded systems, and operating systems. Jacob has a PhD in computer science and engineering from the University of Michigan, Ann Arbor. He is a member of the IEEE and the ACM.']}} %*A case for studying DRAM issues at the system level %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1225969 %f/micro/qy9o0j6krxtug45k3uhgqaidecvamptz.pdf %m61b636f0766f5474c702e5c5c8e8f4f1 %cmicro %@[{'name': 'K. Karadayi', 'affiliation': 'Univ. of Washington, Seattle, WA, USA', 'bio': {'p': ["Kerem Karadayi is a PhD candidate and research assistant at the Image Computing Systems Laboratory, Departments of Electrical Engineering and Bioengineering, University of Washington, Seattle. His research interests include ultrasound imaging, realtime image/video computing, and computer architecture. Karadayi has a master's degree in electrical engineering from the University of Washington, Seattle. He is a student member of the IEEE."]}}, {'name': 'V. Markandey', 'bio': {'p': ['Vishal Markandey is a distinguished member of the technical staff in the Digital Video department at Texas Instruments. His research interests include video processor architectures, digital mediaprocessors, and DLP display systems. Markandey has a masters degree in electrical engineering from Rice University. He is a member of the IEEE.']}}, {'name': 'J. Golston', 'bio': {'p': ['Jeremiah Golston is a distinguished member of the technical staff and CTO for the DSP Video and Imaging Business at Texas Instruments. His research interests include video processor architectures and digital mediaprocessors. Golston has a masters degree in electrical engineering from the University of Missouri-Rolla. He is a senior member of the IEEE.']}}, {'name': 'R.J. Gove', 'bio': {'p': ['Robert J. Gove is vice president of imaging at Micron Technology. His research interests include CMOS image sensors, video DSPs, DLP display systems, and embedded DRAM technologies. Gove has a PhD in electrical engineering from Southern Methodist University.']}}, {'name': ' Yongmin Kim', 'bio': {'p': ['Yongmin Kim is a professor in and chair of the Department of Bioengineering, University of Washington, Seattle. His research interests include mediaprocessor architecture and algorithms, and systems for multimedia, image processing, and medical imaging. Kim has a PhD in electrical engineering from the University of Wisconsin, Madison. He is a Fellow of the IEEE.']}} %*Strategies for mapping algorithms to mediaprocessors for high performance %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1225972 %f/micro/bt7sfxvojc41kjwmlg9abhyv8wedqx6u.pdf %mcc31ce32b217382642a3ad9aa3c29ad9 %cmicro %@[{'name': 'J. Hennessy', 'affiliation': 'Stanford University'}, {'name': 'D. Citron'}, {'name': 'D. Patterson'}, {'name': 'G. Sohi'} %*The use and abuse of SPEC: An ISCA panel %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1225977 %f/micro/3rqg17ibpxzlebgs2u0fsyltav6hzpoa.pdf %m6092f1565a3b02161d6aa29c491a61ba %cmicro %@[{'name': 'A. Clements'} %*CSIDC: Competing students design real-world systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1225979 %f/micro/wqhb4ans6dsi8m2zpjrldi3ac0pz9fxf.pdf %m67bc57c5da76cd44685b7ba52eec374d %cmicro %@[{'name': 'R.H. Stern'} %*Unresolved legal questions about patents and standard setting %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1240194 %f/micro/27ieks04lgqokjfyaredtchd8upmy6qb.pdf %mec453ccdbfdbb027470400e6131a89c7 %cmicro %@[{'name': 'R. Mateosian', 'affiliation': 'PacBell'} %*How the internet works, 7th ed. [Book Review] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1240195 %f/micro/bdedorcsnxstpi9ah2uwpyi7rxqgvkgu.pdf %m8b5a4460f6f9512323286c23608f9bc3 %cmicro %@[{'name': 'P. Bose', 'affiliation': 'IBM T.J. Watson Research', 'bio': {'p': ['Pradip Bose is research staff member and project leader at the IBM T.J. Watson Research Center, he is also editor in chief of IEEE Micro. Hisresearch interests include highperformance computer architectures, power-and complexity-aware design, and computeraided design. Bose has a PhD in electrical and computer engineering from the University of Illinois, Urbana-Champaign. He is a senior member of the IEEE and the Computer Society and a member of ACM.']}}, {'name': 'D.H. Albonesi', 'bio': {'p': ['David H. Albonesi is an associate professor of electrical and computer engineering at the University of Rochester. His research interests include power-aware computing, adaptive microarchitectures, and multithreaded architectures. Albonesi has a PhD in computer engineering from the University of Massachusetts at Amherst. He is a senior member of the IEEE and a member of the ACM.']}}, {'name': 'D. Marculescu', 'bio': {'p': ['Diana Marculescu is an assistant professor of electrical and computer engineering at Carnegie Mellon University, Pittsburgh, Pennsylvania. Her research interests include energy-aware computing, CAD tools for low-power systems, and emerging technologies (such as electronic textiles or ambient intelligent systems). Marculescu has a MS in computer science from the Politehnica University of Bucharest, Romania, and a PhD in computer engineering from the University of Southern California. She is a member of the IEEE, the ACM, and the ACM Special Interest Group on Design Automation (SIGDA).']}} %*Guest editors' introduction: Power and complexity aware design %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1240208 %f/micro/qafbyaeot4o01hixkhmkzdw9d3nvriqu.pdf %m2fc75dc6fcdebb243fe7645950840ef4 %cmicro %@[{'name': 'M.C. Huang', 'affiliation': 'Dept. of Comput. Sci., Rochester Univ., NY, USA', 'bio': {'p': ['Michael C. Huang is an assistant professor in the Department of Electrical and Computer Engineering and the Department of Computer Science at the University of Rochester, New York. His research interests include computer system architecture and processor microarchitecture, with emphases on adaptive architecture, power-aware design, and system optimization. Huang has a PhD in computer science from the University of Illinois at Urbana-Champaign. He is a member of the IEEE and the ACM.']}}, {'name': 'D. Chaver', 'bio': {'p': ['Daniel Chaver is pursuing a PhD in the Computer Architecture Department of the Universidad Complutense de Madrid (UCM). His research interests include energy-aware architectures and code optimization for modern microprocessors. Chaver has an MS in physics from the Universidad de Santiago de Compostela and an MS in electrical and computer engineering from UCM. He is a student member of the IEEE and the Computer Society.']}}, {'name': 'L. Pinuel', 'bio': {'p': ['Luis Piñuel is an assistant professor in the UCM Computer Architecture Department. His research interests include microprocessor architecture with emphasis on value prediction, power-aware processors, and code optimization. Piñuel has MS and PhD degrees in computer science from UCM. He is a member of the IEEE and the Computer Society.']}}, {'name': 'M. Prieto', 'bio': {'p': ['Manuel Prieto is an associate professor in the UCM Computer Architecture Department. His research interests include code optimization, performance, power, and memory issues in superscalar and embedded processors. Prieto has an MS in computational physics and a PhD in computer science, both from UCM. He is a member of the IEEE and the Computer Society.']}}, {'name': 'F. Tirado', 'bio': {'p': ['Francisco Tirado is a professor in the UCM Computer Architecture Department. His research interests include energy-aware processors, dynamic optimization, and parallel architectures. Tirado has MSand PhD degrees in physics from UCM. He is a senior member of the IEEE, a member of the ACM, and adviser to the Spanish National Agency for Research and Development.']}} %*Customizing the branch predictor to reduce complexity and energy consumption %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1240209 %f/micro/lcinhwpxf2gvuttvdodf8z1oxyrmqhr4.pdf %m2a46bf5a1d15c94b22f31eab885b18bb %cmicro %@[{'name': 'L. Eeckhout', 'affiliation': 'Dept. of Electron. & Inf. Syst., Ghent Univ., Belgium', 'bio': {'p': ['Lieven Eeckhout is a postdoctoral researcher in the Department of Electronics and Information Systems at Ghent University, Belgium. His research interests include computer architecture, performance analysis, and workload characterization. Eeckhout has a PhD in Computer Science and Engineering from Ghent University.', 'Direct questions and comments about this article to Lieven Eeckhout, ELIS-Ghent University, Sint-Pietersnieuwstraat 41, B-9000 Gent, Belgium, leeckhou@elis.ugent.be.']}}, {'name': 'S. Nussbaum', 'bio': {'p': ["Sebastien Nussbaum is a microprocessor architect at Sun Microsystems, working on the UltraSparc V processor, in Burlington, Mass. His research interests include statistical simulation of superscalar processors and multiprocessor systems. Nussbaum has a bachelor's degree in electrical and computer engineering from LEcole Superieure d'Electricite, France, and a master's degree in computer engineering from the University of Wisconsin-Madison."]}}, {'name': 'J.E. Smith', 'bio': {'p': ['James E. Smith is a professor of Electrical Computer Engineering at the University of Wisconsin-Madison, where he teaches courses in computer architecture. His research interests include performance-and power-effective processors. Smith has a PhD in computer science from the University of Illinois. He is a member of IEEE and ACM.']}}, {'name': 'K. De Bosschere', 'bio': {'p': ['Koen De Bosschere is a professor in the Faculty of Applied Sciences at Ghent University, where he teaches courses in computer architecture, operating systems, and declarative programming languages. His research interests include logic programming, system programming, parallelism, and debugging. De Bosschere has a PhD in applied sciences from Ghent University. He is a member of IEEE and ACM.']}} %*Statistical simulation: adding efficiency to the computer designer's toolbox %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1240210 %f/micro/lnghi46ctoulrxg7me8u1hayv2zdrdqf.pdf %m04ee8f9a93a97ade9b8afc5408233e9e %cmicro %@[{'name': 'N. Julien', 'affiliation': 'Univ. of South Brittany, Lorient, France', 'bio': {'p': ['Nathalie Julien is an associate professor at the University of South Brittany in Lorient, France, she also works at the Lester Laboratory in high-level design methods applied to low-power constraints for dedicated circuits, FPGAs, and DSPs. Her research interests include power estimation for complex processors and high-level synthesis that integrates power optimization and memory issues. Julien has a PhD in electronics from University of Limoges, France. She is a member of the ACM, SIGDA, and SIGARCH.']}}, {'name': 'J. Laurent', 'affiliation': 'Univ. of South Brittany, Lorient, France', 'bio': {'p': ['Johann Laurent is associate professor at the University of South Brittany and works at the Lester Laboratory. His research interests include software consumption estimation and power characterization for complex processors. Laurent has a PhD in electronic from South Brittany University.']}}, {'name': 'E. Senn', 'affiliation': 'Univ. of South Brittany, Lorient, France', 'bio': {'p': ['Eric Senn is an associate professor at the University of South Brittany and a member of the Lester Laboratory. His research interests include low-power design, architecture synthesis, and asynchronous circuits. Senn has a PhD in electronics from Paris XI University.']}}, {'name': 'E. Martin', 'affiliation': 'Univ. of South Brittany, Lorient, France', 'bio': {'p': ['Eric Martin is a full professor at the University of South Brittany in Lorient and director of the Lester Laboratory. His research interests focus on advanced electronic design automation dedicated to real-time signal processing applications, including system specification, high-level synthesis, intellectual-property reuse, low-power design, systems on a chip, and platform prototyping. Martin has a PhD in electronics from the University of Paris XI, France. He is a member of the IEEE, and the IEEE Computer Society, and the IEEE Circuits and Systems Society.']}} %*Power consumption modeling and characterization of the TI C6201 %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1240211 %f/micro/3miocshtj1w9urhknpbvduazfbj76m0c.pdf %m1d41a56fdcf287afa456fdbc5911a075 %cmicro %@[{'name': 'J. Abella', 'affiliation': "Dept. d'Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain", 'bio': {'p': ['Jaume Abella is a research assistant and a PhD candidate in the Computer Architecture Department at Universitat Politecnica de Catalunya (UPC). His research interests include power-efficient issue logic and data-cache designs. Abella has a BSc and MSc in computer science from UPC.']}}, {'name': 'R. Canal', 'affiliation': "Dept. d'Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain", 'bio': {'p': ["Ramon Canal is an assistant professor and a PhD candidate in the Computer Architecture Department at UPC. His research interests include low-power and energy-efficient micro-processors. Canal has a BSc and MSc in computer science from UPC. He is a member of the Collegi Oficial d'Enginyeria en Informatica de Catalunya."]}}, {'name': 'A. Gonzalez', 'bio': {'p': ['Antonio Gonzalez is a professor in the Computer Architecture Department at UPC. He also leads the Intel-UPC Barcelona Research Center, where research focuses on new microarchi tecture paradigms and code-generation techniques for future microprocessors. Gonzalez has a BSc, an MSc, and a PhD in computer science from UPC. He is a member of the IEEE Computer Society.']}} %*Power- and complexity-aware issue queue designs %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1240212 %f/micro/zxb6wmp3qk052ldetynhyebxrqgitfuk.pdf %m1120312c3917e82078d5ef744c29cbaa %cmicro %@[{'name': 'J.B. Fryman', 'affiliation': 'Coll. of Comput., Georgia Inst. of Technol., Atlanta, GA, USA', 'bio': {'p': ['Joshua B. Fryman is a PhD student at the College of Computing, Georgia Institute of Technology, he also has several years in industry, working in the cable and satellite TV area. His research interests include low-power architectures, embedded systems, and highperformance computing. Fryman has a B.S. in Computer Engineering from University of Florida. He is a student member of the IEEE and ACM.']}}, {'name': 'C.M. Huneycutt', 'affiliation': 'Coll. of Comput., Georgia Inst. of Technol., Atlanta, GA, USA', 'bio': {'p': ['Chad Huneycutt is a PhD student at the College of Computing, Georgia Institute of Technology. His research interests include soft computer architectures and dynamic compilation techniques. Huneycutt has a B.S. in Computer Science from Furman University. He is a student member of the IEEE, ACM, and Upsilon Pi Epsilon.']}}, {'name': ' Hsien-Hsin Lee', 'bio': {'p': ['Hsien-Hsin (Sean) Lee is an assistant professor in the School of Electrical and Computer Engineering, Georgia Institute of Technology. His research interests include microarchitecture, memory systems, information security, and autonomic systems. Lee has a BSEE from National Tsinghua University in Taiwan, and an MSE and PhD in computer science and engineering from the University of Michigan, Ann Arbor. He is a member of ACM, IEEE, Tau Beta Pi, and Sigma Xi.']}}, {'name': 'K.M. Mackenzie', 'bio': {'p': ['Kenneth M. Mackenzie is a member of the technical staff at Reservoir Labs, New York. His research interests include parallel systems, embedded computing, and compilers. Mackenzie has an SB, SM, and PhD from the Department of Electrical Engineering and Computer Science at the Massachussetts Institute of Technology. He is a member of ACM.']}}, {'name': 'D.E. Schimmel', 'bio': {'p': ['David. E. Schimmel is an associate professor in the School of Electrical and Computer Engineering, Georgia Institute of Technology. His research interests include algorithms and interconnection networks for parallel, reconfigurable, and asynchronous computer architectures, and the impact of technology on systems. Schimmel has a BSEE and PhD from Cornell University. He is a member of IEEE, Tau Beta Pi, and Eta Kappa Nu.']}} %*Energy-efficient network memory for ubiquitous devices %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1240213 %f/micro/drbvql7c5kaaey6chlsno4que390fziz.pdf %m08e93ec8c2c9e6c60c81b099c5e3e6f1 %cmicro %@[{'name': 'S. Greenstein', 'affiliation': 'Northwestern'} %*Jumping on bandwagons %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1240214 %f/micro/xt4vdlsha3galv1hedk9j6y02onuzqcm.pdf %m5a1cd3882bff2a46b773eb4385ec7554 %cmicro %@[{'name': 'C. Moore', 'affiliation': 'The University of Texas at Austin', 'bio': {'p': ["Charles Moore is a senior research fellow at The University of Texas at Austin. Previously, he was the chief engineer on the IBM's Power4 and PowerPC 601 microprocessors."]}} %*Managing the transition from complexity to elegance: Knowing when you have a problem %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1240215 %f/micro/mk7bxv2f4ult10axwnshqkdu8zmcctsi.pdf %mce891c481f5f43f20dc781100d4dee13 %cmicro %@[{'name': 'C. Moore', 'affiliation': 'The University of Texas at Austin', 'bio': {'p': ["Charles Moore is a senior research fellow at The University of Texas at Austin. His previous experience includes 18 years at IBM, where he was a Distinguished Engineer, a member of IBM's Academy of Technology, and a Master Inventor. He was the chief engineer for the Power4 chip, and the PowerPC 601 microprocessor. His current research interests include virtualization in system architecture, polymorphic computer architectures, and design verification. Moore has a BSEE from Rensselaer Polytechnic Institute and an MSEE from The University of Texas at Austin. He has 18 patents in various aspects of microprocessor and bus design. He is a senior member of the IEEE and a member of the ACM."]}}, {'name': 'K.W. Rudd', 'bio': {'p': ['Kevin W. Rudd is a senior computer architect, Enterprise Processors Division, Intel Corp. He is responsible for investigating directions for future Itanium microarchitectures and providing Itanium processor architectural support to project teams and other internal and external users. His research interests include instruction-level parallel processors, especially efficient, high-performance architectures, application of software-engineering techniques to improve hardware design, programming languages and systems, and the hardware-software interactions and tradeoffs of various compiler techniques. Rudd has a BS, MS, and PhD in electrical engineering from Stanford University. He is a member of the IEEE, the IEEE Computer Society, and the ACM.']}}, {'name': 'R.B. Lee', 'bio': {'p': ['Ruby B. Lee is the Forrest G. Hamrick Professor in Engineering and a professor of electrical engineering, with an affiliated appointment in computer science, at Princeton University. She is also the director of the Princeton Architecture Lab for Multimedia and Security, where her current research is in architecture for more pervasive cyber security, including designing security into processors and core software. Previously, she was the chief architect at Hewlett-Packard, leading interdisciplinary projects in processor architecture, multimedia architecture and security architecture, including the definition and evolution of the PA-RISC architecture and MAX (the initial general-purpose multimedia instructions for microprocessors). Lee has an AB with distinction from Cornell University, an MS in computer science and computer engineering, and a PhD in electrical engineering, both from Stanford University. She is a fellow of the IEEE, a fellow of ACM, and a member of SPIE, Phi Beta Kappa, and Alpha Lambda Delta. She holds 115 US and international patents.']}}, {'name': 'P. Bose', 'bio': {'p': ['Pradip Bose is a research staff member and manager at the IBM T.]. Watson Research Center, he is also editor in chief of IEEE Micro. His earliest work at IBM was on the Cheetah/America RISC superscalar processor, a project mentored by industry pioneer John Cocke. His current research interests include high-performance computer architectures, power- and complexity-aware design, and computer-aided design. Bose has a PhD in electrical and computer engineering from the University of Illinois, Urbana-Champaign. He is a senior member of the IEEE and the IEEE Computer Society, and a member of the ACM.', 'Direct questions and comments about this special issue to Pradip Bose, IBM T.J. Watson Research Center, PO Box 218, Yorktown Heights, NY 10598, pbose@us.ibm.com.']}} %*Micro's top picks from microarchitecture conferences %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1261381 %f/micro/fnfibvjuopaqjl9kgb7kc08t65lsigem.pdf %mfdd8719c028065a349d6ca502959af0a %cmicro %@[{'name': 'H. Akkary', 'affiliation': 'Portland State Univ., OR, USA', 'bio': {'p': ['Haitham Akkary is an assistant professor in the Electrical and Computer Engineering Department at Portland State University. His main research interest is microprocessor architecture. Akkary has a BS and MS in from Louisiana State University, and a PhD from Portland State University, all in electrical and computer engineering. He is a member of the IEEE and the ACM.']}}, {'name': 'R. Rajwar', 'bio': {'p': ['Ravi Rajwar is with the Intel Microarchitecture Research Lab. His research interests include the theoretical and practical aspects of computer architecture. Rajwar received a PhD degree in computer science from the University of Wisconsin-Madison.']}}, {'name': 'S.T. Srinivasan', 'bio': {'p': ['Srikanth T. Srinivasan is a senior researcher in the Intel Microarchitecture Research Lab. His current research focuses on scalable and efficient microarchitectures. Srinivasan received a BE in computer science from the Birla Institute of Technology and Science, Pilani, India, and a PhD in computer science from Duke University.', 'Direct questions and comments about this article to Srikanth T. Srinivasan, Microarchitecture Research Lab, Intel Corp., 2111 NE 25th Avenue, Hillsboro, OR 97124, srikanth.t.srinivasan@intel.com.', 'For further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/publications/dlib']}} %*Checkpoint processing and recovery: an efficient, scalable alternative to reorder buffers %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1261382 %f/micro/a8jg6x5ordayob0jslk3mmdncvp1buhv.pdf %md679bb0f1b446788e51773abc1f0e9b3 %cmicro %@[{'name': 'O. Mutlu', 'affiliation': 'Texas Univ., Austin, TX, USA', 'bio': {'p': ['Onur Mutlu is a doctoral student at The University of Texas at Austin. His research interests include high-performance processor microarchitecture, with a focus on multi-threading, data prefetching, and memory subsystem design. Mutlu has a BSE in computer engineering and a BS in psychology from the University of Michigan, and an MS in computer engineering from the University of Texas at Austin.']}}, {'name': 'J. Stark', 'bio': {'p': ["Jared Stark is a research scientist at Intel's Hillsboro Microarchitecture Research Lab. His research interests include branch prediction, dynamic instruction scheduling, and aggressive speculation. Stark has a BS in electrical engineering and an MS and a PhD in computer engineering, all from the University of Michigan. He is a member of the IEEE."]}}, {'name': 'C. Wilkerson', 'bio': {'p': ["Chris Wilkerson is a research scientist at Intel's Hillsboro Microarchitecture Research Lab. His research interests include low-power, high-performance, highly scalable processor designs, and high-performance processor designs that target specific application classes such as graphics, media, database, and managed runtime systems. Wilkerson has an MS in electrical and computer engineering from Carnegie Mellon University. He is a member of the AAA."]}}, {'name': 'Y.N. Patt', 'bio': {'p': ['Yale N. Patt is the Ernest Cockrell Jr. Centennial Chair in Engineering at The University of Texas at Austin, where he directs the research of 13 PhD students on problems in high-performance microarchitecture. Patt has a BS from Northeastern University, and an MS and a PhD from Stanford University, all in electrical engineering. He is the coauthor, with Sanjay Patel, of Introduction to Computer Systems: From Bits and Gates to C and Beyond, 2nd ed. (McGraw-Hill, 2004). An IEEE and an ACM Fellow, Patt is a recipient of the IEEE/ACM Eckert-Mauchly Award (1996), the IEEE Piore Medal (1995), and the ACM Karl V. Karlstrom Outstanding Educator Award (2000).']}} %*Runahead execution: An effective alternative to large instruction windows %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1261383 %f/micro/o9saemc2j6uxnfmgkyzwl31vxwdsczgb.pdf %m0be24674bc390243645cd7f2acc7390d %cmicro %@[{'name': 'M.K. Chen', 'affiliation': 'Stanford Univ., CA, USA', 'bio': {'p': ['Michael K. Chen is a PhD candidate in electrical engineering at Stanford University. His research interests include high-performance and parallel computer architectures, and optimizations for improving the performance of modern programming language features, such as garbage collection and dynamic compilation. Chen has a BS and MS in electrical engineering, and an MS in industrial engineering, all from Stanford University. He is a member of the IEEE and the ACM.']}}, {'name': 'K. Olukotun', 'affiliation': 'Stanford Univ., CA, USA', 'bio': {'p': ['Kunle Olukotun is an associate professor of electrical engineering at Stanford University, where he leads the Hydra project. His research interests include the design, analysis, and verification of computer systems using ideas from computer architecture and CAD. Olukotun has a BS in computer engineering from Calvin College and an MS and PhD in computer engineering from the University of Michigan. He is a member of the IEEE and the ACM.']}} %*The JRPM system for dynamically parallelizing sequential Java programs %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1261384 %f/micro/xbzfbulrr3ay9tc8hvktg5sfpoi1hxvm.pdf %mfa075fb1ea2f8b471006fcbd8449dfad %cmicro %@[{'name': 'C.E. Kozyrakis', 'affiliation': 'Stanford Univ., CA, USA', 'bio': {'p': ['Christoforos E. Kozyrakis is an assistant professor of electrical engineering and computer science at Stanford University. His research interests include parallel architectures and compilation techniques for systems ranging from supercomputers to deeply embedded devices. Kozyrakis has a PhD in computer science from the University of California at Berkeley, where he was the architect of the VIRAM processor. He is a member of the IEEE and the ACM.']}}, {'name': 'D.A. Patterson', 'bio': {'p': ['David A. Patterson teaches computer architecture at the University of California at Berkeley, and holds the Pardee Chair of Computer Science. His work has included the design and implementation of RISC I and the redundant arrays of inexpensive disks (RAID) project. Patterson has a PhD in computer science from the University of California at Los Angeles. He is a fellow of the IEEE Computer Society and the ACM, and a member of the National Academy of Engineering.']}} %*Scalable, vector processors for embedded systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1261385 %f/micro/etgwvzmnjrgcfubusoxhjk3dazphk5nc.pdf %mff88c1cfc840a39e43815009028e48a0 %cmicro %@[{'name': 'K. Sankaralingam', 'affiliation': 'Texas Univ., Austin, TX, USA', 'bio': {'p': ['Karthikeyan Sankaralingam is a PhD student in computer sciences at The University of Texas at Austin. His research interests include high performance computer architecture, compilers, and adaptive systems. Sankaralingam has a BTech from the Indian Institute of Technology, Madras. He is a student member of the IEEE and the ACM.']}}, {'name': 'R. Nagarajan', 'affiliation': 'Texas Univ., Austin, TX, USA', 'bio': {'p': ['Ramadass Nagarajan is a PhD student in computer sciences at UT Austin. His research interests include high performance computer architectures and compilers. Nagarajan has a BTech in computer science and engineering from the Indian Institute of Technology, Madras and a MS in computer science from UT Austin. He is a student member of the IEEE and the ACM.']}}, {'name': ' Haiming Liu', 'affiliation': 'Texas Univ., Austin, TX, USA', 'bio': {'p': ['Haiming Liu is a PhD student in computer sciences at UT Austin. His reseacrh interests include computer architecture, and parallel and distributed computing. Liu has an MS in computer science from Institute of Computing Technology, Chinese Academy of Sciences.']}}, {'name': ' Changkyu Kim', 'affiliation': 'Texas Univ., Austin, TX, USA', 'bio': {'p': ['Changkyu Kim is a PhD student in computer sciences at UT Austin. His research interests include high-performance microprocessors, memory systems, and VLSI design. Kim has an MS in computer engineering from Seoul National University. He is a student member of the IEEE amnd the ACM.']}}, {'name': ' Jaehyuk Huh', 'affiliation': 'Texas Univ., Austin, TX, USA', 'bio': {'p': ['Jaehyuk Huh is a PhD student in computer sciences at UT Austin. His research interests include multiprocessor memory systems, commercial workload characterization, and chip-multiprocessors. Huh has an MS in computer sciences from UT Austin.']}}, {'name': 'D. Burger', 'affiliation': 'Texas Univ., Austin, TX, USA', 'bio': {'p': ['Doug Burger is an assistant professor of computer science at UT Austin. His research interests include novel high-performance computer architectures, compilation, and high-performance scientific computing. Burger has a PhD in computer science from the University of Wisconsin. He is an Alfred P. Sloan Foundation fellow, a member of the ACM, and a senior member of the IEEE.']}}, {'name': 'S.W. Keckler', 'affiliation': 'Texas Univ., Austin, TX, USA', 'bio': {'p': ['Stephen W. Keckler is an assistant professor of computer science at UT Austin. His research interests include computer architecture, parallel and embedded processors, VLSI design, and adaptive computing. Keckler earned a PhD in computer science from MIT. He is an Alfred P. Sloan Foundation fellow, a member of the ACM, and a senior member of the IEEE.']}}, {'name': 'C. Moore', 'affiliation': 'Texas Univ., Austin, TX, USA', 'bio': {'p': ["Charles Moore is a senior research fellow at The University of Texas at Austin. His previous experience includes 18 years at IBM, where he was a Distinguished Engineer, a member of IBM's Academy of Technology, and a Master Inventor. He was the chief engineer for the Power4 chip, and the PowerPC 601 microprocessor. His current research interests include virtualization in system architecture, polymorphic computer architectures, and design verification. Moore has a BSEE from Rensselaer Polytechnic Institute and an MSEE from The University of Texas at Austin. He has 18 patents in various aspects of microprocessor and bus design. He is a senior member of the IEEE and a member of the ACM."]}} %*Exploiting ILP, TLP, and DLP with the polymorphous trips architecture %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1261386 %f/micro/h0dfumzim2trgjdtghnpu4sqbrkwi3oy.pdf %m4be0b239feca48f0c2c1ee6da9a614a6 %cmicro %@[{'name': 'K. Skadron', 'affiliation': 'Virginia Univ., Charlottesville, VA, USA'}, {'name': 'M.R. Stan', 'affiliation': 'Virginia Univ., Charlottesville, VA, USA'}, {'name': ' Wei Huang', 'affiliation': 'Virginia Univ., Charlottesville, VA, USA'}, {'name': 'S. Velusamy', 'affiliation': 'Virginia Univ., Charlottesville, VA, USA'}, {'name': 'K. Sankaranarayanan', 'affiliation': 'Virginia Univ., Charlottesville, VA, USA'}, {'name': 'D. Tarjan', 'affiliation': 'Virginia Univ., Charlottesville, VA, USA'} %*Temperature-aware computer systems: Opportunities and challenges %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1261387 %f/micro/sun9ihurpjftp7zwo2kweq0cx1d5y6vm.pdf %m53a6cfa490eadd14c6d1b97adb323697 %cmicro %@[{'name': 'G. Magklis', 'bio': {'p': ['Grigorios Magklis is a researcher at the Intel-UPC Barcelona Research Center. His research interests include architecture, operating systems, application analysis, and tools. Magklis is a PhD candidate and has an MSc in computer science from the University of Rochester. He is a member of the ACM and IEEE.']}}, {'name': 'G. Semeraro', 'bio': {'p': ['Greg Semeraro is an assistant professor in the Department of Computer Engineering at the Rochester Institute of Technology. His research interests include the modeling, analysis, and simulation of microarchitecture, digital and real-time systems, and nonlinear control systems. Semeraro has a PhD in electrical and computer engineering from the University of Rochester. He is a member of the IEEE Computer Society, the IEEE Education Society, and the American Society for Engineering Education.']}}, {'name': 'D.H. Albonesi', 'bio': {'p': ['David H. Albonesi is an associate professor in the Department of Electrical and Computer Engineering at the University of Rochester. His research interests include microarchitecture with an emphasis on adaptive architectures, power-aware computing, and multithreading. Albonesi has a PhD from the University of Massachusetts at Amherst. He is a senior member of the IEEE, and a member of the IEEE Computer Society and the ACM.']}}, {'name': 'S.G. Dropsho', 'bio': {'p': ['Steven G. Dropsho is a postdoctoral researcher in the Department of Computer Science at the University of Rochester. His research interests include architecture, power efficiency, and parallel and distributed systems. Dropsho has a PhD in computer science from the University of Massachusetts at Amherst. He is a member of the IEEE Computer Society and the ACM.']}}, {'name': 'S. Dwarkadas', 'bio': {'p': ['Sandhya Dwarkadas is an associate professor in the Department of Computer Science at the University of Rochester. Her research interests include parallel and distributed computing, computer architecture, and networks, and the interactions among and interfaces between the compiler, runtime system, and underlying architecture. Dwarkadas has a PhD in electrical and computer engineering from Rice University. She is a member of the IEEE, the IEEE Computer Society, and the ACM.']}}, {'name': 'M.L. Scott', 'bio': {'p': ['Michael L. Scott is a professor of computer science at the University of Rochester. His research interests include operating systems, languages, architecture, and tools, with a particular emphasis on parallel and distributed systems. He has a PhD in computer sciences from the University of Wisconsin-Madison. He is a member of the IEEE, the IEEE Computer Society, and the ACM.']}} %*Dynamic frequency and voltage scaling for a multiple-clock-domain microprocessor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1261388 %f/micro/c4mjkpoyzxvw9obh3tsnu8a2wqijvq6z.pdf %md8612591709beff1242b58bfaa4a5224 %cmicro %@[{'name': 'S.S. Mukherjee', 'bio': {'p': ["Shubhendu S. Mukherjee is a senior staff engineer at Intel's Massachusetts Microprocessor Design Center, where he leads the Fault-Aware Computing Technology (FACT) project. His research interests include processor reliability and interconnection networks. Mukherjee has a BTech in Computer Science and Engineering from the Indian Institute of Technology, Kanpur, and an MS and a PhD in Computer Science from the University of Wisconsin-Madison. He is a member of ACM and and a senior member of IEEE."]}}, {'name': 'C.T. Weaver', 'bio': {'p': ["Christopher T. Weaver is a hardware engineer in the VSSAD labs at Intel's Massachusetts Microprocessor Design Center, where he works in the Fault-Aware Computing Technology project. His research interests include reliable computing, performance modeling, semi-custom and ASIC design, and power and fault modeling. Weaver has BS degrees in electrical engineering, computer engineering, and multidisciplinary studies from North Carolina State University and an MS in computer science and engineering from the University of Michigan."]}}, {'name': 'J. Emer', 'bio': {'p': ['Joel Emer is an Intel fellow in the VSSAD group at Intel. His research interests include high-performance microarchitecture, multithreaded processors, processor pipeline organization, processor reliability, and performance-modeling frameworks. Emer has a PhD in electrical engineering from the University of Illinois. He is a Fellow of the IEEE.']}}, {'name': 'S.K. Reinhardt', 'bio': {'p': ['Steven K. Reinhardt is an associate professor of electrical engineering and computer science at the University of Michigan in Ann Arbor, and a consultant to Intel. His research interests include processor architecture, memory systems, and computer system simulation. Reinhardt has a BS from Case Western Reserve University and an MS from Stanford University, both in electrical engineering, and a PhD in computer science from the University of Wisconsin-Madison. He is a member of the IEEE Computer Society and of ACM.']}}, {'name': 'T. Austin', 'bio': {'p': ['Todd Austin is an associate professor of electrical engineering and computer science at the University of Michigan in Ann Arbor. His research interests include computer architecture, compilers, computer system verification, and performance analysis tools and techniques. Austin has a PhD in computer science from the University of Wisconsin.']}} %*Measuring architectural vulnerability factors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1261389 %f/micro/plvigakg0iqqp7k3rseuxtxa2dy6wcc8.pdf %m7d5d3733cbe38225c34547658bca92c7 %cmicro %@[{'name': 'M.A. Gomaa', 'affiliation': 'Purdue Univ., West Lafayette, IN, USA', 'bio': {'p': ['Mohamed A. Gomaa is pursuing a PhD in computer engineering at Purdue University. His research interests include fault tolerance and computer system reliability, particularly architectural methods to incorporate transient-fault detection and recovery techniques in modern processors. Gomaa has a BS and an MS, both in computer engineering, from Cairo University, Egypt. He is a student member of the IEEE and the ACM.']}}, {'name': 'C. Scarbrough', 'affiliation': 'Purdue Univ., West Lafayette, IN, USA', 'bio': {'p': ['Chad Scarbrough is a graduate student in computer engineering at Purdue University. His research interests include fault injection in a fault-tolerant SMT processor and transient-fault detection and recovery in chip multi-processors. Scarbrough has a BS in electrical and computer engineering from The Ohio State University, Columbus. He is a student member of the ACM.']}}, {'name': 'T.N. Vijaykumar', 'affiliation': 'Purdue Univ., West Lafayette, IN, USA', 'bio': {'p': ['T. N. Vijaykumar is an assistant professor in the School of Electrical and Computer Engineering, Purdue University. His research interests include computer architecture, VLSI microarchitecture, low-power microprocessors, fault-tolerant architectures, speculative multithreading, and network processors. Vijaykumar has a BE in electrical and electronics engineering and an MSc in computer science from Birla Institute of Technology and Science, Pilani, India. He also has an MS and a PhD, both in computer science, from the University of Wisconsin-Madison.']}}, {'name': 'I. Pomeranz', 'affiliation': 'Purdue Univ., West Lafayette, IN, USA', 'bio': {'p': ['Irith Pomeranz is a professor of electrical and computer engineering at Purdue University. Her research interests include VLSI circuit testing, design for testability, synthesis, and design verification. Pomeranz has a BSc in computer engineering and a DSc from the Department of Electrical Engineering at the Technion-Israel Institute of Technology.']}} %*Transient-fault recovery for chip multiprocessors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1261390 %f/micro/rnuychivwf6dbsfgr3nmmop9axvejj7s.pdf %mc7f8c77c3587a56e89a9833674f52d55 %cmicro %@[{'name': 'T. Sherwood', 'affiliation': 'California Univ., Santa Barbara, CA, USA'}, {'name': 'E. Perelman'}, {'name': 'G. Hamerly'}, {'name': 'S. Sair'}, {'name': 'B. Calder'} %*Discovering and exploiting program phases %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1261391 %f/micro/hfv73jo8p6mqxukruhyxbp1wenwltdle.pdf %m50dc2cc7180afa3d81a39962de2ad2a4 %cmicro %@[{'name': 'A.R. Alameldeen', 'affiliation': 'Wisconsin Univ., Madison, WI, USA', 'bio': {'p': ["Alaa R. Alameldeen is a PhD candidate in the computer sciences department at the University of Wisconsin-Madison. His research interests include chip multiprocessor memory system design and performance evaluation of multithreaded workloads. Alameldeen has master's degrees in computer science from Alexandria University, Egypt and from the University of Wisconsin-Madison. He is a student member of IEEE and ACM."]}}, {'name': 'D.A. Wood', 'affiliation': 'Wisconsin Univ., Madison, WI, USA', 'bio': {'p': ['David A. Wood is a professor and Romnes Fellow in the computer sciences department and the electrical and computer engineering department at the University of Wisconsin-Madison. His research interests include techniques for improving the availability, designability, programmability, and performance of commercial multiprocessor servers. Wood has a PhD in computer sciences from the University of California, Berkeley. He is a Fellow of the IEEE, and a member of the IEEE Computer Society and the ACM.']}} %*Addressing workload variability in architectural simulations %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1261392 %f/micro/sajq0hb68dlosnig4otcyutwupmia2rc.pdf %m334804f64f2fab191454c10bac35b123 %cmicro %@[{'name': 'M.M.K. Martin', 'affiliation': 'Wisconsin Univ., Madison, WI, USA', 'bio': {'p': ['Milo M.K. Martin is an assistant professor in the Department of Computer and Information Science at the University of Pennsylvania. His research interests include the memory system performance of commercial work-loads, multiprocessor cache coherence, techniques to improve multiprocessor availability, and the use of dynamic feedback to build adaptive and robust systems. Martin has a PhD in computer sciences from the University of Wisconsin-Madison. He is a member of the IEEE and the ACM.']}}, {'name': 'M.D. Hill', 'affiliation': 'Wisconsin Univ., Madison, WI, USA', 'bio': {'p': ['Mark D. Hill is a professor in both the computer sciences department and the electrical and computer engineering department at the University of Wisconsin-Madison, where he also co-leads the Wisconsin Multifacet (http://www.cs.wisc.edu/multifacet) project with David Wood. His research interests include cache design, cache simulation, translation buffers, memory consistency models, parallel simulation, and parallel-computer design. Hill has a PhD in computer science from the University of California, Berkeley. He is a Fellow of the IEEE and a member of the ACM.', 'The biography of David A. Wood appears on p. 98 of this issue.', 'Direct questions and comments about this article to Mark D. Hill, Computer Sciences Department, University of Wisconsin-Madison, 1210 West Dayton Street, Madison, WI 53706–1685, markhill@cs.wisc.edu.', 'For further information on this or any other computing topic, visit our Digital Library at http://www.computer.org/publications/dlib.', 'Our new Manuscript Central site lets you monitor your submission as it progresses through the review process. This new Web-based systems helps our editorial board and reviewers track your manuscript.']}}, {'name': 'D.A. Wood', 'affiliation': 'Wisconsin Univ., Madison, WI, USA'} %*Token coherence: a new framework for shared-memory multiprocessors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1261394 %f/micro/e1ljxr3ymdlpiuom5odagcv2sbtzzqkp.pdf %mc3e8453faac143576b9f1a831957a35d %cmicro %@[{'name': 'R. Rajwar', 'bio': {'p': ['Ravi Rajwar is with the Intel Microarchitecture Research Lab. His research interests include the theoretical and practical aspects of computer architecture. Rajwar received a PhD degree in computer science from the University of Wisconsin-Madison.']}}, {'name': 'J. Goodman', 'bio': {'p': ['James Goodman is a professor of computer science at the University of Auckland, New Zealand. He is on leave from the University of Wisconsin-Madison, where he performed the work reported in this article. His research interests include memory systems and parallel computing. Goodman has a PhD in electrical engineering and computer science from the University of California, Berkeley.']}} %*Transactional execution: toward reliable, high-performance multithreading %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1261395 %f/micro/sumykdwq4fn06qlngcp5vzbeejag2wbo.pdf %mc3cd0905f4f227da81f17ff4f51b70c1 %cmicro %@[{'name': 'J.F. Martinez', 'affiliation': 'Cornell Univ., Ithaca, NY, USA', 'bio': {'p': ["José F. Martínez is an assistant professor of electrical and computer engineering at Cornell University. His research interests are in parallel computer architecture, microarchi-tecture, and hardware-software interaction. Martínez has a PhD in computer science from the University of Illinois at Urbana-Cham-paign and is a two-time recipient of the Spanish government's national award for academic excellence. He is a member of the IEEE Computer Society and the ACM."]}}, {'name': 'J. Torrellas', 'bio': {'p': ['Josep Torrellas is a professor of computer science and Willett Faculty Scholar at the Uni-versity of Illinois at Urbana-Champaign and vice-chair of the IEEE Technical Committee on Computer Architecture (TCCA). His research interests are in computer architecture. Torrellas has a PhD in electrical engineering from Stanford University and is a recipient of an NSF Young Investigator Award. He is an IEEE Fellow and a member of the ACM.']}} %*Speculative synchronization: programmability and performance for parallel codes %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1261396 %f/micro/miwntbkoydayx2cb0qjgfu56ig1mpqhd.pdf %med02b5808485f1193b7713f477746415 %cmicro %@[{'name': 'K. Sakamura'} %*The next challenge %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=988663 %f/micro/wdw6fsx8g5vjemmcvhni7aro3ijusula.pdf %m3b94da027739b6cb965b426f3567a6e7 %cmicro %@[{'name': 'S. Greenstein'} %*The ride before the fall. An inside scoop on the high-tech stock market bust %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=988665 %f/micro/wg06vot4ch3qboaef5xsvkcytnuphjgz.pdf %mb65cde3ada48c0e89350d07534282380 %cmicro %@[{'name': 'R. Stern'} %*Is gatoring unfair or illegal? %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=988680 %f/micro/xnaghrkmgy1lyjawopmckfdjtl3enbui.pdf %m7db204114c6c64c78a0eb6dea8947c78 %cmicro %@[{'name': 'J. Lockwood', 'affiliation': 'University of Arizona', 'bio': {'p': ['John Lockwood is an assistant professor at Washington University in St. Louis. His research interests include the design of reconfigurable networking hardware systems. Lockwood has a BS, MS, and PhD in electrical engineering from the University of Illinois at Urbana/Champaign. He is a member of the IEEE, the ACM, Tau Beta Pi, and Eta Kappa Nu.']}}, {'name': 'M. Krunz', 'bio': {'p': ['Marwan M. Krunz is an associate professor in the Department of Electrical and Computer Engineering at the University of Arizona. His research interests include computer networks with a focus on performance and traffic control, wireless communications, QoS routing, and traffic analysis. Krunz has a PhD in electrical engineering from Michigan State University. He is a recipient of the National Science Foundation Career Award. He serves on the editorial board of the IEEE/ACM Transactions on Networking, the IEEE Communications Interactive Magazine, and the Computer Communications Journal. He is a member of the IEEE and the ACM.']}} %*Guest Editor's Introduction Hot Interconnects %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=988684 %f/micro/8aenyszizhqtdrpcioxb1ufekc5shau6.pdf %ma40a08036ba832c3517b9d3b0d24215b %cmicro %@[{'name': 'D. Shah', 'affiliation': 'Dept. of Comput. Sci., Stanford Univ., CA, USA', 'bio': {'p': ["Devavrat Shah is a PhD candidate in the Department of Computer Science at Stanford University. His research interests include the design, analysis, and implementation of network algorithms. Shah has a bachelor's degree in computer science and engineering from the Indian Institute of Technology, Bombay."]}}, {'name': 'P. Giaccone', 'bio': {'p': ['Paolo Giaccone is a PhD student in the Electronics Department at Politecnico di Torino, Italy. His research interests include scheduling algorithms for input-queued switches. Giaccone has a DrIng in telecommunications engineering from Politecnico di Torino. He is a student member of the IEEE.']}}, {'name': 'B. Prabhakar', 'bio': {'p': ['Balaji Prabhakar is an assistant professor of electrical engineering and computer science and a Terman Fellow at Stanford University. He is also a fellow of the Alfred P. Sloan Foundation. His research interests include network algorithms (especially for switching, routing and quality of service), wireless networks, Web caching, network pricing, information theory, and stochastic network theory. Prabhakar has a PhD from the University of California at Los Angeles. He has received a Career award from the National Science Foundation and the Erlang Prize from the Informs Applied Probability Society.']}} %*Efficient randomized algorithms for input-queued switch scheduling %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=988685 %f/micro/v2klevizjwt94enmchuai8gkfysbt56x.pdf %mc1a79223fb3ccc3510733c82030e9465 %cmicro %@[{'name': 'P. Giaccone', 'affiliation': 'Electron. Dept., Politecnico di Torino, Italy', 'bio': {'p': ['Paolo Giaccone is a PhD student in the Electronics Department at Politecnico di Torino, Italy. His research interests include scheduling algorithms for input-queued switches. Giaccone has a DrIng in telecommunications engineering from Politecnico di Torino. He is a student member of the IEEE.']}}, {'name': 'D. Shah', 'bio': {'p': ["Devavrat Shah is a PhD candidate in the Department of Computer Science at Stanford University. His research interests include the design, analysis, and implementation of network algorithms. Shah has a bachelor's degree in computer science and engineering from the Indian Institute of Technology, Bombay."]}}, {'name': 'B. Prabhakar', 'bio': {'p': ['Balaji Prabhakar is an assistant professor of electrical engineering and computer science and a Terman Fellow at Stanford University. He is also a fellow of the Alfred P. Sloan Foundation. His research interests include network algorithms (especially for switching, routing and quality of service), wireless networks, Web caching, network pricing, information theory, and stochastic network theory. Prabhakar has a PhD from the University of California at Los Angeles. He has received a Career award from the National Science Foundation and the Erlang Prize from the Informs Applied Probability Society.', 'Direct questions and comments about this article to Paolo Giaccone, Dipartimento di Elettronica, Politecnico di Torino, C.so Duca Abruzzi 24, 10129 Torino, Italy, giaccone@polito.it.']}} %*An implementable parallel scheduler for input-queued switches %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=988686 %f/micro/m3ioekrxecvku47aqurnvzyass1b0hno.pdf %m1b9766ececb8c19ec64e2595d1b92a2d %cmicro %@[{'name': 'S.S. Mukherjee', 'bio': {'p': ["Shubhendu S. Mukherjee is a senior hardware engineer in Intel's VSSAD group and partic-ipated in the Alpha 21364 development in a previous position at Compaq Computer Corp. His research interests include multiprocessor networks, fault-tolerant processors, and performance modeling. Mukherjee has a PhD in computer science and engineering from the University of Wisconsin-Madison. He is a member of the IEEE and ACM."]}}, {'name': 'P. Bannon', 'bio': {'p': ['Peter Bannon is a principal member of the technical staff in the Alpha Development Group at Compaq Computer Corp and currently coarchitect of the Alpha 21364 design. His previous experience includes the design and verification of several microprocessor chips, including the Alpha 21164 and Alpha 21164PC. Bannon has a BS in computer system design from the University of Massachusetts.']}}, {'name': 'S. Lang', 'bio': {'p': ['Steve Lang is an IC design engineer at Compaq Computer Corp. His previous experience includes work on the architecture and implementation of microprocessors, core-logic chipsets, and peripheral chips. Lang has an SB in electrical engineering and an SM in electrical engineering and computer science, both from MIT.']}}, {'name': 'A. Spink', 'bio': {'p': ['Aaron Spink is a senior hardware engineer at Intel, currently involved in the definition and design of future system interfaces for the Itanium processor family. He participated in Alpha 21364 development in a previous position at Compaq Computer Corp. His previous experience includes work on StrongARM microprocessors for Digital Equipment Corp. Spink has a BSE in electrical engineering from the University of Michigan.']}}, {'name': 'D. Webb', 'bio': {'p': ['David Webb is a senior member of the technical staff at Compaq Computer Corp. and the architecture lead for the Alpha 21364 router. His previous experience includes work on the VAX 9000 and the 21264 memory system, for which he was the lead architect. Webb has a BS in electrical engineering from the Worcester Polytechnic Institute.']}} %*The Alpha 21364 network architecture %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=988687 %f/micro/o657edlld1cwspuykqa2fmbxezwxtcyf.pdf %m599ac3df6879d0b43d416daa58ee8282 %cmicro %@[{'name': 'A. Charlesworth', 'bio': {'p': ['Alan Charlesworth is a staff engineer with the Enterprise Server Products Group of Sun Microsystems. He has worked in high-performance computing since developing software pipelining for a long-instruction-word array processor in the mid-1970s. He has helped develop several generations of large Unix servers, including the Cray Research CS6400, the Sun Enterprise 10000, and most recently the Sun Fire 15K. He attended Stanford University.']}} %*The Sun Fireplane Interconnect %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=988688 %f/micro/iaem7cnzos9gllv3r2khdtfp15jb0yu4.pdf %ma10cdcd74eaf5254cc349de89e00bb18 %cmicro %@[{'name': 'F. Petrini', 'affiliation': 'Comput. & Computational Sci. Div., Los Alamos Nat. Lab., NM, USA', 'bio': {'p': ['Fabrizio Petrini is a member of the Modeling, Algorithms, and Informatics Group (CCS-3) of the Los Alamos National Laboratory. His research interests include high-performance interconnection networks and network interfaces, job scheduling algorithms, simulation of parallel architectures, and operating systems. Petrini received a Laurea and a PhD in computer science, from the University of Pisa, Italy. He is a recipient of the European Community Marie Curie Research Fellowship. He is a member of the IEEE Computer Society.']}}, {'name': ' Wu-chun Feng', 'bio': {'p': ['Wu-chun Feng is a technical staff member and team leader of Research and Development in Advanced Network Technology (Radiant) at Los Alamos National Laboratory. His research interests include high-performance networking, network protocols and architecture, and cybersecurity. Feng has a BS in computer engineering and music and an MS in computer engineering from Penn State University and a PhD in computer science from the University of Illinois at Urbana-Champaign. He is a member of the IEEE and the ACM.']}}, {'name': 'A. Hoisie', 'bio': {'p': ['Adolfy Hoisie is a staff scientist and the Leader of the Modeling, Algorithms and Informatics Group in the Computer and Computational Sciences Division at the Los Alamos National Laboratory. His research interests include performance analysis and modeling, distributed computing, and parallel computer architectures. He is a member of the IEEE.']}}, {'name': 'S. Coll', 'bio': {'p': ['Salvador Coll is a faculty member in electronic engineering at the Technical University of Valencia, Spain. His research interests include multicomputer systems and interconnection networks, with a special interest in routing algorithms and collective communications. Coll has a BS in electronic engineering and an MS in computer science from the Technical University of Valencia. He is member of the Spanish Academy of Engineering.']}}, {'name': 'E. Frachtenberg', 'bio': {'p': ['Eitan Frachtenberg is a research assistant at Los Alamos National Laboratory and a graduate student at Hebrew University of Jerusalem, Israel. His research interests include operating systems, networks, and data compression. Frachtenberg has an MS in computer science and mathematics from the Hebrew University of Jerusalem. He is a member of the IEEE.', 'Direct questions and comments about this article to Fabrizio Petrini, Computer and Computational Sciences Division, Modeling, Algorithms, and Informatics (CCS-3), MS B256, Los Alamos National Laboratory, Los Alamos, NM 87545, fabrizio@lanl.gov. For additional information and related publications on the Quadrics network, please visit http://www.c3.lanl.gov/~fabrizio/quadrics.html.']}} %*The Quadrics network: high-performance clustering technology %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=988689 %f/micro/ij3v4em2kuyp7zon9dwvsifahurxtcgq.pdf %m5f226bc44f748218b2b0815bb695e149 %cmicro %@[{'name': ' Huan Liu', 'affiliation': 'Dept. of Electr. Eng., Stanford Univ., CA, USA', 'bio': {'p': ['Huan Liu is a PhD candidate in electrical engineering at Stanford University. His research interests include high-speed switch and network processor design. Liu received BS degrees in both physics and computer science from the Harbin Institute of Technology, China, and an MS in computer science from the University of California, Los Angeles.', 'Direct questions or comments about this article to Huan Liu, Department of Electrical Engineering, Stanford University, Stanford, CA 94305, huanliu@stanford.edu.']}} %*Routing table compaction in ternary CAM %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=988690 %f/micro/ozwb4r5dmejtcvnmui0twofa9ygfx6n1.pdf %m5cbc81627976648f7b0cf5b874d3427d %cmicro %@[{'name': 'F. Braun', 'affiliation': 'Stuttgart Univ., Germany', 'bio': {'p': ['Florian Braun is working toward the Diplom (MS) from the University of Stuttgart, Germany. His research interests include high-speed networking, reprogrammable hardware, and mobile communications. Braun has a Vordiplom (BSc) in computer engineering from the University of Stuttgart, Germany. He worked on reconfigurable networking hardware from 2000 to 2001 as an exchange student at Washington University in St. Louis.']}}, {'name': 'J. Lockwood', 'bio': {'p': ['John Lockwood is an assistant professor at Washington University in St. Louis. His research interests include the design of reconfigurable networking hardware systems. Lockwood has a BS, MS, and PhD in electrical engineering from the University of Illinois at Urbana-Champaign. He is a member of the IEEE, the ACM, Tau Beta Pi, and Eta Kappa Nu.']}}, {'name': 'M. Waldvogel', 'bio': {'p': ['Marcel Waldvogel is a research staff member at IBM Zurich Research Laboratory. His research interests include high-speed networking and data dissemination efficiency. Waldvogel has a PhD in electrical engineering and a Dipl.-Ing. in computer science from the Swiss Federal Institute of Technology (ETH), Zurich. He is a senior member of the IEEE and a member of the ACM.', 'Direct questions and comments about this article to John Lockwood, Applied Research Laboratory, Dept. of Computer Science, Washington Univ., Campus Box 1045, 1 Brookings Drive, St. Louis, MO 63130, lockwood@arl.wustl.edu.']}} %*Protocol wrappers for layered network packet processing in reconfigurable hardware %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=988691 %f/micro/lpvbjfswu5exdotvzm8iqormrbns6f92.pdf %m11bf6cec3cb90dd493394b4ba4833e41 %cmicro %@[{'name': 'D. Shah', 'affiliation': 'Dept. of Comput. Sci., Stanford Univ., CA, USA', 'bio': {'p': ["Devavrat Shah is a PhD candidate in the Department of Computer Science at Stanford University. His research interests include the design, analysis, and implementation of network algorithms. Shah has a bachelor's degree in computer science and engineering from the Indian Institute of Technology, Bombay."]}}, {'name': 'S. Iyer', 'bio': {'p': ["Sundar Iyer is a doctoral candidate in the Computer Science Department at Stanford University, where he works in the high-performance networking group. His research interests include load-balancing algorithms for network design with an emphasis on packet switching, packet buffer design, packet classification, and routing. Iyer has a BTech in computer science from the Indian Institute of Technology, Bombay and an MS in computer science from Stanford University. He received the Christofer Stephenson award for the best Master's thesis in computer science at Stanford University."]}}, {'name': 'B. Prahhakar', 'bio': {'p': ['Balaji Prabhakar is an assistant professor of electrical engineering and computer science and a Terman Fellow at Stanford University. He is also a fellow of the Alfred P. Sloan Foundation. His research interests include network algorithms (especially for switching, routing and quality of service), wireless networks, Web caching, network pricing, information theory, and stochastic network theory. Prabhakar has a PhD from the University of California at Los Angeles. He has received a Career award from the National Science Foundation and the Erlang Prize from the Informs Applied Probability Society.', 'Nick McKeown is a professor of electrical engineering and computer science at Stanford University. His research interests include the architecture, analysis, and design of high-performance switches and Internet routers, IP lookup and classification algorithms, scheduling algorithms, Internet traffic analysis, traffic modeling, and network processors. McKeown has a PhD from the University of California at Berkeley in electrical engineering and computer sciences. He is the Robert Noyce Faculty Fellow at Stanford, a Fellow of the Alfred P. Sloan Foundation, and recipient of a Career award from the National Science Foundation. He received the 2000 IEEE Rice Award for the best paper in communications theory. He is a senior member of the IEEE and serves as an editor for the IEEE Transactions on Communications and ACM/IEEE Transactions on Networking.']}}, {'name': 'N. McKeown', 'bio': {'p': ["Devavrat Shah is a PhD candidate in the Department of Computer Science at Stanford University. His research interests include the design, analysis, and implementation of network algorithms. Shah has a bachelor's degree in computer science and engineering from the Indian Institute of Technology, Bombay."]}} %*Maintaining statistics counters in router line cards %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=988692 %f/micro/jm9i4e5knx7shua8hvqwxipqms1j3gld.pdf %m1e167a7e5fc4d71c59eeda8a649852e9 %cmicro %@[{'name': 'P. Molinero-Fernandez', 'affiliation': 'Stanford Univ., CA, USA', 'bio': {'p': ['Pablo Molinero-Fernández is a PhD candidate in electrical engineering at Stanford University. His research interests include circuit and packet switching for high-speed networks, Internet traffic analysis, and reliable multicast. Molinero-Fernández has an MS in electrical engineering from Stanford University, a Telecommunications Engineer degree from the Technical University of Madrid (UPM) and the National School of Higher Education in Telecommunications in Paris (ENST-Paris), and an MS in physics from the National Distance-Learning University (UNED), Madrid.']}}, {'name': 'N. McKeown', 'bio': {'p': ['Nick McKeown is a professor of electrical engineering and computer science at Stanford University. His research interests include the architecture, analysis, and design of highperformance switches and Internet routers, IP lookup and classification algorithms, scheduling algorithms, Internet traffic analysis, traffic modeling, and network processors. McKeown has a PhD from the University of California at Berkeley in electrical engineering and computer sciences. He is the Robert Noyce Faculty Fellow at Stanford, a Fellow of the Alfred P. Sloan Foundation, and recipient of a Career award from the National Science Foundation. He received the 2000 IEEE Rice Award for the best paper in communications theory. He is a senior member of the IEEE and serves as an editor for the IEEE Transactions on Communications and ACM/IEEE Transactions on Networking.', 'For further information on this or any other computing topic, visit our Digital Library at http://computer.org/publications/dlib.']}} %*TCP switching: exposing circuits to IP %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=988693 %f/micro/tevth87zriygjhfb96ojrcimqm5eb1ak.pdf %m1ff78cf1148ab2db6dcdcfc4915f57f2 %cmicro %@[{'name': 'K. Sakamura'} %*A new definition for high-performance computing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=997872 %f/micro/qmab975t16yklamilftkhr3wc8denr4n.pdf %m63a98026b99141483ffdbac7922add3c %cmicro %@[{'name': 'S. Greenstein'} %*Competition policy for innovative industries %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=997873 %f/micro/lttodsr65cfxmgeb7cqhdpwow8kal4jv.pdf %m869378f5bc7a55b099c93aab855f3c59 %cmicro %@[{'name': 'J. Kubiatowicz', 'affiliation': 'University of California'}, {'name': 'A. Wolfe'} %*Hot Chips 13 %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=997874 %f/micro/0duy3uerjqnxcogazksoqkema7stgfpp.pdf %m733b89651f68336764fa98607efcdf25 %cmicro %@[{'name': 'D.H. Davies', 'affiliation': 'Dataplay, Boulder, CO, USA', 'bio': {'p': ['David H. Davies is chief technology officer at DataPlay, where he is responsible for the overall development of DataPlay technology and products. He has a PhD from University College, London, in physical chemistry and an MBA from the University of Pittsburgh. Davies is a senior member of the IEEE and a fellow of the Society of Photo-Optical Instrumentation Engineers.', 'Direct questions or comments about this article to David H. Davies, DataPlay, 55th St., Boulder, CO 80301, ddavies@dataplay.com']}} %*DataPlay's mobile information distribution and storage technology %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=997875 %f/micro/v0gxlv62zqj9k5p7zdsiumywltdnwa3m.pdf %mf3f336019efa52535182e051b346eb3f %cmicro %@[{'name': 'D.C. Bossen', 'affiliation': 'Server Group, IBM Corp., Austin, TX, USA', 'bio': {'p': ['Douglas C. Bossen is a distinguished engineer at the IBM Server Group, Austin, Texas. His research interests include computer hardware fault-tolerant design, RAS, and migration of cost-effective RAS techniques into the pSeries and iSeries server brands during product development. Bossen has a BS, MS, and PhD in electrical engineering from Northwestern University. He is a fellow of the IEEE and a member of Sigma Xi.']}}, {'name': 'J.M. Tendler', 'affiliation': 'Server Group, IBM Corp., Austin, TX, USA', 'bio': {'p': ['Joel M. Tendler is program director of technology assessment at the IBM Server Group, Austin, Texas. His research interests include assessing emerging technologies for applicability in future eServer, iSeries, and pSeries product offerings. He was also the lead performance analyst on the Power4 project. Tendler has a BS in engineering from the Cooper Union, and a PhD in electrical engineering from Syracuse University.']}}, {'name': 'K. Reick', 'affiliation': 'Server Group, IBM Corp., Austin, TX, USA', 'bio': {'p': ['Kevin Reick is a senior technical staff member at the IBM Server Group, Austin, Texas. His research interests include systems, storage, service processor and microprocessor architectures, architecture for RAS design, system debugging, and design for testability. Reick has a BS in electrical engineering from Rutgers University, and an MS in computer engineering from Syracuse University.', 'For further information on this or any other computing topic, visit our Digital Library at http://computer.org/publications/dlib.']}} %*Power4 system design for high reliability %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=997876 %f/micro/wur7vo8hzjxdzbi9pqhmqnyarncwgyk5.pdf %m6383b06203f3ccca203054f7baea27ae %cmicro %@[{'name': 'M.B. Taylor', 'affiliation': 'Lab. for Comput. Sci., MIT, Cambridge, MA, USA'}, {'name': 'J. Kim'}, {'name': 'J. Miller'}, {'name': 'D. Wentzlaff'}, {'name': 'F. Ghodrat'}, {'name': 'B. Greenwald'}, {'name': 'H. Hoffman'}, {'name': 'P. Johnson'}, {'name': ' Jae-Wook Lee'}, {'name': 'W. Lee'}, {'name': 'A. Ma'}, {'name': 'A. Saraf'}, {'name': 'M. Seneski'}, {'name': 'N. Shnidman'}, {'name': 'V. Strumpen'}, {'name': 'M. Frank'}, {'name': 'S. Amarasinghe'}, {'name': 'A. Agarwal'} %*The Raw microprocessor: a computational fabric for software circuits and general-purpose programs %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=997877 %f/micro/y68xwymptksdx7ngqflrnzgqfoijerte.pdf %m3e0e526919b25bde89f2d46ecdf79677 %cmicro %@[{'name': 'F. Briggs', 'affiliation': 'Intel Corp., Hillsboro, OR, USA', 'bio': {'p': ['Faye Briggs is director of chipset architecture in the Enterprise Platform Group at Intel, where he has also led architecture and engineering teams to develop the 870 chipset for the Itanium and Xeon servers. Briggs has a MSEE from Stanford and a PhD-ECE from the University of Illinois.']}}, {'name': 'M. Cekleov', 'bio': {'p': ["Michel Cekleov was architecture manager and lead architect of the 870 chipset at Intel. He now works on utility storage server architecture for 3PARdata, Inc. Cekleov has an MS from Ecole Nationale Superieure d'Ingenieurs de Marseille and a PhD from Ecole Nationale Superieure des Telecommunications."]}}, {'name': 'K. Creta', 'bio': {'p': ['Ken Creta is a staff chipset architect for server chipsets at Intel and was I/O architect for the 870 chipset. While at Intel, his research interests have focused on the i960 processor, I/O processor architecture, and I/O technologies and products implementing both industry supported I/O interfaces and proprietary, high-performance interfaces. Creta has a BSE in computer engineering from Arizona State University.']}}, {'name': 'M. Khare', 'bio': {'p': ['Manoj Khare was a principal architect at Intel and led the definition of the scalability port interconnect protocol for the 870 chipset. His research interest include the Intel backside bus and the level 3 cache subsystem on the Iranium processor. Manoj has an MSEE from the University of Rochester and a BSEE from the Indian Institute of Technology, Bombay. He holds two patents in the field of computer system architecture.']}}, {'name': 'S. Kulick', 'bio': {'p': ['Steve Kulick is a chipset architect in the Enterprise Platforms Group at Intel.']}}, {'name': 'A. Kumar', 'bio': {'p': ['Akhilesh Kumar is a senior staff engineer in the Enterprise Architecture Lab at Intel. His research interests have included the definition of system interfaces and architectures of Intel microprocessors and system components. Kumar has a BE in electronics engineering from South Gujarat University, an MTech in computer engineering from the Indian Institute of Technology and a PhD in computer science from Texas A & M University.']}}, {'name': ' Lily Pao Looi', 'bio': {'p': ['Lily Pao Looi is a senior staff architect at Intel, where she architects server chipsets. Her research interests include flash memory components and cards, supercomputer components, the 450NX chipset, the 870 chipset, coherency/bus protocols, multiprocessor architectures, and chipset programming models. Looi has an engineering degree from the University of Michigan in Ann Arbor. She holds 10 patents and was a recipient of an Intel Achievement Award.']}}, {'name': 'C. Natarajan', 'bio': {'p': ['Chitra Natarajan is an engineer in the Enterprise Platform Group at Intel, where she works on enterprise server chipsets such as the 450NX and the 870. Her research interests include computer architecture, shared memory multiprocessors, performance modeling, and analysis. Natarajan has a B.Tech in electrical engineering from the Indian Institute of Technology, Bombay, and an MS and PhD in electrical and computer engineering from the University of Illinois, Urbana-Champaign. She was the recipient of the Institute Silver Medal from the Indian Institute of Technology and is a member of the IEEE Computer Society and the IEEE.']}}, {'name': 'S. Radhakrishnan', 'bio': {'p': ['Sivakumar Radhakrishnan is a senior performance architect with the Advanced Computing Division in the Enterprise Products Group at Intel. His research interests include I/O bus and networking protocols, chipset performance analysis and design, distributed computing, and register-transfer-level validation. Radhakrishnan has a B.Eng in computer science engineering from the University of Madras, India, and an M.A.Sc and PhD in electrical engineering from the University of Victoria, B.C., Canada.']}}, {'name': 'L. Rankin', 'bio': {'p': ['Linda Rankin is senior staff engineer at Intel, where she has worked on the iWarp multi-processor, interconnect architecture for high-end systems (teraflops machine), the IA32 processor, and 870 chipset. She is currently a BIOS/firmware architect. Rankin has an MS in computer science and engineering. She holds four patents, and has 19 patents pending.', 'Direct questions and comments about this article to Lily Pao Looi, Intel Corporation, JF5–256, 2111 N.E. 25th, Hillsboro, OR 97124–5961, lily.p.looi@intel.com.']}} %*Intel 870: a building block for cost-effective, scalable servers %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=997878 %f/micro/avdyh9gopsotwi34fuzrrlhiafn25dkq.pdf %ma5110c667f8209ec19f4eece0b9d696d %cmicro %@[{'name': 'C.R. Eddington', 'affiliation': 'Mellanox Technol., Santa Clara, CA, USA', 'bio': {'p': ['Chris Eddington is director of technical marketing at Mellanox Technologies. His research interests include high-performance computing, embedded system design, and signal and image processing. Eddington has a MS in electrical engineering from the University of Southern California. He is a member of IEEE Communications Society.']}} %*InfiniBridge: an InfiniBand channel adapter with integrated switch %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=997879 %f/micro/jrvgdbleay5k8zwrdss1ni7j64txh90u.pdf %me06c7f3b274cf9c595d12486aaf86e3e %cmicro %@[{'name': 'S. Greenstein'} %*Markets for technology %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1013297 %f/micro/hkrdeqqzubmg84eoaupb9jtyvsvfjlkx.pdf %mfeeeed8b521d5eb686ddf06bc21500fe %cmicro %@[{'name': 'R.H. Stern'} %*Challenging search engines under copyright law: Part 1 %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1013298 %f/micro/jhbgifnmhwuzac0ba1z2reswl8nmxxyd.pdf %m997c2eed6c57261b1d2c7cb9b5bc208a %cmicro %@[{'name': 'K.E. Grosspietsch', 'affiliation': 'Fraunhofer Institute of Autonomous Intelligent Systems', 'bio': {'p': ["Karl E. Grosspietsch's biography appears on page 70 of this issue.", 'Direct questions or comments about this special issue to Karl E. Grosspietsch, German National Research Center for Information Technology, Fraunhofer Institute of Autonomous Intelligent Systems, Schloss Birling-hoven, D-53754 St. Augustin, Germany, grosspietsch@gmd.de.']}} %*Unorthodox computer architectures %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1013299 %f/micro/0h3wklem7uhpqor6zmsqbibi2scnozdc.pdf %mf8870db9af6221b16a4f5fe0b25b76e5 %cmicro %@[{'name': 'U. Ruckert', 'affiliation': 'Paderborn Univ., Germany'} %*ULSI architectures for artificial neural networks %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1013300 %f/micro/nqpy0af3vjg1lskitrlm9yzusihc5gc7.pdf %ma62cabc2900d11255dd3ebb03d2ea308 %cmicro %@[{'name': 'G. Danese', 'affiliation': 'Pavia Univ., Italy', 'bio': {'p': ['Giovanni Danese is full professor of computer science at the University of Pavia, where he heads the Microcomputer Laboratory. His research interests include computer architecture, computerized instrumentation, micro-processors, and parallel computing. Danese has a Laurea degree and a PhD in electronic engineering from the University of Pavia. He is a member of the IEEE Computer Society.']}}, {'name': 'F. Leporati', 'affiliation': 'Pavia Univ., Italy', 'bio': {'p': ['Francesco Leporati is an assistant professor of computer science at the University of Pavia. His research interests include microprocessors, systems on chips, computational physics, and ANNs. Leporati has a Laurea degree and a PhD in electronic engineering from the University of Pavia. He also had, in collaboration with INFM (the Italian Institute for the Physics of Matter), a postdoctoral fellowship for the design and analysis of parallel architectures dedicated to interacting particle systems. He is a member of the IEEE Computer Society.']}}, {'name': 'S. Ramat', 'affiliation': 'Pavia Univ., Italy', 'bio': {'p': ['Stefano Ramat is a contract professor of biomedical engineering at the University of Pavia. His research interests include motor control, mathematical modeling, neural networks, and signal processing. Ramat has a university degree in computer science engineering from the University of Pavia, a PhD in biomedical engineering from the Polytechnic of Milan, and a postdoctoral fellowship with the Ocular Motility Laboratory at Johns Hopkins University.', 'Direct questions and comments about this article to Francesco Leporati, Lab. Microcalcolatori, Dip. Informatica e Sistemistica, Univ. of Pavia, via Ferrata 1, 27100 Pavia, Italy, francesco.leporati@unipv.it.']}} %*A parallel neural processor for real-time applications %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1013301 %f/micro/mxjrl5lzdhbypy0gtvevkucwztw2rpka.pdf %m74aab3129ef01ec694cf26b3325e3202 %cmicro %@[{'name': 'J. Buddefeld', 'bio': {'p': ['Jürgen Büddefeld is a professor for microelectronics and microsystems at the Hochschule Niederrhein, University of Applied Sciences, in Krefeld, Germany. His research interests include CAD tools for VLSI design, analog circuit design, microelectronics, and microsystems. Büddefeld has a diploma in communication engineering from the University of Dortmund, Germany, and a PhD in electrical engineering from the Gerhard-Mercator University of Duisburg, Germany. He is a member of the VDE/GMM task force for analog circuit design.']}}, {'name': 'K.E. Grosspietsch', 'bio': {'p': ['Karl E. Grosspietsch is a senior scientist at the Fraunhofer Institute of Autonomous Intelligent Systems in Sankt Augustin, Germany. His research interests include computer architecture, dependable computing, and autonomous systems. Grosspietsch has a diploma in computer science from the University of Hamburg and a PhD in computer science from the University of Bonn. He is a member of the IEEE, Euromicro, and the German Computing Society (Gesellschaft für Informatik).', 'Direct questions and comments about this article to Jürgen Büddefeld, Hochschule Niederrhein, Univ. of Applied Sciences, Dept. of Electrical Engineering, PO Box 2850, D-47728 Krefeld, Germany, juergen.bueddefeld@hs-niederrhein.de.']}} %*Intelligent-memory architecture for artificial neural networks %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1013302 %f/micro/nz45nlevrlgychaj708wd2r96gdfmsmf.pdf %m37fb19449a08ab938af68d9ac13e2f03 %cmicro %@[{'name': 'M. Perkowski', 'affiliation': 'Portland State Univ., OR, USA'}, {'name': 'D. Foote', 'affiliation': 'Portland State Univ., OR, USA'}, {'name': ' Qihong Chen', 'affiliation': 'Portland State Univ., OR, USA'}, {'name': 'A. Al-Rabadi', 'affiliation': 'Portland State Univ., OR, USA'}, {'name': 'L. Jozwiak'} %*Learning hardware using multiple-valued logic - Part 1: introduction and approach %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1013303 %f/micro/isvksoebann6tcr0wz8ghdw5jy9fr3px.pdf %m15defd4ea8bf965342bbd427ba06ab1f %cmicro %@[{'name': 'M. Perkowski', 'affiliation': 'Portland State Univ., OR, USA', 'bio': {'p': ['Marek Perkowski is a professor of Electrical and Computer Engineering in the ECE Department at Portland State University, Oregon. His research interests include multiple-valued logic, logic synthesis, testing and verification, reversible and quantum computing, intelligent robotics, walking robots, robot soccer, machine vision, and VLSI design. Perkowski received a PhD in automatic control from the Warsaw University of Technology, Poland. He is a member of the IEEE Computer Society and vice-chair of technical activities of its Technical Committee on Multi-Valued Logic. He is an editorial board member of the Soft Computing Journal and an academic advisor of the PSU student chapter of the IEEE Robotics and Automation Society.']}}, {'name': 'D. Foote', 'affiliation': 'Portland State Univ., OR, USA', 'bio': {'p': ['David Foote works at Intel. His research interests include computer hardware and system design and networking. Foote received a BS in physics from Linfield College in McMinville, Oregon, and an MS in electrical and computer engineering from Portland State University, Oregon.']}}, {'name': ' Qihong Chen', 'affiliation': 'Portland State Univ., OR, USA', 'bio': {'p': ['Qihong Chen is a senior software engineer at the Portland Development Center of Oracle Corporation. His research interests include database systems, software engineering, software-hardware integration, and FPGA design. Chen received a BS in electronics and information technology from the Ocean University of Qingdao, China, and an MS in electrical and computer engineering from Portland State University, Oregon.']}}, {'name': 'A. Al-Rabadi', 'affiliation': 'Portland State Univ., OR, USA', 'bio': {'p': ['Anas Al-Rabadi is a PhD candidate at Portland State University. His research interests include logic synthesis, signal processing, image processing, regular structures, intelligent robotics, machine learning, system architectures, logic decomposition, reconstructability analysis, logic factorization, spectral methods, XOR logic, reversible logic, quantum logic, and logic testing. He is a member of the IEEE, the ACM, Eta Kappa Nu, Tau Beta Pi, Sigma Xi, and the Robotics and Automation Society of the IEEE.']}}, {'name': 'L. Jozwiak', 'bio': {'p': ['Lech Jozwiak is an associate professor at the Faculty of Electrical Engineering of the Eindhoven University of Technology, Netherlands. His research interests include system and circuit theory and technology, design technology including EDA tools, artificial intelligence, multiple-valued logic, VLSI circuit and system synthesis, application-specific processors, embedded systems, programmable hardware, and reconfigurable computing. Jozwiak received a PhD in technological sciences (in the field of automatic control and computer engineering) from the Faculty of Electronics, Warsaw University of Technology, Poland. He is a member of the IEEE, the EDAA, and the Euromicro board of directors. He is cofounder and steering committee chairman of the Euromicro Symposium on Digital System Design, and an editor of the Journal of Systems Architecture and the Journal of Computer Research.', 'Direct questions and comments about this article to Marek Perkowski, Portland State Univ., Dept. of Electrical and Computer Engineering, Portland, OR 97207, mperkows@ece.pdx.edu.']}} %*Learning hardware using multiple-valued logic - Part 2: Cube calculus and architecture %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1013304 %f/micro/tpnphdisoombaueqkux5f0kzhvjzlryj.pdf %me6b691a7d69970f8ea48f82839de2c40 %cmicro %@[{'name': 'F. Eschmann', 'affiliation': 'Johann Wolfgang Goethe Univ., Frankfurt, Germany', 'bio': {'p': ['Frank Eschmann is a research assistant in the Technical Computer Sciences Department at J.W Goethe University in Frankfurt, Germany. His research interests include parallel computer architectures and automatic parallelization methods. Eschmann has an MSc in computer science from J.W Goethe University.']}}, {'name': 'B. Klauer', 'affiliation': 'Johann Wolfgang Goethe Univ., Frankfurt, Germany', 'bio': {'p': ['Bernd Klauer holds a postdoctoral position in the Technical Computer Sciences Department at J.W Goethe University. His research interests include parallel computer architectures and automatic parallelization methods. Klauer has an MSc and a PhD in computer science from J.W Goethe University. He is a member of the German National Association for Computer Sciences and the German Electrical Engineering Council.']}}, {'name': 'R. Moore', 'affiliation': 'Johann Wolfgang Goethe Univ., Frankfurt, Germany', 'bio': {'p': ['Ronald Moore is an assistant to the CEO/CTO at IS Innovative Software. His research interests include parallel computing and complex adaptive systems. Moore has a BSc from Michigan State University and an MSc and a PhD in computer science from J.W Goethe University.']}}, {'name': 'K. Waldschmidt', 'affiliation': 'Johann Wolfgang Goethe Univ., Frankfurt, Germany', 'bio': {'p': ['Klaus Waldschmidt heads the Technical Computer Sciences Department at J.W Goethe University. His research interests include parallel computer architectures and CAD for mixed analog and digital circuits. Waldschmidt has a Dipl.-Ing. and a Dr.-Ing. in electrical engineering from the Technical University of Berlin. He is a member of the Society for Information Technologies, the German National Association for Computer Sciences, and Euromicro.']}} %*SDAARC: an extended cache-only memory architecture %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1013305 %f/micro/ml0avokkyxmrt1hjygubrhg937nbuswe.pdf %mb6fe95708c4338a8bb3fee2d92d17bf0 %cmicro %@[{'name': 'R. Mateosian', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/21821/1013306/1013306-photo-1-small.gif', 'p': ['RICHARDMATEOSIAN xrm@pacbell.net']}} %*Enterprise computing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1013306 %f/micro/bz9xhsgfdnttlyiemqn6prqbwwoigouj.pdf %m9450fa8e393aed5939591ddda503d545 %cmicro %@[{'name': 'W. Stern'} %*FTC piles onto standardization Rambus' skullduggery %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1028465 %f/micro/qlkt3ntgywaksxb9upumvp7gdio6jfbr.pdf %mbbadbb20361f2f8975d0894266f637c3 %cmicro %@[{'name': 'S. Greenstein'} %*The crash in competitive telephony %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1028466 %f/micro/ggcsdts5vn3imwomqdqpapufozalcxlf.pdf %m4520113f2df7e9351c816fae9d035f5e %cmicro %@[{'name': 'R. Mateosian'} %*Effective Java: Programming Language Guide [Book Review] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1028468 %f/micro/xxlmt6pz3tgur8ifkofyavhm4cdsle02.pdf %mf7d43052fae7e0bb7884a8c078f20c01 %cmicro %@[{'name': 'P. Koopman', 'affiliation': 'Carnegie Mellon University', 'bio': {'p': ['Philip Koopman is an associate professor in the Department of Electrical and Computer Engineering at Carnegie Mellon University. His research interests include methodologies and architectures to create gracefully degrading distributed embedded systems. Koopman received both a BS and an M.Eng. in computer and systems engineering from Rensselaer Polytechnic Institute, New York, and a PhD in computer engineering from CMU. He is a senior member of the IEEE and the IEEE Computer Society. Additionally, he is affiliated with the Institute for Complex Engineered Systems (as lab director of the Embedded and Reliable Information Systems Laboratory), the Institute for Software Research, International, and the General Motors satellite research laboratory at CMU (as the dependable embeddable systems thrust leader).']}} %*Critical embedded automotive networks %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1028471 %f/micro/macuyhe0wihvrq6okfzpz4ixtp981xqj.pdf %m8f88fc681cb800dafed1af0f4dc7ea16 %cmicro %@[{'name': 'M. Ellims', 'affiliation': 'Pi Technol., Cambridge, UK', 'bio': {'p': ['Michael Ellims is a chief engineer at Pi Technology, Cambridge, England. His technical interests include embedded electronic control system and software testing. Ellims has an MSc in computer science from the University of Canterbury, New Zealand. He is a member of the IEEE Computer Society and the ACM.']}}, {'name': 'S. Parker', 'bio': {'p': ['Stephen Parker is a senior engineer at Pi Technology. His technical interests include embedded systems and in-vehicle networks. Parker has a BSc in theoretical physics from the University of York, UK.']}}, {'name': 'J. Zurlo', 'bio': {'p': ['James Zurlo is a staff engineer with Waukesha Engine. His technical interests include engine controls and engine modeling. Zurlo has a PhD in mechanical engineering from Carnegie Mellon University. He is a member of the Society of Automotive Engineers and the American Society of Mechanical Engineers.', 'For further information on this or any other computing topic, visit our Digital Library at http://computer.org/publications/dlib.']}} %*Design and analysis of a robust real-time engine control network %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1028472 %f/micro/hnlfwn5surpjpg82d9jvcl7ka0rtbgya.pdf %ma859d037680688755c62a934b8638fcb %cmicro %@[{'name': 'L.-B. Fredriksson', 'affiliation': 'Kvaser AB, Kinnahult, Sweden', 'bio': {'p': ['Lars-Berno Fredriksson is president and cofounder of Kvaser. His research interests include distributed embedded control systems and advanced real-time systems, especially architectures. Fredriksson has an MSc in mechanics from the Chalmers University of Technology in Gothenburg, Sweden. He holds the appointed position of the Swedish expert for TTCAN in ISO/TC22/SC3.']}} %*CAN for critical embedded automotive networks %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1028473 %f/micro/r9nbrkwlnawgdfhzi1pvgbodej47s8qv.pdf %mc9727487e38ef41bf8009923082765a4 %cmicro %@[{'name': 'R. Maier', 'affiliation': 'TTTech Computertechnik, Vienna, Austria', 'bio': {'p': ['Reinhard Maier is a protocol expert for realtime systems at TTTech Computertechnik, Vienna. His research interests include realtime buses and fault-tolerant real-time systems. Maier has an MSc in computer science from the Vienna University of Technology and an MBA from Vienna University.']}}, {'name': 'G. Bauer', 'bio': {'p': ["Günther Bauer is a technical coordinator for the IST research project in the Real-Time Systems Group at the Vienna University of Technology. His research interests include the design and implementation of a central guardian for TTA. Bauer has a diploma in electrical engineering and a PhD in computer science from the Vienna University of Technology. Georg Stöger is director of training and sup-port at TTTech Computertechnik. His research interests include training and support for projects in the area of time-triggered architectures, especially by-wire architectures. Stöger has a diplomingenieur (master's) of computer science certificate from the Vienna University of Technology."]}}, {'name': 'G. Stoger'}, {'name': 'S. Poledna', 'bio': {'p': ['Stefan Poledna is cofounder and chief executive officer of TTTech Computertechnik, and he lectures on fault-tolerant computer systems at the Vienna University of Technology. His research interests are in the area of automotive electronics and fault-tolerant systems. Poledna has an MSc in computer science and a PhD in computer science from the Vienna University of Technology.']}} %*Time-triggered architecture: a consistent computing platform %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1028474 %f/micro/7zctguiu3diep9k8psghbk0d2yoaxb5q.pdf %m5904692c97045c297f15d7df2ed17173 %cmicro %@[{'name': 'J. Ferreira', 'affiliation': 'Aveiro Univ., Portugal', 'bio': {'p': ['Joaquim Ferreira is currently a PhD student at the Universidade de Aveiro, Portugal. He is also professor adjunto at the Instituto Politecnico de Castelo Branco, Portugal. His research interests include real-time communication systems, fieldbuses, fault tolerance, and digital design. He has a licenciatura degree in electronics and telecommunications engineering and an MSc in electrical engineering from the Universidade de Aveiro, Portugal.']}}, {'name': 'P. Pedreiras', 'bio': {'p': ['Paulo Pedreiras is a PhD student at the Universidade de Aveiro, Portugal. His research interests include real-time communication systems, scheduling, fieldbuses, and real-time operating systems. He has a licenciatura degree in electronics and telecommunications engineering from the Universidade de Aveiro, Portugal.']}}, {'name': 'L. Almeida', 'bio': {'p': ['Luis Almeida is assistant professor in the Department of Electronics and Telecommunications at the Universidade de Aveiro, Portugal. His research interests include real-time networks for distributed industrial/ embedded systems and navigation control for mobile robots. He has a licenciatura degree in electronics and telecommunications engineering and a PhD in electrical engineering from the Universidade de Aveiro, Portugal. He is an IEEE Computer Society member.']}}, {'name': 'J.A. Fonseca', 'bio': {'p': ['Jose Alberto Fonseca is an associate professor in the Department of Electronics and Telecommunications at the University of Aveiro, Portugal. His research interests include embedded systems, distributed systems, and industrial communications. He has a licenciatura degree in electronics and telecommunications engineering and a PhD in electrical engineering from the University of Aveiro, Portugal. He is a member of the IEEE Industrial Electronics Society.']}} %*The FTT-CAN protocol for flexibility in safety-critical systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1028475 %f/micro/zarsyzeogc9fwytewur6dljkukvhba0p.pdf %mba2e03a4225a3f07a8e72b636108c5c7 %cmicro %@[{'name': 'R. Nossal', 'bio': {'p': ['Roman Nossal is a team manager at DECOMSYS. His research interests include time-driven systems, scheduling, and the development process. Nossal has a PhD in computer science from the Vienna University of Technology. He is a member of the IEEE.']}}, {'name': 'R. Lang', 'bio': {'p': ['Roland Lang is a team manager at DECOMSYS. His research interests include the simulation of embedded systems and real-time communication. Lang has an MSc in computer science from the Vienna University of Technology.']}} %*Model-based system development %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1028476 %f/micro/irdn86sfasckgvhpo3relglu4jp9hyxm.pdf %m55a1de8f04e0c3f6b7b516d6c957c0ca %cmicro %@[{'name': 'B. Sprunt', 'affiliation': 'Bucknell Univ., Lewisburg, PA, USA', 'bio': {'p': ['Brinkley Sprunt is an assistant professor of electrical engineering at Bucknell University. His research interests include computer performance modeling, measurement, and optimization. Sprunt has a PhD in electrical and computer engineering from Carnegie Mellon University. He previously worked at Intel where he was a member of the architecture teams for the 80960, Pentium Pro, and Pentium 4 projects. He is a member of the IEEE and ACM.', 'Direct questions and comments about this article to Brinkley Sprunt, Bucknell Univ., Electrical Engineering Dept., Moore Ave., Lewisburg, PA 17837, bsprunt@bucknell.edu.']}} %*The basics of performance-monitoring hardware %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1028477 %f/micro/m359hulugkj4awniy8btzfhe1or7nxdz.pdf %m033757d8ecccabbab0bb0ceb1db0b128 %cmicro %@[{'name': 'B. Sprunt', 'affiliation': 'Bucknell Univ., Lewisburg, PA, USA', 'bio': {'p': ['Brinkley Sprunt is an assistant professor of electrical engineering at Bucknell University. His research interests include computer performance modeling, measurement, and optimization. Sprunt has a PhD in electrical and computer engineering from Carnegie Mellon University. He previously worked at Intel where he was a member of the architecture teams for the 80960, Pentium Pro, and Pentium 4 projects. He is a member of the IEEE and ACM.']}} %*Pentium 4 performance-monitoring features %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1028478 %f/micro/n3cihu5k4zplwehsvgjjt8im176aaru0.pdf %m469460f61a1eabdad3300aa8a170e549 %cmicro %@[{'name': 'S. Greenstein', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/22379/1044294/1044294-photo-1-small.gif', 'p': []}} %*Micro economics - The price is not right %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1044294 %f/micro/7ehvaxuo9wevk4mg3wtcfti1osybz5q0.pdf %me95d1de34e177be31de1a64adff41060 %cmicro %@[{'name': 'L. Lavagno', 'affiliation': 'Politecnico di Torino', 'bio': {'p': ['Luciano Lavagno is an associate professor with Politecnico di Torino, Italy, and a research scientist with Cadence Berkeley Laboratories. His research interests include the synthesis of asynchronous and low-power circuits, the concurrent design of mixed hardware and software embedded systems, and the formal verification of digital systems. Lavagno has a PhD in electrical engineering and computer science from the University of California at Berkeley. He is a coauthor of two books on asynchronous circuit design and of a book on hardware/software codesign of embedded systems. He was the architect of the POLIS project, a cooperation between UC Berkeley, Cadence Design Systems, Magneti Marelli, and Politecnico di Torino, which developed a complete hard-ware/software codesign environment for control-dominated embedded systems.', 'Please direct comments and questions about this special issue to Luciano Lavagno, Politecnico di Torino, Dipartimento di Elettronica, Corso Duca degli Abruzzi 24, 10129 Torino, Italy, lavagno@polito.it.']}} %*Guest editor's introduction - systems on a chip: the next electronic design frontier %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1044295 %f/micro/39oga1dbtnfxclvxjg7vlip85sqmyqy6.pdf %mb318a25c42ebfc0191b244c66cd8f309 %cmicro %@[{'name': 'J. Bainbridge', 'affiliation': 'Dept. of Comput. Sci., Manchester Univ., UK', 'bio': {'p': ['John Bainbridge is a research associate in the Department of Computer Science at the University of Manchester, England. His interests include asynchronous logic and SOC design. Bainbridge has an M. Eng in electronic systems engineering and a PhD in computer science from the University of Manchester. His doctoral thesis was the winner of the 2001 Distinguished Dissertation Competition awarded jointly by the British Computer Society and the Conference of Professors and Heads of Computing. He is a member of the IEEE and the IEE.']}}, {'name': 'S. Furber', 'affiliation': 'Dept. of Comput. Sci., Manchester Univ., UK', 'bio': {'p': ['Steve Furber is the ICL Professor of Computer Engineering in the Department of Computer Science at the University of Manchester. His research interests include asynchronous logic design and power-efficient computing. Furber has a BA in mathematics and a PhD in aerodynamics, both from the University of Cambridge, England. He is a fellow of the Royal Society, the Royal Academy of Engineering, and the British Computer Society, a chartered engineer, and a senior member of the IEEE.', 'Direct questions and comments about this article to John Bainbridge, Univ. of Manchester, Oxford Rd., Manchester, M13 9PL, UK, jbainbridge@cs.man.ac.uk.']}} %*Chain: a delay-insensitive chip area interconnect %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1044296 %f/micro/fvutknrhyoufqoc1mtys5bejzgkawh9q.pdf %mabb9f4303c3ca4565f13a4ac656fbad0 %cmicro %@[{'name': 'L.P. Carloni', 'affiliation': 'California Univ., Berkeley, CA, USA', 'bio': {'p': ['Luca P. Carloni is a PhD candidate in the Electrical Engineering and Computer Science Department of the University of California, Berkeley. His research interests include computer-aided design and design methodologies for electronic systems, embedded system design, logic synthesis, and combinatorial optimization. He has a Laurea in electrical engineering from the University of Bologna, Italy, and an MS in electrical engineering and computer science from the University of California, Berkeley.']}}, {'name': 'A.L. Sangiovanni-Vincentelli', 'affiliation': 'California Univ., Berkeley, CA, USA', 'bio': {'p': ['Alberto L. Sangiovanni-Vincentelli holds the Buttner Chair in electrical engineering and computer science at the University of California, Berkeley. His research interests include all aspects of computer-aided design of electronic systems, hybrid systems and control, and embedded system design. He cofounded Cadence and Synopsys and received the Kaufman Award from the Electronic Design Automation Consortium for pioneering contributions to EDA. He is a fellow of the IEEE and a member of the National Academy of Engineering.', 'For further information on this or any other computing topic, visit our Digital Library at http://computer.org/publications/dlib.']}} %*Coping with latency in SOC design %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1044297 %f/micro/ql7rexu5awdmzfnjyibwdq8ihvrmuck9.pdf %m19f12576e6010c19cfac80117f31f829 %cmicro %@[{'name': 'F. Karim', 'bio': {'p': ["Faraydon Karim is an ST Fellow at STMicro-electronics' Advanced System Technology, Advanced Computing Lab in La Jolla, California. His research interests include computer and embedded system architecture. Karim has a PhD in computer engineering from La Salle University. He is a member of the IEEE."]}}, {'name': 'A. Nguyen', 'bio': {'p': ['Anh Nguyen is a research engineer at the STMicroelectronics Advanced Systems Technology, Advanced Computing Lab in La Jolla, California. His research interests include performance analysis, resource allocation, and algorithm development. Nguyen has a PhD in electrical engineering from the University of California, Los Angeles. He is a member of the IEEE.']}}, {'name': 'S. Dey', 'bio': {'p': ['Sujit Dey is a professor in the Electrical and Computer Engineering Department at the University of California, San Diego. His research interests include configurable platforms consisting of adaptive wireless protocols and algorithms, and deep-submicron adaptive SOCs for next-generation wireless appliances and network infrastructure devices. Dey has a PhD in computer science from Duke University. He is a member of the IEEE.']}} %*An interconnect architecture for networking systems on chips %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1044298 %f/micro/weyjmxnncbryavs2vsu0fopldce6ipkj.pdf %mb9a5d18bd47dbe90e02bb686f0b5b2b3 %cmicro %@[{'name': 'M. Forsell', 'bio': {'p': ['Martti Forsell is a senior research scientist at VTT Electronics, Oulu, Finland. His research interests include processor and computer architectures, parallel computing, performance analysis, and compiler technology. Forsell has a PhD in computer science from the University of Joensuu, Finland.']}} %*A scalable high-performance computing solution for networks on chips %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1044299 %f/micro/mhvj0xwzckgnbrxoa87etsr6do3liepw.pdf %m47aa1a109b2a5187a411102749f488d1 %cmicro %@[{'name': 'C. Wolinski', 'affiliation': 'Rennes I Univ., France', 'bio': {'p': ['Christophe Wolinski is an associate professor at the University of Rennes, France. At present, he is a visiting staff member at Los Alamos National Laboratory. His research interests include real-time systems, embedded systems, digital signal processing architectures, high-level synthesis, and reconfigurable computing systems. Wolinski has an MS and PhD from the Polytechnic University of Warsaw, Poland, and a D. Sc from the University of Rennes 1, France.']}}, {'name': 'M. Gokhale', 'bio': {'p': ['Maya Gokhale is project leader of the Deployable Adaptive Processing Systems Project and deputy group leader (acting) of the Space Data Systems Group at Los Alamos National Laboratory. Her research interests include highperformance embeddable processors and programming models and compilers for hybrid hardware and software processing. Gokhale has a PhD from the University of Pennsylvania, Philadelphia, and is a member of the IEEE and IEEE Computer Society.']}}, {'name': 'K. McCave', 'bio': {'p': ['Kevin McCabe works in the space engineering group at Los Alamos National Laboratory. His research interests include space applications of FPGAs. McCabe has an MSEE from Southern Methodist University, Dallas.', 'For further information on this or any other computing topic, visit our Digital Library at http://computer.org/publications/dlib.']}} %*A polymorphous computing fabric %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1044300 %f/micro/6rl51d9yfsxwlrikofbuqmjwmjeiet04.pdf %me3caa25a6d761e340e8cf9c99bf1ad0a %cmicro %@[{'name': ' Jin-Fu Li', 'affiliation': 'Nat. Central Univ., Chung-li, Taiwan', 'bio': {'p': ['Jin-Fu Li is an assistant professor at National Central University, Chung-Li, Taiwan. His research interests include advanced VLSI design and testing, SOC testing, and memory testing, diagnosis, and repair. Li has a BSEE from National Taiwan University of Science Technology, Taipei, Taiwan, and an MSEE and PhD from National Tsing Hua University.']}}, {'name': ' Hsin-Jung Huang', 'bio': {'p': ['Hsin-Jung Huang is an associate researcher at the Chip Implement Center, National Science Council of Taiwan. His research interests include design for testability and SOC testing. Huang has a BSEE degree from National Cheng Kung University, Tainan, Taiwan, and an MSEE degree from National Tsing Hua University.']}}, {'name': ' Jeng-Bin Chen', 'bio': {'p': ['Jeng-Bin Chen is an associate researcher at the Chip Implement Center. His research interests include design for testability and SOC testing. Chen has a BS in electronic engineering from Chung Yuan Christian University, Chungli, Taiwan, and an MSEE from National Tsing Hua University.']}}, {'name': ' Chih-Pin Su', 'bio': {'p': ['Chih-Pin Su is a PhD student at National Tsing Hua University. His research interests include design and test of high-performance VLSI circuits and SOCs. Su has a BSEE and an MSEE from National Tsing Hua University. He received the Best Paper Award from the 2002 IEEE International Workshop on Design and Diagnostics of Electronic Circuits and Systems.']}}, {'name': ' Cheng-Wen Wu', 'bio': {'p': ['Cheng-Wen Wu is a professor and the chair of the Department of Electrical Engineering, National Tsing Hua University. His research interests include design and testing of highperformance VLSI circuits and systems. Wu has an MS and PhD in electrical and computer engineering from the University of California, Santa Barbara. He received the 2001 Distinguished Research Award from the National Science Council, the 2001 Industrial Collaboration Award from the Ministry of Education in Taiwan, and the 2002 Best Paper Award from the IEEE International Workshop on Design and Diagnostics of Electronic Circuits and Systems.']}}, {'name': ' Chuang Cheng', 'bio': {'p': ['Chuang Cheng is an ASIC consultant at Faraday Technology, Taiwan. His research interests include design for testability, especially memory and SOC testing. Cheng has a BS and MS in electrical engineering from National Tsing Hua University.']}}, {'name': ' Shao-I Chen', 'bio': {'p': ['Shao-I Chen was a DFT engineer at Faraday Technology. She is now a graduate student studying the management of intellectual property law at Queen Mary College, University of London. Her research interests include design for testability and design automation. Chen has a BSEE from Yuan Ze University, Taiwan.']}}, {'name': ' Chi-Yi Hwang', 'bio': {'p': ['Chi-Yi Hwang is vice president of ASIC technology at Faraday Technology. His research interests include design automation, especially physical design. Hwang has a BS in computer science from Tatung Institute of Technology, Taipei, and an MS and PhD in computer engineering from National Tsing Hua University.']}}, {'name': ' Hsiao-Ping Lin', 'bio': {'p': ["Hsiao-Ping Lin is president of Faraday Technology. His research interests include design automation and SOC design technologies. Lin has a BSEE from National Taiwan University and an MSEE from the University of California, Santa Barbara. He received the 1987 Engineering Achievement Award from ECAD Technologies, and the Republic of China's 1991 Best Young Engineer Award and 1998 Top 10 Distinguished Engineer Award."]}} %*A hierarchical test methodology for systems on chip %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1044301 %f/micro/uebxkoc8tmhdr2z9i7ojylfp0gw1n3fg.pdf %m16b23fb98d97b6b15b5fbe9cb60738d5 %cmicro %@[{'name': 'O. Sinanoglu', 'affiliation': 'Comput. Sci. & Eng. Dept., Univ. of California, San Diego, CA, USA', 'bio': {'p': ['Ozgur Sinanoglu is a PhD student in the Computer Science and Engineering Department at the University of California, San Diego. His research interests include VLSI test, digital signal processors, and computer architecture. Sinanoglu has a BS in electrical and electronics engineering and a BS in computer engineering, both from Bogazici University, Turkey, and an MS in computer engineering from the University of California, San Diego. He is a member of the IEEE.', 'Direct questions and comments about this article to Ozgur Sinanoglu, Computer Science and Engineering Dept., Univ. of California, San Diego, La Jolla, CA 92093–0114, ozgursin@cs.ucsd.edu.']}}, {'name': 'A. Orailoglu', 'affiliation': 'Comput. Sci. & Eng. Dept., Univ. of California, San Diego, CA, USA', 'bio': {'p': ['Alex Orailoglu is a professor in the Computer Science and Engineering Department at the University of California, San Diego. His research interests include digital and analog test, fault-tolerant computing, computer-aided design, and embedded processors. Orailoglu has an SB in applied mathematics from Harvard University, and an MS and PhD in computer science from the University of Illinois, Urbana-Champaign. He is a member of the IEEE.']}} %*Efficient construction of aliasing-free compaction circuitry %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1044302 %f/micro/lxajwp1qiituzbcjkhtfd307cbhl48ae.pdf %me4928d64891f1943c9147a92c7c9782a %cmicro %@[{'name': 'R. Mateosian'} %*Micro Review - Personal effectiveness %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1044303 %f/micro/tmo6cxdzvduea1yipkrjukblp8wy5gci.pdf %md7dcd799a59d48c6ea668724d66f4eb2 %cmicro %@[{'name': 'R.H. Stern'} %*Standardization and competitive advantage %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1134330 %f/micro/rnbxkuhgfoa6t4i5dqvcwzcarpj2dnqj.pdf %m7559446f13ac5581c03e4ca56c9e1f70 %cmicro %@[{'name': 'K. Sakamura', 'affiliation': 'University of Tokyo', 'bio': {'p': ["Ken Sakamura, IEEE Micro's editor in chief, is a professor in the Interfaculty Initiative in Information Studies at the University of Tokyo. His primary interests lie in computer architecture as well as real-time processing and computer-augmented environments. He initiated the TRON project in 1984 to help build computers in the 1990s and beyond. Under his leadership, more than 100 manufacturers participate in the TRON project. He now guides the T-Engine project, which attempts to provide the open standard real-time system development environment. He is now also the leader of the YRP Ubiquitous Network Laboratory, where ubiquitous computing environment research is carried out. Since he is also interested in how computer use will change society in the 21st century, his design activities extend to electronic appliances, furniture, houses, buildings, digital museums, and urban planning. Sakamura has a BS, ME, and PhD in electrical engineering from Keio University in Yokohama, Japan. He is an IEEE fellow, and a member of the ACM."]}} %*Making computers invisible %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1134335 %f/micro/kuf8wpbghrqn7unz514yivpwlcc2s96o.pdf %m912a9b9402edaa0db79779c7e4c50aac %cmicro %@[{'name': 'S. Shimada', 'affiliation': 'Central Res. Lab., Hitachi Ltd., Tokyo, Japan', 'bio': {'p': ["Shigeru Shimada is a senior researcher in the Intelligent System Research Department at Hitachi's Central Research Laboratory. His research interests include semantic data modeling of geospatial information and augmented reality in mobile environments. Shimada has an MS in mechanical engineering from Nagoya Institute of Technology and a PhD in information engineering from Tokyo University. He is a member of the Institute of Electronics, Information and Communication Engineers (IEICE), the IEEE, and ACM SIGMOD."]}}, {'name': 'M. Tanizaki', 'affiliation': 'Central Res. Lab., Hitachi Ltd., Tokyo, Japan', 'bio': {'p': ["Masaaki Tanizaki is a researcher in the Intelligen t System Research Department at Hitachi's Central Research Laboratory. His research interests include object-oriented and geospatial database systems. Tanizaki has a BS and MS in information engineering from Kobe University."]}}, {'name': 'K. Maruyarna', 'affiliation': 'Central Res. Lab., Hitachi Ltd., Tokyo, Japan', 'bio': {'p': ["Kishiko Maruyama is a senior researcher in the Intelligent System Research Department at Hitachi's Central Research Laboratory. Her research interests include pattern recognition and media processing. Maruyama has a BS and MS in science from Ochanomizu University, and a PhD in mathematical and physical science from the Graduate University for Advanced Studies in Hayama, Japan. She is a member of the IEICE."]}} %*Ubiquitous spatial-information services using cell phones %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1134341 %f/micro/md3huluv9wgwtxzei7hm6qcakn1d5sjj.pdf %m3891a9291c4aaa02f03b025ddb781b13 %cmicro %@[{'name': 'P. Tandler', 'affiliation': 'Ambiente Div., Fraunhofer IPSI, Darmstadt, Germany', 'bio': {'p': ['Peter Tandler is a scientific staff member of the Ambiente division of the Fraunhofer Integrated Publication and Information Systems Institute (IPSI). He leads software development within the Beach and i-Land projects. His research interests include synchronous groupware, integration of virtual and physical environments, new forms of human-computer and team-computer interaction for roomware, software architecture, programming languages, object-oriented frameworks, and object-oriented design and programming. Tandler is working on a PhD in the context of application models and software infrastructure for roomware environments at Fraunhofer IPSI. He has a Dipl.-Inform. in computer science from the Darmstadt University of Technology, Germany.']}}, {'name': 'N. Streitz', 'bio': {'p': ['Norbert Streitz is the head of the research division at Ambiente1Workspaces of the Future, which he founded to initiate work on roomware and cooperative buildings at Fraunhofer IPSI. He also teaches in the computer science department of the Technical University Darmstadt. He is the chair of the steering group of the European research initiative The Disappearing Computer (DC) and manager of the DC project Ambient Agoras. His research interests include human-computer interaction, hypermedia, computer-supported cooperative work, ubiquitous computing, user-centered design of smart artifacts, and the relationship between real and virtual worlds. Streitz has an MSc and PhD in physics and a second PhD in psychology. He is a member of the German Society of Computer Science (GI) and the German Society of Psychology (DGP).']}}, {'name': 'T. Prante', 'bio': {'p': ['Thorsten Prante is a scientific staff member of the Ambiente division at Fraunhofer IPSI. He also coordinates activities of the Future Office Dynamics consortium, and he teaches at the Darmstadt University of Technology in the departments of computer science and architecture. His research interests include human-computer interaction and computer-supported cooperative work, focusing on user interfaces for cooperative software in ubiquitous computing. Prante has a Dipl.-Inform. in computer science with minors in architecture and software ergonomics.']}} %*Roomware-moving toward ubiquitous computers %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1134342 %f/micro/ilqyy0c3b9aezxfpqfkhnt48otmlgwb2.pdf %m11acea0b7d85eadb6fa8b31a19ec88c4 %cmicro %@[{'name': 'K. Sakamura', 'affiliation': 'Tokyo Univ., Japan', 'bio': {'p': ["Ken Sakamura's biography appears in the the Guest Editor's Introduction starting on page 7 of this issue."]}}, {'name': 'N. Koshizuka', 'bio': {'p': ['Noboru Koshizuka is an associate professor at the Information Technology Center, University of Tokyo, and is assistant director at YRP Ubiquitous Networking Laboratory. His research interests include ubiquitous computing, operating systems, and interactive systems. Koshizuka has a BS, MS, and PhD, all in information science, from the University of Tokyo. He is a member of the IEEE and the ACM.']}} %*T-Engine: the open, real-time embedded-systems platform %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1134343 %f/micro/ll4zfprnsvpynbzerioytugoxta0u2ic.pdf %m98e3011331154959e109ab982f744f60 %cmicro %@[{'name': ' Fei Xia', 'affiliation': 'Sch. of Electr., Electron., & Comput. Eng., Newcastle upon Tyne Univ., UK', 'bio': {'p': ["Fei Xia is a research associate with the School of Electrical, Electronic, and Computer Engineering at the University of Newcastle upon Tyne, UK. His research interests include the design, modeling, and analysis of real-time asynchronous systems and in particular asynchronous data communication in such systems. Xia has a BEng in automation from Tsinghua University, an MSc in control systems from the University of Alberta, and a PhD in electronic engineering from King's College, University of London."]}}, {'name': 'A.V. Yakovlev', 'affiliation': 'Sch. of Electr., Electron., & Comput. Eng., Newcastle upon Tyne Univ., UK', 'bio': {'p': ['Alex V. Yakovlev is a professor with the School of Electrical, Electronic, and Computer Engineering at the University of Newcastle upon Tyne. His research interests include the modeling and design of asynchronous, concurrent, real-time, and dependable systems. Yakovlev has an MSc and PhD in computer science from St. Petersburg Electrotechnical University. He is $a$ member of the IEEE.']}}, {'name': 'I.G. Clark', 'affiliation': 'Sch. of Electr., Electron., & Comput. Eng., Newcastle upon Tyne Univ., UK', 'bio': {'p': ["Ian G. Clark is a research associate with the School of Electrical, Electronic, and Computer Engineering at the University of Newcastle upon Tyne. He is also $a$ senior researcher at Kingston University, UK. His research interests include the design, modeling, and analysis of real-time asynchronous systems, GALS, and asynchronous communication mechanisms. Clark has a BSc (Eng) and a PhD in electronic engineering from King's College, University of London. He is a member of the IEE."]}}, {'name': ' Delong Shang', 'affiliation': 'Sch. of Electr., Electron., & Comput. Eng., Newcastle upon Tyne Univ., UK', 'bio': {'p': ['Delong Shang is a research associate with the School of Electrical, Electronic, and Computer Engineering at the University of Newcastle upon Tyne. His research interests include computer system and VLSI circuit design and testing, especially in asynchronous systems. Shang has a BSc in computer science and technology from Nanjing University and an MEng in computer engineering from the Chinese Academy of Sciences.']}} %*Data communication in systems with heterogeneous timing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1134344 %f/micro/sqjarg7urvlt56nd1pwzvihincfscpqo.pdf %mf1fd1e936d4b1bb8ffa2a06fcb131bcd %cmicro %@[{'name': 'S. Greenstein'} %*Which industries use the internet? %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1134345 %f/micro/utcaolmbd0qhfgw2ra98ywri4dgulhkc.pdf %m5dd47aca9aac7adf6a3eaa097d900d48 %cmicro %@[{'name': 'J. Yee', 'affiliation': 'Pacific Broadband Communcations'}, {'name': 'M. Thapar'} %*Red Hot Chili Papers %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=903057 %f/micro/hkg3jkmtbof5vtwrvjxn4zmuzgnc2dae.pdf %m0e5c47dcd7f85dcf4c29217feed192f6 %cmicro %@[{'name': 'G. Welling', 'affiliation': 'Winphoria Networks, Tewksbury, MA, USA', 'bio': {'p': ['Girish Welling is a senior member of the technical staff at Winphoria Networks in Tewksbury, Mass. Welling obtained a BS degree in computer science and engineering from the Indian Institute of Technology, Madras, and MS and PhD degrees in computer science from Rutgers University. His research interests include mobile computing, distributed object systems, and adaptive application architectures. The work described in this article was mostly conceived and developed when he was at the Computer and Communications (C & C) Research Laboratories of NEC-USA.']}}, {'name': 'M. Ott', 'bio': {'p': ['Maximilian Ott is the chief technical officer and a cofounder of Semandex Networks in Princeton, N.J., which develops content routing technologies. Ott received an MSEE degree from the Technical University of Vienna and a PhD from the University of Tokyo. His research focuses on intelligent, network-centric information discovery, distribution, and presentation. He is a member of ACM and Usenix. The work described in this article was mostly conceived and developed when he was at the Computer and Communications (C & C) Research Laboratories of NEC-USA.']}}, {'name': 'S. Mathur', 'bio': {'p': ["Saurabh Mathur is a research associate with the Distributed System Software Group at NEC-USA's C & C Research Laboratories. His work involves building highly distributed systems for next-generation network services. Previous work included design and development of system software for the networking and telecom industry. Mathur is currently pursuing an MS degree at the Department of Computer Science, Rutgers University. His current research interests include distributed computing and programmable networks."]}} %*A cluster-based active router architecture %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=903058 %f/micro/a4ibc5mrvywkxtzp0otme9nr1vcfjsuw.pdf %m4777297a80368712eca45237166fbfe0 %cmicro %@[{'name': ' Li-Shiuan Peh', 'affiliation': 'Stanford Univ., CA, USA', 'bio': {'p': ['Li-Shiuan Peh is a PhD candidate in computer science at Stanford University. Her interests are high-speed interconnection networks and communication systems. She received a BS in computer and information systems from the National University of Singapore. She is a student member of the IEEE.']}}, {'name': 'W.J. Dally', 'bio': {'p': ['William J. Dally is a professor of electrical engineering and computer science at Stanford University, where his group developed the Imagine processor, which introduced the concepts of stream processing, partitioned register organizations, and low-power, high-speed signaling technology. Earlier, he was a professor at the Massachusetts Institute of Technology, where he and his group built the J-Machine and the M-Machine, experimental parallel computer systems. As a research assistant and research fellow at Caltech, he designed the MOSSIM Simulation Engine and the Torus Routing Chip, which pioneered wormhole routing and virtual-channel flow control. Dally received the BS in electrical engineering from Virginia Polytechnic Institute, the MS in electrical engineering from Stanford University, and the PhD in computer science from Caltech. He is a member of the IEEE, the Computer Society, the Solid-State Circuits Society, and the ACM.', 'Send questions and comments about this article to Li-Shiuan Peh, Stanford University, Gates Building 2A, Room 212, Stanford, CA 94305, Ispeh@cs.stanford.edu.']}} %*A delay model for router microarchitectures %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=903059 %f/micro/jshpecka4bulk28pu9mbt1nwmlgnixgj.pdf %m5ca097d3033d02fe8f80e9555ef69cb5 %cmicro %@[{'name': 'D. Shah', 'affiliation': 'Stanford Univ., CA, USA', 'bio': {'p': ['Devavrat Shah is working toward his PhD degree in the Computer Science Department at Stanford University. His interests include algorithms for networks, probabilistic analysis of algorithms and queuing theory. Shah received a BTech degree in computer science from IIT-Bombay.']}}, {'name': 'P. Gupta', 'bio': {'p': ['Pankaj Gupta is a PhD candidate in the Computer Science Department, Stanford University. His interests include packet classification and routing lookup for high-speed networks. Gupta received a BTech degree from IIT-Delhi and a PhD degree from Stanford University, both in computer science.']}} %*Fast updating algorithms for TCAM %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=903060 %f/micro/bqkshjyvxkmo9f17nqawngmusgfaudht.pdf %m1c55de86b897e30f29f8f010ee37c01d %cmicro %@[{'name': 'K. Psounis', 'affiliation': 'Stanford Univ., CA, USA', 'bio': {'p': ['Konstantinos Psounis is a PhD candidate in the Electrical Engineering Department at Stanford University. He received an MS from Stanford in electrical engineering. Psounis graduated (his first degree) from the Electrical Engineering and Computer Science Department of the National Technical University of Athens, Greece. He researches probabilistic, scalable algorithms for Internet-related problems. He has worked mainly in Web caching and performance, and congestion control.']}}, {'name': ' Rong Pan', 'bio': {'p': ['Rong Pan is a PhD candidate in the Electrical Engineering Department at Stanford University. Prior to Stanford, she was with Bell Labs, Lucent Technologies as a member of the technical staff, where she worked on Ethernet switch and wireless ATM designs. Her research interests are active-queue management schemes at network routers. She is interested in both router algorithm design and modeling.']}}, {'name': 'B. Prabhakar', 'bio': {'p': ["Balaji Prabhakar is an assistant professor of electrical engineering, computer science and (by courtesy) of engineering-economic systems and operations research at Stanford University. He received his PhD from the Electrical Engineering Department at the University of California, Los Angeles. He has also served as a postdoctoral fellow at the Basic Research Institute in the Mathematical Sciences (BRIMS), Hewlett-Packard Labs, England. He was a research scientist and lecturer at the Electrical Engineering and Computer Science Department at MIT. Prabhakar's research interests include high-speed computer and wireless networks, simple packet switch schedulers and router mechanisms for Internet quality of service, Web caching and accelerating content delivery, computer network pricing mechanisms, and ad hoc wireless network algorithms. His theoretical interests include stochastic network theory and its relationship to information theory, randomized algorithms arising in networking, and probability theory. He has been awarded the NSF Career award, the Alfred Sloan Fellowship, an Okawa Foundation Research Grant, a Terman Fellowship from Stanford University, and the Erlang Prize.", 'Direct comments about this article to Konstantinos Psounis, Stanford University, Department of Electrical Engineering, Barnes 4B, Stanford, CA 94305, kpsounis@leland.stanford.edu.']}} %*Approximate fair dropping for variable length packets %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=903061 %f/micro/qqflan6vmzhwox7bft1glbd4yyxc50je.pdf %mee1f1d552303882c7f329cf9b1fc7f88 %cmicro %@[{'name': 'K.Y. Yun', 'affiliation': 'Appl. Micro Circuits Corp., San Diego, CA, USA', 'bio': {'p': ['Kenneth Yun is currently on leave from the University of California, San Diego to serve as a chief technical officer for Applied Micro Circuits Corporation. He has been an associate professor in the Department of Electrical and Computer Engineering at the University of California, San Diego and held design-engineering positions at TRW, Hitachi, Intel, AMD, and IBM. His current research interests include high-speed networking and mixed-timed design methodologies. Yun holds a PhD degree in electrical engineering from Stanford University and an SM degree in electrical engineering and computer science from MIT.', 'Direct comments about this article to Kenneth Yun, Chief Technical Officer, Applied Micro Circuits Corporation, 6310 Sequence Drive, San Diego, CA 92121, kyun@amcc.com.']}} %*A terabit multiservice switch %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=903062 %f/micro/tcfwcd8ezs4oaikyrnjyvl2psotlhwmi.pdf %m0ebe76576556f9ce68e0e5563d97d606 %cmicro %@[{'name': 'E. Haq', 'affiliation': 'JAZiO Inc., San Jose, CA, USA', 'bio': {'p': ['Ejaz Haq is chief technical officer for JAZiO, Incorporated, of San Jose, California. Earlier, he was involved in the design and development of DRAMs, SRAMs, nonvolatile RAMs, and a derivative of the Alpha 21164 CPU at companies such as Samsung, Hitachi, VLSI Technology, Alliance Semiconductor, and National Semiconductor. Haq holds more than 15 patents with several others pending for JAZiO.']}}, {'name': 'J. Slager', 'bio': {'p': ['Jim Slager, chief evangelist for JAZiO, has been involved for many years in microprocessor and VLSI design activities including the SH3, SH4, and SH5 SuperH embedded microprocessors at Hitachi Semiconductor America, second- and third-generation Sparc chips at Sun Microsystems, and the 286, 386, and 486 microprocessors at Intel Corporation.']}}, {'name': 'J. Pecoraro', 'bio': {'p': ['John Pecoraro, executive VP for JAZiO, has over 25 years of test and product engineering experience in the semiconductor industry. He was involved in the development, characteri-zation, debug, and production transfer of various DRAM, SRAM, ASM, nonvolatile and embedded memories, microcontrollers, the SuperSparc microprocessor, ASIC products, and analog circuitry.']}}, {'name': 'J.D. Johnson', 'bio': {'p': ['John D. Johnson, a senior engineer at Micro Magic, Inc., was responsible for the routing, chip assembly, and physical verification of the JAZiO chip. His interests include computer architecture, EDA tools, and VLSI design. Johnson received a PhD degree in electrical engineering from Stanford University.']}}, {'name': 'M. Santoro', 'bio': {'p': ['Mark Santoro is president and cofounder of Micro Magic, Inc., a design services and CAD tool development company in Sunnyvale, California. Previously, he held positions at Sun Microsystems and Apple Computers. Santoro received MSEE and PhD degrees in electrical engineering from Stanford University.']}}, {'name': 'L. Tavrow', 'bio': {'p': ['Lee Tavrow is chief engineer and cofounder of Micro Magic, Inc. He is currently involved in high-speed circuit design and CAD tool development. Tavrow received BS, MS, and PhD degrees in electrical engineering from MIT.']}}, {'name': 'S. Wakefield', 'bio': {'p': ['David Weisner has over 20 years of experience in the design of high-speed CMOS circuits. Earlier, he was with Raycer Graphics, Silicon Graphics, and Sun Microsystems, where he worked on high-speed microprocessor design. Weisner holds a BSEE degree from UCLA.']}}, {'name': 'D. Weisner', 'bio': {'p': ['Scott Wakefield, a senior engineer at Micro Magic, has designed parallel and network processors at IBM, Amdahl, Sierra Research and Technologies, and CyberIQ. His interests include microprocessor, arithmetic, and logic design. Wakefield earned a PhD in electrical engineering from Stanford University.', 'Direct comments about this article to Ejaz Haq, JAZiO, Inc., 2099 Gateway Place, Suite 470, San Jose, CA 95110, ehaq@jazio.com.']}} %*JAZiO signal switching technology: a low-cost digital I/O for high-speed applications %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=903063 %f/micro/mdkpysb530pqmdec9gzlrnyqtjo8akwf.pdf %maca53debbad3fb3e38523cdd9214fca1 %cmicro %@[{'name': 'W.A. Samaras', 'affiliation': 'Intel Corp., Santa Clara, CA, USA', 'bio': {'p': ['William (Bill) Samaras is a principal engineer and the engineering manager of the Itanium Processor Cartridge Development Group at Intel in Santa Clara. Previously, he worked for Digital Equipment Corporation in Massachusetts, specializing in high-speed interconnects, bus design, and clocking systems. He was one of the contributors to the electrical section of the original PCI specification and the electrical sections of IEEE Std. 896.2, and a visiting lecturer at the University of Massachusetts, Lowell, as an electronics instructor. Samaras received a BSEE degree from the University of Massachusetts, North Dartmouth.']}}, {'name': 'N. Cherukuri', 'bio': {'p': ['Naveen Cherukuri, a lead designer on the Itanium processor cartridge at Intel, is responsible for the external L3 bus (BSB) design and overall cartridge electrical and physical design. Earlier, he worked for Fujitsu Microelectronics in M CM design for portable applications and signal integrity analysis on memory boards. He also worked as a software engineer at Tata Consultancy Services, India. Cherukuri has a BSEE degree from Jawaharlal Nehru Technological University, Kakinada, India, and an MSEE degree from the University of Arizona, Tucson.']}}, {'name': 'S. Venkataraman', 'bio': {'p': ['Srinivas Venkataraman is responsible for the electrical design, interconnect modeling, and analysis of the Itanium processor system bus interface. Earlier, he worked at Tandem Computers in Cupertino, Calif., where he was responsible for the electrical design of high-speed buses on systems based on the MIPS R10K processor. Srinivas received an MS degree in electrical engineering from the University of Arizona, Tucson.']}} %*The IA-64 Itanium processor cartridge %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=903064 %f/micro/kzlvbqywtacxwqlp71hc2u8noji9ipxg.pdf %m62472c445f229c89fd16e6b172e93fd6 %cmicro %@[{'name': 'G.S. Robinson'} %*International standards: why do them? %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=917995 %f/micro/acuxs0l8teqapmkjopybyxnfmzrohznv.pdf %mdcbfb88f8ec4bda78f8e4f28f9f32984 %cmicro %@[{'name': 'S. Greenstein'} %*Pricing Internet access %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=917996 %f/micro/ptcuc43uw8krb9lnwdfz6mageithq2ay.pdf %m78672f4d329e03de0ed9500de5e99c28 %cmicro %@[{'name': 'R.H. Stern'} %*Amazon's one-click patent loses its teeth %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=917997 %f/micro/s4m8g6fadv9jt5naz2flhuor3qebzlri.pdf %m444b3d65f564f4c6308c668c5bc79dad %cmicro %@[{'name': 'W.J. Dally', 'affiliation': 'Stanford University'}, {'name': 'M. Tremblay'}, {'name': 'A.J. Baum'} %*Hot chips 12 %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=917998 %f/micro/pqe2gibluxy0fnntcosar9mjsz4jwog6.pdf %ma63a131bb2774d0c6fb3c699d6b73f51 %cmicro %@[{'name': "M. O'Connor", 'affiliation': 'Silicon Access Networks, San Jose, CA, USA', 'bio': {'p': ["Mike O'Connor is the director of advanced architecture at Silicon Access Networks, where he is the chief architect of the iFlow Address Processor. He is responsible for designing a family of chips supporting high-speed next-generation networking equipment. O'Connor received an MS in electrical engineering from the University of Texas at Austin and a BSEE from Rice University. He holds 21 patents and is a member of the IEEE Computer Society."]}}, {'name': 'C.A. Gomez', 'bio': {'p': ['Christopher A. Gomez is a staff architect at Silicon Access Networks, where he is responsible for the architecture and microarchitecture of next-generation network-processing elements. His interests include computer architecture, network architecture, and architectural modeling and verification. Gomez is a member of the IEEE Computer Society.']}} %*The iflow address processor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=917999 %f/micro/4nsfp5yxwpdadc0qsehmrtfv9uhgmti6.pdf %m1f486ee5e8c1f0ebf9da9a05762c25e6 %cmicro %@[{'name': 'M. Steffen', 'affiliation': 'Dept. of Electr. Eng., Stanford Univ., CA, USA', 'bio': {'p': ['Matthias Steffen is a PhD candidate in the Electrical Engineering Department at Stanford University and a research scientist at the IBM Almaden Research Center in California. He received a BS in physics at Emory University. His research interests are in quantum information and experimental NMR techniques.']}}, {'name': 'M.K. Lieven', 'bio': {'p': ['Lieven M.K. Vandersypen is a PhD candidate in electrical engineering at Stanford University as a Yansouni Family Stanford Graduate Fellow, and is a research scientist at the IBM Almaden Research Center. He received a BS/MS in mechanical engineering from the Katholieke Universiteit Leuven and an MS in electrical engineering from Stanford University as a Francqui Fellow of the Belgian American Educational Foundation. His research interests are in the physics of information and the coherent control of quantum systems.']}}, {'name': ' Vandersypen', 'bio': {'p': ["Isaac L. Chuang is a research staff member at the IBM Almaden Research Center and a consulting professor in electrical engineering at Stanford University. Chuang received a PhD in electrical engineering from Stanford where he was a Hertz Foundation Fellow. He has been a visiting researcher at the Fujitsu Parallel Computing Research Center, Nippon Telephone and Telegraph Basic Research Laboratory, and the University of California at Santa Barbara's Institute for Theoretical Physics. He was also a postdoctoral fellow at Los Alamos National Laboratory and the University of California at Berkeley. In 1999, MIT Technology Review named Chuang one of the top 100 young innovators of the year. His research interests are quantum computation and quantum information."]}}, {'name': 'I.L. Chuang'} %*Toward quantum computation: a five-qubit quantum processor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=918000 %f/micro/e5wvh7iyluxzapn0lgfk4uwsko92p1bc.pdf %m02abab428b74f7ec3fc55eadfa508cd2 %cmicro %@[{'name': 'B. Khailany', 'affiliation': 'Stanford Univ., CA, USA', 'bio': {'p': ['Brucek Khailany is a PhD candidate in the Computer Systems Laboratory at Stanford University. He leads the VLSI implementation of the Imagine processor. Khailany has an MS in electrical engineering from Stanford University and a BS in electrical engineering from the University of Michigan. He is a student member of the IEEE and the ACM.']}}, {'name': 'W.J. Dally', 'bio': {'p': ['WilliamJ. Dally is a professor of electrical engineering and computer science at Stanford University, where his group developed the Imagine processor. He currently leads projects on high-speed signaling, computer architecture, and network architecture. Dally has a BS in electrical engineering from Virginia Polytechnic Institute, an MS in electrical engineering from Stanford University, and a PhD in computer science from Caltech. He is a member of the Computer Society, the Solid-State Circuits Society, the IEEE, and the ACM.']}}, {'name': 'U.J. Kapasi', 'bio': {'p': ['Ujval J. Kapasi is a PhD candidate in the Department of Electrical Engineering at Stanford University. He is one of the architects of the Imagine stream processor, and his research interests lie in parallel computer systems and software support for these systems. Kapasi holds an MS from Stanford University and a BS from Brown University.']}}, {'name': 'P. Mattson', 'bio': {'p': ['Peter Mattson is a PhD candidate at Stanford University. His research interests include programming languages and compilers for highperformance processors. He has a BS in electrical engineering from the University of Washington and an MS in electrical engineering from Stanford University. He is a member of the IEEE and the ACM.']}}, {'name': 'J. Namkoong', 'bio': {'p': ['Jinyung Namkoong is working toward the PhD in electrical engineering at Stanford University. His research interests include VLSI circuit techniques, systems architecture, and interconnection networks. Namkoong has a BS in electrical engineering and computer science from the University of California at Berkeley and an MS in electrical engineering from Stanford University.']}}, {'name': 'J.D. Owens', 'bio': {'p': ['John D. Owens is a PhD candidate in electrical engineering at Stanford University, where he is an architect of the Imagine stream processor. His research interests are computer architecture and computer graphics. Owens has a BS in electrical engineering and computer science from the University of California at Berkeley and an MS in electrical engineering from Stanford.']}}, {'name': 'B. Towles', 'bio': {'p': ["Brian Towles is a master's student in electrical engineering at Stanford. He is a system architect for the Imagine processor, with research interests in computer architecture and on-chip interconnection networks. Towles has a BS in computer engineering from the Georgia Institute of Technology."]}}, {'name': 'A. Chang', 'bio': {'p': ['Andrew Chang is a PhD candidate in electrical engineering at Stanford. His research interests include VLSI CAD, computer architecture, and circuit design. Chang received a BS and an MS degrees from the Massachusetts Institute of Technology. He is a student member of the IEEE and the ACM.']}}, {'name': 'S. Rixner', 'bio': {'p': ['Scott Rixner is an assistant professor of computer science and electrical and computer engineering at Rice University. Previously, he was the lead architect for the Imagine stream processor. His interests include computer architecture and media processing. Rixner has a BS and an MS in computer science and engineering and a PhD in electrical engineering from the Massachusetts Institute of Technology. He is a member of Tau Beta Pi and the ACM.', 'Direct questions and comments about this article to Brucek Khailany, Stanford University, Computer Systems Laboratory, Stanford, CA 94305, khailany@cva.stanford.edu.']}} %*Imagine: media processing with streams %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=918001 %f/micro/okjxpyfr7prceb0quu2bmh6nnwimc4az.pdf %m3172a9e7ae704165b6065075e97df401 %cmicro %@[{'name': 'I.E. Opris', 'bio': {'p': ['Ion E. Opris is an independent consultant in the areas of data acquisition, clock recovery, analog filters, and data communication circuits, including RF. Opris has an Engineer degree from Bucharest Polytechnic Institute and a MS and PhD in electrical engineering from Stanford University. He has published over 20 technical papers, holds 18 patents, and has six pending applications in various areas of circuit design, including data conversion architectures.']}}, {'name': 'S. Watanabe', 'bio': {'p': ['Seiichiro Watanabe is principal founder of NuCore Technology Inc. in Santa Clara, Calif. His research is in the area of developing very high speed over 12bits-granularity. Watanabe has an Engineer degree from Keio University. He was a member of the MITI industrial structure council.']}} %*A fast analog front-end processor for digital imaging systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=918002 %f/micro/fubothhuigwne1xs8v02fl3baymlzd7p.pdf %mb600bfdb3b4e5a91e10960fb4ff02854 %cmicro %@[{'name': 'R.B. Tremaine', 'affiliation': 'IBM T.J. Watson Res. Center, Yorkbourn Heights, NT, USA', 'bio': {'p': ['R. Brett Tremaine is a senior technical staff member at the IBM T.J. Watson Research Center, where he is responsible for commercial server and memory hierarchy architecture, design, and ASIC implementation. Tremaine received an MS in computer engineering from Syracuse University and a BS in electrical engineering from Michigan Technological University. He is a member of the IEEE.']}}, {'name': 'T.B. Smith', 'bio': {'p': ['T. Basil Smith is a senior manager at the IBM T.J. Watson Research Center, where he researches the exploitation of high-leverage server innovations. His work has focused on memory hierarchy architecture, reliability, durability, and storage efficiency enhancements in advanced servers. Smith received a BS, an MS, and a PhD in computer systems from MIT. He is a member of the IEEE Computer Society Technical Committee on Fault-Tolerant Computing and an IEEE Fellow.']}}, {'name': 'M. Wazlowski', 'bio': {'p': ['Mike Wazlowski is a research staff member at the IBM T.J. Watson Research Center, where he is responsible for high-performance memory system architecture and design. His research interests include computer architecture, memory systems, and ASIC design. Wazlowski received a BS in computer engineering from the University of Massachusetts at Amherst and an MS and a PhD in electrical sciences from Brown University. He is a member of the IEEE.']}}, {'name': 'D. Har', 'bio': {'p': ['David Har is an advisory engineer at the IBM T.J. Watson Research Center, where he implemented the MXT compression algorithm and hardware. His technical interests include microarchitecture and low-power DSP design. Har received MS and BS degrees in electrical engineering from MIT']}}, {'name': ' Kwok-Ken Mak', 'bio': {'p': ['KwokKen Mak is a senior hardware engineer at Cisco Systems, where he is responsible for high-performance memory architecture and design. Earlier, he was a senior engineer at the IBM T.J. Watson Research Center, where he participated in the MXT project. He received a BS in electrical engineering from Polytechnic University of New York.']}}, {'name': 'S. Arramreddy', 'bio': {'p': ['Sujith Arramreddy is the chief technology officer and a founding member of Server-Works, where he is responsible for technology direction. Arramreddy received an MS in computer engineering from Wayne State University and a BS in electrical engineering from Jawaharlal Nehru Technical University in Hyderabad, India.', 'Direct questions about this article to Brett Tremaine, IBM T.J. Watson Research Center, PO Box 218, Yorktown Heights, NY 10598, afton@us.ibm.com.']}} %*Pinnacle: IBM MXT in a memory controller chip %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=918003 %f/micro/enribfpxdkttmgeghfdsn74ocuowjj16.pdf %m130ec881a77b30a5c63eb5ec0a7897c1 %cmicro %@[{'name': 'M. Stadler', 'affiliation': 'bridgeCo., Switzerland'}, {'name': 'M. Thalmann'}, {'name': 'T. Rower'}, {'name': 'H. Kaeslin'}, {'name': 'N. Felber'}, {'name': 'W. Fichtner'} %*Design and verification of a stack processor virtual component %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=918004 %f/micro/ckok2f4sgfus8cdt7ngmx6joxwlzedet.pdf %m354f69f73a45670388a30ba3696edad3 %cmicro %@[{'name': 'H. Kirrmann', 'affiliation': 'ABB Corp. Res., Baden, Switzerland'}, {'name': 'P.A. Zuber'} %*The IEC/IEEE train communication network %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=918005 %f/micro/hwykoinp1nydczx7qegu6jtw48bd3xel.pdf %mfb59916e03c6e3c6ea03afd0230e5af8 %cmicro %@[{'name': 'R. Mateosian'} %*Embedded system design computers as components: principles of enbedded computing system design [Book Reviews] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=918006 %f/micro/fugortnkyqpwc49rm1nsd5e0mczfilbd.pdf %m33be5b174aa8b61764a555395957d12a %cmicro %@[{'name': 'A. Pentland', 'affiliation': 'MIT Media Laboratory'} %*Wearable information devices %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=928761 %f/micro/xmdn1m8oxwyrwgzf2ohflicakqzerg3s.pdf %mcf5215426320678159d113ce12733ce6 %cmicro %@[{'name': 'P. Lukowicz', 'affiliation': 'Swiss Federal Inst. of Technol., Zurich, Switzerland', 'bio': {'p': ['Paul Lukowicz is a research associate in charge of the Wearable Computing Lab and the Computer Architecture Group at the ETH Electronics Laboratory. His research interests include wearable computing, low-power and high-performance computer architecture, and optical interconnections. Lukowicz has MS degrees in both computer science and physics and a PhD in computer science from the University of Karlsruhe, Germany. He is a member of the IEEE and the ACM.']}}, {'name': 'U. Anliker', 'bio': {'p': ['Urs Anliker is a research assistant at the Wearable Computing Laboratory at the ETH Electronics Laboratory. His research interests include low-power system design and context-awareness power management. Anliker has a Dipling in electrical engineering from the ETH.']}}, {'name': 'G. Troster', 'bio': {'p': ['Gerhard Tröster is a full professor and head of the ETH Electronics Lab. His research interests include wearable computing, signal processing, mechatronics, and electronic packaging. He has an MSc from the Technical University of Karlsruhe, Germany, and a PhD from the Technical University, Darmstadt, Germany. He has authored and coauthored more than 90 articles and holds five patents in integrated circuit design. He is a member of the IEEE.']}}, {'name': 'S.J. Schwartz', 'bio': {'p': ['Steven J. Schwartz is a research scientist in the Human Design Group at the Massachusetts Institute of Technology Media Laboratory. His research interests include wearable computing. He has been chief video engineer at Lucasfilm LTD, director of HDTV research and principal colorist at The Post Group, founder of Excalibur Video Systems, and vice president of research for a wearable computer company where he developed four generations of wearable computing platforms.']}}, {'name': 'R.W. DeVaul', 'bio': {'p': ['Richard W. DeVaul is a PhD student and Toshiba Fellow in the Human Design group at the Massachusetts Institute of Technology Media Laboratory. His research interests include mathematical modeling, computational neuroscience, and wearable computing. DeVaul has a B. Ed in environmental design from Texas A&M University and an MS from the MIT Media Lab.']}} %*The wearARM modular, low-power computing core %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=928762 %f/micro/cavs1wxx8ato2bur7d4zgyrndynpesm0.pdf %m1129e264b7ec77954e44c3f006764fec %cmicro %@[{'name': 'N.S. Shenck', 'affiliation': 'Media Lab., MIT, Cambridge, MA, USA', 'bio': {'p': ['Nathan S. Shenck is a submarine lieutenant on the USS Philadelphia, stationed in Groton, Connecticut. While not at sea, he enjoys investigating alternative energy sources and researching wireless technology. Shenck has a BS in electrical engineering from the US Naval Academy and an MS in electrical engineering from MIT.']}}, {'name': 'J.A. Paradiso', 'bio': {'p': ['Joseph A. Paradiso is a principal research scientist at the MIT Media Laboratory, where he leads the Responsive Environments Group and is the Technology Director of the Things That Think Consortium. In earlier work, he developed high-energy physics detectors, spacecraft control algorithms, and various sensor systems. Paradiso has a BS in electrical engineering and physics from Tufts University and a PhD in physics from MIT, where he was a Compton Fellow. He is a member of the IEEE, AIAA, ACM, and APS.']}} %*Energy scavenging with shoe-mounted piezoelectrics %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=928763 %f/micro/k2m69mcout13gsllehdabip0oyvxsrih.pdf %m3004815666eb3a34ffde6a951ec7b92e %cmicro %@[{'name': 'M.H. Samadzadeh', 'affiliation': 'Dept. of Comput. Sci., Oklahoma State Univ., Stillwater, OK, USA', 'bio': {'p': ['Mansur H. Samadzadeh is an associate professor in the Computer Science Department of Oklahoma State University, Stillwater, Oklahoma. His research interests include software engineering, operating systems, parallel computing, and the theory of computation. Samadzadeh has an MS and PhD in computer science from the University of Louisiana at Lafayette. He is a member of the IEEE Computer Society, IEEE, and the ACM.']}}, {'name': 'L.E. Garalnabi', 'bio': {'p': ['Loai E. Garalnabi is a system programmer and telecommunications specialist in Abu Dhabi, United Arab Emirate. His research interests include operating systems and computer architecture. Garalnabi has a BS in computer science from the University of Khartoum, Sudan, and an MS in computer science from Oklahoma State University. He is a member of the ACM.']}} %*Hardware/software cost analysis of interrupt processing strategies %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=928766 %f/micro/2olfamt1r6o4nwhlgw3id8jeb7zyuvbe.pdf %m6f1a1c32072f1a98e792ad3041178a72 %cmicro %@[{'name': 'K. Sakamura'} %*A java-enabled evolution %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=946665 %f/micro/5krksf2uxctpmrd9mgcujywhwvi7elon.pdf %m7b0925e0028ed729c1c441d6b4d5f002 %cmicro %@[{'name': 'G.S. Robinson'} %*Why standards are here to stay %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=946667 %f/micro/rnoqskf0dilbc4hrwvmgyp9kg7zxnjae.pdf %m23f4283d1e5071a92a807aef168be681 %cmicro %@[{'name': 'S. Greenstein', 'bio': {'graphic': '/mediastore/IEEE/content/freeimages/40/20475/946669/946669-photo-1-small.gif', 'p': ['']}} %*An earful about Zvi's e-mail %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=946669 %f/micro/yobqyja65dpw1t0ccmm7b4gveqovkht8.pdf %mad4536a8f595746afef5aee5d8993d8f %cmicro %@[{'name': 'R.H. Stern'} %*More standardization skullduggery %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=946671 %f/micro/rczcslnjvfw58faqwugygp2mhkliphjv.pdf %m3988ac6764dbeaf000a59476f4076cb7 %cmicro %@[{'name': 'S. Hachiya', 'bio': {'p': ['Shouichi Hachiya is a senior researcher at Aplix. His research interests include embedded systems (JTRON), logical format of optical discs (ISO 9660, OSTA UDF, DVD), and standardization.']}} %*Java use in mobile information devices: Introducing JTRON %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=946675 %f/micro/kf5o4bdgpaiewcf2uu3pcyxbzm8r9dzw.pdf %mdae24d117a6017abf09dccc77bdf27bc %cmicro %@[{'name': 'Z. Zhang', 'affiliation': 'Coll. of William & Mary, Williamsburg, VA, USA'}, {'name': 'Z. Zhu'}, {'name': 'X. Zhang'} %*Cached DRAM for ILP processor memory access latency reduction %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=946676 %f/micro/2c1qksbr6yypgtc8zuveoq9vlgwd5hjf.pdf %mc221ff09fbbd801b3c74933c987ac6df %cmicro %@[{'name': 'D. Kim', 'affiliation': 'Washington Univ., Seattle, WA, USA', 'bio': {'p': ['Donglok Kim is a research assistant professor in the Department of Electrical Engineering at the University of Washington, Seattle. His research interests include mediaprocessor architectures, processor-memory interface, multimedia video and graphics processing, and portable image computing libraries. Kim has a PhD in electrical engineering from the University of Washington, Seattle.']}}, {'name': 'R. Managuli', 'bio': {'p': ['Ravi Managuli is a research assistant professor in the Department of Bioengineering at the University of Washington, Seattle. His research interests include algorithms and systems for medical imaging, digital signal processing, image processing, computer architecture, and real-time multimedia applications. Managuli has a PhD in electrical engineering from the University of Washington, Seattle.']}}, {'name': 'Y. Kim', 'bio': {'p': ['Yongmin Kim is a professor and chair of bioengineering and a professor of electrical engineering, both at the University of Washington, Seattle, where he is also an adjunct professor of computer science and engineering, and of radiology. His research interests include mediaprocessor architecture and algorithms, and systems for multimedia, image processing, and medical imaging. Kim has a PhD in electrical engineering from the University of Wisconsin, Madison.', 'Direct questions and comments about this article to Yongmin Kim, Depts. of Electrical Engineering and Bioengineering, Univ. of Washington, Box 352500, Seattle, WA98195, ykim@u.washington.edu.', 'For further information on this or any other computing topic, please visit our Digital Library at http://computer.org/publications/dlib.']}} %*Data cache and direct memory access in programming mediaprocessors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=946678 %f/micro/dropjc54vz6gf3tiqxhllinv0mubwdry.pdf %m14d775b3ff24dff42423416721de7b5d %cmicro %@[{'name': 'T. Starner', 'affiliation': 'Georgia Inst. of Technol., Atlanta, GA, USA', 'bio': {'p': ['Thad Starner is an assistant professor at the Georgia Institute of Technology. His research interests include intelligent agents, wearable computing, computer vision, and pattern recognition. Starner has a PhD from the Massachusetts Institute of Technology Media Laboratory and has been wearing general-purpose computers as part of his daily life for eight years. He is a member of the IEEE Computer Society, the ACM, and the AAAS.']}} %*The challenges of wearable computing: Part 1 %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=946681 %f/micro/cd07xrizegbmsiztf9pgjuqakvab4l8j.pdf %m8d0a1bbddb46a265fe875072f1d74059 %cmicro %@[{'name': 'T. Starner', 'affiliation': 'Georgia Inst. of Technol., Atlanta, GA, USA', 'bio': {'p': ['Thad Starner is an assistant professor at the Georgia Institute of Technology. His research interests include intelligent agents, wearable computing, computer vision, and pattern recognition. Starner has a PhD from the Massachusetts Institute of Technology Media Laboratory and has been wearing general-purpose computers as part of his daily life for eight years. He is a member of the IEEE Computer Society, the ACM, and the AAAS.']}} %*The challenges of wearable computing: Part 2 %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=946683 %f/micro/wmpxqc2ueko0cvauba9przrjtvd37shi.pdf %mcb6959221c0ff15aeaced92cce829fbb %cmicro %@[{'name': 'R. Mateosian'} %*Making it work %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=946684 %f/micro/61vmnqzfpmdl4iuvhfxocaz9yxhge2ga.pdf %m96e2302c2e77198f6020fe9bbd1bd880 %cmicro %@[{'name': 'S. Greenstein'} %*Explaining booms, busts, and errors [microeconomics] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=958693 %f/micro/ejd1auqkpvllcjtt6fri39ybxsm48chk.pdf %mfc0fff4a44181cec32358ac8d54ea81a %cmicro %@[{'name': 'R.H. Stern'} %*Another update on standardization skullduggery %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=958694 %f/micro/vn186wiabd9a3sggxsjvlyymtrup72uq.pdf %mca7fb01deaafafaee3c1aa33dfd7dee1 %cmicro %@[{'name': 'D.R. Avresky', 'affiliation': 'Northeastern University'}, {'name': 'F. Lombardi'}, {'name': 'K.E. Grosspietsch'}, {'name': 'B.W. Johnson'} %*Fault-tolerant embedded systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=958695 %f/micro/jpgr9q5txrnkszjdxyoeieobnfl0da6i.pdf %mf230030f0671f99099a290c8b539875c %cmicro %@[{'name': 'A. Benso', 'affiliation': 'Politecnico di Torino, Italy', 'bio': {'p': ['Alfredo Benso is a research assistant at Politecnico di Torino, Italy. His research interests include design-for-testability techniques, dependability analysis, and software-implemented hardware fault tolerance of computer-based systems. Benso received a PhD in computer engineering from the Politecnico di Torino. He is the chair of the IEEE Computer Society Test Technology Technical Council Web-based activities group.']}}, {'name': 'S. Chiusano', 'bio': {'p': ['Silvia Chiusano is a research assistant at Politecnico di Torino, Italy. Her research interests include high-level testing, design-for-testability techniques, BIST, and dependability. Chiusano received a PhD in computer engineering from Politecnico di Torino.']}}, {'name': 'P. Prinetto', 'bio': {'p': ['Paolo Prinetto is a full professor of computer engineering at Politecnico di Torino, Italy, and a joint professor at the University of Illino is at Chicago. His research interests include testing, test generation, BIST, and dependability. Prinetto received an MS in electronic engineering from Politecnico di Torino. He is a Golden Core Member of the IEEE Computer Society and the elected chair of the IEEE Computer Society Test Technology Technical Council.', 'For further information on this or any other computing topic, please visit our Digital Library at http://computer.org/publications/dlib.']}} %*A self-repairing execution unit for microprogrammed processors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=958696 %f/micro/e0cfflbdxjoj6viuxwqagr1kumy9opsy.pdf %ma16396cf3588b021d8580a96f0178ea5 %cmicro %@[{'name': 'M. Pflanz', 'affiliation': 'Brandenburg Tech. Univ., Cottbus, Germany', 'bio': {'p': ['Matthias Pflanz is an assistant professor in the Department of Computer Engineering at Brandenburg Technical University at Cottbus. His research interests include embedded processor design, online test, and fast recovery techniques for dependable processors. Pflanz has a diploma in electrical engineering and a PhD in computer engineering from Brandenburg Technical University at Cottbus. He is a member of the IEEE.']}}, {'name': 'H.T. Vierhaus', 'bio': {'p': ['Heinrich Theodor Vierhaus is a professor of computer engineering at Brandenburg Technical University at Cottbus. His research interests include IC design and test technology, fault behavior and fault models, and design of dependable embedded systems. Vierhaus has a diploma in electrical engineering from Ruhr University, Bochum, Germany, and a PhD in electrical engineering from the University of Siegen, Germany. He is a member of the IEEE.', 'For further information on this or any other computing topic, visit our Digital Library at http://computer.org/publications/dlib.']}} %*Online check and recovery techniques for dependable embedded processors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=958697 %f/micro/txscgxp6ru2ww3ifdzybt40ijclfvuse.pdf %md4377e043492c8a2d5aa428b985bc3e9 %cmicro %@[{'name': 'P. Richardson', 'affiliation': 'Michigan Univ., Dearborn, MI, USA', 'bio': {'p': ['Paul Richardson is an assistant professor in the Department of Electrical and Computer Engineering at the University of Michigan-Dear-born. His research interests include embedded real-time systems, in-vehicle networks, and mobile networks. Richardson has a BSE in computer engineering, an MSE in computer and electrical engineering, and a PhD in systems engineering from Oakland University. He is a member of the IEEE and ACM.']}}, {'name': 'L. Sieh', 'bio': {'p': ['Larry Sieh is a research associate at the US Army Research Center in Warren, Michigan. His research interests include wireless combat networks, multimedia networks, network simulation, combat vehicle simulation, and software engineering. Sieh has a BSE in computer engineering and MS degrees in electrical engineering, systems engineering, and computer science from Oakland University. He is a PhD candidate in software engineering at the Naval Postgraduate School and a member of the IEEE.']}}, {'name': 'A.M. Elkateeb', 'bio': {'p': ['Ali M. Elkateeb is an associate professor in the Department of Electrical and Computer Engineering at the University of Michigan-Dearborn. His research interests include embedded RISC architectures, reconfigurable computing, and high-speed networks. Elkateeb has a BS, MS, and PhD in computer science. He is a member of the IEEE.', 'Direct questions and comments about this article to Paul Richardson, Dept. of Electrical and Computer Eng., Univ. of Michigan-Dear-born, 4901 Evergreen Rd., Dearborn, MI 48128–1491, paul_richardson@umich.edu.']}} %*Fault-tolerant adaptive scheduling for embedded real-time systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=958698 %f/micro/re5mbqupf2pc4ixngw9luly1w7stzjoe.pdf %m071b86e90cd0d9586fc8de29b3176472 %cmicro %@[{'name': 'A. Bondavalli', 'affiliation': 'Univ. of Firenze, Italy', 'bio': {'p': ['Andrea Bondavalli is an associate professor at the University of Firenze, Italy. His research interests include software fault tolerance, evaluation of dependability attributes, and the design and validation of dependable systems. He is a member of the IEEE Computer Society and the International Federation for Information Processing Working Group 10.4 on Dependable Computing and Fault Tolerance.']}}, {'name': 'A. Fantechi', 'bio': {'p': ['Alessandro Fantechi is an associate professor for the Faculty of Engineering at the University of Firenze, Italy, he is also a collaborator for the Istituto di Elaborazione della Informazione (Information Processing Institute) of the Italian National Research Council. His research interests include the application of formal verification methods, especially the verification of critical components of an architecture for dependable systems. He is member of the ACM and the International Federation for Information Processing Working Group 6.1.']}}, {'name': 'D. Latella', 'bio': {'p': ['Diego Latella is a researcher at CNUCE, an institute of the Italian National Research Council, he is also a lecturer in computer science at the University of Pisa. His current research interests include specification and verification models and tools for concurrent systems and their application. He is member of the ACM and the European Association of Theoretical Computer Science.']}}, {'name': 'L. Simoncini', 'bio': {'p': ['Luca Simoncini is a professor of computer engineering at the University of Pisa and is director of CNUCE, an institute of the Italian National Research Council. His research interests include theory and practice in the design and validation of dependable systems and architectures and design environments for safety-critical control applications. He is a member of the International Federation for Information Processing Working Group 10.4 on Dependable Computing and Fault Tolerance.']}} %*Design validation of embedded dependable systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=958699 %f/micro/osnkidjun15thzmapgb4fxdgqqlryjxv.pdf %maf596292a78c3a747fab24b96a6082e9 %cmicro %@[{'name': 'G. Provan', 'affiliation': 'Rockwell Sci., Thousand Oaks, CA, USA', 'bio': {'p': ['Gregory Provan is a technical manager at Rockwell Scientific in Thousand Oaks, Calif. His research interests include diagnosis, discrete-event control, distributed and agent-based systems, and embedded systems. Provan has a DPhil in mathematics from the University of Oxford, an MS from Stanford University, and a BSE from Princeton University. He is a member of the IEEE and AAAI.']}}, {'name': ' Yi-Liang Chen', 'bio': {'p': ['Yi-Liang Chen is a member of the technical staff at Rockwell Scientific. His research interests include discrete-event systems (modeling, control, and diagnosis), conflict resolution, system autoconfiguration, and hybrid systems. Chen has a PhD and MS in electrical engineering (systems) from the University of Michigan, Ann Arbor, and a BSE from National Taiwan University, Taiwan. He is a member of the IEEE and AAAI.', 'Direct questions and comments about this article to Gregory Provan, Rockwell Scientific, 1049 Camino Dos Rios, Thousand Oaks, CA 91360, gprovan@rwsc.com.', 'For further information on this or any other computing topic, please visit our Digital Library at http://computer.org/publications/dlib.']}} %*Model-based fault-tolerant control reconfiguration for general network topologies %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=958700 %f/micro/i5xkcvghxqrto3raj1gy92m7sfwnvwfd.pdf %m641123c69ab328db54c7d6f6feb1954d %cmicro %@[{'name': ' Wenyi Feng'}, {'name': 'F. Karimi'}, {'name': 'F. Lombardi'} %*Fault detection in a tristate system environment %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=958701 %f/micro/fx2vclcygaiqtekozunavo1hrgpxksfr.pdf %mb31cf5f4ecfad21366f9baae3e642fcf %cmicro %@[{'name': 'R. Mateosian'} %*Managing development %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=958702 %f/micro/yq37i9rfgkvewhxsswcxelzndbad2hpm.pdf %m55268b75e9bf414666f761c630e76776 %cmicro %@[{'name': 'K. Sakamura', 'affiliation': 'University of Tokyo', 'bio': {'p': ["Ken Sakamura, IEEE Micro's editor-in-chief, is a professor in the Interfaculty Initiative in Information Studies at the University of Tokyo. He is currently constructing the Digital Museum, which uses various computer technologies. His primary interests lie in computer architecture and digital museums as well as real-time processing and computer-augmented environments. He initiated the TRON project in 1984 to help build computers in the 1990s and beyond. Under his leadership, over 100 manufacturers participate in the project. Since he is also interested in how computer use will change society in the 21st century, his design activities extend to electronic appliances, furniture, houses, buildings, and urban planning. Sakamura received a BS, an ME, and a PhD in electrical engineering from Keio University in Yokohama. He is a senior member of the IEEE and a member of the ACM.", 'Direct questions or comments about this special issue to Ken Sakamura, University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-0033, Japan, k.sakamura@computer.org.']}} %*Radio frequency identification and noncontact smart cards %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=977752 %f/micro/ciasi4ltsgh20vdngbd6o8kneubeqjy7.pdf %m3648b0e4dfe9db5f4da6881e00826711 %cmicro %@[{'name': 'K. Sakamura', 'affiliation': 'Univ. of Tokyo, Japan', 'bio': {'p': ["Ken Sakamura's biography appears in this issue's “Guest Editors' Introduction.”"]}}, {'name': 'N. Koshizuka', 'bio': {'p': ['Noboru Koshizuka is an associate professor at the Information Technology Center, University of Tokyo. His research interests include secure systems, operating systems, and interactive systems. Koshizuka has a BS, MS, and a PhD, all in information science, from the University of Tokyo. He is a member of IEEE and ACM.']}} %*The eTRON wide-area distributed-system architecture for e-commerce %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=977753 %f/micro/cq8se4wvgstwr6yadouklnzvgi12hpoh.pdf %m16851622b3c29c05f9a0c24455496255 %cmicro %@[{'name': 'J.-F. Dhem', 'bio': {'p': ['Jean-François Dhem is a researcher at Gem-plus in the Card Security Group, leading the hardware security team. His research interests include cryptographic hardware and software implementations, and hardware security features in smart cards. Dhem has an MS and a PhD in electrical engineering from the Catholic University of Louvain (UCL), Belgium. He is an associate member of the IEEE and a member of the IEEE Computer Society, the IEEE Solid-State Circuits Society, and the International Association for Cryptologic Research.']}}, {'name': 'N. Feyt', 'bio': {'p': ["Nathalie Feyt is a smart card engineer at Gem-plus in the Card Security Group, where she also leads the public-key algorithms development team. Her research interests include security and cryptography. She developed the first Gemplus public-key card, included in public-key infrastructure solutions. Feyt has an MS in electronics and computer science from the University of Bordeaux, Ecole Nationale Superieure d'Electronique et d'Informatique de Bordeaux, France. She is a member of the Java Card Forum."]}} %*Hardware and software symbiosis helps smart card evolution %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=977754 %f/micro/z46ayi1h7wbectsrempzurqbfxnj35mo.pdf %m10b4d916e094d3c96af1d6c23fadbc27 %cmicro %@[{'name': 'E. Trichina', 'affiliation': 'Gemplus CryptoDesign Center, Rome, Italy', 'bio': {'p': ['Elena Trichina is a cryptodesigner at the Gemplus CryptoDesign Center, Rome, and an adjunct professor at the University of Joensuu, Finland. Her research interests include parallel processing, programmable hardware, formal methods of software and hardware design, hardware implementation of cryptographic primitives, implementation of elliptic curve cryptosystems, and analysis and design of algorithmic countermeasures against side-channel attacks. Trichina has an MS in mathematics from Novosibirsk State University and a PhD in computer science from the Computing Center of the Siberian Division of the Russian Academy of Sciences.']}}, {'name': 'M. Bucci', 'bio': {'p': ['Marco Bucci is a cryptodesigner at the Gemplus CryptoDesign Center. His research interests include smart card cryptographic and security hardware design. Bucci has a Laurea in electronic engineering from the University of Rome, La Sapienza.']}}, {'name': 'D. De Seta', 'bio': {'p': ['Domenico De Seta is the digital design project leader at the Gemplus CryptoDesign Center. His research interests include digital speech processing, network performance, synchronization, and the evaluation of IP over wavelength-division multiplexing. Seta has an EE from the University of Rome, La Sapienza.']}}, {'name': 'R. Luzzi', 'bio': {'p': ['Raimondo Luzzi is a PhD student in electrical engineering at the University of Rome, La Sapienza. His research interests include the design of mixed-signal circuits and system-on-a-chip design techniques, with special emphasis on hardware for cryptographic applications. Luzzi has a DrEng in electrical engineering from the University of Rome, La Sapienza.']}} %*Supplemental cryptographic hardware for smart cards %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=977755 %f/micro/nznua61tk5ke9h7yotbcw0mrfmojwlxx.pdf %m869a70c32f42d99fe58c4ae056f2e840 %cmicro %@[{'name': 'T. Gyger', 'bio': {'p': ['Thomas Gyger is project manager for systems development in the Internet and high-tech business development team at Swatch Group, EM Microelectronic-Marin SA. His research interests include systems engineering with a focus on software development and data security. Gyger has an Ecole Technique Supérieure (ETS) degree in engineering from the engineering school of Saint-Imier, Switzerland. He is a member of the Swiss Informaticians Society.']}}, {'name': 'O. Desjeux', 'bio': {'p': ["Olivier Desjeux is project manager and group leader of RFID solutions support at EM Microelectronic-Marin SA. His research interests include radio frequency development with an emphasis on radio localization. Desjeux has a Diplôme d'Ingénieur in electrical engineering from the Ecole Française d'Electronique et d'Informatique, Paris and an MS in project management and quality from the Institut de Gestion Sociale. He is a member of the IEEE."]}} %*EasyRide: active transponders for a fare collection system %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=977756 %f/micro/vlzhgjbanowgzqickynki74fu1otyrdp.pdf %m9ffa196392ec4b27059fea1efead1491 %cmicro %@[{'name': 'K. Takaragi', 'affiliation': 'Hitachi Syst. Dev. Lab., Yokohama, Japan', 'bio': {'p': ['Kazuo Takaragi is a senior manager at the Hitachi Systems Development Laboratory, Yokohama, Japan. His research interests include cryptography and information security techniques. Takaragi received an MS in control engineering from the Tokyo Institute of Technology and PhD in reliability engineering from Tokyo University. He is a member of the IEEE, the Information Processing Society of Japan, the Institute of Electronics, Information, and Communication Engineers, and the Institute of Electrical Engineers of Japan.']}}, {'name': 'M. Usami', 'bio': {'p': ['Mitsuo Usami is assistant to the general manager in the Hitachi Multimedia Systems Research Department. His research interests include application devices using thinned silicon chips, magnetic-card-like ultrathin IC cards, and bipolar high-speed logic LSIs for large-scale mainframe computers. Usami received a BS in electronics engineering from the Tokyo Institute of Technology.']}}, {'name': 'R. Imura', 'bio': {'p': ['Ryo Imura is chief executive officer of Mu-solutions, an in-house venture company at Hitachi. His research interests include information and secure ID systems. Imura received a PhD in material science from the University of Nagoya. He is a member of the Academic Society of Applied Physics and Applied Magnetics in Japan.']}}, {'name': 'R. Itsuki', 'bio': {'p': ['Rei Itsuki is a senior business coordinator of Mu-solutions, Hitachi. His research interests include knowledge engineering and business-to-business e-marketplace systems. Itsuki received a PhD in information system engineering from Osaka University. He is a member of the Information Processing Society of Japan and the Institute of Electrical Engineers of Japan.']}}, {'name': 'T. Satoh', 'bio': {'p': ['Tsuneo Satoh is director of the IC Card Business Unit at Hitachi. His research interests include microprocessors with nonvolatile memory. Satoh received an M.Eng. in electronics from Tokyo Metropolitan University.', 'Direct questions and comments about this article to Kazuo Takaragi, Security Systems Research Dept., Hitachi Systems Development Laboratory, 292 Yoshida-cho, Totsukaku, Yokohama-shi, Kanagawa-ken, 244–0817 Japan, takara@sdl.hitachi.co.jp.']}} %*An ultra small individual recognition security chip %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=977757 %f/micro/98hyffl6vdgehysraqnrbgiilzwtknm5.pdf %m7fac8176b78aff05d7e76c98072d3c6e %cmicro %@[{'name': 'S. Sarma', 'affiliation': 'Massachusetts Inst. of Technol., MA, USA', 'bio': {'p': ['Sanjay Sarma is an associate professor of mechanical engineering at the Massachusetts Institute of Technology and research director of the Auto-ID Center. His research interests include RFID, IC manufacturing, control, automation, and computational geometry. Sarma has a BTech from the Indian Institute of Technology, Kanpur, India, an MS from Carnegie Mellon University, and a PhD in from the University of California, Berkeley, all in mechanical engineering.']}}, {'name': 'D. Brock', 'bio': {'p': ["David Brock is the director of the Languages Research Group at the Auto-ID Center. His research interests include distributed-systems control, Internet control, large-system simulation, robotics, and artificial intelligence. Brock has a bachelor's degree in theoretical mathematics and mechanical engineering, a master's degree in mechanical engineering, and a PhD in mechanical engineering from MIT."]}}, {'name': 'D. Engels', 'bio': {'p': ['Daniel Engels is a program manager at the Auto-ID Center. His research interests include scheduling theory and applications, real-time system design, distributed and mobile computing, and computer-aided design for embedded systems. Engels has a BS from the University at Buffalo, an MS from the University of California, Berkeley, and a PhD from MIT, all his degrees are in electrical engineering and computer science. He is a member of the IEEE.']}} %*Radio frequency identification and the electronic product code %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=977758 %f/micro/o50yzetyshvdjnifk214wx3bgusxpllc.pdf %m72aa69cc81c63043d5f20f70b3376599 %cmicro %@[{'name': 'R.B. Lee', 'affiliation': 'Dept. of Electr. Eng., Princeton Univ., NJ, USA', 'bio': {'p': ['Ruby B. Lee is the Forrest G. Hamrick Professor in Engineering and professor of electrical engineering at Princeton University. She is also the director of the Princeton Architecture Lab for Multimedia and Security (PALMS). Her research interests include designing security and multimedia features into core processor and platform architectures for pervasive security and ubiquitous multimedia information processing. Lee has an AB from Cornell University, and an MS in computer science and computer engineering, and a PhD in electrical engineering from Stanford University. She is a senior member of the IEEE, and a member of ACM, SPIE, Phi Beta Kappa, and Alpha Lambda Delta. She holds 88 US and international patents.']}}, {'name': ' Zhijie Shi', 'bio': {'p': ['Zhijie Shi is a PhD student at Princeton University. His research interests include computer architecture for fast cryptography and multimedia. Shi has a MS in computer science from Tsinghua University and an MA in electrical engineering from Princeton University.']}}, {'name': ' Xiiao Yang', 'bio': {'p': ['Xiao Yang is a PhD student at Princeton Universi-ty. His research interests include highperformance architecture for multimedia, especially 3D graphics. Yang has an MS in physics from Northwestern University.']}} %*Efficient permutation instructions for fast software cryptography %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=977759 %f/micro/cizgldmitpzsyqkqlebjhw9n5kah4r20.pdf %mc056d4986bfcf56b2dcecf06c31bb78f %cmicro %@[{'name': 'S. Greenstein'} %*E-business infrastructure %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=977760 %f/micro/albq7jae1gvntxh59dhzjwqptnlrgc4f.pdf %m5f4613905bf0527dd7669b609e9bae09 %cmicro %@[{'name': 'R. Stern'} %*Is mousetrapping unfair? %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=977761 %f/micro/ebcarbzwc37rvw5aftqosn8nx4md16kl.pdf %mda09c7bcba3ce26883d925b7fe362860 %cmicro %@[{'name': 'A. Varma', 'affiliation': 'University of California'}, {'name': 'M. Laubach'} %*Solving interconnection problems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=820047 %f/micro/xbrul5ie2sfvwbd1y9an6eogomljq8is.pdf %m56617b20ec3972550956ca5b460dab0f %cmicro %@[{'name': 'C.D. Cranor', 'affiliation': 'AT&T Labs. Res., Florham Park, NJ, USA'}, {'name': 'R. Gopalakrishnan'}, {'name': 'P.Z. Onufryk'} %*Architectural considerations for CPU and network interface integration %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=820048 %f/micro/0q8nqlwyupncjf4t3e9kzi6mf25kvabr.pdf %m106e608f29964bf685bb594e5d695928 %cmicro %@[{'name': ' Tzi-cker Chiueh', 'affiliation': 'State Univ. of New York, Stony Brook, NY, USA'}, {'name': 'P. Pradham'} %*Cache memory design for Internet processors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=820050 %f/micro/bmab1p5hdgx2jdkoa9t3kiovswcsm6xl.pdf %mdb7ddb50d92392192e3c23e324b4be7d %cmicro %@[{'name': 'P. Gupta', 'affiliation': 'Stanford Univ., CA, USA'}, {'name': 'N. McKeown'} %*Classifying packets with hierarchical intelligent cuttings %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=820051 %f/micro/bdwy91ogjhfcauwjphcz0f84nxttigxz.pdf %m0bbb20e42a800a6d92ff007e8a33d040 %cmicro %@[{'name': 'L.L. Zhang', 'affiliation': 'QoS Express Inc., Toronto, Ont., Canada'}, {'name': 'B. Beacham'}, {'name': 'M.R. Hashemi'}, {'name': 'P. Chow'}, {'name': 'A. Leon-Garcia'} %*A scheduler ASIC for a programmable packet switch %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=820052 %f/micro/lnfefizhiueybgtwvgt96jdowbp8yans.pdf %mda3b41acfb1fa07d470a44c3c0aecc44 %cmicro %@[{'name': 'B.C. Reed', 'affiliation': 'IBM Almaden Res. Center, San Jose, CA, USA'}, {'name': 'E.G. Chron'}, {'name': 'R.C. Burns'}, {'name': 'D.D.E. Long'} %*Authenticating network attached storage %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=820053 %f/micro/lhgtorarwkp0i4vebvpj8y5mfkotcjwn.pdf %m55b68c12667357117b913a5ed8d26e2e %cmicro %@[{'name': 'D. Steinberg', 'affiliation': 'Technion-Israel Inst. of Technol., Haifa, Israel'}, {'name': 'Y. Birk'} %*An empirical analysis of the IEEE-1394 serial bus protocol %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=820054 %f/micro/ciopqph4tya1bf8vbt97rvdjs3hc2zax.pdf %mcd0f9751baa4f840f1f85384bb241711 %cmicro %@[{'name': 'S. Greenstein'} %*A revolution? how do you know? %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=848467 %f/micro/fp3auqbtweg7woy9uy8lkfdobhx5hcpz.pdf %mf1bba4236eb63200a07387593197c1b5 %cmicro %@[{'name': 'M. Lam', 'affiliation': 'Stanford University'}, {'name': 'F. Baskett'} %*Cutting-edge designs %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=848468 %f/micro/42sseqicjw5urn6pknxmkp0qarbfhyfl.pdf %m63d7d50714a03c3104a3af2528e52434 %cmicro %@[{'name': 'H. Samueli', 'affiliation': 'Broadcom Corp., Sunnyvale, CA, USA'} %*The broadband revolution %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=848469 %f/micro/xpupqesindv7kmo64isbahylrg19jra2.pdf %mb26d153cb72855674c25071602e2c09d %cmicro %@[{'name': 'E.H. Frank', 'affiliation': 'Braodcom Corp., Sunnyvale, CA, USA'}, {'name': 'J. Holloway'} %*Connecting the home with a phone line network chip set %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=848470 %f/micro/joh67gt18meinygrtzofjpfrqpnzkubc.pdf %m242f382aae77d5f8c7b65230151c9502 %cmicro %@[{'name': 'A. Kunimatsu', 'affiliation': 'Toshiba Corp., Japan'}, {'name': 'N. Ide'}, {'name': 'T. Sato'}, {'name': 'Y. Endo'}, {'name': 'H. Murakami'}, {'name': 'T. Kamei'}, {'name': 'M. Hirano'}, {'name': 'F. Ishihara'}, {'name': 'H. Tago'}, {'name': 'M. Oka'}, {'name': 'A. Ohba'}, {'name': 'T. Yutaka'}, {'name': 'T. Okada'}, {'name': 'M. Suzuoki'} %*Vector unit architecture for emotion synthesis %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=848471 %f/micro/oa3bjzsvdifr1uvxtqesywzd72pgbtrh.pdf %me7c00d120c5a3c3c2503120722772afb %cmicro %@[{'name': 'C. Basoglu', 'affiliation': 'Equator Technol. Inc., Seattle, WA, USA'}, {'name': ' Woobin Lee'}, {'name': "J.S. O'Donnell"} %*The MAP1000A VLIM mediaprocessor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=848472 %f/micro/fsz2qvkctw0brxwlmybogfuj3mnlzaej.pdf %mb45d371d8ac49f4759c9684c49d5eaff %cmicro %@[{'name': 'R.E. Gonzalez', 'affiliation': 'Tensilica Inc., Santa Clara, CA, USA'} %*Xtensa: a configurable and extensible processor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=848473 %f/micro/zipf5avdxqltf8phdy3mmkjqu0nh2nws.pdf %m698378679ef7e3f741919ebee7b62d74 %cmicro %@[{'name': 'L. Hammond', 'affiliation': 'Stanford Univ., CA, USA'}, {'name': 'B.A. Hubbert'}, {'name': 'M. Siu'}, {'name': 'M.K. Prabhu'}, {'name': 'M. Chen'}, {'name': 'K. Olukolun'} %*The Stanford Hydra CMP %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=848474 %f/micro/q9hexsrynga5bmmobjhnizicxd0sdycz.pdf %m335f75f4d8e8400d1999cdd84f183fec %cmicro %@[{'name': 'K. Diefendorff'}, {'name': 'P.K. Dubey'}, {'name': 'R. Hochsprung'}, {'name': 'H. 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Hyde', 'affiliation': 'Bucknell Univ., Lewisburg, PA, USA'} %*Teaching design in a computer architecture course %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=846306 %f/micro/vyttsk97cudbj8rrwwqm4mi5vzo0s6ge.pdf %m5a0dbc8cc96c00cbbb765a54d6abaabf %cmicro %@[{'name': 'J.O. Hamblen', 'affiliation': 'Georgia Inst. of Technol., Atlanta, GA, USA'} %*Rapid prototyping using field-programmable logic devices %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=846307 %f/micro/e09qfnavbp4kr3qinbkdutiwdoyyhv8j.pdf %mb7964ab3524088aa83fb59ed059b8ed7 %cmicro %@[{'name': 'N.H. Kapadia', 'affiliation': 'Purdue Univ., West Lafayette, IN, USA'}, {'name': 'R.J. Figueiredo'}, {'name': 'J.A.B. Fortes'} %*Punch: web portal for running tools %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=846308 %f/micro/mobmr1vs8c0oczglk2jgaxb4ykqitaps.pdf %mf3ae0c528508006039be6b2eeedee574 %cmicro %@[{'name': 'A.K. Uht', 'affiliation': 'Rhode Island Univ., Kingston, RI, USA'}, {'name': ' Jien-Chung Lo'}, {'name': ' Ying Sun'}, {'name': 'J.G. Daly'}, {'name': 'J. Kowalski'} %*Building real computer systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=846309 %f/micro/tgr4hqjpckb1mhgnelv2xbj93c8wyzi7.pdf %mc42313a9adc62a5cf427b3e07ac1cf25 %cmicro %@[{'name': 'R.N. Ibbett', 'affiliation': 'Edinburgh Univ., UK'} %*HASE DLX simulation model %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=846310 %f/micro/krgsvqrldnyt9dqka8hsfvzmup6be4ix.pdf %m5e85cb8e23f2c0c6438cf16d6446638a %cmicro %@[{'name': 'J. Djordjevic', 'affiliation': 'Univ. of Belgrade, Yugoslavia'}, {'name': 'A. Milenkovic'}, {'name': 'N. Grbanovic'} %*An integrated environment for teaching computer architecture %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=846311 %f/micro/c3mfpbtmwlg9vhkkuzcle7wivsiz4ya1.pdf %m7754db450f5fc64fe63baf66d7564be3 %cmicro %@[{'name': ' Arvind', 'affiliation': 'Lab. for Comput. Sci., MIT, USA'}, {'name': 'A.T. Dahbura'}, {'name': 'A. Caro'} %*From Monsoon to StarT-Voyager-university-industry collaboration in research %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=846312 %f/micro/jesajgn2il56xcbymezphtd1urfxw87g.pdf %me8c00fe611df22796d90b6ab124081f8 %cmicro %@[{'name': 'R. Mateosian'} %*Summer cleanup %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=865861 %f/micro/bxi26fj0mtpcfucdsnzvad9kwoewql47.pdf %m826ca7884b886e62cc2bb7d70a2dcecc %cmicro %@[{'name': 'M. Edahiro', 'affiliation': 'NEC Corporation'}, {'name': 'S. Matsushita'}, {'name': 'M. Yamashina'}, {'name': 'N. Nishi'} %*A single-chip multiprocessor for smart terminals %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=865862 %f/micro/xn1duyi3etf0bajgspsmz4bncljwamtr.pdf %m30ecb4cf620a44d3b4a729f8ebe678e1 %cmicro %@[{'name': 'A. Suga', 'affiliation': 'Fujitsu Labs. Ltd., Kawasaki, Japan'}, {'name': 'K. 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Eng., Southern Illinois Univ., Carbondale, IL, USA'}, {'name': 'J. Moore'} %*An interactive fuzzy CAD tool %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=491464 %f/micro/hxbwln4pcwjfnkmgtg57emoefcbqxrua.pdf %mbc2c2a1ccf40e55c1aff59edc30d3179 %cmicro %@[{'name': 'S. Greenstein'} %*Upgrading, catching up, and shooting for par [Micro Economics] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=502398 %f/micro/q2rs9twezguomwranoeack10bgf654xh.pdf %m98d172e73b5ccd9fb1d393c8b0b22c2c %cmicro %@[{'name': 'S. Greenstein', 'affiliation': 'Illinois Univ., Champaign, IL, USA'} %*Upgrading, catching up, and shooting for par [PC market economics] %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=502407 %f/micro/xzdcappis9glvhrljen5q0thu8zix6f7.pdf %m7e73cffac0d58765c932a62f3c4261ad %cmicro %@[{'name': 'R.H. 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Quisquater', 'affiliation': 'Lab. de Microelectron., Katholieke Univ., Leuven, Belgium'} %*SCALPS: Smart card for limited payment systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=502405 %f/micro/j2qtnpxlkkpd7syezrwhtgxlwbc3vuq1.pdf %m314e3285ae506cd1a3356686f1b5ce8f %cmicro %@[{'name': 'S.P. Amarasinghe', 'affiliation': 'Dept. of Electr. Eng., Stanford Univ., CA, USA'}, {'name': 'J.M. Anderson', 'affiliation': 'Dept. of Electr. Eng., Stanford Univ., CA, USA'}, {'name': 'C.S. Wilson', 'affiliation': 'Dept. of Electr. Eng., Stanford Univ., CA, USA'}, {'name': ' Shih-Wei Liao', 'affiliation': 'Dept. of Electr. Eng., Stanford Univ., CA, USA'}, {'name': 'B.R. Murphy', 'affiliation': 'Dept. of Electr. Eng., Stanford Univ., CA, USA'}, {'name': 'R.S. French', 'affiliation': 'Dept. of Electr. Eng., Stanford Univ., CA, USA'}, {'name': 'M.S. Lam', 'affiliation': 'Dept. of Electr. Eng., Stanford Univ., CA, USA'}, {'name': 'M.W. Hall'} %*Multiprocessors from a software perspective %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=502406 %f/micro/9xn7wqlaicqa3rfyteh0thzd5wfbujgj.pdf %m1f0a8378f66cb7f8b0449f1b807a8647 %cmicro %@[{'name': 'S.L. Diamond', 'affiliation': 'Picosoft Inc., San Mateo, CA, USA'} %*IEEE 1394: status and growth path %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=502408 %f/micro/4uzgp3ot2rwg6z97bvb0h5i1fqimkjhu.pdf %m7e80a7bacaa2dbbec011dde06ea45845 %cmicro %@[{'name': 'S. Greenstein', 'affiliation': 'Illinois Univ., Champaign, IL, USA'} %*Debunking the productivity paradox %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=526941 %f/micro/nljhyqkfpig1syfl4gbi5awjcqw9oaun.pdf %md28e44a300091811ade7c2ac637aae4e %cmicro %@[{'name': 'R.H. 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Greenstein', 'affiliation': 'Illinois Univ., Champaign, IL, USA'} %*Don't call it a highway! %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=546572 %f/micro/mfiyns1r4nkuquk2bg96l8wjz5ioqcre.pdf %md8e8de5bd74dea296404ab80b124b917 %cmicro %@[{'name': 'R. Minnich', 'affiliation': 'David Sarnoff Res. Center, Princeton, NJ, USA'}, {'name': 'D. Burns'}, {'name': 'F. Hady'} %*The memory-integrated network interface %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=342013 %f/micro/pqc7knjyvqigh2ft1f5sj4akvpezzg0s.pdf %mcd5d252e09f8c944cfeca9c4a7855292 %cmicro %@[{'name': 'M.A. Blumrich', 'affiliation': 'Princeton Univ., NJ, USA'}, {'name': 'C. Dubnicki', 'affiliation': 'Princeton Univ., NJ, USA'}, {'name': 'E.W. Felten', 'affiliation': 'Princeton Univ., NJ, USA'}, {'name': ' Kai Li', 'affiliation': 'Princeton Univ., NJ, USA'}, {'name': 'M.R. Mesarina', 'affiliation': 'Princeton Univ., NJ, USA'} %*Virtual-memory-mapped network interfaces %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=342014 %f/micro/p1ejgrcdduxiyaowur6tnpvyhnsz4l8w.pdf %mf6d4f45a7825214d692c1682a40c5112 %cmicro %@[{'name': 'N.J. Boden', 'affiliation': 'Myricom Inc., Arcadia, CA, USA'}, {'name': 'D. Cohen', 'affiliation': 'Myricom Inc., Arcadia, CA, USA'}, {'name': 'R.E. Felderman', 'affiliation': 'Myricom Inc., Arcadia, CA, USA'}, {'name': 'A.E. Kulawik', 'affiliation': 'Myricom Inc., Arcadia, CA, USA'}, {'name': 'C.L. Seitz', 'affiliation': 'Myricom Inc., Arcadia, CA, USA'}, {'name': 'J.N. Seizovic', 'affiliation': 'Myricom Inc., Arcadia, CA, USA'}, {'name': ' Wen-King Su', 'affiliation': 'Myricom Inc., Arcadia, CA, USA'} %*Myrinet: a gigabit-per-second local area network %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=342015 %f/micro/um4tdnuxcfyrhcqdgx36sbp5y8eo7jkf.pdf %m8b1b7aaeeee81dfbd5efd6b305d612ce %cmicro %@[{'name': 'R.W. Horst', 'affiliation': 'Tandem Comput. Inc., Cupertino, CA, USA'} %*TNet: a reliable system area network %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=342016 %f/micro/yqlugskakptx5t9zm6gdz0h3fxhpolef.pdf %m8e96e4dd1f935c97539fdcef3fcff5d5 %cmicro %@[{'name': 'T. von Eicken', 'affiliation': 'Cornell Univ., Ithaca, NY, USA'}, {'name': 'A. Basu', 'affiliation': 'Cornell Univ., Ithaca, NY, USA'}, {'name': 'V. Buch', 'affiliation': 'Cornell Univ., Ithaca, NY, USA'} %*Low-latency communication over ATM networks using active messages %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=342017 %f/micro/joia6d2guvktbm5vyqgkswemuhfzrqhr.pdf %ma601ce62935e61658d16d572f0311e8a %cmicro %@[{'name': 'T.E. Anderson', 'affiliation': 'California Univ., Berkeley, CA, USA'}, {'name': 'D.E. Culler', 'affiliation': 'California Univ., Berkeley, CA, USA'}, {'name': 'D. Patterson', 'affiliation': 'California Univ., Berkeley, CA, USA'} %*A case for NOW (Networks of Workstations) %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=342018 %f/micro/bumrqfhvcp8jh4wfxt0m7gcs6153iasa.pdf %m8aa1e15eefae9f4f6a3fa33982ecbf40 %cmicro %@[{'name': 'Y.I. Fet', 'affiliation': 'Acad. of Sci., Novosibirsk, Russia'} %*Vertical processing systems: a survey %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=342019 %f/micro/exwuvz3bd8qgmmnvo6fiwjdi1aslhy0x.pdf %mb7d23e4b96dddf260eb073472466aecd %cmicro %@[{'name': 'J. Circello', 'affiliation': 'Motorola Inc., Phoenix, AZ, USA'}, {'name': 'G. Edgington', 'affiliation': 'Motorola Inc., Phoenix, AZ, USA'}, {'name': 'D. McCarthy', 'affiliation': 'Motorola Inc., Phoenix, AZ, USA'}, {'name': 'J. Gay', 'affiliation': 'Motorola Inc., Phoenix, AZ, USA'}, {'name': 'D. Schimke', 'affiliation': 'Motorola Inc., Phoenix, AZ, USA'}, {'name': 'S. Sullivan', 'affiliation': 'Motorola Inc., Phoenix, AZ, USA'}, {'name': 'R. Duerden', 'affiliation': 'Motorola Inc., Phoenix, AZ, USA'}, {'name': 'C. Hinds', 'affiliation': 'Motorola Inc., Phoenix, AZ, USA'}, {'name': 'D. Marquette', 'affiliation': 'Motorola Inc., Phoenix, AZ, USA'}, {'name': 'L. Sood', 'affiliation': 'Motorola Inc., Phoenix, AZ, USA'}, {'name': 'A. Couch', 'affiliation': 'Motorola Inc., Phoenix, AZ, USA'}, {'name': 'D. Chow', 'affiliation': 'Motorola Inc., Phoenix, AZ, USA'} %*The superscalar architecture of the MC68060 %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=372345 %f/micro/i1xa8evn3ywesg2fsztbroo6hpcb5dk7.pdf %mf0b2ad6d76e3fe0a67efb0a8345d86ec %cmicro %@[{'name': 'R.B. Lee', 'affiliation': 'Hewlett-Packard Co., Cupertino, CA, USA'} %*Accelerating multimedia with enhanced microprocessors %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=372347 %f/micro/wxhfyzksaudiun1bvjdwi38omlrgr7ke.pdf %m3a24e66e84fdee984040917fdacdca13 %cmicro %@[{'name': 'J.H. Edmondson', 'affiliation': 'Digital Equipment Corp., Hudson, MA, USA'}, {'name': 'P. Rubinfeld', 'affiliation': 'Digital Equipment Corp., Hudson, MA, USA'}, {'name': 'R. Preston', 'affiliation': 'Digital Equipment Corp., Hudson, MA, USA'}, {'name': 'V. Rajagopalan'} %*Superscalar instruction execution in the 21164 Alpha microprocessor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=372349 %f/micro/4ognz7scktba5y6qehmdfl10pyei2gav.pdf %m0d75a876fae68c354fe292b5452069a5 %cmicro %@[{'name': 'K. Wang', 'affiliation': 'Somerset Design Center, Austin, TX, USA'}, {'name': 'C. Bryant', 'affiliation': 'Somerset Design Center, Austin, TX, USA'}, {'name': 'M. Carlson', 'affiliation': 'Somerset Design Center, Austin, TX, USA'}, {'name': 'T. Elmer', 'affiliation': 'Somerset Design Center, Austin, TX, USA'}, {'name': 'A. Harris', 'affiliation': 'Somerset Design Center, Austin, TX, USA'}, {'name': 'M. Garcia', 'affiliation': 'Somerset Design Center, Austin, TX, USA'}, {'name': 'C.S. Hui', 'affiliation': 'Somerset Design Center, Austin, TX, USA'}, {'name': 'C.K. Leong', 'affiliation': 'Somerset Design Center, Austin, TX, USA'}, {'name': 'B. Reynolds', 'affiliation': 'Somerset Design Center, Austin, TX, USA'}, {'name': 'R. Tang', 'affiliation': 'Somerset Design Center, Austin, TX, USA'}, {'name': 'L. Weber', 'affiliation': 'Somerset Design Center, Austin, TX, USA'}, {'name': 'J. Wenzel', 'affiliation': 'Somerset Design Center, Austin, TX, USA'}, {'name': 'G. Wilson', 'affiliation': 'Somerset Design Center, Austin, TX, USA'}, {'name': 'M. Becker', 'affiliation': 'Somerset Design Center, Austin, TX, USA'} %*Designing the MPC105 PCI bridge/memory controller %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=372351 %f/micro/3ibmrjftkrxnyz0uswcmfu9t7iq6kblp.pdf %mc3da107ef5fe8f129b9279101e9256df %cmicro %@[{'name': 'J.M. Stone', 'affiliation': 'IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA'}, {'name': 'R.P. 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Goethe Univ., Frankfurt, Germany'} %*The AM/sup 3/ associative processor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=372356 %f/micro/ph6twxzygfm5eur4oi8qjsdnakgcxjkz.pdf %m392973295c31ac61ace7fa8e7058760b %cmicro %@[{'name': 'S.L. Diamond', 'affiliation': 'Picosoft Inc., San Mateo, CA, USA'} %*Micro standards: IEEE std P1394 %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=372359 %f/micro/attueop6g1ffev0zhxyilc48krn3ywcm.pdf %mc673af5796a995461df2cc54fa6a3ba2 %cmicro %@[{'name': 'D. Price'} %*Pentium FDIV flaw-lessons learned %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=372360 %f/micro/lj4ap6tlbrexqsfxzqytwd5igvpwyrbu.pdf %m29a75d8a0e9fada4bd254dad1f801cb8 %cmicro %@[{'name': 'R.H. Stern', 'affiliation': '2000 M St., N.W. Suite 700, Washington, DC, USA'} %*Fuzziness versus all or nothing %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=387674 %f/micro/svv5rcbdpnz86a049dbwgaxtsoxjkumq.pdf %m25fa6cc3e340eee8d8620dd4ad7d787e %cmicro %@[{'name': 'S. Greenstein', 'affiliation': 'Illinois Univ., Champaign, IL, USA'} %*The market and computer technology %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=387675 %f/micro/y0p9o1ji6rkgm4sundhkaiugqtxvbfmx.pdf %m20bd9347c4a5890ca4892fbea05919a7 %cmicro %@[{'name': 'H. Eichfeld', 'affiliation': 'Siemens AG, Munich, Germany'}, {'name': 'M. Klimke', 'affiliation': 'Siemens AG, Munich, Germany'}, {'name': 'M. Menke', 'affiliation': 'Siemens AG, Munich, Germany'}, {'name': 'J. Nolles', 'affiliation': 'Siemens AG, Munich, Germany'}, {'name': 'T. Kunemund', 'affiliation': 'Siemens AG, Munich, Germany'} %*A general-purpose fuzzy inference processor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=387677 %f/micro/usdqia5ngrswzv0tr9fe7lbxj3odtbl1.pdf %mac39be2eeb848cefea9790fcbb8d1389 %cmicro %@[{'name': 'R. Coggins', 'affiliation': 'Syst. Eng. & Design Autom. Lab., Sydney Univ., NSW, Australia'}, {'name': 'M. Jabri', 'affiliation': 'Syst. Eng. & Design Autom. Lab., Sydney Univ., NSW, Australia'}, {'name': 'B. Flower', 'affiliation': 'Syst. Eng. & Design Autom. Lab., Sydney Univ., NSW, Australia'}, {'name': 'S. Pickard', 'affiliation': 'Syst. Eng. & Design Autom. Lab., Sydney Univ., NSW, Australia'} %*A low-power network for on-line diagnosis of heart patients %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=387678 %f/micro/vcawuifcqn7g3dftkops0nmqu18rem4h.pdf %m7cf90168b4e7440d1c36b6ec8c21ee35 %cmicro %@[{'name': 'A. Konig', 'affiliation': 'Inst. for Microelectron. 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Ruckert'} %*Neural networks-extraordinary variation %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=387685 %f/micro/1x43owpujsx0ryjklqc2b8hykl6nteff.pdf %m4d8ea09f0a3642c258b816755916d657 %cmicro %@[{'name': 'A. Louri', 'affiliation': 'Opt. Comput. & Parallel Process. Lab., Arizona Univ., Tucson, AZ, USA'}, {'name': 'J.A. Hatch', 'affiliation': 'Opt. Comput. & Parallel Process. Lab., Arizona Univ., Tucson, AZ, USA'}, {'name': ' Jongwhoa Na', 'affiliation': 'Opt. Comput. & Parallel Process. Lab., Arizona Univ., Tucson, AZ, USA'} %*A constant-time parallel sorting algorithm and its optical implementation %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=387690 %f/micro/jtsg8sv2fwoqlyzke7dknpeafr5wcgir.pdf %m498d630da6cc86cdbf17b1bff575efec %cmicro %@[{'name': 'R.H. Stern', 'affiliation': '2000 M St., N.W. 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Ward'} %*2D silicon/ferroelectric liquid crystal spatial light modulators %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=400643 %f/micro/x6iazjrtpmcliur9on3sghxjfz1ouawe.pdf %mdfd59f815c2c558b572f61a4a9ac4a12 %cmicro %@[{'name': 'V.K. Madisetti', 'affiliation': 'Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA'}, {'name': 'T.W. Egolf', 'affiliation': 'Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA'} %*Virtual prototyping of embedded microcontroller-based DSP systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=464577 %f/micro/7whgzbuwe3aldrpdl2gq6skyrttcxu0v.pdf %me84023271b2a919b4022aa88d2699b11 %cmicro %@[{'name': 'S. Segars', 'affiliation': 'Adv. RISC Machines, Cambridge, UK'}, {'name': 'K. Clarke', 'affiliation': 'Adv. RISC Machines, Cambridge, UK'}, {'name': 'L. Goudge', 'affiliation': 'Adv. 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Avnon', 'affiliation': 'Intel Corp., Santa Clara, CA, USA'} %*Architecture of the Pentium microprocessor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=216745 %f/micro/lwvq8sao2kmbtnm6nxfcduqhz3iukvy0.pdf %me297a250dc467e89e92eb2d67a2c38bb %cmicro %@[{'name': 'T. Asprey', 'affiliation': 'Hewlett-Packard, Fort Collins, CO, USA'}, {'name': 'G.S. Averill', 'affiliation': 'Hewlett-Packard, Fort Collins, CO, USA'}, {'name': 'E. DeLano', 'affiliation': 'Hewlett-Packard, Fort Collins, CO, USA'}, {'name': 'R. Mason', 'affiliation': 'Hewlett-Packard, Fort Collins, CO, USA'}, {'name': 'B. Weiner', 'affiliation': 'Hewlett-Packard, Fort Collins, CO, USA'}, {'name': 'J. Yetter', 'affiliation': 'Hewlett-Packard, Fort Collins, CO, USA'} %*Performance features of the PA7100 microprocessor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=216746 %f/micro/wc5g4jxlbcmoeuszb9ke6utipraipoj7.pdf %m6d34377bdfcf87ba1da828192c5ff465 %cmicro %@[{'name': 'E. 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Narita', 'affiliation': 'Hitachi Ltd., Tokyo, Japan'}, {'name': 'H. Aoki', 'affiliation': 'Hitachi Ltd., Tokyo, Japan'}, {'name': 'I. Kawasaki', 'affiliation': 'Hitachi Ltd., Tokyo, Japan'}, {'name': 'S. Matsui', 'affiliation': 'Hitachi Ltd., Tokyo, Japan'}, {'name': 'M. Yamamoto', 'affiliation': 'Hitachi Ltd., Tokyo, Japan'}, {'name': 'N. Nakagawa', 'affiliation': 'Hitachi Ltd., Tokyo, Japan'}, {'name': 'I. Kudo', 'affiliation': 'Hitachi Ltd., Tokyo, Japan'} %*The Gmicro/500 superscalar microprocessor with branch buffers %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=237998 %f/micro/sbfsyhcolp5yaxet7kuovjdgni28cwrt.pdf %md43f6c830f164e355ed1b4beed5501c2 %cmicro %@[{'name': 'M. Awaga', 'affiliation': 'Fujitsu Ltd., Kawasaki, Japan'}, {'name': 'H. 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(software industry) %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=238005 %f/micro/ichvn3owxasgkllebo085e9q4tavzrbt.pdf %m20e64a6a03525437a30377f85fed6bb1 %cmicro %@[{'name': 'C. Halliwell'} %*Camp development: the art of building a market through standards %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=248047 %f/micro/fsyi6rrcgaqljiu9wgemkudtclv48htb.pdf %ma44d35f9b0067804aee26e7ee5e2e28c %cmicro %@[{'name': 'G.G. Davis', 'affiliation': 'Davis & Schroeder, Monterey, CA, USA'} %*War of the words: intellectual property laws and standardization %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=248049 %f/micro/unv3fye8yiarh1uznxwkb5dvqj9phcar.pdf %m31a00bebc763172cbbfbce1e59bb807f %cmicro %@[{'name': 'D.L. Garcia', 'affiliation': 'US Office of Technol. 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Asakura', 'affiliation': 'Mitsubishi Electr. Corp., Itami, Japan'}, {'name': 'K. Fujishima', 'affiliation': 'Mitsubishi Electr. Corp., Itami, Japan'} %*The cache DRAM architecture: a DRAM with an on-chip cache memory %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=52944 %f/micro/lf4myubzprtj58ongyaxjeqvuvn6c1be.pdf %m5273cd9006de729d577e077626bbe083 %cmicro %@[{'name': 'K. Kaneko', 'affiliation': 'Matsushita Electr. Ind. Co. Ltd., Osaka, Japan'}, {'name': 'M. Nakajima', 'affiliation': 'Matsushita Electr. Ind. Co. Ltd., Osaka, Japan'}, {'name': 'Y. Kakakura', 'affiliation': 'Matsushita Electr. Ind. Co. Ltd., Osaka, Japan'}, {'name': 'J. Nishikawa', 'affiliation': 'Matsushita Electr. Ind. Co. Ltd., Osaka, Japan'}, {'name': 'I. Okabayashi', 'affiliation': 'Matsushita Electr. Ind. Co. Ltd., Osaka, Japan'}, {'name': 'H. Kadota', 'affiliation': 'Matsushita Electr. Ind. Co. Ltd., Osaka, Japan'} %*Processing element design for a parallel computer %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=52945 %f/micro/ct9wvurfu6saxkbviznky8brpnqsjyeq.pdf %ma18f99c63905aadf000529cd28258965 %cmicro %@[{'name': 'Y. Hatano', 'affiliation': 'Hitachi Ltd., Tokyo, Japan'}, {'name': 'S. Yano', 'affiliation': 'Hitachi Ltd., Tokyo, Japan'}, {'name': 'H. Mori', 'affiliation': 'Hitachi Ltd., Tokyo, Japan'}, {'name': 'H. Yamada', 'affiliation': 'Hitachi Ltd., Tokyo, Japan'}, {'name': 'M. Hirano', 'affiliation': 'Hitachi Ltd., Tokyo, Japan'}, {'name': 'U. Kawabe', 'affiliation': 'Hitachi Ltd., Tokyo, Japan'} %*A 4-bit, 250-MIPS processor using Josephson technology %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=52946 %f/micro/jro0yjbhbc4ivhnlxnfzxtg2mqk9mryc.pdf %mda136df6d96c3c530382fbe5b6eb820a %cmicro %@[{'name': 'H. Kaneko', 'affiliation': 'NEC Corp., Kanagawa, Japan'}, {'name': 'N. Suzuki', 'affiliation': 'NEC Corp., Kanagawa, Japan'}, {'name': 'H. Wabuka', 'affiliation': 'NEC Corp., Kanagawa, Japan'}, {'name': 'K. Maemura'} %*Realizing the V80 and its system support functions %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=52947 %f/micro/162sgypbvghk4shqrfqocclumxu39dlt.pdf %mcb78681e270b44bd32b4bcb2d37dee27 %cmicro %@[{'name': 'M. Milenkovic', 'affiliation': 'IBM Corp., Boca Raton, FL, USA'} %*Microprocessor memory management units %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=52948 %f/micro/gauhpz6v8ub34zd9cbheqttpexwo0ij5.pdf %m7ec6d2cb219f5691e443bed72a62f440 %cmicro %@[{'name': 'D.V. James'} %*Multiplexed buses: the endian wars continue %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=56322 %f/micro/vc5djuk7t2rixmapgeqxmsknzvfbo46n.pdf %m6373ef5d4d47a7f48e55aca18123f62a %cmicro %@[{'name': 'R.W. Edenfield', 'affiliation': 'Motorola Inc., Austin, TX, USA'}, {'name': 'M.G. Gallup', 'affiliation': 'Motorola Inc., Austin, TX, USA'}, {'name': 'W.B. Ledbetter', 'affiliation': 'Motorola Inc., Austin, TX, USA'}, {'name': 'R.C. McGarity', 'affiliation': 'Motorola Inc., Austin, TX, USA'}, {'name': 'E.E. Quintana', 'affiliation': 'Motorola Inc., Austin, TX, USA'}, {'name': 'R.A. Reininger', 'affiliation': 'Motorola Inc., Austin, TX, USA'} %*The 68040 processor. 2. Memory design and chip %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=56323 %f/micro/sa14pvnw3golbpiexvfcumtjsq5q90lr.pdf %m195c9e1c6299e98d5a1028a2a07ee053 %cmicro %@[{'name': 'M. Darley', 'affiliation': 'Texas Instrum. Inc., Dallas, TX, USA'}, {'name': 'B. Kronlage', 'affiliation': 'Texas Instrum. Inc., Dallas, TX, USA'}, {'name': 'D. Bural', 'affiliation': 'Texas Instrum. Inc., Dallas, TX, USA'}, {'name': 'B. Churchill', 'affiliation': 'Texas Instrum. Inc., Dallas, TX, USA'}, {'name': 'D. Pulling', 'affiliation': 'Texas Instrum. Inc., Dallas, TX, USA'}, {'name': 'P. Wang', 'affiliation': 'Texas Instrum. Inc., Dallas, TX, USA'}, {'name': 'R. Iwamoto'}, {'name': 'L. Yang'} %*The TMS390C602A floating-point coprocessor for Sparc systems %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=56324 %f/micro/twogulfajg79txypdasqzeb5hq83dcpb.pdf %m0924408d79f86e8e82b9d110c600c2ad %cmicro %@[{'name': 'M. Alsup', 'affiliation': 'Motorola Inc., Austin, TX, USA'} %*Motorola's 88000 family architecture %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=56325 %f/micro/lkomyhq5cxzaq9fnbnvxjhdw6vyr8uw0.pdf %m3c9277ef38fc6304a827f420604017d4 %cmicro %@[{'name': 'T. Kitahara', 'affiliation': 'Fujitsu Ltd., Kawasaki, Japan'}, {'name': 'T. Satoh', 'affiliation': 'Fujitsu Ltd., Kawasaki, Japan'} %*The Gmicro/300 32-bit microprocessor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=56326 %f/micro/lhdf1pmmhi5snajpx4obk83yqsouyzdc.pdf %m3ce983e9cdd110a08074873ce0be36d1 %cmicro %@[{'name': 'R.D. Chamberlain', 'affiliation': 'Washington Univ., St. Louis, MO, USA'}, {'name': 'M.A. Franklin', 'affiliation': 'Washington Univ., St. Louis, MO, USA'} %*Hierarchical discrete-event simulation on hypercube architectures %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=57727 %f/micro/hnitsqkyv5bwmdotlfrsxdbx3egpwzjg.pdf %mb1d95b71909679e10d08aaa0d7bbd155 %cmicro %@[{'name': 'F.N. Sibai', 'affiliation': 'Dept. of Electr. Eng., Akron Univ., OH, USA'}, {'name': 'K.L. Watson'}, {'name': 'M. Lu'} %*A parallel unification machine %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=57728 %f/micro/rk4urqunafnixgojphzd35vwteybeql9.pdf %mf0afff1c1a47d2a25acf8b427e54f859 %cmicro %@[{'name': 'M. Rumsey', 'affiliation': 'Texas Instrum. Ltd., Bedford, UK'}, {'name': 'J. Sackett', 'affiliation': 'Texas Instrum. Ltd., Bedford, UK'} %*An ASIC methodology for mixed analog-digital simulation %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=57729 %f/micro/t4zldjbbkiwsogynmo072prjpiuchxma.pdf %mde2216b39d58d373af4017cddec1e5a2 %cmicro %@[{'name': 'A.J. van der Hoeven', 'affiliation': 'Delft Univ. of Technol., Netherlands'}, {'name': 'A.A.J. de Lange', 'affiliation': 'Delft Univ. of Technol., Netherlands'}, {'name': 'E.F. Deprettere', 'affiliation': 'Delft Univ. of Technol., Netherlands'}, {'name': 'P.M. Dewilde', 'affiliation': 'Delft Univ. of Technol., Netherlands'} %*A model for the high-level description and simulation of VLSI networks %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=57730 %f/micro/fwjmuhfbnktoaiys6l0ehlrxrdqativy.pdf %me4f047714faac725ff4be7322fe0bd48 %cmicro %@[{'name': 'K.H. Lee', 'affiliation': 'Chinese Univ. of Hong Kong, Hong Kong'}, {'name': 'K.S. Leung', 'affiliation': 'Chinese Univ. of Hong Kong, Hong Kong'}, {'name': 'S.M. Cheang', 'affiliation': 'Chinese Univ. of Hong Kong, Hong Kong'} %*A microprogrammable list processor for personal computers %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=57731 %f/micro/gkwecaw3xl7dp0yiahbsedlpthbjmr1f.pdf %m2844121c5cba710bb011eeac26efda37 %cmicro %@[{'name': 'Y.A. El-Imam', 'affiliation': 'IBM Kuwait Sci. Center, Safat, Kuwait'}, {'name': 'K. Banat'} %*Text-to-speech conversion on a personal computer %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=57732 %f/micro/edglqvmydybs067hvbmxqisogafufrt5.pdf %mce351977c875f9b21585358755bf32b7 %cmicro %@[{'name': 'D.K. Kahaner', 'affiliation': 'US Office of Naval Res. Far East, Tokyo, Japan'} %*The Pax parallel computer %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=60519 %f/micro/ug3enhwp7rmbbh6zlquflf08y1rcj4g9.pdf %m7ba325eeab32173fd92c91db126a933c %cmicro %@[{'name': 'E.A. Lee', 'affiliation': 'Dept. of Electr. Eng. & Comput. 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Sci., California Univ., Berkeley, CA, USA'}, {'name': 'P.D. Lapsley', 'affiliation': 'Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA'}, {'name': "M.P. O'Reilly", 'affiliation': 'Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA'}, {'name': 'G.C. Sih', 'affiliation': 'Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA'}, {'name': 'E.A. Lee', 'affiliation': 'Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA'} %*Gabriel: a design environment for DSP %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=60524 %f/micro/tuzkudyznbqc0cr2dfsshpmwmqoov8pg.pdf %m03c5fbbf8138126e0be65f95e46582ef %cmicro %@[{'name': 'K.A. Kumar', 'affiliation': 'Intermetrics Inc., Bethesda, MD, USA'}, {'name': 'B. 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Roncarolo', 'affiliation': 'Elsag SpA, Italy'} %*EMMA2: a high-performance hierarchical multiprocessor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=16793 %f/micro/j2titwg5oczgd0ekznvcu1pfkw38vmhb.pdf %m1ce91ce8c5bb3ad5457f5e3c441e8dc9 %cmicro %@[{'name': 'B. Lazzerini', 'affiliation': 'Fac. of Eng., Pisa Univ., Italy'} %*Effective VLSI processor architectures for HLL computers: the RISC approach %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=16794 %f/micro/3yz61unqqv0oc9krabyelxgwsukmedao.pdf %mf523caf54e54158a3bee2e7a17350342 %cmicro %@[{'name': 'M. Kabuka', 'affiliation': 'Dept. of Electr. & Comput. Eng., Miami Univ., Coral Gables, FL, USA'}, {'name': 'R. Escoto', 'affiliation': 'Dept. of Electr. & Comput. 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Thompson', 'affiliation': 'AT&T Bell Lab., Holmdel, NJ, USA'} %*The AT&T WE32200 design challenge %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=24847 %f/micro/ezclxfbmq50ugiuqdyerkntwsvicd6kv.pdf %m1197d0d0bb82581458a0bfdf859fa6a5 %cmicro %@[{'name': 'C. Melear', 'affiliation': 'Motorola Inc., Austin, TX, USA'} %*The design of the 88000 RISC family %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=24848 %f/micro/7yoaeozz51dmc2jxnbliw0yhukhpfx6i.pdf %m895c65bfa55eed2ab09fd5a15b2fad76 %cmicro %@[{'name': 'I. Dancea', 'affiliation': 'Dept. of Comput. Sci., Quebec Univ., Hull, Que., Canada'} %*Dynamically changing the logical behavior of the microcomputer interface %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=24849 %f/micro/ymr2qb1dvotrssqfwy5ha4u9ex0bwaum.pdf %mdda446e4cd6fb3f4b3cafa158ceae624 %cmicro %@[{'name': 'M.P. Papazoglou', 'affiliation': 'Int. fuer Syst., German Res. Center for Comput. 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Terada'} %*The data-driven microprocessor %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=31477 %f/micro/bawyse2zgvgkhp35pn4hutladvofcnrt.pdf %m7189f8ff4593bd973d484892f9fd6200 %cmicro %@[{'name': 'J.-D. Nicoud', 'affiliation': 'Lab. de Microinformatique, Ecole Polytech. Federal de Lausanne, Switzerland'}, {'name': 'A.M. Tyrrell', 'affiliation': 'Lab. de Microinformatique, Ecole Polytech. Federal de Lausanne, Switzerland'} %*The transputer T414 instruction set %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=31478 %f/micro/nss5fmgwzoiatbkevd3phuhl1ewnyp2j.pdf %m6cdf043d81b26b1cdc59957f393e98e0 %cmicro %@[{'name': 'M. Mehdi Owrang O', 'affiliation': 'Dept. of Comput. Sci. & Inf. Syst., American Univ., Washington, DC, USA'}, {'name': 'W.G. Gunaratna', 'affiliation': 'Dept. of Comput. Sci. & Inf. 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Kumar', 'affiliation': 'Indian Inst. of Sci., Bangalore, India'}, {'name': 'L.M. Patnaik', 'affiliation': 'Indian Inst. of Sci., Bangalore, India'} %*An efficient scheme for interprocessor communication using dual-ported RAMs %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=45822 %f/micro/kuyfdqhtc7ojcdnp9rm1rwx3j8sokiye.pdf %md8e8439186ae4f207b43ed6224ede9d7 %cmicro %@[{'name': 'T. Le-Ngoc', 'affiliation': 'Concordia Univ., Montreal, Que., Canada'}, {'name': 'M.T. Vo', 'affiliation': 'Concordia Univ., Montreal, Que., Canada'} %*Implementation and performance of the fast Hartley transform %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=45824 %f/micro/8pfkpegvnjblgyszqdv5rosi6b327adm.pdf %m82f800a27dff67a65f4fbb3fd7b023f1 %cmicro %@[{'name': 'W.J. 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Siewiorek'} %*The Micon system for computer design %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=45823 %f/micro/ogkx6bjduzlrmyt5dywwzke7pncougs3.pdf %mbaca3575f7612a1dc4c6ad8e2a821165 %cmicro %@[{'name': 'M. Walker', 'affiliation': 'Arizona State Univ., Tempe, AZ, USA'}, {'name': 'P. Hasler', 'affiliation': 'Arizona State Univ., Tempe, AZ, USA'}, {'name': 'L. Akers', 'affiliation': 'Arizona State Univ., Tempe, AZ, USA'} %*A CMOS neural network for pattern association %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=45828 %f/micro/1clxmkhi0suajvj2berhplda5ge9gnnq.pdf %mf39c60341d960d4977f789b6d36b5678 %cmicro %@[{'name': 'P. Treleaven', 'affiliation': 'Dept. of Comput. Sci., Univ. Coll. London, UK'}, {'name': 'M. Pacheco', 'affiliation': 'Dept. of Comput. Sci., Univ. Coll. London, UK'}, {'name': 'M. Vellasco', 'affiliation': 'Dept. of Comput. Sci., Univ. Coll. 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Lab., Catholic Univ. of Louvain, Belgium'} %*An analog VLSI implementation of Hopfield's neural network %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=42986 %f/micro/nk3r4a8fvm6pgwntr2qz0s7xcobdcdym.pdf %mf31f33f812c1a6ac6ce9751befd1b154 %cmicro %@[{'name': 'O. Rossetto', 'affiliation': 'Nat. Polytech. Inst. of Grenoble, France'}, {'name': 'C. Jutten', 'affiliation': 'Nat. Polytech. Inst. of Grenoble, France'}, {'name': 'J. Herault', 'affiliation': 'Nat. Polytech. Inst. of Grenoble, France'}, {'name': 'I. Kreuzer'} %*Analog VLSI synaptic matrices as building blocks for neural networks %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=42987 %f/micro/5g27vp014zjalismpmznxqko968wfabq.pdf %m0baa61401b207273aafefe4dffc4358c %cmicro %@[{'name': 'A.F. Murray', 'affiliation': 'Dept. of Electr. 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Sakamura'} %*Realization of Gmicro/200 %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=526 %f/micro/q0wlopweztfsmld3gb7pv8xbvfoi5tnh.pdf %m040bf7e15cfba7b29b8e79b7658c348d %cmicro %@[{'name': 'S. Kimura', 'affiliation': 'NEC Corp., Kawasaki, Japan'}, {'name': 'Y. Komoto', 'affiliation': 'NEC Corp., Kawasaki, Japan'}, {'name': 'Y. Yano', 'affiliation': 'NEC Corp., Kawasaki, Japan'} %*Implementation of the V60/V70 and its FRM function %uhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=527 %f/micro/y1bufhj7abvskncgvtnzdr3268ipejms.pdf %mc8c1eba487926b6de56d07b5e7204472 %cmicro %@[{'name': 'M. Miyata', 'affiliation': 'Toshiba Corp., Saiwaiku, Japan'}, {'name': 'H. Kishigami', 'affiliation': 'Toshiba Corp., Saiwaiku, Japan'}, {'name': 'K. Okamoto', 'affiliation': 'Toshiba Corp., Saiwaiku, Japan'}, {'name': 'S. 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optimizing android smartwatch energy consumption: poster %uhttp://dl.acm.org/ft_gateway.cfm?id=2985259&type=pdf %f/mobicom/bwpwjxokjgh4y3eaqsbomv6ac7mguknd.pdf %ma24f640aeed3a84fcbae8a349ee2a873 %cmobicom %@Liu, Jian, Chen, Yingying, Gruteser, Marc %*Sensing on ubiquitous surfaces via vibration signals: poster %uhttp://dl.acm.org/ft_gateway.cfm?id=2985260&type=pdf %f/mobicom/lchubmzrwqhlz4obusy6sy0w3cdfjiet.pdf %ma1591c70dfcfce315e3980fe1ed28650 %cmobicom %@Liu, Jian, Wang, Chen, Chen, Yingyin %*PIN number-based authentication leveraging physical vibration: poster %uhttp://dl.acm.org/ft_gateway.cfm?id=2985261&type=pdf %f/mobicom/761e3o0ytydsnczstpi9ba4hhvkma2iu.pdf %mb27c14010361c8fb151ab00ca72af35d %cmobicom %@Stone, Theodore, Stone, Nathaniel, Guan, Xiang, Nelakuditi, Srihari, Roy, Nirupam, Melton, Will, Cole, Kayla, Jackson, Benjamin, Kidane, Addi %*Assessing header impacts in soccer with smartball: poster %uhttp://dl.acm.org/ft_gateway.cfm?id=2985262&type=pdf %f/mobicom/syjlotdc239zuuovzyrnbht1wlvx5beq.pdf %m2e3e0fca50f12fa2a3926b331771cf9e %cmobicom %@Kulkarni, Vaibhav, Moro, Arielle, Garbinato, Benoî %*A mobility prediction system leveraging realtime location data streams: poster %uhttp://dl.acm.org/ft_gateway.cfm?id=2985263&type=pdf %f/mobicom/cxhkrp9fk206z3n5vuodmsvoqsya7up1.pdf %m92c9d72656e5cb76432c05d38500387b %cmobicom %@Goel, Utkarsh, Steiner, Moritz, Wittie, Mike P., Flack, Martin, Ludin, Stephe %*HTTP/2 performance in cellular networks: poster %uhttp://dl.acm.org/ft_gateway.cfm?id=2985264&type=pdf %f/mobicom/ibqoltufzvq6pkcfsrut10w4kijamn7x.pdf %me921d9f3b5b5a50cb7dd84cb2d481a99 %cmobicom %@Machen, Andrew, Wang, Shiqiang, Leung, Kin K., Ko, Bong Jun, Salonidis, Theodoro %*Migrating running applications across mobile edge clouds: poster %uhttp://dl.acm.org/ft_gateway.cfm?id=2985265&type=pdf %f/mobicom/keydrljkpzwtgh7onm230cjzqat6pssl.pdf %mbb275a04f12b1aebd2b8dd0f457d4d6e %cmobicom %@Guo, Xiaonan, Liu, Jian, Chen, Yingyin %*Automatic personal fitness assistance through wearable mobile devices: poster %uhttp://dl.acm.org/ft_gateway.cfm?id=2985266&type=pdf %f/mobicom/0rizdasjzhn7qgvam6dbeiox3wgpkpmt.pdf %m19fc2c5ef6864c9a762ed3d0c0d878ae %cmobicom %@Chang, Liqiong, Wang, Xuan, Wang, Ju, Ren, Yuhui, Chen, Xiaojiang, Fang, Dingy %*Low-cost wireless phase calibration that works on COTS RFID systems: poster %uhttp://dl.acm.org/ft_gateway.cfm?id=2985267&type=pdf %f/mobicom/bsoqafzpgy8j0wrd436cihjlf5vniuvx.pdf %me56f192f7cd2ce03b41e9da1f06f3ac6 %cmobicom %@Qi, Bozhao, Banerjee, Suma %*GonioSense: a wearable-based range of motion sensing and measurement system for body joints: poster %uhttp://dl.acm.org/ft_gateway.cfm?id=2985268&type=pdf %f/mobicom/hnceykgc6jyxfbh0utzrl8oqozlvf5mu.pdf %m725f6f5882c7e6c10b4ac3641ccb0ca1 %cmobicom %@Senapathi, Sivaprakash, Foukas, Xenofon, Marina, Mahesh K %*VALI -- an SDN-based management framework for public wireless LANs: poster %uhttp://dl.acm.org/ft_gateway.cfm?id=2985269&type=pdf %f/mobicom/tdufosq8eb1p2ah4vmwyixukdplcgyzs.pdf %m2fd5a6ab279610d5db6f2ea55758ff4f %cmobicom %@Im, Taeyu, De, Pradipt %*An infrastructureless and self-deployable indoor navigation approach using semantic signatures: poster %uhttp://dl.acm.org/ft_gateway.cfm?id=2985270&type=pdf %f/mobicom/egsa2ckezn49brnfjojswiv7ymgz6ath.pdf %mbd5f985027015f72768acb82a94b8a3d %cmobicom %@Xia, Xianjin, Li, Shining, Zhang, Yu, Li, Lin, Wei, Mingfei, Qin, We %*ToneSense: communication across technologies through power-channel: poster %uhttp://dl.acm.org/ft_gateway.cfm?id=2985271&type=pdf %f/mobicom/oj7hpebndlvjzikmkf6lfm0g1qc4qb5p.pdf %m0ce86363a8b160e608215c3d3b0bd973 %cmobicom %@Fund, Fraida, Shahsavari, Shahram, Panwar, Shivendra S., Erkip, Elza, Rangan, Sundee %*Do open resources encourage entry into the millimeter wave cellular service market?: poster %uhttp://dl.acm.org/ft_gateway.cfm?id=2985272&type=pdf %f/mobicom/4dqmspjlxsakmwvvki0zqeoffcgzwah5.pdf %m0dfdffd68629cc4d4255ebd1c740fce1 %cmobicom %@Hessar, Mehrdad, Iyer, Vikram, Gollakota, Shyamnat %*Enabling on-body transmissions with commodity devices: poster %uhttp://dl.acm.org/ft_gateway.cfm?id=2985273&type=pdf %f/mobicom/r5cn3zqnm1hxfjftejohar2wkagqyedo.pdf %mc563cb8d80c178ca71025165434b8929 %cmobicom %@Zhang, Tongguang, Zhao, Shuai, Cheng, Bo, Chen, Junlian %*SEEM: simulation experimental environments for mobile applications in MANETs: poster %uhttp://dl.acm.org/ft_gateway.cfm?id=2985274&type=pdf %f/mobicom/p7p8iv3qfynbmrd2idethtzq0lularx6.pdf %mae59995dd1c7d9ab56e1184e03896c78 %cmobicom %@Dhekne, Ashutosh, Gowda, Mahanth, Choudhury, Romit Ro %*Cell tower extension through drones: poster %uhttp://dl.acm.org/ft_gateway.cfm?id=2985275&type=pdf %f/mobicom/ioadjxigsxucz304hpqhwyjmtar1d2fs.pdf %m70b443445926251a54256c06ff03ca65 %cmobicom %@Ren, Bingfei, Liu, Chuanchang, Cheng, Bo, Hong, Shuangxi, Zhao, Shuai, Chen, Junlian %*EasyGuard: enhanced context-aware adaptive access control system for android platform: poster %uhttp://dl.acm.org/ft_gateway.cfm?id=2985276&type=pdf %f/mobicom/usrgxcw7qzwhk5in1ujynbhil4d8moxl.pdf %ma74621e17ad63c7b9ab681e938999976 %cmobicom %@Mahmoodi, S. Eman, Subbalakshmi, K. P., Uma, R. N %*Harnessing spectrum awareness to enhance mobile computing: poster %uhttp://dl.acm.org/ft_gateway.cfm?id=2985277&type=pdf %f/mobicom/5wqz7j8aezmi6j3becqhpytght2udblf.pdf %m5192fc90024a063ff0c4f5b034acadf2 %cmobicom %@Zou, Han, Zhou, Yuxun, Jiang, Hao, Huang, Baoqi, Xie, Lihua, Spanos, Costa %*A transfer kernel learning based strategy for adaptive localization in dynamic indoor environments: poster %uhttp://dl.acm.org/ft_gateway.cfm?id=2985278&type=pdf %f/mobicom/xjizy0yk5ic8ugpmnrrlt6qcjdvthe2l.pdf %m9cd56535e2acc6bd8a68928abfea15ec %cmobicom %@Zhang, Zhenning, Zhao, Baokang, Feng, Zhenqian, Yu, Wanrong, Wu, Chunqin %*MSN: a mobility-enhanced satellite network architecture: poster %uhttp://dl.acm.org/ft_gateway.cfm?id=2985279&type=pdf %f/mobicom/b7kma4hpozskor9pns3tylq2u0lvgxew.pdf %m227e18c8fd0039b041d083b2267b185a %cmobicom %@Mathur, Siddarth, Saha, Dola, Raychaudhuri, Dipanka %*Cross-layer MAC/PHY protocol to support IoT traffic in 5G: poster %uhttp://dl.acm.org/ft_gateway.cfm?id=2985280&type=pdf %f/mobicom/7fnl83p9wfi1lvpcdvtrzqeq5sajrzgm.pdf %mb5c74210d06aedf0eb0796889dd8adf9 %cmobicom %@Cai, Yuanhang, Xi, Wei, Wang, Zhi, Zhao, Kun, Han, Jinsong, Qian, Chen, Ding, Han, Zhao, Jizhon %*CSI feedback reduction by checking its validity period: poster %uhttp://dl.acm.org/ft_gateway.cfm?id=2985281&type=pdf %f/mobicom/mkvzwajnb2jqhwrsuxec45eoi93786c1.pdf %m148103dde8f7f41cebbc80bc225c849c %cmobicom %@Zhao, Yan %*Robust respiration monitoring using low-cost doppler sensor and wireless network: poster %uhttp://dl.acm.org/ft_gateway.cfm?id=2985282&type=pdf %f/mobicom/phdubua2m3nvzqhndxb67spejrwtisxi.pdf %ma117fbe4febbbbea3404e937285ec9a8 %cmobicom %@Dou, Yanzhi, Zeng, Kexiong (Curtis), Yang, Yaling, Ren, Ku %*Preserving incumbent users' privacy in exclusion-zone-based spectrum access systems: poster %uhttp://dl.acm.org/ft_gateway.cfm?id=2985283&type=pdf %f/mobicom/fjq96c0dzroizrs3t1klg8uy5ydjwkme.pdf %mae3e00c47463554f067bfa323ff9c39f %cmobicom %@Quadrio, G., Bujari, A., Palazzi, C. E., Ronzani, D., Maggiorini, D., Ripamonti, L. A %*Network analysis of the steam in-home streaming game system: poster %uhttp://dl.acm.org/ft_gateway.cfm?id=2985284&type=pdf %f/mobicom/axrcy59mfhpkdzlpscdxoor7imnfbweg.pdf %m8badf4cd48ba91b55c77df709af6ecd5 %cmobicom %@Pérez-Penichet, Carlos, Hermans, Frederik, Varshney, Ambuj, Voigt, Thiem %*Passive sensor tags: demo %uhttp://dl.acm.org/ft_gateway.cfm?id=2985610&type=pdf %f/mobicom/bx0zrcuavdqk4le9tofhuajz3flv7yi6.pdf %m3516c3b82ef9c51002e3b36f6a71de18 %cmobicom %@Li, Ruirui, Huang, Xinxin, Song, Shuo, Wang, Jia, Wang, We %*Towards customer trouble tickets resolution automation in large cellular services: demo %uhttp://dl.acm.org/ft_gateway.cfm?id=2985611&type=pdf %f/mobicom/loskmqzntki8badoju0cfvw56rgdhvbl.pdf %md7dc5b9a16918efbb8e5a4c68f071a7d %cmobicom %@Zhang, Chi, Zhang, Xiny %*LiTell: indoor localization using unmodified light fixtures: demo %uhttp://dl.acm.org/ft_gateway.cfm?id=2985612&type=pdf %f/mobicom/slgh7ibkcormrtkqagyxqvtz2w84njen.pdf %me262c79240ffa14b1fccc1249694f4a8 %cmobicom %@Wei, Teng, Zhang, Xiny %*Tracking orientation of batteryless internet-of-things using RFID tags: demo %uhttp://dl.acm.org/ft_gateway.cfm?id=2985613&type=pdf %f/mobicom/1cj2ljoypgdazxmh6wwn05vtrkhslp9g.pdf %m994c4bdcaa83751746028ed56f78bc24 %cmobicom %@Zhang, Jialiang, Zhang, Xinyu, Kulkarni, Pushkar, Ramanathan, Parameswara %*OpenMili: a 60 GHz software radio with a programmable phased-array antenna: demo %uhttp://dl.acm.org/ft_gateway.cfm?id=2985614&type=pdf %f/mobicom/vzskkd5wyiditermrn3yze0bnfo1hoq9.pdf %m285e58fabfe303131bcab6dea1330280 %cmobicom %@Yang, Lei, Lin, Qiongzheng, Li, Ya %*Making sense of mechanical vibration with COTS RFID systems: demo %uhttp://dl.acm.org/ft_gateway.cfm?id=2985615&type=pdf %f/mobicom/1q7lwhfxzpuc4dlyjzjx9nrknb6y5cqa.pdf %m32ad74fbf0dfa3806f9e57615946c871 %cmobicom %@Cho, Junguk, Duerig, Jonathan, Eide, Eric, Nguyen, Binh, Ricci, Robert, Syed, Aisha, Van der Merwe, Jacobus, Webb, Kirk, Wong, Gar %*Repeatable mobile networking research with phantomNet: demo %uhttp://dl.acm.org/ft_gateway.cfm?id=2985616&type=pdf %f/mobicom/dj23pjezaf6rh7r1u5i0zogfbna9gvqd.pdf %m4f59dc05d07ece4afb673f892dc7bd41 %cmobicom %@Mao, Wenguang, He, Jian, Zheng, Huihuang, Zhang, Zaiwei, Qiu, Lil %*High-precision acoustic motion tracking: demo %uhttp://dl.acm.org/ft_gateway.cfm?id=2985617&type=pdf %f/mobicom/ont8velfqe6fm2kgruq3d7iakvsh0gdl.pdf %m2a37932baa5a34c07965428edb6e9e76 %cmobicom %@Wang, Qian, Ren, Kui, Zhou, Man, Lei, Tao, Koutsonikolas, Dimitrios, Su, L %*Real-time hidden acoustic signal capture with smartphones: demo %uhttp://dl.acm.org/ft_gateway.cfm?id=2985618&type=pdf %f/mobicom/yzqjg6d4ctriww92phov8s1ijke0qfvh.pdf %m3ce830f8294563ff694f6c697f4967a2 %cmobicom %@Tian, Zhao, Wright, Kevin, Zhou, Xi %*The darklight rises: visible light communication in the dark: demo %uhttp://dl.acm.org/ft_gateway.cfm?id=2987384&type=pdf %f/mobicom/s736lvxvut2ducbawrm8rlboyfy1hnop.pdf %m9bd5f41af867f9675161ecf0d3b1c25a %cmobicom %@Wang, Wei, Liu, Alex X., Sun, K %*Device-free gesture tracking using acoustic signals: demo %uhttp://dl.acm.org/ft_gateway.cfm?id=2987385&type=pdf %f/mobicom/qgbotkexhwu2vlducwjlnrf6zbt8diyp.pdf %m976957f15fbe5ed1d367a8378bff9921 %cmobicom %@Song, Lixing, Striegel, Aaro %*FMNC - rapid and accurate wifi characterization: demo %uhttp://dl.acm.org/ft_gateway.cfm?id=2985619&type=pdf %f/mobicom/ze6gd015zcx3w8vuwobjqy9dblftaony.pdf %m622bf2423072ad07888961161051c09f %cmobicom %@Fan, Songchun, Salonidis, Theodoros, Lee, Benjami %*A framework for collaborative sensing and processing of mobile data streams: demo %uhttp://dl.acm.org/ft_gateway.cfm?id=2985620&type=pdf %f/mobicom/pva4kbwjygxzvcrnolsfutuifdd0qtyj.pdf %m12ad7d3687030716a9a70f9131faf28c %cmobicom %@Li, Yuanjie, Deng, Haotian, Xiangli, Yuanbo, Yuan, Zengwen, Peng, Chunyi, Lu, Songw %*In-device, runtime cellular network information extraction and analysis: demo %uhttp://dl.acm.org/ft_gateway.cfm?id=2985622&type=pdf %f/mobicom/peia07fbu4z9kixjqjt62o3gomyenwsc.pdf %m37a46552691e001fcb551cbfbffdc853 %cmobicom %@Cho, Junguk, Sundaresan, Karthikeyan, Mahindra, Rajesh, Van der Merwe, Jacobus, Rangarajan, Sampat %*A cacia -- context-aware edge computing for continuous interactive applications over mobile networks: demo %uhttp://dl.acm.org/ft_gateway.cfm?id=2985623&type=pdf %f/mobicom/ksmknbow0curdefmnrqwvp3h4txhulgl.pdf %md5fb6edf3ca59e4dd5cb071e1bdbe2f2 %cmobicom %@Liu, Jian, Chen, Yingying, Gruteser, Marc %*VibKeyboard: virtual keyboard leveraging physical vibration: demo %uhttp://dl.acm.org/ft_gateway.cfm?id=2985624&type=pdf %f/mobicom/z0rtlc8akjuufxy1ebyh6gp2cnh9as43.pdf %m2f80b21fca121f83c4082537ebd8a39f %cmobicom %@Kirby, Ellington, Park, Seoyoon, Wang, Yan, Chen, Yingyin %*HearHere: smartphone based audio localization using time difference of arrival: demo %uhttp://dl.acm.org/ft_gateway.cfm?id=2985625&type=pdf %f/mobicom/n5w0dkqbg7z8iv2jqptsdanouyfxoier.pdf %mee72dbabcfe58663428afc59cfa72566 %cmobicom %@Nguyen, Danh H., Chacko, James, Henderson, Logan, Paatelma, Anton, Saarnisaari, Harri, Kandasamy, Nagarajan, Dandekar, Kapil R %*WiART - visualize and interact with wireless networks using augmented reality: demo %uhttp://dl.acm.org/ft_gateway.cfm?id=2985626&type=pdf %f/mobicom/pxnifr7ygchzeovwx8caqjtkvdzf5dpw.pdf %m2fdd323d01f414afc5ea9ad1b93d0fd9 %cmobicom %@Gosain, Abhimanyu, Seskar, Iva %*GENI wireless testbed: a flexible open ecosystem for wireless communications research: demo %uhttp://dl.acm.org/ft_gateway.cfm?id=2985627&type=pdf %f/mobicom/jxowh75xn4vb6z1mldbesptmpcy0gofq.pdf %m5b840210a88b5189cd0c8017248a6d57 %cmobicom %@Maselli, Gaia, Piva, Mauro, Ramponi, Giorgia, Ganesan, Deepa %*JoyTag: a battery-less videogame controller exploiting RFID backscattering: demo %uhttp://dl.acm.org/ft_gateway.cfm?id=2985628&type=pdf %f/mobicom/2ojgrzufx68jtw4afve9ychywmn5db1k.pdf %m26a64f1d1d7bd5b9d0784e36f6ef9770 %cmobicom %@Psaras, I., Reñé, S., Katsaro, K. V., Sourlas, V., Pavlou, G., Bezirgiannidis, N., Diamantopoulos, S., Komnios, I., Tsaoussidis, V %*Keyword-based mobile application sharing %uhttp://dl.acm.org/ft_gateway.cfm?id=2980141&type=pdf %f/mobicom/cs93udl8ntshq2ab5nitamjmyxcd04bz.pdf %ma1821ed691e9b77a499de9844a15215f %cmobicom %@Schulz-Zander, Julius, Schmid, Stefan, Kempf, James, Riggio, Roberto, Feldmann, Anj %*LegoFi the wifi building blocks!: the case for a modular wifi architecture %uhttp://dl.acm.org/ft_gateway.cfm?id=2980142&type=pdf %f/mobicom/tpxu6n5kadqmwpybyhmkillisvc9ad18.pdf %m058f9b50465fad6950a51f1a8eeca5be %cmobicom %@Chang, Chia-Yu, Alexandris, Konstantinos, Nikaein, Navid, Katsalis, Kostas, Spyropoulos, Thrasyvoulo %*MEC architectural implications for LTE/LTE-A networks %uhttp://dl.acm.org/ft_gateway.cfm?id=2980139&type=pdf %f/mobicom/trgajqxidnldg8cy2390z41kb6wyh7se.pdf %m2f1850a9295de699481482bbe6943e52 %cmobicom %@Municio, Esteban, Latré, Steve %*Decentralized broadcast-based scheduling for dense multi-hop TSCH networks %uhttp://dl.acm.org/ft_gateway.cfm?id=2980143&type=pdf %f/mobicom/k65dr2a9fpceignn3twpvdljguzkt4yy.pdf %ma34fb3226cceb1f317191e3b2c98f4db %cmobicom %@Siris, Vasilios A., Dimopoulos, Dimitrio %*Smooth DASH adaptation exploiting throughput prediction %uhttp://dl.acm.org/ft_gateway.cfm?id=2980140&type=pdf %f/mobicom/oel0zdcx7um1akh2z4rsp3amhxg9cqsb.pdf %m9df71e6ac7c661fa2bb9d054f589c683 %cmobicom %@Sanchez, M. Isabel, de la Oliva, Antonio, Mancuso, Vincenz %*Experimental evaluation of an SDN-based distributed mobility management solution %uhttp://dl.acm.org/ft_gateway.cfm?id=2980138&type=pdf %f/mobicom/v21wljerqojm865ubm3ehvrcfy4p7z09.pdf %m0bf2b245b4cc4bfb7513fdf78a31cc0a %cmobicom %@Seddiki, Anass, Lim, David, Benbadis, Fari %*DECODE: DisruptivE COntent DissEmination with or without infrastructure, it syncs %uhttp://dl.acm.org/ft_gateway.cfm?id=2980145&type=pdf %f/mobicom/fr7zxwybicooj6s92ek5luvlw13kzvuf.pdf %m780a55defed0848e3c472cbb4c8b32e0 %cmobicom %@Kärkkäinen, Teemu, Välimaa, Mika, Hyytiä, Esa, Ott, Jör %*Opportunistic content dissemination performance in dense network segments %uhttp://dl.acm.org/ft_gateway.cfm?id=2979692&type=pdf %f/mobicom/efnjimvqzuov9bcwpsapkt48ydxzjslt.pdf %m2f4a85394195f95de7daa5354ccd7f38 %cmobicom %@Meißner, Dominik, Erb, Benjamin, van der Heijden, Rens, Lange, Kristin, Kargl, Fran %*Mobile triage management in disaster area networks using decentralized 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Yingying, Yang, Jie, Gruteser, Marc %*Snooping Keystrokes with mm-level Audio Ranging on a Single Phone %uhttp://dl.acm.org/ft_gateway.cfm?id=2790122&type=pdf %f/mobicom/ywzmqvlhqdwrt14mafpceud2osjzhkri.pdf %md114f327d27ad60dbfcf72b79011f90b %cmobicom %@Wang, He, Lai, Ted Tsung-Te, Roy Choudhury, Romi %*MoLe: Motion Leaks through Smartwatch Sensors %uhttp://dl.acm.org/ft_gateway.cfm?id=2790121&type=pdf %f/mobicom/cvrybwsjgdiafxqgv2bmk7ncatehuhkn.pdf %ma9dcdfa873e0e37ac52528f7fbc4904f %cmobicom %@Santos, Pedro M., Calcada, Tania, Guimarães, Diogo, Condeixa, Tiago, Sargento, Susana, Aguiar, Ana, Barros, Joã %*Demo: Platform for Collecting Data From Urban Sensors Using Vehicular Networking %uhttp://dl.acm.org/ft_gateway.cfm?id=2789169&type=pdf %f/mobicom/qumkhnhsrivgtdjx5d2basyxgwzz87e1.pdf %m06664f64f7b6bebea3f6786e0f5af6c1 %cmobicom %@Shuba, Anastasia, Le, Anh, Gjoka, Minas, Varmarken, Janus, Langhoff, Simon, Markopoulou, Athin %*Demo: AntMonitor: A System for Mobile Traffic Monitoring and Real-Time Prevention of Privacy Leaks %uhttp://dl.acm.org/ft_gateway.cfm?id=2789170&type=pdf %f/mobicom/hjqzkgdlup2t5poygxflitr0fo8mihsj.pdf %mb83b41dee6ae2b494000ec02d8be088f %cmobicom %@Pesavento, Davide, Grassi, Giulio, Pau, Giovanni, Bahl, Paramvir, Fdida, Serg %*Demo: Car-Fi: Opportunistic V2I by Exploiting Dual-Access Wi-Fi Networks %uhttp://dl.acm.org/ft_gateway.cfm?id=2789171&type=pdf %f/mobicom/cet3xyh4n1zj7lndbsfeqzrcu9k2mwag.pdf %maf69ce59b69ccfd427a7609e0b3bccef %cmobicom %@Harter, Gaetan, Pissard-Gibollet, Roger, Saint-Marcel, Frederic, Schreiner, Guillaume, Vandaele, Julie %*Demo: FIT IoT-LABA: Large Scale Open Experimental IoT Testbed %uhttp://dl.acm.org/ft_gateway.cfm?id=2789172&type=pdf %f/mobicom/8sfcqnjbdxwhcurty5zlvqyoeduii1tk.pdf %mb13a28d266a4f4116339a878bd262d8e %cmobicom %@Wang, Qing, Yin, Shengrong, Gnawali, Omprakash, Giustiniano, Domenic %*Demo: OpenVLC1.0 Platform for Research in Visible Light Communication Networks %uhttp://dl.acm.org/ft_gateway.cfm?id=2789173&type=pdf %f/mobicom/wo2gmycp0uoftzmhhc4bsuj95tnde1dk.pdf %mddf3d19074735c29ab79ca3b9ac60104 %cmobicom %@Ding, Aaron Yi, Liu, Yanhe, Tarkoma, Sasu, Flinck, Hannu, Crowcroft, Jo %*Demo: An Open-source Software Defined Platform for Collaborative and Energy-aware WiFi Offloading %uhttp://dl.acm.org/ft_gateway.cfm?id=2789174&type=pdf %f/mobicom/fhqxafrllxevnbbgh8dgpj02i6yw7znr.pdf %m992216128451edba0452c8a1db661b93 %cmobicom %@He, Songtao, Liu, Yunxin, Zhou, Huchen %*Demo: Optimizing Smartphone Power Consumption through Dynamic Resolution Scaling %uhttp://dl.acm.org/ft_gateway.cfm?id=2789175&type=pdf %f/mobicom/ampknur8ombx3jszxyee0wr12hp6klic.pdf %m01f3114c57c0dc84433abd0705f0cd93 %cmobicom %@Mikhaylov, Konstantin, Petäjäjärvi, Juha, Mäkeläinen, Marko, Paatelma, Anton, Hänninen, Tuom %*Demo: Modular Multi-radio Wireless Sensor Platform for IoT Trials with Plug&Play Module Connection %uhttp://dl.acm.org/ft_gateway.cfm?id=2789176&type=pdf %f/mobicom/scmwqpq02hofoxarjybgyudikdzgfanb.pdf %m10984c2b3877fe65b8f5979f4dd44c28 %cmobicom %@Grochla, Krzysztof, Foremski, Pawe %*Demo: Wireless Link Selection on Smartphone: Throughput vs Battery Drain %uhttp://dl.acm.org/ft_gateway.cfm?id=2789177&type=pdf %f/mobicom/hnledaoifqbz2d1kcg8ln5amyt7hc6x0.pdf %me95b87183fbf093abc9b5998cead869e %cmobicom %@Nikaein, Navid, Knopp, Raymond, Gauthier, Lionel, Schiller, Eryk, Braun, Torsten, Pichon, Dominique, Bonnet, Christian, Kaltenberger, Florian, Nussbaum, Dominiqu %*Demo: Closer to Cloud-RAN: RAN as a Service %uhttp://dl.acm.org/ft_gateway.cfm?id=2789178&type=pdf %f/mobicom/yt7talmnfx1vhig6ci25o4pj8urb3nzg.pdf %m855cf3e1527ca68c7baff4597523b68e %cmobicom %@Maity, Mukulika, Chaurasia, Avinash, Srivastava, Rachit, Raman, Bhaskaran, Vutukuru, Mythil %*Demo: Witals, AP-centric Health Diagnosis of WiFiNetworks %uhttp://dl.acm.org/ft_gateway.cfm?id=2789179&type=pdf %f/mobicom/zwksqrpqgxceulj8d63u0gfvlaom12yz.pdf %m999d05ad385a4b53adb40fd6415d657c %cmobicom %@Baron, Loïc, Boubekeur, Fadwa, Klacza, Radomir, Rahman, Mohammed Yasin, Scognamiglio, Ciro, Kurose, Nina, Friedman, Timur, Fdida, Serg %*Demo: OneLab: Major Computer Networking Testbeds for IoT and Wireless Experimentation %uhttp://dl.acm.org/ft_gateway.cfm?id=2789180&type=pdf %f/mobicom/h8itubuoesjxn1mm4zdqog6ypi9wvrqk.pdf %m58aa4e11988f7ed3306ad18963c103dd %cmobicom %@Lee, Changmin, Koo, Bonhong, Kim, Na-Rae, Yilmaz, H. Birkan, Farsad, Nariman, Eckford, Andrew, Chae, Chan-Byoun %*Demo: Molecular MIMO with Drift %uhttp://dl.acm.org/ft_gateway.cfm?id=2789181&type=pdf %f/mobicom/0oee9fjjqbikkn37qhwnrlvd6rxpbpta.pdf %m680ebacb4b287bda8f6bafc05a9e6054 %cmobicom %@Masood, Wasif, Schmidt, Jorge F %*Demo: Exploring Autoregressive Integrated Models for Time Synchronization in Wireless Sensor Networks %uhttp://dl.acm.org/ft_gateway.cfm?id=2789182&type=pdf %f/mobicom/hzsumhikgdt4oatb6df2ojz8lwypxgql.pdf %me7b0f1d528e34448d684a91a23462489 %cmobicom %@Papadopoulos, Georgios Z., Gallais, Antoine, Schreiner, Guillaume, Noël, Thoma %*Demo: Abstract: Live Adaptations of Low-power MAC Protocols %uhttp://dl.acm.org/ft_gateway.cfm?id=2789184&type=pdf %f/mobicom/knistpbj3godzr721hir0qz8xenmv5g4.pdf %mad5ae8ce81116914529b7c8de01e10dc %cmobicom %@Stewart, Gordon, Gowda, Mahanth, Mainland, Geoffrey, Radunović, Božidar, Vytiniotis, Dimitrio %*Demo: Implementation of Real-time WiFi Receiver in Ziria, Language for Rapid Prototyping of Wireless PHY %uhttp://dl.acm.org/ft_gateway.cfm?id=2789185&type=pdf %f/mobicom/hcdlm2dzuhyzb03x5qrpfw4avkcp8gjm.pdf %mae71f2fba3c3026fba4a048ec30675ee %cmobicom %@Pozza, Matteo, Palazzi, Claudio Enrico, Bujari, Armi %*Poster: Mobile Data Offloading Testbed %uhttp://dl.acm.org/ft_gateway.cfm?id=2795159&type=pdf %f/mobicom/fuhoqtqfrv8ykesjo7wxck5vpazmmbtg.pdf %m39921c08263d2723de0c4820e1554547 %cmobicom %@Ferrari, Alan, Puccinelli, Daniele, Giordano, Silvi %*Poster: Can Smart Devices Protect Us from Violent Crime? %uhttp://dl.acm.org/ft_gateway.cfm?id=2795160&type=pdf %f/mobicom/gi5dauwromlr3y41qfqy9mkbavsejhtu.pdf %mea167595307b0c1c753b5c4d241c5475 %cmobicom %@Dou, Yanzhi, Zeng, Kexiong (Curtis), Yang, Yalin %*Poster: Privacy-Preserving Server-Driven Dynamic Spectrum Access System %uhttp://dl.acm.org/ft_gateway.cfm?id=2795161&type=pdf %f/mobicom/4sd7gmi6jymfchjpriftnlz21eqoz3qb.pdf %m5485013567aacf1f953e08137cfc7617 %cmobicom %@Liu, Chen, Fang, Dingyi, Jiang, Hongbo, Chen, Xiaojiang, Tang, Zhany, Wang, Ju, Nie, Weik %*Poster: On the Low-Cost and Distance-Adaptive Device-free Localization %uhttp://dl.acm.org/ft_gateway.cfm?id=2795162&type=pdf %f/mobicom/de5q3jn6ylgvtxf0wyuo7qkp9vkh8acw.pdf %m137ea6ab3bede343904d636ba2a380e6 %cmobicom %@Schröder, Yannic, von Zengen, Georg, Wolf, Lar %*Poster: NLOS-aware Localization Based on Phase Shift Measurements %uhttp://dl.acm.org/ft_gateway.cfm?id=2795163&type=pdf %f/mobicom/g3uuxkmmyenjcf26pdavdyhobiwilzes.pdf %me2faad20db71d353bd54cab6586a9ba1 %cmobicom %@Chan, Justin, Zheng, Changxi, Zhou, Xi %*Poster: 3D Printing Your Wireless Coverage %uhttp://dl.acm.org/ft_gateway.cfm?id=2795164&type=pdf %f/mobicom/xhnirtmq59dgxv6ruiycvo8lz1b3slf0.pdf %md1cdac9eaf5a85b718488cc1e99ac25e %cmobicom %@De Coninck, Quentin, Baerts, Matthieu, Hesmans, Benjamin, Bonaventure, Olivie %*Poster: Evaluating Android Applications with Multipath TCP %uhttp://dl.acm.org/ft_gateway.cfm?id=2795165&type=pdf %f/mobicom/ibpbej3ep8ygkq4lksotau1h7wnaq0v6.pdf %mc5095478743867c0b8ef3071e8372494 %cmobicom %@Herculea, Dalia-Georgiana, Haddad, Majed, Capdevielle, Veronique, Chen, Chung Shu %*Poster: Network-Based UE Mobility Estimation in Mobile Networks %uhttp://dl.acm.org/ft_gateway.cfm?id=2795166&type=pdf %f/mobicom/6txlmupqzvieby9ore23kdrjufohakgp.pdf %mae5c824bb1a6f72fd3815a5cd740df11 %cmobicom %@Hoque, Mohammad A., Tarkoma, Sasu, Anttila, Tuikk %*Poster: Extremely Parallel Resource Pre-Fetching for Energy Optimized Mobile Web Browsing %uhttp://dl.acm.org/ft_gateway.cfm?id=2795167&type=pdf %f/mobicom/hdyjz0yixednmsgm2uiu8fkwo7eaxbr6.pdf %mfbbdefd3d1fbd5a019e9d3ffe060a0c7 %cmobicom %@Hoque, Mohammad A., Saarikoski, Kasperi, Lagerspetz, Eemil, Mineraud, Julien, Tarkoma, Sas %*Poster: VPN Tunnels for Energy Efficient Multimedia Streaming %uhttp://dl.acm.org/ft_gateway.cfm?id=2795168&type=pdf %f/mobicom/kw81mxi6nnewdycv2ezqrdu0r7gqxsv5.pdf %mc0538f618bddc6fe34d3dff2f23fd405 %cmobicom %@Wang, Ju, Fang, Dingyi, Chen, Xiaojiang, Chang, Liqiong, Tang, Zhanyong, Xing, Tianzhang, Liu, Che %*Poster: A Low Cost People Flow Monitoring System For Sensing The Potential Danger %uhttp://dl.acm.org/ft_gateway.cfm?id=2795169&type=pdf %f/mobicom/tkxejpdg3nwek1h9wjszaliqnymd0blu.pdf %mfe07a2b5ec10e187b36cdef02824378a %cmobicom %@Carvalho, Miguel Almeida, Silva, João Nun %*Poster: Unified RemoteU¡ for Mobile Environments %uhttp://dl.acm.org/ft_gateway.cfm?id=2795170&type=pdf %f/mobicom/v5ipr261zoebtvpmy8bdjldgufzy7soe.pdf %m62eaccbc302210a19e24b3e67ce2a659 %cmobicom %@Frömmgen, Alexander, Sadasivam, Sreeram, Müller, Sabrina, Klein, Anja, Buchmann, Alejandr %*Poster: Use your Senses: A Smooth Multipath TCP WiFi/Mobile Handover %uhttp://dl.acm.org/ft_gateway.cfm?id=2795171&type=pdf %f/mobicom/2yvsxoa0atzgj1l8efskdun9qrlmp3ir.pdf %mdbfa63f1011f63506765bc3dc91cdb75 %cmobicom %@Shafagh, Hossein, Hithnawi, Anwar, Droescher, Andreas, Duquennoy, Simon, Hu, We %*Poster: Towards Encrypted Query Processing for the Internet of Things %uhttp://dl.acm.org/ft_gateway.cfm?id=2795172&type=pdf %f/mobicom/oc9u8gdmpnvgysjxovfheck3ralmyber.pdf %m4febe28210c7ea9b18ff159691f53ced %cmobicom %@Costa Molero, Edgar, Kriara, Lito, Gross, Thoma %*Poster: Regression-based Characterization of 802.11ac Indoor Performance %uhttp://dl.acm.org/ft_gateway.cfm?id=2795173&type=pdf %f/mobicom/ayhw7ysuritkkmpbotl3soup0zqeaffi.pdf %m41b1de972f9a6e14b2ef18c5c9461a4e %cmobicom %@Grassi, Giulio, Sammarco, Matteo, Bahl, Paramvir, Jamieson, Kyle, Pau, Giovann %*Poster: ParkMaster: Leveraging Edge Computing in Visual Analytics %uhttp://dl.acm.org/ft_gateway.cfm?id=2795174&type=pdf %f/mobicom/xitrqjzkbcpysa2hwqug3gijedfnr9z7.pdf %m8a2a459db8a1832d13d5efee1d3a25b7 %cmobicom %@Jain, Puneet, Manweiler, Justin, Roy Choudhury, Romi %*Poster: User Location Fingerprinting at Scale %uhttp://dl.acm.org/ft_gateway.cfm?id=2795175&type=pdf %f/mobicom/au4gqtpd8xkvk9evns7ooimh52lqyw1r.pdf %m961240f564e83ee703c4a40d609e0718 %cmobicom %@Wamser, Florian, Seufert, Michael, Casas, Pedro, Irmer, Ralf, Tran-Gia, Phuoc, Schatz, Raimun %*Poster: Understanding YouTube QoE in Cellular Networks with YoMoApp: A QoE Monitoring Tool for YouTube Mobile %uhttp://dl.acm.org/ft_gateway.cfm?id=2795176&type=pdf %f/mobicom/qxo7vto31mipgwnjfe4bsq85xj09mgkt.pdf %mfc879a9b8440d8bdfa2106983b9c6e62 %cmobicom %@Nguyen, Phuc, Zhang, Xinyu, Halbower, Ann C., Vu, Ta %*Poster: Continuous and Fine-grained Respiration Volume Monitoring Using Continuous Wave Radar %uhttp://dl.acm.org/ft_gateway.cfm?id=2795177&type=pdf %f/mobicom/oqbjp51ndixusvz39ambmfe8sqlkxoaw.pdf %m0a1f53b47fda56f0964a67b25a70a5c9 %cmobicom %@Zheng, Xueshu, Jin, Naigao, Wang, Lei, Wymore, Mathew L., Qiao, Daj %*Poster: Distributed Voronoi-based Acoustic Source Localization with Wireless Sensor Networks %uhttp://dl.acm.org/ft_gateway.cfm?id=2795178&type=pdf %f/mobicom/t85huscxoafoyznagpzelrsbqvdumvf0.pdf %m5172685b062c8c275eaea2c13ab9f527 %cmobicom %@Fan, Yue, Sun, Hailong, Liu, Xudon %*Poster: TRIM: A Truthful Incentive Mechanism for Dynamic and Heterogeneous Tasks in Mobile Crowdsensing %uhttp://dl.acm.org/ft_gateway.cfm?id=2795179&type=pdf %f/mobicom/1ndosvktz5fwlt27b0kyhrcug8rb6cdi.pdf %m68c6217a319eef8868262f3d11aec6fc %cmobicom %@Yoo, Seungho, Kim, Kangho, Jung, Jongtack, Chung, Albert Yongjoon, Lee, Jiyeon, Lee, Suk Kyu, Lee, Hyung Kyu, Kim, Hwangna %*Poster: A Multi-Drone Platform for Empowering Drones' Teamwork %uhttp://dl.acm.org/ft_gateway.cfm?id=2795180&type=pdf %f/mobicom/zfdkklxrf0eqyas9atsnbuxumvjitoqd.pdf %mf300f54e4db0468e849a5f2570e10ab1 %cmobicom %@Tian, Zhao, Campbell, Andrew T., Zhou, Xi %*Poster: Visible Light Communication in the Dark %uhttp://dl.acm.org/ft_gateway.cfm?id=2795181&type=pdf %f/mobicom/yrswfbu1kmfcnbzilh8lita7psoehxr6.pdf %m0da2f7735c21c870c58b8517caee78ca %cmobicom %@Sur, Sanjib, Zhang, Xiny %*Poster: Scoping Environment to Assist 60 GHz Link Deployment %uhttp://dl.acm.org/ft_gateway.cfm?id=2795182&type=pdf %f/mobicom/n8354s1r6u0bgjewa2khpyzmgzxdix7f.pdf %m8861b3fb8951ae464a1697659b97cd67 %cmobicom %@Lu, Bingxian, Zeng, Zhicheng, Wang, Lei, Peck, Brian, Qiao, Daj %*Poster: Crowdsourced Location Aware Wi-Fi Access Control %uhttp://dl.acm.org/ft_gateway.cfm?id=2795183&type=pdf %f/mobicom/xcpa53lmkegjdr1yuqn2zs0grihd9467.pdf %m56322dd89293cc87c6af8d5910754835 %cmobicom %@Jin, Meng, Fang, Dingyi, Chen, Xiaojiang, Cai, Lin, Yang, Zhe, Tang, Zhanyon %*Poster: An Insomnia Therapy for Clock Synchronization in Wireless Sensor Networks %uhttp://dl.acm.org/ft_gateway.cfm?id=2795184&type=pdf %f/mobicom/sjuvmzcyxwyc9f72hvzdl6n3lba1gbxj.pdf %m4d34126ba67903f461dcfaa52c965e30 %cmobicom %@Kurose, James F %*Research Challenges and Opportunities in a Mobility-centric World %uhttp://dl.acm.org/ft_gateway.cfm?id=2790089&type=pdf %f/mobicom/wlb6juatndzlt0sh2uixgceiemqcvpqb.pdf %m8746b37c482692c4721890508635c3fa %cmobicom %@Li, Zhenjiang, Xie, Yaxiong, Li, Mo, Jamieson, Kyl %*Recitation: Rehearsing Wireless Packet Reception in Software %uhttp://dl.acm.org/ft_gateway.cfm?id=2790126&type=pdf %f/mobicom/cqktt2hn5i60mfeuzr3y7wgh4vpxopcz.pdf %m6a7d0f16be1b3f117e62203f1eeb3d63 %cmobicom %@Xie, Xiufeng, Chai, Eugene, Zhang, Xinyu, Sundaresan, Karthikeyan, Khojastepour, Amir, Rangarajan, Sampat %*Hekaton: Efficient and Practical Large-Scale MIMO %uhttp://dl.acm.org/ft_gateway.cfm?id=2790116&type=pdf %f/mobicom/rakuafoqt9eihxyvn5mpwbim7qjo3dgv.pdf %mbe1bd14056f59fab24635892efd05ce6 %cmobicom %@Kim, Song Min, He, Tia %*FreeBee: Cross-technology Communication via Free Side-channel %uhttp://dl.acm.org/ft_gateway.cfm?id=2790098&type=pdf %f/mobicom/vizrh0u9eos7dj3qaebxvtcg6k2funyh.pdf %mf045459ca37a2cf05d00fd674198dd64 %cmobicom %@Li, Tianxing, An, Chuankai, Tian, Zhao, Campbell, Andrew T., Zhou, Xi %*Human Sensing Using Visible Light Communication %uhttp://dl.acm.org/ft_gateway.cfm?id=2790110&type=pdf %f/mobicom/2cxzauck6w5vrzhaonlrnyvhm3sl1s0x.pdf %m85fb4e3fb7cb33fae36017e5fef9e645 %cmobicom %@Zhang, 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Volunteer Mobile Devices %uhttp://dl.acm.org/ft_gateway.cfm?id=2799660&type=pdf %f/mobicom/kimyxvgfzo9doiqcupb2xnl105teaszk.pdf %m74d0892cc1bcd7853a76fd7bda826cd7 %cmobicom %@Ashok, Ashwin, Steenkiste, Peter, Bai, Fa %*Enabling Vehicular Applications using Cloud Services through Adaptive Computation Offloading %uhttp://dl.acm.org/ft_gateway.cfm?id=2802131&type=pdf %f/mobicom/2jlgec0fjua9bsdkowktwqh6gzafy5qp.pdf %md561598845adddd31bdfb250e43ed955 %cmobicom %@Bohez, Steven, Couvreur, Jaron, Dhoedt, Bart, Simoens, Piete %*Cloudlet-based Large-scale 3D Reconstruction Using Real-time Data from Mobile Depth Cameras %uhttp://dl.acm.org/ft_gateway.cfm?id=2802134&type=pdf %f/mobicom/ouq19cxgmi5mwtz0rrlcdts3gzakevfw.pdf %mc6604c1302b057c63d13efe14b843358 %cmobicom %@Wang, Xiaolei, Yang, Yuexiang, Zeng, Yingzhi, Tang, Chuan, Shi, Jiangyong, Xu, Kel %*A Novel Hybrid Mobile Malware Detection System Integrating Anomaly Detection With Misuse Detection %uhttp://dl.acm.org/ft_gateway.cfm?id=2802132&type=pdf %f/mobicom/i87wyj4pzkdhgd0zaq1tsgtsxmfewjlr.pdf %mc126ab1e9b8e7a72ed0f9d7f47c8097f %cmobicom %@Saeed, Ahmed, Ammar, Mostafa, Harras, Khaled A., Zegura, Elle %*Vision: The Case for Symbiosis in the Internet of Things %uhttp://dl.acm.org/ft_gateway.cfm?id=2802133&type=pdf %f/mobicom/cgrbvpisfn3c1ee9pukmoskjz72owgtm.pdf %mdde6663a052fa506d0d02a29d12dff1e %cmobicom %@Kravets, Robin, Tuncay, Güliz Seray, Sundaram, Har %*For Your Eyes Only %uhttp://dl.acm.org/ft_gateway.cfm?id=2802137&type=pdf %f/mobicom/xs3dc0e7dkjanzljyzb4fatw9viqlg5f.pdf %m74af8a335081c1163dac85e6fbdde70b %cmobicom %@Nikaein, Navi %*Processing Radio Access Network Functions in the Cloud: Critical Issues and Modeling %uhttp://dl.acm.org/ft_gateway.cfm?id=2802136&type=pdf %f/mobicom/icnww1tfa9vnydrk5p0lgic8zqsxhyeb.pdf %ma78d6931d8b610ae03baa35536d554e7 %cmobicom %@Ding, Aaron Yi, Liu, Yanhe, Tarkoma, Sasu, Flinck, Hannu, Schulzrinne, Henning, Crowcroft, Jo %*Vision: Augmenting WiFi Offloading with An Open-source Collaborative Platform %uhttp://dl.acm.org/ft_gateway.cfm?id=2802135&type=pdf %f/mobicom/rdsz8jul6k14dy0c3xppvxfhuqw9t2nw.pdf %m5ac7504e9bc413cbfdf4dc7657ffe209 %cmobicom %@Herculea, Dalia-Georgiana, Haddad, Majed, Capdevielle, Veronique, Chen, Chung Shu %*Network-Based UE Mobility Estimation in Mobile Networks %uhttp://dl.acm.org/ft_gateway.cfm?id=2801704&type=pdf %f/mobicom/phqrdel49cxb5ljyfn0nbiokg2vs7afr.pdf %m10fcd704fb4171b17efa5deea942b3d9 %cmobicom %@Zhao, Cong, Shi, Fengrui, Huang, Ran, Yang, Xinyu, McCann, Juli %*Trustworthy Device Pairing for Opportunistic Device-to-Device Communications in Mobile Crowdsourcing Systems %uhttp://dl.acm.org/ft_gateway.cfm?id=2801705&type=pdf %f/mobicom/8tmj5yu01s9pxqlmuih2veerngozawrn.pdf %m20c74c62863b83162ee4ec2f00a01d1f %cmobicom %@Montanari, Alessandr %*Multimodal Indoor Social Interaction Sensing and Real-time Feedback for Behavioural Intervention %uhttp://dl.acm.org/ft_gateway.cfm?id=2801706&type=pdf %f/mobicom/v5musacsdtcliv4wgqou6bxrx0bzjqfn.pdf %me7f4c87b4c00f0255016ed7117ad7f18 %cmobicom %@Sooriyaarachchi, S. J %*Poster: A Cell Biology Inspired Model for Controlling Redundant Rebroadcasts in Mobile Ad-hoc Networks %uhttp://dl.acm.org/ft_gateway.cfm?id=2801713&type=pdf %f/mobicom/ph69zcunwswqycddljr28avkstgf3fmy.pdf %mbbcb74bdfcc64598f229027b9366a277 %cmobicom %@Sun, Li, Sen, Souvik, Koutsonikolas, Dimitrios, Kim, Kyu-Ha %*Poster: Enabling Hands-free Drawing on WiFi Devices %uhttp://dl.acm.org/ft_gateway.cfm?id=2802144&type=pdf %f/mobicom/1ofmre68dh5ls3ymnwokznhuz9x4itc2.pdf %m7d618465e5739191aaf794030d2314fa %cmobicom %@Drolia, Utsav, Mickulicz, Nathan, Gandhi, Rajeev, Narasimhan, Priy %*Poster: Krowd: A Key-Value Store for Crowded Venues %uhttp://dl.acm.org/ft_gateway.cfm?id=2802145&type=pdf %f/mobicom/huf73elb01nna854otmkqpfxbhdruyyd.pdf %m67645044e284e1b290e1d671545fce68 %cmobicom %@Ferrari, Alan, Puccinelli, Daniel, Giordano, Silvi %*Poster: Can Smart Devices Protect Us from Violent Crime? %uhttp://dl.acm.org/ft_gateway.cfm?id=2802146&type=pdf %f/mobicom/empi2dnpcysf1sjwhhj3y6glqk09t84e.pdf %m8eb5d49ecbf1108b227c6a2cd4c91cce %cmobicom %@Chen, Guangshuo, Viana, Aline Carneir %*Poster: On the Quest for Representative Mobile Datasets %uhttp://dl.acm.org/ft_gateway.cfm?id=2802147&type=pdf %f/mobicom/z3s8avx7hbfpwsutha0wq1njnvit65rm.pdf %m1952215854f33aa27c04762cdc44ce21 %cmobicom %@Shi, Lixin, Kabelac, Zachary, Katabi, Dina, Perreault, Davi %*Poster: Wireless Power Hotspot that Charges All of Your Devices %uhttp://dl.acm.org/ft_gateway.cfm?id=2801715&type=pdf %f/mobicom/glis2wmdzoy7m0tuly4hxrkvbezeqt3n.pdf %m631e42c5b64348610a6eeef496f69031 %cmobicom %@Sklivanitis, George, Demirors, Emrecan, Batalama, Stella N., Pados, Dimitris A., Melodia, Tommas %*Poster: Realizing All-spectrum Cognitive Networking on a Software-defined Radio Testbed %uhttp://dl.acm.org/ft_gateway.cfm?id=2802148&type=pdf %f/mobicom/dx0dl9bfswytukaevyvqjoucnhgz7xji.pdf %mc6c136f0fc4c24fd13f6f5e1a99e4a3e %cmobicom %@Everett, Evan, Shepard, Clayton, Zhong, Lin, Sabharwal, Ashutos %*Poster: SoftNull: All-digital Massive MIMO Full-duplex Wireless %uhttp://dl.acm.org/ft_gateway.cfm?id=2801716&type=pdf %f/mobicom/0ivzhebri6snaukxxmwlpml2qrutf5dj.pdf %mce4e05b65f564713f534606520445640 %cmobicom %@Hafeez, Ibbad, Ding, Aaron Yi, Suomalainen, Lauri, Hätönen, Seppo, Niemi, Valtteri, Tarkoma, Sas %*Demo: Cloud-based Security as a Service for Smart IoT Environments %uhttp://dl.acm.org/ft_gateway.cfm?id=2802140&type=pdf %f/mobicom/sxrlujdbmv8igndltpoka39meahctxgu.pdf %mdbd592513087b8cf625d74d6aa518c21 %cmobicom %@Kononenko, Kiril %*Demo: Dynamic Neutralization of Data Leakages %uhttp://dl.acm.org/ft_gateway.cfm?id=2802141&type=pdf %f/mobicom/aakmwdj06bfn8dzchjykg2lxusgph5vu.pdf %m6c6ae74424a4548f29af7d863810e620 %cmobicom %@Shuba, Anastasia, Le, Anh, Gjoka, Minas, Varmarken, Janus, Langhoff, Simon, Markopoulou, Athin %*Demo: AntMonitor: Network Traffic Monitoring and Real-Time Prevention of Privacy Leaks in Mobile Devices %uhttp://dl.acm.org/ft_gateway.cfm?id=2801696&type=pdf %f/mobicom/c3bdanldu2s5kqr1i6pw4fnsoizgt9cf.pdf %mde671cbc60a7557a18f835aa09a43636 %cmobicom %@Seufert, Michael, Wamser, Florian, Casas, Pedro, Irmer, Ralf, Tran-Gia, Phuoc, Schatz, Raimun %*Demo: On the Monitoring of YouTube QoE in Cellular Networks from End-devices %uhttp://dl.acm.org/ft_gateway.cfm?id=2802142&type=pdf %f/mobicom/x3r79jneb0zhmidyzf1gc4ovhmeos8uq.pdf %m11eda9674f14c877e24bd36cb21e294a %cmobicom %@Bloessl, Bastian, Dressler, Falk %*Demo: mSync in Action %uhttp://dl.acm.org/ft_gateway.cfm?id=2801698&type=pdf %f/mobicom/ga3bhubdwoyestv9zpeffyc2roc65r0s.pdf %m3c884d227a1f53fed4aec2fa54a38ecc %cmobicom %@Shuba, Anastasia, Le, Anh, Gjoka, Minas, Varmarken, Janus, Langhoff, Simon, Markopoulou, Athin %*AntMonitor: Network Traffic Monitoring and Real-Time Prevention of Privacy Leaks in Mobile Devices %uhttp://dl.acm.org/ft_gateway.cfm?id=2801707&type=pdf %f/mobicom/i3ojnsld7wqyasa0efxqmvigpvhtocpl.pdf %m7a4764da5c5ef77a40eca17f05f8074c %cmobicom %@Macedo, Ricardo, Santos, Aldri, Ghamri-Doudane, Yacine, Nogueira, Michel %*Guard Mounting: Reorganizations to Mitigate DDoS Attacks over Identity Providers Clustering %uhttp://dl.acm.org/ft_gateway.cfm?id=2801709&type=pdf %f/mobicom/p2uz540n1bowc3ri7rvz8pdsft6jefvd.pdf %mc2e9460db0029b14ba3484abe4c659ef %cmobicom %@Masood, Wasif, Schmidt, Jorge F %*Exploring Autoregressive Integrated Models for Time Synchronization in Wireless Sensor Networks %uhttp://dl.acm.org/ft_gateway.cfm?id=2801699&type=pdf %f/mobicom/fvep953eznslromyit0yiwknkabgh1zb.pdf %mf2f73f0d8493b44e7f3cc810148c001a %cmobicom %@Ganesan, Deepa %*Towards Ultra-low Power Wearable Health Sensing with Sparse Sampling and Asymmetric Communication %uhttp://dl.acm.org/ft_gateway.cfm?id=2801710&type=pdf %f/mobicom/d8tavdybustkpvrwijipc7ragw1lz9q3.pdf %m48d12884a2db6d32fdb8c661a54085a7 %cmobicom %@Saha, Swetank Kumar, Sun, Li, Koutsonikolas, Dimitrio %*Improving Connectivity, Coverage, and Capacity in 60 GHz Indoor WLANs Using Relays %uhttp://dl.acm.org/ft_gateway.cfm?id=2804446&type=pdf %f/mobicom/7uxvsqhf2gtxtdrliby36oorceskdbcz.pdf %m2ac2382c7c1ba793f6cf05e6ab3bbc67 %cmobicom %@Papadopoulos, Georgios Z., Gallais, Antoine, Schreiner, Guillaume, Noel, Thoma %*Live Adaptations of Low-power MAC Protocols %uhttp://dl.acm.org/ft_gateway.cfm?id=2801700&type=pdf %f/mobicom/ufelj8pmjsrtocv6k243xmubab7igigs.pdf %m0e1662bd97c94248b8d1c1ca55a2a575 %cmobicom %@Nikolaidis, Georgios, Handley, Mark, Jamieson, Kyle, Karp, Bra %*On the Synergy between Nulling and Power Allocation in OFDM Systems %uhttp://dl.acm.org/ft_gateway.cfm?id=2801701&type=pdf %f/mobicom/pk9ix4nv8y2svutsqletojfzpymmrudl.pdf %m20e89818e537fb784757f500ae66c26c %cmobicom %@Nya, Narcisse, Baynat, Brun %*A PS Queue Model for Lte Macrocells Taking into Account Mobility of Users %uhttp://dl.acm.org/ft_gateway.cfm?id=2801708&type=pdf %f/mobicom/dngdl6sju2ouhje0yty17pqkwv9sgiaq.pdf %m0dcba493b95c3ff2f03e723b50a2e480 %cmobicom %@Belli, Laura, Cirani, Simone, Gorrieri, Andrea, Picone, Marc %*A Novel Smart Object-Driven UI Generation Approach for Mobile Devices in the Internet of Things %uhttp://dl.acm.org/ft_gateway.cfm?id=2797046&type=pdf %f/mobicom/psyw0fl6r1rjau5xej92bx4zkvd3nuvq.pdf %mb1b46b2dc616927108ff3cf4d98ba973 %cmobicom %@Huang, Yu-Te, Ho, Yao-Hua, Chu, Hao-hua, Chen, Ling-Jy %*Adaptive Drone Sensing with Always Return-To-Home Guaranteed %uhttp://dl.acm.org/ft_gateway.cfm?id=2797054&type=pdf %f/mobicom/doyf6npwy8jvgkilerpze0tcqvfshbo2.pdf %m5ab8cbfadd11ad3ec7d5ab3270eea826 %cmobicom %@Zhang, Maotian, Yang, Panlong, Tian, Chang, Shi, Lei, Tang, Shaojie, Xiao, F %*SoundWrite: Text Input on Surfaces through Mobile Acoustic Sensing %uhttp://dl.acm.org/ft_gateway.cfm?id=2797045&type=pdf %f/mobicom/vlvudam2bozckwtfnqpbsi3awi8ek17t.pdf %m22e2200ae11488894d917b9f469bf66d %cmobicom %@Corbellini, Giorgio, Schmid, Stefan, Mangold, Stefa %*Two-Way Communication Protocol using Bluetooth Low Energy Advertisement Frames %uhttp://dl.acm.org/ft_gateway.cfm?id=2797049&type=pdf %f/mobicom/64hxdyhfjm7lm9vczonqxw8sbyvjcki5.pdf %mb79fe6c6849230fe6c873b57eb9cc176 %cmobicom %@Martín-Fernández, Francisco, Caballero-Gil, Pino, Caballero-Gil, Cándid %*Poster: Revocation in VANETs Based on k-ary Huffman Trees %uhttp://dl.acm.org/ft_gateway.cfm?id=2797051&type=pdf %f/mobicom/hvjm9netrlqcwz4taoxsn2biv6gdfyuk.pdf %m3340cbf268a0166465208d8e1218caba %cmobicom %@Santos-González, Iván, Caballero-Gil, Pino, Rivero-García, Alexandra, Hernández-Goya, Candelari %*Poster: Indoor Location System for Vehicles %uhttp://dl.acm.org/ft_gateway.cfm?id=2797053&type=pdf %f/mobicom/nfyazv2z1jxvckqqi7cnsdarjtrpgdlo.pdf %m034d0b7f88a90f7a179065cef90ec60f %cmobicom %@Touati, Lyes, Challal, Yacin %*Poster: Activity-Based Access Control for IoT %uhttp://dl.acm.org/ft_gateway.cfm?id=2797052&type=pdf %f/mobicom/qaoxumiswjk50hei2qwozbazd83fgyuv.pdf %m7029b1c3d48d9bb7ce7db72e5b0ef06b %cmobicom %@Asadpour, Mahdi, Burger, Mario, Schuiki, Fabian, Hummel, Karin Ann %*Needle in a Haystack: Limiting the Search Space in Mission-aware Packet Forwarding for Drones %uhttp://dl.acm.org/ft_gateway.cfm?id=2797057&type=pdf %f/mobicom/b6yantysb3ajtvizlwsgmqgh5rjdc2zm.pdf %mee18636f588d4450bdd40fd746633593 %cmobicom %@Pace, Pasquale, Aloi, Gianluca, Caliciuri, Giuseppe, Fortino, Giancarl %*Management and Coordination Framework for Aerial-Terrestrial Smart Drone Networks %uhttp://dl.acm.org/ft_gateway.cfm?id=2797047&type=pdf %f/mobicom/ndec0lymagak91tb3il5zxtikmubswfh.pdf %m698637d56696f48b60f3fa919cacb664 %cmobicom %@Bhojan, Anand, Tan, Guo We %*mumble: Framework for Seamless Message Transfer on Smartphones %uhttp://dl.acm.org/ft_gateway.cfm?id=2797048&type=pdf %f/mobicom/tyj2zqqaloxcpzubsfmyr9drgc8wli0e.pdf %mda759a352ddc075175b458056fcfc417 %cmobicom %@Zaouche, Lotfi, Natalizio, Enrico, Bouabdallah, Abdelmadji %*ETTAF: Efficient Target Tracking and Filming with a Flying Ad Hoc Network %uhttp://dl.acm.org/ft_gateway.cfm?id=2797055&type=pdf %f/mobicom/o7ajr0ub1ryxsaht8mzsxjq9eyhtmnql.pdf %mab7db3904b1304b842f29c48deafbdfc %cmobicom %@Wang, Ju, Xie, Binbin, Fang, Dingyi, Chen, Xiaojiang, Liu, Chen, Xing, Tianzhang, Nie, Weik %*Accurate Device-Free Localization with Little Human Cost %uhttp://dl.acm.org/ft_gateway.cfm?id=2797050&type=pdf %f/mobicom/gj6w8tev2smzrvmflh4juezrgdawbi1n.pdf %m4e34d518fa98b17534215a32d019d28a %cmobicom %@Vermeulen, Tom, Van den Bergh, Bertold, Pollin, Sofi %*Demo: A Software Defined Radio Platform for Rapid Cross-Layer Prototyping %uhttp://dl.acm.org/ft_gateway.cfm?id=2801683&type=pdf %f/mobicom/q9izcfkcuafnxrj7lg4mdsayo1v5x36o.pdf %m90d3c837feb7b0a5a7ce1cbf284e5d18 %cmobicom %@Arnold, Julian, Simic, Ljiljana, Petrova, Marina, Mähönen, Petr %*Demo: Spectrum-Agile mm-Wave Packet Radio Implementation on USRPs %uhttp://dl.acm.org/ft_gateway.cfm?id=2801681&type=pdf %f/mobicom/spjxtkjl0eisc1grmwrm9yx6uhzg5dq7.pdf %m3e7419117e7202977f0a7d65a0baee5e %cmobicom %@Cercueil, Pau %*Demo: IIO Blocks for GNU Radio %uhttp://dl.acm.org/ft_gateway.cfm?id=2801684&type=pdf %f/mobicom/taxoei1c0wg3ftmcbanfuqp9hw7j8usv.pdf %m480bfd50c04ee67fb931648636f03594 %cmobicom %@Sklivanitis, George, Demirors, Emrecan, Batalama, Stella N., Pados, Dimitris A., Melodia, Tommas %*Demo: ROCH: Software-defined Radio Toolbox for Experimental Evaluation of All-spectrum Cognitive Networking %uhttp://dl.acm.org/ft_gateway.cfm?id=2801686&type=pdf %f/mobicom/ngk7w3ljtrndzxmu9fwakbrebcovh82u.pdf %m2c55adac059b3fbe3e69684f972e1648 %cmobicom %@Bloessl, Bastian, Dressler, Falk %*Poster: mSync -- Frames without Preambles %uhttp://dl.acm.org/ft_gateway.cfm?id=2801678&type=pdf %f/mobicom/vnbysywimwildogfqpdabgothrhjv2mk.pdf %m096a8cb3fd326efd962c41a06cd42e32 %cmobicom %@Muniz, Alfred %*Enhancing GNU Radio with Heterogeneous Computing %uhttp://dl.acm.org/ft_gateway.cfm?id=2801689&type=pdf %f/mobicom/tbcyflqvn6qj7ispg3hurh2zcu8ablzk.pdf %mff50ffe9364197aee5a1476f301b3581 %cmobicom %@Li, Ping, Yang, Panlong, Shi, Lei, Yan, Yub %*Poster: Push the Limit of Cross Technology Coexistence %uhttp://dl.acm.org/ft_gateway.cfm?id=2801679&type=pdf %f/mobicom/daxqojejvbsat9wqgilptk3w6m4fdep5.pdf %m30e36f593dd86a7885993d72fc640cec %cmobicom %@Hithnawi, Anwar, Kulkarni, Vaibhav, Li, Su, Shafagh, Hossei %*Controlled Interference Generation for Wireless Coexistence Research %uhttp://dl.acm.org/ft_gateway.cfm?id=2801682&type=pdf %f/mobicom/orzlknrbzabhkdvemc8x6p2ifl9g37yw.pdf %mac71e4d7046de81bb7e92aa664c70a8e %cmobicom %@Bhatt, Bhaumik, Anderson, Austin M., Grunwald, Dir %*Architecture-Based Software Designs for SDR's %uhttp://dl.acm.org/ft_gateway.cfm?id=2801687&type=pdf %f/mobicom/s3zsi29elyrecq4jctarf81lb0uhnxqv.pdf %ma10998f972ae3feceebbee1d8463dc40 %cmobicom %@Surligas, Manolis, Makrogiannakis, Antonis, Papadakis, Stefano %*Maximizing GPU Exploitation for SDR with GPUDirect %uhttp://dl.acm.org/ft_gateway.cfm?id=2801688&type=pdf %f/mobicom/5cyxtnndshblyjo4rikgdr3vawzuf6c7.pdf %m9e21c99322d8e4c8a21da6e619b10e28 %cmobicom %@Otterbach, Nico, Kaiser, Cornelius, Stoica, Vlad, Han, Bin, Dostert, Klau %*Software-Defined Radio for Power Line Communication Research and Development %uhttp://dl.acm.org/ft_gateway.cfm?id=2801690&type=pdf %f/mobicom/ck2erw3tqgcseyjvn584yfdfkrslz9lp.pdf %mb62af707ecafea583b3b5c81f5ae5bf3 %cmobicom %@Haas, Haral %*The Future of Wireless Light Communication %uhttp://dl.acm.org/ft_gateway.cfm?id=2801692&type=pdf %f/mobicom/8pf1otezt4elu6bcxi3djqgh2bn9nrlx.pdf %m9db48495f02da64bb095d62658d7467b %cmobicom %@Schmid, Stefan, Bourchas, Theodoros, Mangold, Stefan, Gross, Thomas R %*Linux Light Bulbs: Enabling Internet Protocol Connectivity for Light Bulb Networks %uhttp://dl.acm.org/ft_gateway.cfm?id=2801074&type=pdf %f/mobicom/wqguhkcrxfdiptch4x81d3qzpnwtjzoi.pdf %m6d3d850c1c5ae9014c27e074015e4f15 %cmobicom %@Classen, Jiska, Chen, Joe, Steinmetzer, Daniel, Hollick, Matthias, Knightly, Edwar %*The Spy Next Door: Eavesdropping on High Throughput Visible Light Communications %uhttp://dl.acm.org/ft_gateway.cfm?id=2801075&type=pdf %f/mobicom/nxepscns9kypui2zvjgli5afwbyqr03c.pdf %ma04994e32aa6852b257e55d7b7e57f53 %cmobicom %@Yao, Zhongqiang, Tian, Hui, Fan, B %*Joint Illumination-Communication Optimization in Visible Light Communication %uhttp://dl.acm.org/ft_gateway.cfm?id=2801076&type=pdf %f/mobicom/g26hxefkw85ldy9ba0nliotjgt1cfqkp.pdf %mdd332e32a8b8159daf2ec2eae25742f2 %cmobicom %@Palathingal, Prabath, Yuksel, Murat, Guvenc, Ismail, Pala, Nezi %*A Multi-Element VLC Architecture for High Spatial Reuse %uhttp://dl.acm.org/ft_gateway.cfm?id=2801077&type=pdf %f/mobicom/l8ngpi1kjalchn3zjwyx7firkdvetrbg.pdf %md0def8b2e240e9355cb2090d1c5abd48 %cmobicom %@Dehghani Soltani, Mohammad, Wu, Xiping, Safari, Majid, Haas, Haral %*On Limited Feedback Resource Allocation for Visible Light Communication Networks %uhttp://dl.acm.org/ft_gateway.cfm?id=2801693&type=pdf %f/mobicom/u9y7w6wtqsxdjrauki58ydhz3op4pmvl.pdf %m0e6eef0a0d3cfb53f83e2e9b88fbbf49 %cmobicom %@Huang, Chang-Jung, Wei, Yu-Lin, Fu, Chiao, Shen, Wen-Hsuan, Tsai, Hsin-Mu, Lin, Ching-Ju Kat %*LiBeamScanner: Accurate Indoor Positioning with Sweeping Light Beam %uhttp://dl.acm.org/ft_gateway.cfm?id=2801079&type=pdf %f/mobicom/tkxkgacdlvsi3uuqq9ehjtp5obmxjmnw.pdf %m510e0150942bef1e02cb8d777e20e172 %cmobicom %@An, Chuankai, Li, Tianxing, Tian, Zhao, Campbell, Andrew T., Zhou, Xi %*Visible Light Knows Who You Are %uhttp://dl.acm.org/ft_gateway.cfm?id=2801078&type=pdf %f/mobicom/q9vbmgys53kdtcw8agqkxyloiijefc6j.pdf %m3c2fe6665ff3b7f2cca06e91c7826510 %cmobicom %@Biswas, Sanji %*From grad school, to startup to acquisition %uhttp://dl.acm.org/ft_gateway.cfm?id=2639416&type=pdf %f/mobicom/upiybnqmclk1hv6rkspat7xrclgyd2w4.pdf %m3c216dee363de103332d6c789b55fa52 %cmobicom %@Subramanian, Lakshminarayanan, Biswas, Sanjit, Borriello, Gaetano, Dutta, Prabal, Katabi, Dina, Katz, Rand %*Tackling societal grand challenges using mobile computing %uhttp://dl.acm.org/ft_gateway.cfm?id=2641729&type=pdf %f/mobicom/fhswcdjumenx2cardak3qijizqy4gwey.pdf %m724e1abb5ed1ca9900fa2a70d3865a17 %cmobicom %@Zhu, Yibo, Zhang, Zengbin, Marzi, Zhinus, Nelson, Chris, Madhow, Upamanyu, Zhao, Ben Y., Zheng, Haita %*Demystifying 60GHz outdoor picocells %uhttp://dl.acm.org/ft_gateway.cfm?id=2639121&type=pdf %f/mobicom/fiykgnwvmqqucbzjv9usdgpmjfrek51s.pdf %mcffa894ff2aa868c813bdc73adaad56f %cmobicom %@Zhang, Tan, Leng, Ning, Banerjee, Suma %*A vehicle-based measurement framework for enhancing whitespace spectrum databases %uhttp://dl.acm.org/ft_gateway.cfm?id=2639114&type=pdf %f/mobicom/st16kvshowficrd2byzhut4xjwlbgnop.pdf %m2466a40146eb8608326c563f53128ce7 %cmobicom %@Anand, Narendra, Guerra, Ryan E., Knightly, Edward W %*The case for UHF-band MU-MIMO %uhttp://dl.acm.org/ft_gateway.cfm?id=2639144&type=pdf %f/mobicom/opdq16ihsf5bjr3ccutn27xoza9wnlk4.pdf %m1b8b8aad699ca109cd89a4e8798a3761 %cmobicom %@Wang, Anran, Ma, Shuai, Hu, Chunming, Huai, Jinpeng, Peng, Chunyi, Shen, Guobi %*Enhancing reliability to boost the throughput over screen-camera links %uhttp://dl.acm.org/ft_gateway.cfm?id=2639135&type=pdf %f/mobicom/udohjnedewilfgav5rq0hbcqytpxwntv.pdf %m4f789b6ba566cfe0e0c0b0b122da538e %cmobicom %@Gehlhaar, Jef %*The future of mobile computing %uhttp://dl.acm.org/ft_gateway.cfm?id=2639417&type=pdf %f/mobicom/5zk1mxijsgnc4ebazjuaky3mwqhshrlv.pdf %m467180a3c178036fe506bfe62f4096a0 %cmobicom %@Lu, Feng, Ling, Patrick, Voelker, Geoffrey M., Snoeren, Alex C %*Enfold: downclocking OFDM in WiFi %uhttp://dl.acm.org/ft_gateway.cfm?id=2639123&type=pdf %f/mobicom/yo4fgbultv0tvirbxrafuqds2n8pm6s7.pdf %m28dc5779f687654b666baaf2c0c74479 %cmobicom %@Yu, Hang, Bejarano, Oscar, Zhong, Li %*Combating inter-cell interference in 802.11ac-based multi-user MIMO networks %uhttp://dl.acm.org/ft_gateway.cfm?id=2639122&type=pdf %f/mobicom/egzrv6lkfuqmdswbs50neczfwy2daut1.pdf %m57c5d5088614c6d0ce976b246fe87e45 %cmobicom %@Gjengset, Jon, Xiong, Jie, McPhillips, Graeme, Jamieson, Kyl %*Phaser: enabling phased array signal processing on commodity WiFi access points %uhttp://dl.acm.org/ft_gateway.cfm?id=2639139&type=pdf %f/mobicom/3fswp6pagmmykxtjvjckqe54f9nu0lng.pdf %mf2700ba3995fb5ce832ca11f1bb99f20 %cmobicom %@Zhou, Wenjie, Bansal, Tarun, Sinha, Prasun, Srinivasan, Kanna %*BBN: throughput scaling in dense enterprise WLANs with Bind Beamforming and Nulling %uhttp://dl.acm.org/ft_gateway.cfm?id=2639113&type=pdf %f/mobicom/bnmobongpj24gulshxetqvfyjqc13xpz.pdf %mfa91ec215100b4b98e2fdb72a63f4b6b %cmobicom %@Rosen, Sanae, Luo, Haokun, Chen, Qi Alfred, Mao, Z. Morley, Hui, Jie, Drake, Aaron, Lau, Kevi %*Discovering fine-grained RRC state dynamics and performance impacts in cellular networks %uhttp://dl.acm.org/ft_gateway.cfm?id=2639115&type=pdf %f/mobicom/mwdaupe4fo3zwbfc9jkeac8or6t2r1gj.pdf %m04aa267bc2b1e1b5a09eaf68a4b32bb4 %cmobicom %@Mahindra, Rajesh, Viswanathan, Hari, Sundaresan, Karthik, Arslan, Mustafa Y., Rangarajan, Sampat %*A practical traffic management system for integrated LTE-WiFi networks %uhttp://dl.acm.org/ft_gateway.cfm?id=2639120&type=pdf %f/mobicom/sh5cxrek1wph2zntmlkql0svy3yqgvj4.pdf %m84490b43a0851afd472419d2bc60755b %cmobicom %@Zhang, Desheng, Huang, Jun, Li, Ye, Zhang, Fan, Xu, Chengzhong, He, Tia %*Exploring human mobility with multi-source data at extremely large metropolitan scales %uhttp://dl.acm.org/ft_gateway.cfm?id=2639116&type=pdf %f/mobicom/gidtrjzfpklwj7auvvsbfiwyu8xk1nal.pdf %m2a535f8d99c4629eeca3d861aff1ec68 %cmobicom %@Balachandran, Athula, Aggarwal, Vaneet, Halepovic, Emir, Pang, Jeffrey, Seshan, Srinivasan, Venkataraman, Shobha, Yan, H %*Modeling web quality-of-experience on cellular networks %uhttp://dl.acm.org/ft_gateway.cfm?id=2639137&type=pdf %f/mobicom/ejyvhhtsxzgq3n0xq19kirwgiymu46jl.pdf %m0df3b132b005f00b145a2c015d4d1f49 %cmobicom %@Fang, Song, Liu, Yao, Shen, Wenbo, Zhu, Haoji %*Where are you from?: confusing location distinction using virtual multipath camouflage %uhttp://dl.acm.org/ft_gateway.cfm?id=2639117&type=pdf %f/mobicom/yp3bukxozhtncwr4dfsqqsv0t9ivieje.pdf %mcd37cf5fee605e0bb445750c117fbc77 %cmobicom %@Yang, Lei, Chen, Yekui, Li, Xiang-Yang, Xiao, Chaowei, Li, Mo, Liu, Yunha %*Tagoram: real-time tracking of mobile RFID tags to high precision using COTS devices %uhttp://dl.acm.org/ft_gateway.cfm?id=2639111&type=pdf %f/mobicom/ry3bozhejkilst9u6gjxsppt2fk4l5rz.pdf %m5eb98ad405c75f5201fda955ca8e2688 %cmobicom %@Gao, Ruipeng, Zhao, Mingmin, Ye, Tao, Ye, Fan, Wang, Yizhou, Bian, Kaigui, Wang, Tao, Li, Xiaomin %*Jigsaw: indoor floor plan reconstruction via mobile crowdsensing %uhttp://dl.acm.org/ft_gateway.cfm?id=2639134&type=pdf %f/mobicom/eesdpz1ybxloqaly523gpvhc7okivd8s.pdf %m29dac5b8503873ba064d37f37b473dbf %cmobicom %@Adib, Fadel, Kabelac, Zachary, Mao, Hongzi, Katabi, Dina, Miller, Robert C %*Demo: real-time breath monitoring using wireless signals %uhttp://dl.acm.org/ft_gateway.cfm?id=2641756&type=pdf %f/mobicom/kgrtyrzsygon2atp5neawjhp0fdekx81.pdf %mbdae64b9df2f0fca5d198f0d87d09ba7 %cmobicom %@Aucinas, Andrius, Crowcroft, Jo %*Demo: PhoneLets: offloading the phone off your phone for energy, cost and network load optimization %uhttp://dl.acm.org/ft_gateway.cfm?id=2641744&type=pdf %f/mobicom/u0qhh2wxaodxov8fbalwz6rengylutmy.pdf %m686939c6d960217852015cc233893d30 %cmobicom %@Ben Abdesslem, Fehmi, Lindgren, Ander %*Demo: mobile opportunistic system for experience sharing (MOSES) in indoor exhibitions %uhttp://dl.acm.org/ft_gateway.cfm?id=2641750&type=pdf %f/mobicom/o1gfxwj84zeipc7lb5kfqjl2ecdpv9gb.pdf %m12da788251f701398546f904458b7ed1 %cmobicom %@Ganesan, Aishwarya, Rallapalli, Swati, Chintalapudi, Krishna, Padmanabhan, Venkat, Qiu, Lil %*Demo: tracking user browsing on a demo floor %uhttp://dl.acm.org/ft_gateway.cfm?id=2641754&type=pdf %f/mobicom/snydwhkcqcllebpzytadxuregvqrmfka.pdf %maa17f405884f47433994c259eb955f47 %cmobicom %@Guerra, Ryan E., Anand, Narendra, Knightly, Edward W %*Demo: an open-source development platform for long-range UHF-connected wifi hotspots %uhttp://dl.acm.org/ft_gateway.cfm?id=2641753&type=pdf %f/mobicom/67ulfbsdvpf4mwwo5g0ui1tsjcybxndq.pdf %ma16ca585b8e1f3d151db6431ba20bc26 %cmobicom %@Hunter, Chris, Murphy, Patrick, Welsh, Eri %*Demo: real-time MU-MIMO channel analysis with a custom 802.11 implementation %uhttp://dl.acm.org/ft_gateway.cfm?id=2641746&type=pdf %f/mobicom/fusqiw0xbepr2d1phtj4jbnavimauywk.pdf %m2277abd5576ec6b6cf7413d8714db845 %cmobicom %@Irish, Andrew, Isaacs, Jason, Iland, Daniel, Hespanha, João, Belding, Elizabeth, Madhow, Upamany %*Demo: ShadowMaps, the urban phone tracking system %uhttp://dl.acm.org/ft_gateway.cfm?id=2641755&type=pdf %f/mobicom/nxdhwe26kngmroipfmp9icuysdfzays3.pdf %m8f71a449876b703edb8cc1fba349b840 %cmobicom %@Joerer, Stefan, Bloessl, Bastian, Huber, Matthaeus, Jamalipour, Abbas, Dressler, Falk %*Demo: simulating the impact of communication performance on road traffic safety at intersections %uhttp://dl.acm.org/ft_gateway.cfm?id=2641737&type=pdf %f/mobicom/bsuelxqhwwktlqoyg3uh1k8mdr6zgrjb.pdf %m6dd1e95998f3b6cfd37332ea91183f56 %cmobicom %@Jokinen, Markku, Mäkeläinen, Marko, Hänninen, Tuom %*Demo: co-primary spectrum sharing with inter-operator D2D trial %uhttp://dl.acm.org/ft_gateway.cfm?id=2641749&type=pdf %f/mobicom/i4eorz5gbkxdhqz90lam7ykiqnfpwuuc.pdf %md9afd34fe52f6f33f6b3daec5e69a75b %cmobicom %@Keranidis, Stratos, Chounos, Kostas, Korakis, Thanasis, Koutsopoulos, Iordanis, Tassiulas, Leandro %*Demo: enabling AGILE spectrum adaptation in commercial 802.11 WLAN deployments %uhttp://dl.acm.org/ft_gateway.cfm?id=2641752&type=pdf %f/mobicom/uus9zbrpypogn4rjt1miz57aanwvj2ok.pdf %m187e71dae253764e8f1edcf0c872c2e3 %cmobicom %@Kuo, Ye-Sheng, Pannuto, Pat, Dutta, Praba %*Demo: Luxapose: indoor positioning with mobile phones and visible light %uhttp://dl.acm.org/ft_gateway.cfm?id=2641747&type=pdf %f/mobicom/2mgr6tans8b1iurplex09j5cejztczqw.pdf %m23d51f24af28c2589c711243387fbf81 %cmobicom %@Liu, Wei, De Poorter, Eli, Becue, Pieter, Jooris, Bart, Sercu, Vincent, Moerman, Ingrid, Vanhaverbeke, Jeroen, Lylon, Carl, Gesquiere, Joh %*Demo: a cognitive solution for commercial wireless conferencing system %uhttp://dl.acm.org/ft_gateway.cfm?id=2641751&type=pdf %f/mobicom/ubjzrvskfuwqekaoj5mvdaphz6clxpgs.pdf %m80cf54282aa1f0ef545ec0b32375713d %cmobicom %@Nikaein, Navid, Knopp, Raymond, Kaltenberger, Florian, Gauthier, Lionel, Bonnet, Christian, Nussbaum, Dominique, Ghaddab, Riad %*Demo: OpenAirInterface: an open LTE network in a PC %uhttp://dl.acm.org/ft_gateway.cfm?id=2641745&type=pdf %f/mobicom/zxg5x48dvapquepjlkiy0jbrlbigtcao.pdf %m6452fad600df599fa1388e911a7a9ab6 %cmobicom %@Nychis, George, DeBruhl, Bruce, Tang, Haiyu %*Demo: TV white space networking capabilities and potential with an embedded & open-API platform %uhttp://dl.acm.org/ft_gateway.cfm?id=2641740&type=pdf %f/mobicom/d8kwc3b9agsynzfpvnqxeq0yj16uhrwh.pdf %md1f00f3ced9a19e857163bf83e036b44 %cmobicom %@Park, Yongtae, Ko, JeongGil, Kim, Hyogo %*Demo: software defined radio: on a smartphone, as an app! %uhttp://dl.acm.org/ft_gateway.cfm?id=2641742&type=pdf %f/mobicom/lo28fgspxwkrko9fbiqbv3uy15ndvezu.pdf %m4482aa351011183a43c979197c8e31b0 %cmobicom %@Tsai, Hsin-Mu, Lin, Hao-Min, Lee, Hui-Y %*Demo: rollinglight - universal camera communications for single led %uhttp://dl.acm.org/ft_gateway.cfm?id=2641748&type=pdf %f/mobicom/zfkyejzbhoiannfltbyqcovhsrkpw6id.pdf %m680a6ba3e328ab6756de8580a57a78f6 %cmobicom %@Wang, Anran, Ma, Shuai, Hu, Chunming, Huai, Jinpeng, Peng, Chunyi, Shen, Guobi %*Demo: a robust barcode system for data transmissions over screen-camera links %uhttp://dl.acm.org/ft_gateway.cfm?id=2641741&type=pdf %f/mobicom/efp3rg0gymlv4zudarw92cjsnfkojntd.pdf %m4d46d54e47c282bbcdc5185782c23583 %cmobicom %@Yang, Lei, Chen, Yekui, Chen, Chen, Li, Xiang-Yang, Ding, Xuan, Guo, Yi, Liu, Yunha %*Demo: high-precision RFID tracking using COTS devies %uhttp://dl.acm.org/ft_gateway.cfm?id=2641743&type=pdf %f/mobicom/abdcoz1m2jagry8nhedxhvfpmkyf9il4.pdf %m63a2f533fbfd3e1fee4444579125811f %cmobicom %@Zhang, Lan, Li, Xiang-Yang, Huang, Wenchao, Liu, Kebin, Zong, Shuwei, Jian, Xuesi, Feng, Puchun, Jung, Taeho, Liu, Yunha %*Demo: visual attention driven networking with smart glasses %uhttp://dl.acm.org/ft_gateway.cfm?id=2641739&type=pdf %f/mobicom/bx8uf0lfpkchugbmvayrgsanziy2hcm3.pdf %m2e531f13e6bd1b7ec7fbb90e3d48b0f8 %cmobicom %@Zhou, Pengfei, Chan, Weiming, Jiang, Shiqi, Ou, Jiajue, Li, Mo, Shen, Guobi %*Demo: instant phone attitude estimation and its applications %uhttp://dl.acm.org/ft_gateway.cfm?id=2641738&type=pdf %f/mobicom/js8v2ilfqtddbem5qgpn1im0c49snuy3.pdf %me3d4efc3680503021bd0675109e8ee72 %cmobicom %@Abari, Omid, Rahul, Hariharan, Katabi, Din %*Poster: clock synchronization for distributed wireless protocols at the physical layer %uhttp://dl.acm.org/ft_gateway.cfm?id=2642894&type=pdf %f/mobicom/its2tfpqcbwsnvxlxjhwzerjqoa6oy94.pdf %m5f17c78bf04e37c7758f788c60f62b6c %cmobicom %@Tong, Fei, Ahmadi, Maryam, Pan, Jianping, Zheng, Lei, Cai, Li %*Poster: geometrical distance distribution for modeling performance metrics in wireless communication networks %uhttp://dl.acm.org/ft_gateway.cfm?id=2642905&type=pdf %f/mobicom/vejut2xp5dms6ykqtrc9k1evxcgzio3f.pdf %m62b8993fe6bf407cdad7d20e87352124 %cmobicom %@Ahsan, Shegufta Bakht, Vaidya, Niti %*Poster: overheard ACK with token passing: an optimization to 802.11 MAC protocol %uhttp://dl.acm.org/ft_gateway.cfm?id=2642903&type=pdf %f/mobicom/jmda69zqiboyktmwfylpntievz4chjre.pdf %mc5c1b4c192922b1c4ae34a79b6a2ef47 %cmobicom %@Alasaadi, Abdulla, Nadeem, Tame %*Poster: in-lane communication framework using smartphone's inertial sensors %uhttp://dl.acm.org/ft_gateway.cfm?id=2642912&type=pdf %f/mobicom/rg2ukbxetajpamiwnf7hzvqvdclelhty.pdf %m9ad083f493bfd036ea66481da64f2b91 %cmobicom %@Chen, Changsheng, Mow, Wai H %*Poster: a coarse-fine corner detection approach for two-dimensional barcode decoding %uhttp://dl.acm.org/ft_gateway.cfm?id=2642915&type=pdf %f/mobicom/gp8elxnritn92hmyju1vqkurocdxvwti.pdf %mab1e4bc5762c759201eb1b35231e3fe2 %cmobicom %@Gao, Xin, Tian, Jie, Wang, Guilin %*Poster: detection of transportation mode based on smartphones for reducing distracted driving %uhttp://dl.acm.org/ft_gateway.cfm?id=2642911&type=pdf %f/mobicom/lewpvna4k0k35jvyf2sze8t7dutaupmi.pdf %mf17b2052336d8711413803915af29d4b %cmobicom %@Gowda, Mahanth, Stewart, Gordon, Mainland, Geoffrey, Radunović, Bozidar, Vytiniotis, Dimitrios, Patterson, Dou %*Poster: Ziria: language for rapid prototyping of wireless PHY %uhttp://dl.acm.org/ft_gateway.cfm?id=2642893&type=pdf %f/mobicom/zhudstrol7n1mb2ugkmq9safxv6wb05x.pdf %m23108ae3a29f7b434666eac8cc239047 %cmobicom %@Hu, Xiping, Deng, Jun-qi, Hu, Wenyan, Fotopoulos, Georgios, Ngai, Edith C.-H., Sheng, Zhengguo, Liang, Min, Li, Xitong, Leung, Victor C.M., Fels, Sidne %*Poster -- SAfeDJ community: situation-aware in-car music delivery for safe driving %uhttp://dl.acm.org/ft_gateway.cfm?id=2642902&type=pdf %f/mobicom/bccqftne9vzlvtm27hza6agnuwe1uxfs.pdf %mc5ab958fc5a9ccca937878b456370c19 %cmobicom %@Huang, Huan, Sun, Hailong, Ma, Guoqing, Wang, Xu, Liu, Xudon %*Poster: a framework for instant mobile web browsing with smart prefetching and caching %uhttp://dl.acm.org/ft_gateway.cfm?id=2642899&type=pdf %f/mobicom/jvaip1sctzqkfbm7aqvdy8lg5zjmpnwy.pdf %m8a7a7959ebe1aa4d3f2894d89def2547 %cmobicom %@Jung, Woo-Sung, Lim, Keun-Woo, Ko, Young-Ba %*Poster: adaptive flow control for wireless serial bus using wi-fi transmission opportunity %uhttp://dl.acm.org/ft_gateway.cfm?id=2642900&type=pdf %f/mobicom/twxlgolskcr5zhusek1ynma86eftv3nv.pdf %m3a4037ab3a03d465546e3f057a1d131f %cmobicom %@Katevas, Kleomenis, Haddadi, Hamed, Tokarchuk, Lauriss %*Poster: SensingKit: a multi-platform mobile sensing framework for large-scale experiments %uhttp://dl.acm.org/ft_gateway.cfm?id=2642910&type=pdf %f/mobicom/yg7ebjihxwnzgt4cru21h5dsxlcdu6pe.pdf %m66d5aeac475529fbaf5706dca94bd6b3 %cmobicom %@Li, Tao, Xi, Wei, Tang, Shaojie, Han, Jinsong, Zhao, Jizhong, Li, Xiang-Yang, Wang, Zhi, Jiang, Zhipin %*Poster: locating RFID tags by rotation %uhttp://dl.acm.org/ft_gateway.cfm?id=2642907&type=pdf %f/mobicom/qm4sfbefxpmxz8vwnoqzyrjuekkh9t5b.pdf %m4cb26c795898cc7228f4bc2a5809f58d %cmobicom %@Li, Tianxing, An, Chuankai, Campbell, Andrew, Zhou, Xi %*Poster: HiLight: hiding bits in pixel translucency changes %uhttp://dl.acm.org/ft_gateway.cfm?id=2642895&type=pdf %f/mobicom/3we67ox2tvmykpyu9hqvflfbq8rjdwsn.pdf %m92792ca9058860daae316d672379e16c %cmobicom %@LiKamWa, Robert, Reyes, Eddie, Zhong, Li %*Poster: retrofitting computer vision libraries for concurrent support on mobile devices %uhttp://dl.acm.org/ft_gateway.cfm?id=2642891&type=pdf %f/mobicom/mug20avrd5ihlcznfezeujmg6kkria9s.pdf %m59a12a522261c2102407ca66b2976ce1 %cmobicom %@Meng, Meng, Tan, Kun, Wang, Wenji %*Poster: AirEye: blind monitor the ISM band using narrowband radio %uhttp://dl.acm.org/ft_gateway.cfm?id=2642890&type=pdf %f/mobicom/rnky7lxs06vonpdbyeodu5vsxqhggalw.pdf %m005da4ed39a85e25a81599eb51f03227 %cmobicom %@Niu, Yong, Li, Yong, Jin, Depen %*Poster: promoting the spatial reuse of millimeter wave networks via software-defined cross-layer design %uhttp://dl.acm.org/ft_gateway.cfm?id=2642917&type=pdf %f/mobicom/s7ogqm3umuy0xvbxlkjay9cfhtrqe4fz.pdf %me2952c8bc237b27d7807cc7fc28f42bf %cmobicom %@Park, Homin, Ahn, DaeHan, Won, Myounggyu, Son, Sang H., Park, Taejoo %*Poster: Are you driving?: non-intrusive driver detection using built-in smartphone sensors %uhttp://dl.acm.org/ft_gateway.cfm?id=2642896&type=pdf %f/mobicom/t1pqrzplo7oudjxb0wn9f4ckhya2lvct.pdf %m563d306718dc5171e8f27453b962b85b %cmobicom %@Radu, Valentin, Katsikouli, Panagiota, Sarkar, Rik, Marina, Mahesh K %*Poster: am i indoor or outdoor? %uhttp://dl.acm.org/ft_gateway.cfm?id=2642916&type=pdf %f/mobicom/8flo5edbwgphdkihssyi9yj7vt3anjwc.pdf %mafa840c17d934252d8dc22d2844ae17b %cmobicom %@Ramirez, David, LiKamWa, Robert, Holloway, Jaso %*Poster: styrofoam: a tightly packed coding scheme for camera-based visible light communication %uhttp://dl.acm.org/ft_gateway.cfm?id=2642901&type=pdf %f/mobicom/qbom4unsecl1j9zhftwfyonhgcpairb0.pdf %mbf921e3fad0dbcb82b9284ceabd1f030 %cmobicom %@Ren, Yanzhi, Wang, Chen, Chen, Yingying, Yang, Ji %*Poster: hearing your breathing: fine-grained sleep monitoring using smartphones %uhttp://dl.acm.org/ft_gateway.cfm?id=2642898&type=pdf %f/mobicom/egoavfgmwz3qsrx5uzplin0khbxvdtob.pdf %m6e257e2bd72b6b514f3c42d63601e36e %cmobicom %@Riggio, Roberto, Rasheed, Tinku, Marina, Mahesh K %*Poster: programming software-defined wireless networks %uhttp://dl.acm.org/ft_gateway.cfm?id=2642897&type=pdf %f/mobicom/qjemloz0ut5bv9cxppkvursr81ifqg6o.pdf %m3e6bc69051e3e7843c9e39fd997cefd8 %cmobicom %@Salem, Ahmed, Nadeem, Tame %*Poster: ColPhone: a smartphone is just a piece of the puzzle %uhttp://dl.acm.org/ft_gateway.cfm?id=2642906&type=pdf %f/mobicom/gwn6lqjev0nrhvwimifqasg9yo5dk8tj.pdf %m379fcf5437a4b80f5e4e1952c9acb38e %cmobicom %@Shafagh, Hossein, Hithnawi, Anwa %*Poster: come closer: proximity-based authentication for the internet of things %uhttp://dl.acm.org/ft_gateway.cfm?id=2642904&type=pdf %f/mobicom/4ftwcrj5gh9o13dh7yuzsuy0nbnaqjmb.pdf %m3148d0d065d94d24c1ebbcaac280cb78 %cmobicom %@Spachos, Petros, Hatzinakos, Dimitrio %*Poster: cognitive networking in a self-powered wireless sensor network testbed %uhttp://dl.acm.org/ft_gateway.cfm?id=2642909&type=pdf %f/mobicom/uak8ltcqbsmrekpixz7t0hwfypfzgjav.pdf %m64d5673d0536b44eac99987448b32d30 %cmobicom %@Spachos, Petros, Hatzinakos, Dimitrio %*Poster - SEA-OR: spectrum and energy aware opportunistic routing for self-powered wireless sensor networks %uhttp://dl.acm.org/ft_gateway.cfm?id=2642914&type=pdf %f/mobicom/ekiyni1hv7pbwzgm4fs6yldurtah9fqg.pdf %ma29c012a577ae988db1aacf0cee35903 %cmobicom %@Sun, Li, Sen, Souvik, Koutsonikolas, Dimitrio %*Poster: detecting client mobility in WLANs using PHY layer information %uhttp://dl.acm.org/ft_gateway.cfm?id=2642892&type=pdf %f/mobicom/a5mulcrcd3jtixawgfyi1ywhshsbxk0u.pdf %mcf512961b806aca7186986c055b09764 %cmobicom %@Tuncay, Güliz Seray, Varshavskiy, Kirill, Kravets, Robin H., Nahrstedt, Klar %*Poster: SaveAlert: an efficient and scalable sensor-driven danger detection system %uhttp://dl.acm.org/ft_gateway.cfm?id=2642908&type=pdf %f/mobicom/b9582emcnyqd1wudhkyfop7cmqi0fgeu.pdf %mf9fb4459d3bcb0918c57d2caddf9f666 %cmobicom %@Zhao, Kang, Fang, Dingyi, Chen, Xiaojiang, Zhang, Yuan, Nie, Weike, Xing, Tianzhan %*Poster: doppler effect based device-free moving object localization %uhttp://dl.acm.org/ft_gateway.cfm?id=2642913&type=pdf %f/mobicom/glprhhqmgyjpu32oekmeurwftynt9ssi.pdf %mc5245775feb4a9b9dadc5305f800e44f %cmobicom %@Bahl, Victor, Kleinrock, Leonard, Katz, Randy, Chlamtac, Imric %*Applying the lessons learnt for navigating the future: a conversation with the pioneers %uhttp://dl.acm.org/ft_gateway.cfm?id=2641728&type=pdf %f/mobicom/fxore2uhx8ibwgtsmp0tzjjcnrkfw5s3.pdf %m8f7b7e5bc0f2fed4c79a9fc5370ca770 %cmobicom %@Kuo, Ye-Sheng, Pannuto, Pat, Hsiao, Ko-Jen, Dutta, Praba %*Luxapose: indoor positioning with mobile phones and visible light %uhttp://dl.acm.org/ft_gateway.cfm?id=2639109&type=pdf %f/mobicom/b9qllas2j6frporccgqaoh58nhviwye4.pdf %m831f6dec19e962f0ad07ff619f12c8bf %cmobicom %@Li, Liqun, Shen, Guobin, Zhao, Chunshui, Moscibroda, Thomas, Lin, Jyh-Han, Zhao, Fen %*Experiencing and handling the diversity in data density and environmental locality in an indoor positioning service %uhttp://dl.acm.org/ft_gateway.cfm?id=2639118&type=pdf %f/mobicom/wk5lwlbdyf4pvki8y2rndgtocqmuntua.pdf %mc21772aef018dd5e600c7ed4d96335a9 %cmobicom %@Zheng, Yuanqing, Shen, Guobin, Li, Liqun, Zhao, Chunshui, Li, Mo, Zhao, Fen %*Travi-Navi: self-deployable indoor navigation system %uhttp://dl.acm.org/ft_gateway.cfm?id=2639124&type=pdf %f/mobicom/lqlwbg6zcammpfrd534p0xvjhno2fvut.pdf %mb76f4c4efdbfd36fd2796961cc877f94 %cmobicom %@Kumar, Swarun, Gil, Stephanie, Katabi, Dina, Rus, Daniel %*Accurate indoor localization with zero start-up cost %uhttp://dl.acm.org/ft_gateway.cfm?id=2639142&type=pdf %f/mobicom/drgaxn8igjlf1hikovtw2yvpcbuyo3ez.pdf %mebe723e46ada7bd54523e9d598d66ba3 %cmobicom %@Jadidian, Jouya, Katabi, Din %*Magnetic MIMO: how to charge your phone in your pocket %uhttp://dl.acm.org/ft_gateway.cfm?id=2639130&type=pdf %f/mobicom/mdpalsbhkjyr9pcbsuiqvxxwumzal2ty.pdf %m6e196565f2a94a16f59502d11749079b %cmobicom %@Khan, Hassan, Atwater, Aaron, Hengartner, Ur %*Itus: an implicit authentication framework for android %uhttp://dl.acm.org/ft_gateway.cfm?id=2639141&type=pdf %f/mobicom/c6ynkxsd80cx27mabj9jml5nfph4ldor.pdf %m2a6f4de778ba0edc0d79d2baf04c34ae %cmobicom %@Liang, Chieh-Jan Mike, Lane, Nicholas D., Brouwers, Niels, Zhang, Li, Karlsson, Börje F., Liu, Hao, Liu, Yan, Tang, Jun, Shan, Xiang, Chandra, Ranveer, Zhao, Fen %*Caiipa: automated large-scale mobile app testing through contextual fuzzing %uhttp://dl.acm.org/ft_gateway.cfm?id=2639131&type=pdf %f/mobicom/sgpwtwflf6gzen9rv0cbijb2xy5tmqqu.pdf %m2f2dc69e7833bf1e0cbf59cc4655dd4e %cmobicom %@Dong, Mian, Lan, Tian, Zhong, Li %*Rethink energy accounting with cooperative game theory %uhttp://dl.acm.org/ft_gateway.cfm?id=2639128&type=pdf %f/mobicom/zjoxbtrn9q50twgcid4wa7uidzk8eueb.pdf %mf4b31dde94d91a1bff3eb31294c677d6 %cmobicom %@Colbert, Ki %*BYOzzzz: focusing on the unsolved challenges in mobility, an industry perspective %uhttp://dl.acm.org/ft_gateway.cfm?id=2639418&type=pdf %f/mobicom/cwqahv1isdoocfgd3lai6bkjyb4zjunu.pdf %m591b5b030d7d8fcd2d25747776af142e %cmobicom %@Chen, Yi-Chao, Qiu, Lili, Zhang, Yin, Xue, Guangtao, Hu, Zhenxia %*Robust network compressive sensing %uhttp://dl.acm.org/ft_gateway.cfm?id=2639129&type=pdf %f/mobicom/3lniazhjsgw9ufraol6chmnfqty07xvp.pdf %m6ae05461f3569a49a41e6b31500a3c8d %cmobicom %@Zhang, Pengyu, Hu, Pan, Pasikanti, Vijay, Ganesan, Deepa %*EkhoNet: high speed ultra low-power backscatter for next generation sensors %uhttp://dl.acm.org/ft_gateway.cfm?id=2639138&type=pdf %f/mobicom/glodn0irnxdcu3aq8rwksvmfeyf2b7zw.pdf %mff1248a34664cd71df65e8438eca8ce4 %cmobicom %@Sen, Sayandeep, Griepentrog, Michael, Yoon, Jongwon, Banerjee, Suma %*A case for enhancing dual radio repeater performance through striping, aggregation, and channel sharing %uhttp://dl.acm.org/ft_gateway.cfm?id=2639133&type=pdf %f/mobicom/juxmsqkwt8gjh6kevc0ubtisp1cxriaq.pdf %m7b9526214089b99bbbd3fa3c645ea156 %cmobicom %@Zhu, Yibo, Zhou, Xia, Zhang, Zengbin, Zhou, Lin, Vahdat, Amin, Zhao, Ben Y., Zheng, Haita %*Cutting the cord: a robust wireless facilities network for data centers %uhttp://dl.acm.org/ft_gateway.cfm?id=2639140&type=pdf %f/mobicom/uemn261jqxd3de5gorwyl9twyhlim7vz.pdf %m9a9a0bc04efc6a70b9f22caeed65abad %cmobicom %@Wang, Guanhua, Zou, Yongpan, Zhou, Zimu, Wu, Kaishun, Ni, Lionel M %*We can hear you with Wi-Fi! %uhttp://dl.acm.org/ft_gateway.cfm?id=2639112&type=pdf %f/mobicom/wrc9hupnmslwkdedlvba6c5zktvibyeo.pdf %mab464fd1504d5b1a724b0abc24ab972c %cmobicom %@Zhou, Pengfei, Li, Mo, Shen, Guobi %*Use it free: instantly knowing your phone attitude %uhttp://dl.acm.org/ft_gateway.cfm?id=2639110&type=pdf %f/mobicom/ovekmkbmds0xl1ouyqtu4taawg8hs3ix.pdf %meaf6dc436b52f6b370e7175d8f9bf47f %cmobicom %@Wang, Yan, Liu, Jian, Chen, Yingying, Gruteser, Marco, Yang, Jie, Liu, Hongb %*E-eyes: device-free location-oriented activity identification using fine-grained WiFi signatures %uhttp://dl.acm.org/ft_gateway.cfm?id=2639143&type=pdf %f/mobicom/v8dze5ibtxbsunlgqzh3dsj1apgojneo.pdf %m74c5a257a4abb82ed086edd0f816095e %cmobicom %@Phoomikiattisak, Ditchaphong, Bhatti, Saleem N %*IP-layer soft handoff implementation in ILNP %uhttp://dl.acm.org/ft_gateway.cfm?id=2645895&type=pdf %f/mobicom/gi8a0fun1lqfwdjkhksc7gy9zbqysh5e.pdf %mdc0c377fc1b919845bfbf0e2cfa4d486 %cmobicom %@Liu, Xiruo, Trappe, Wade, Lindqvist, Jann %*A policy-driven approach to access control in future internet name resolution services %uhttp://dl.acm.org/ft_gateway.cfm?id=2645897&type=pdf %f/mobicom/sbzlntxw9xeicf64vokcdgsiaqvhyjry.pdf %mc0e228f792be6b0dffa335498920d44a %cmobicom %@Jeon, Seil, Guimarães, Carlos, Aguiar, Rui L %*SDN-based mobile networking for cellular operators %uhttp://dl.acm.org/ft_gateway.cfm?id=2645903&type=pdf %f/mobicom/sze4qr30b1taheyoxj5w8igfwigfl6mb.pdf %md08cc3e17d6164c8add0e7228ae4ca99 %cmobicom %@Galvani, Andrea, Rodriguez-Natal, Alberto, Cabellos-Aparicio, Albert, Risso, Fulvi %*LISP-ROAM: network-based host mobility with LISP %uhttp://dl.acm.org/ft_gateway.cfm?id=2645898&type=pdf %f/mobicom/pd3iph52o16ajlhquxqvgfgndwtyu8vc.pdf %m1849e3d8fed17fc37e2a364c384750b7 %cmobicom %@Guo, Katherine, Sanadhya, Shruti, Woo, Thoma %*ViFi: virtualizing WLAN using commodity hardware %uhttp://dl.acm.org/ft_gateway.cfm?id=2645893&type=pdf %f/mobicom/7cbuhlxhjz3lsnwfrv9jovn1dyptkugd.pdf %m74586249f668da198889c6dac0d74e8b %cmobicom %@Patro, Ashish, Banerjee, Suma %*COAP: a software-defined approach for home WLAN management through an open API %uhttp://dl.acm.org/ft_gateway.cfm?id=2645902&type=pdf %f/mobicom/fwnluootgx2mytbl9kb3hyfgvszjdc8v.pdf %mbc7ebb7bc418f3774a24b9c3ed27eca9 %cmobicom %@Sapio, Amedeo, Liao, Yong, Baldi, Mario, Ranjan, Gyan, Risso, Fulvio, Tongaonkar, Alok, Torres, Ruben, Nucci, Antoni %*Per-user policy enforcement on mobile apps through network functions virtualization %uhttp://dl.acm.org/ft_gateway.cfm?id=2645896&type=pdf %f/mobicom/uzhzxvcdiorcgn65mkf9oaq8yybjhve3.pdf %mb6e766fa87912ebe1c520f0feab162bd %cmobicom %@Willis, Dale, Dasgupta, Arkodeb, Banerjee, Suma %*ParaDrop: a multi-tenant platform to dynamically install third party services on wireless gateways %uhttp://dl.acm.org/ft_gateway.cfm?id=2645901&type=pdf %f/mobicom/hg0lqmxniqdv2rp97mycj3ekk5opfatl.pdf %m3c32fcccf43350f76784571a353cafbb %cmobicom %@Roos, Stefanie, Wang, Liang, Strufe, Thorsten, Kangasharju, Juss %*Enhancing compact routing in CCN with prefix embedding and topology-aware hashing %uhttp://dl.acm.org/ft_gateway.cfm?id=2645900&type=pdf %f/mobicom/mm3eooznyqkjwuip4qyvpfgkbsl0ti7a.pdf %m89db9219698f5e9a1ee4584291120d22 %cmobicom %@Moghaddam, Saeed, Helmy, Ahme %*Interest-aware implicit multicast (iCast): opportunistic mobile data dissemination without per-group management %uhttp://dl.acm.org/ft_gateway.cfm?id=2645894&type=pdf %f/mobicom/pte1rj2nszvla07emdl4cqf6pa8rfnqg.pdf %m86b759e336981faa55d7f00e83b97b8f %cmobicom %@Lin, Tao, Xu, Yuemei, Zhang, Guoqiang, Xin, Yonghui, Li, Yang, Ci, Son %*R-iCDN: an approach supporting flexible content routing for ISP-operated CDN %uhttp://dl.acm.org/ft_gateway.cfm?id=2645899&type=pdf %f/mobicom/gnvtsrt2qlhpfynkj4gbezwac3yzh7x0.pdf %m1a9c9a4cd8c7b2455abbcbfef3c189ed %cmobicom %@Chen, Bo, Tummala, Gopi Krishna, Qiao, Yue, Srinivasan, Kanna %*In-band wireless cut-through: is it possible? %uhttp://dl.acm.org/ft_gateway.cfm?id=2643623&type=pdf %f/mobicom/7g8mbrgblkzoprwxoieydsvccuhfz3yv.pdf %me21630925c263316a7bf33310fe3d058 %cmobicom %@Gowda, Mahanth, Roy, Nirupam, Roy Choudhury, Romit, Nelakuditi, Srihar %*Backing out of linear backoff in wireless networks %uhttp://dl.acm.org/ft_gateway.cfm?id=2643622&type=pdf %f/mobicom/ax6m8ikdtyzogbhjpxe30wnncbpaleko.pdf %me543c3ab9423f6b92c31d264271beb1e %cmobicom %@Hu, Pan, Zhang, Pengyu, Ganesan, Deepa %*Leveraging interleaved signal edges for concurrent backscatter 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Sundaresan, Karthikeya %*Synchronicity: pushing the envelope of fine-grained localization with distributed mimo %uhttp://dl.acm.org/ft_gateway.cfm?id=2643619&type=pdf %f/mobicom/amyooef6dq0g8tnil7a4imybzrvuvcpj.pdf %m1878af6f6d402a95527a6de670cd4f8b %cmobicom %@Zeng, Yunze, Pathak, Parth H., Xu, Chao, Mohapatra, Prasan %*Your AP knows how you move: fine-grained device motion recognition through WiFi %uhttp://dl.acm.org/ft_gateway.cfm?id=2643620&type=pdf %f/mobicom/jfcaxxrv6z0ig8uh9435um2redqbvowp.pdf %m4f5d35fd618086a55e9c86b33f29f882 %cmobicom %@Zhou, Xia, Campbell, Andrew T %*Visible light networking and sensing %uhttp://dl.acm.org/ft_gateway.cfm?id=2643621&type=pdf %f/mobicom/7qzemxlvpf6ju1wxydowglr9zacbsjhq.pdf %m8f88d0d037aedecc6712e172a6536752 %cmobicom %@Nagy, Marcin, Kärkkäinen, Teemu, Ott, Jör %*Enhancing opportunistic networks with legacy nodes %uhttp://dl.acm.org/ft_gateway.cfm?id=2645681&type=pdf %f/mobicom/v9iodept2n0lnmfqckxorubugv3zhj7s.pdf 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%uhttp://dl.acm.org/ft_gateway.cfm?id=1028696&type=pdf %f/oopsla/szhzyqgrv4sardjbkwivmubcfxyqci6l.pdf %mbb1f53322f2a33204233354fbb09a5c2 %coopsla %@Silaghi, Rau %*Refining designs along middleware-specific concern-dimensions at different MDA-levels of abstraction %uhttp://dl.acm.org/ft_gateway.cfm?id=1028697&type=pdf %f/oopsla/vzh45w61qtuh0fb7a3ev2slkigrgwxy8.pdf %m638ec858b3c17167b47ddb1ef403a6a1 %coopsla %@Schmolitzky, Axe %*Objects first, interfaces next or interfaces before inheritance %uhttp://dl.acm.org/ft_gateway.cfm?id=1028699&type=pdf %f/oopsla/8t9bpampz5dxjudtq6e2oq4ysvwfiigz.pdf %mbf5c9e15a819f916a310858562bbd8a8 %coopsla %@Ventura, Phil, Egert, Christopher, Decker, Adrienn %*Ancestor worship in CS1: on the primacy of arrays %uhttp://dl.acm.org/ft_gateway.cfm?id=1028700&type=pdf %f/oopsla/fk6x3smg7uhedu9vpgzstaiyrbm0eqay.pdf %m5248b9647a1ff7282c7a53712f160458 %coopsla %@Henriksen, Poul, Kölling, Michae %*greenfoot: combining object visualisation with interaction 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%uhttp://dl.acm.org/ft_gateway.cfm?id=1028705&type=pdf %f/oopsla/dnxfghyq5csa3vlhmtdbfpqsazxtwkce.pdf %m8de3b6cde03dba0931288be567e97dea %coopsla %@Wick, Michael R %*Using the game of life to introduce freshman students to the power and elegance of design patterns %uhttp://dl.acm.org/ft_gateway.cfm?id=1028706&type=pdf %f/oopsla/4vqf82hytzr5vw0l36yjm9arcqegue1b.pdf %m28d3deff90b6c2a6e532ca43da7396c9 %coopsla %@Nevison, Christopher H %*From concrete to abstract: the power of generalization %uhttp://dl.acm.org/ft_gateway.cfm?id=1028707&type=pdf %f/oopsla/xc1pziox0bprk3meg68luazd2yjtwu4l.pdf %m593ac4b0f322e78c206ea113c12c586f %coopsla %@Cheng, Eric, Nguyen, Dung Zung, Ricken, Mathias, Wong, Stephe %*Marine biology simulation %uhttp://dl.acm.org/ft_gateway.cfm?id=1028708&type=pdf %f/oopsla/t1iq569lpbufiw4xrsa2zlcjdxhsymfp.pdf %me15084ec02203df45e024bc89dcc4eda %coopsla %@Noble, James, Biddle, Rober %*Notes on notes on postmodern programming: radio edit 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Bruc %*Cluster-based language models for distributed retrieval %uhttp://dl.acm.org/ft_gateway.cfm?id=312687&type=pdf %f/sigir/lx3stfrale7yjzqo6fhtq1emscdp9igi.pdf %m4539cffc62743186f873dff15466c8a1 %csigir %@Fidel, Raya, Efthimiadis, Efthimis, Pejtersen, Annelise Mark/Bates, Marcia J %*Applying user research directly to information system design (panel session) %uhttp://dl.acm.org/ft_gateway.cfm?id=317560&type=pdf %f/sigir/0bhtu7g5yhbvqiizopfrsdllemkeuo92.pdf %m8b89e11189edbf21d2868f550c840923 %csigir %@Eguchi, Koj %*Adaptive cluster-based browsing using incrementally expanded queries and its effects (poster abstract) %uhttp://dl.acm.org/ft_gateway.cfm?id=312688&type=pdf %f/sigir/0ikjt6qsnmg7vphle4rpwvfoyife1uxa.pdf %mb7b1793fd10bb489c3684feacb205a47 %csigir %@Lewis, David D., Stern, Daniel L., Singhal, Ami %*ATTICS (poster abstract): a software platform for online text classification %uhttp://dl.acm.org/ft_gateway.cfm?id=313469&type=pdf %f/sigir/fbmac7rvbhydkgrqufinuwxvqnjilt3o.pdf %mcb347ef6e8cc82da15887b904951be51 %csigir %@Jones, Gareth, Sakai, Tetsuya, Collier, Nigel, Kumano, Akira, Sumita, Kazu %*A comparison of query translation methods for English-Japanese cross-language information retrieval (poster abstract) %uhttp://dl.acm.org/ft_gateway.cfm?id=312690&type=pdf %f/sigir/t3cjaucnauzmqvv2kthoripdgyfbbzk0.pdf %mef8c9f6f482241e96e4ff50d271727da %csigir %@Ge, Xianping, Pratt, Wanda, Smyth, Padhrai %*Discovering Chinese words from unsegmented text (poster abstract) %uhttp://dl.acm.org/ft_gateway.cfm?id=313472&type=pdf %f/sigir/0qsuv5yza3gpbyfdjmjqompbhwlxecou.pdf %m50881c376dcddb9a9b19356d810276c4 %csigir %@Cormack, Gordon V., Lhotak, Ondrej, Palmer, Christopher R %*Estimating precision by random sampling (poster abstract) %uhttp://dl.acm.org/ft_gateway.cfm?id=312692&type=pdf %f/sigir/wgahi5imek1sdbcnvaz98lxjfhrteqpb.pdf %m60ad29f7da1bb68a08af74f4e03bfeca %csigir %@Rodden, Kerry, Basalaj, Wojciech, Sinclair, David, Wood, Kennet %*Evaluating a visualisation of image similarity (poster abstract) %uhttp://dl.acm.org/ft_gateway.cfm?id=312693&type=pdf %f/sigir/6rdqnfsqgmzo8epcaecbb5pxoin3wr2l.pdf %mc4bd5fb4451fe8d5d55b41418836236e %csigir %@Bruza, Peter, Song, Dawei, Wong, Kam-Fa %*Fundamental properties of aboutness (poster abstract) %uhttp://dl.acm.org/ft_gateway.cfm?id=312696&type=pdf %f/sigir/7flex2zepg6aybs5lmuzr0v8ht4dbcoo.pdf %m76731be6683046c3b584cb0af6a5ef7a %csigir %@Song, Fei, Croft, W. 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What is it? Has it had any impact? What's next? %uhttp://dl.acm.org/ft_gateway.cfm?id=2684428&type=pdf %f/sigsoft/c80kn43asrqxtwkb7iohdrmhmfvpu5aj.pdf %mda7bbddc0a9b84bef765ebb73a74b33f %csigsoft %@Penix, Joh %*Experiences developing tools for developers (invited talk) %uhttp://dl.acm.org/ft_gateway.cfm?id=2684429&type=pdf %f/sigsoft/wzlg4axsnbyeptj5pkutfkvr9cvuwm6h.pdf %mc0919cb35351a51ee97eee585fff3886 %csigsoft %@Chandra, Satis %*Are you getting traction? tales from the tech transfer trenches (invited talk) %uhttp://dl.acm.org/ft_gateway.cfm?id=2684430&type=pdf %f/sigsoft/xwtkyu26kbjmu9wlf7d4glphtcasizng.pdf %m5e1f29e2741c8e80fa49db84f16e7285 %csigsoft %@Zimmermann, Thoma %*Data hard with a vengeance (invited talk) %uhttp://dl.acm.org/ft_gateway.cfm?id=2684431&type=pdf %f/sigsoft/t0asackf9xmpnifdq47rslwo18rhuine.pdf %m471361e7f6df552ebfd84a689e18af13 %csigsoft %@Fritz, Thomas, Shepherd, David C., Kevic, Katja, Snipes, Will, Bräunlich, Christop %*Developers' code context models for change tasks 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